45th week of 2017 patent applcation highlights part 53 |
Patent application number | Title | Published |
20170323953 | Integrated strained stacked nanosheet FET - Transistors and methods of forming the same include forming a fin of alternating layers of a channel material and a sacrificial material. Stress liners are formed in contact with both ends of the fin. The stress liners exert a stress on the fin. The sacrificial material is etched away from the fin, such that the layers of the channel material are suspended between the stress liners. A gate stack is formed over and around the suspended layers of channel material. | 2017-11-09 |
20170323954 | FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A fin-type field effect transistor including a substrate, insulators, a gate stack, a seal spacer, a first offset spacer, and a second offset spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The seal spacer is located over the sidewall of the gate stack. The first offset spacer is located over the seal spacer. The second offset spacer is located over the first offset spacer. | 2017-11-09 |
20170323955 | APPARATUS AND METHODS OF FORMING FIN STRUCTURES WITH SIDEWALL LINER - An includes an epitaxial sub-fin structure disposed on a substrate, wherein a first portion of the sub-fin structure is disposed within a portion of the substrate, and a second portion of the sub-fin structure is disposed adjacent a dielectric material. A fin device structure is disposed on the sub-fin structure, wherein the fin device structure comprises the epitaxial material. A liner is disposed between the second portion of the sub-fin structure and the dielectric material. Other embodiments are described herein. | 2017-11-09 |
20170323956 | PUNCH THROUGH STOPPER IN BULK FINFET DEVICE - A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure. | 2017-11-09 |
20170323957 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained. | 2017-11-09 |
20170323958 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE - In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type. | 2017-11-09 |
20170323959 | INSULATED GATE POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE - An insulated gate power semiconductor device has an (n−) doped drift layer between an emitter side and a collector side. A trench gate electrode has a trench bottom and trench lateral sides and extends to a trench depth. A p doped first protection pillow covers the trench bottom. An n doped second protection pillow encircles the trench gate electrode at its trench lateral sides. The second protection pillow has a maximum doping concentration in a first depth, which is at least half the trench depth, wherein a doping concentration of the second protection pillow decreases towards the emitter side from the maximum doping concentration to a value of not more than half the maximum doping concentration. An n doped enhancement layer has a maximum doping concentration in a second depth, which is lower than the first depth, wherein the doping concentration has a local doping concentration minimum between the second depth and the first depth. | 2017-11-09 |
20170323960 | EPITAXIAL WAFER, SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING EPITAXIAL WAFER, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - An epitaxial wafer including: a silicon-based substrate; a first buffer layer on the substrate and including a first multilayer structure buffer region composed of Al | 2017-11-09 |
20170323961 | SEMICONDUCTOR DEVICE COMPRISING A GATE FORMED FROM A GATE RING - In some examples, a semiconductor device includes a substrate, a first doped region formed in the substrate, a second doped region around and spaced apart from the first doped region, and a channel between the first and second doped regions and formed using a gate ring on the substrate as a mask. A gate is formed over only a portion of the channel, the gate being a portion of the gate ring. | 2017-11-09 |
20170323962 | CARRIER CONFINEMENT FOR HIGH MOBILITY CHANNEL DEVICES - An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein. | 2017-11-09 |
20170323963 | THIN CHANNEL REGION ON WIDE SUBFIN - An embodiment includes a device comprising: a fin structure including an upper portion and a lower portion, the upper portion having a bottom surface directly contacting an upper surface of the lower portion; wherein (a) the lower portion is included in a trench having an aspect ratio (depth to width) of at least 2:1; (b) the bottom surface has a bottom maximum width and the upper surface has an upper maximum width that is greater the bottom maximum width; (c) the bottom surface covers a middle portion of the upper surface but does not cover lateral portions of the upper surface; and (d) the upper portion includes an upper III-V material and the lower portion includes a lower III-V material different from the upper III-V material. Other embodiments are described herein. | 2017-11-09 |
20170323964 | SPLIT FIN FIELD EFFECT TRANSISTOR ENABLING BACK BIAS ON FIN TYPE FIELD EFFECT TRANSISTORS - A method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may further include forming a split fin structure from the substrate. The metal nitride is positioned in the split portion of the fin structure. The method may continue with removing the metal nitride from a source region and drain region portion of the split fin structure, in which the metal nitride remains in a channel region portion of the split fin structure. A gate structure may then be formed on a channel region portion of the fin structure. A back bias is applied to the semiconductor device using the metal nitride in the split portion of the fin structure as an electrode. | 2017-11-09 |
20170323965 | TRIGATE TRANSISTOR STRUCTURE WITH UNRECESSED FIELD INSULATOR AND THINNER ELECTRODES OVER THE FIELD INSULATOR - Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed. | 2017-11-09 |
20170323966 | SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure. | 2017-11-09 |
20170323967 | PRECISE CONTROL OF VERTICAL TRANSISTOR GATE LENGTH - Transistor and methods of forming the same include forming a channel fin on a bottom source/drain region. A dielectric fill is formed around the channel fin with a gap in an area directly above the channel fin that has a width greater than a width of the channel fin. Spacers are formed in the gap. The dielectric fill is etched away. A gate stack is formed on sidewalls of the channel fin directly underneath the spacers. | 2017-11-09 |
20170323968 | PRECISE CONTROL OF VERTICAL TRANSISTOR GATE LENGTH - A transistor includes a vertical channel fin directly on a bottom source/drain region. A gate stack is formed on sidewalls of the vertical channel fin. Spacers are formed directly above the gate stack, one above each sidewall of the vertical channel fin. A top source/drain region is formed directly on a top surface of the vertical channel fin, between the spacers. | 2017-11-09 |
20170323969 | SGT-INCLUDING PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar, and so as to extend through a NiSi layer as an upper wiring conductor layer connecting to a gate TiN layer, and a NiSi layer as an intermediate wiring conductor layer connecting to an N+ layer. A second contact hole is formed so as to extend to the NiSi layer, and surround, in plan view, the first contact hole. An insulating SiO2 layer is formed on a side surface of the NiSi layer. A wiring metal layer in the contact holes connects the NiSi layer and the NiSi layer to each other. | 2017-11-09 |
20170323970 | DEVICES AND METHODS FOR A POWER TRANSISTOR HAVING A SCHOTTKY OR SCHOTTKY-LIKE CONTACT - Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region. | 2017-11-09 |
20170323971 | FINFET DEVICE - A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm | 2017-11-09 |
20170323972 | FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION - A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode. | 2017-11-09 |
20170323973 | SOI WAFERS AND DEVICES WITH BURIED STRESSOR - A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer. | 2017-11-09 |
20170323974 | SEMICONDUCTOR DEVICE - A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions. | 2017-11-09 |
20170323975 | SEMICONDUCTOR DEVICE - Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers Accordingly, the interface state hardly influences the movement of electrons. | 2017-11-09 |
20170323976 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A transistor including an oxide semiconductor, which has good on-state characteristics, and a high-performance semiconductor device including a transistor capable of high-speed response and high-speed operation. In the transistor including an oxide semiconductor, oxygen-defect-inducing factors are introduced (added) into an oxide semiconductor layer, whereby the resistance of a source and drain regions are selectively reduced. Oxygen-defect-inducing factors are introduced into the oxide semiconductor layer, whereby oxygen defects serving as donors can be effectively formed in the oxide semiconductor layer. The introduced oxygen-defect-inducing factors are one or more selected from titanium, tungsten, and molybdenum, and are introduced by an ion implantation method. | 2017-11-09 |
20170323977 | VERTICAL TRANSISTOR INCLUDING CONTROLLED GATE LENGTH AND A SELF-ALIGNED JUNCTION - A vertical transistor includes a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type. The proximate spacer is formed on an upper surface of a semiconductor substrate. At least one channel region extends vertically from the proximate doping source layer to the distal doping source layer. A proximate S/D extension region is adjacent the proximate spacer and a distal S/D extension region is adjacent the distal spacer. The proximate and distal S/D extension regions include dopants that match the first dopant-type of the proximate and distal doping sources. | 2017-11-09 |
20170323978 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a semiconductor device which has transistor characteristics with little variation and includes an oxide semiconductor. The semiconductor device includes an insulating film over a conductive film and an oxide semiconductor film over the insulating film. The oxide semiconductor film includes a first oxide semiconductor layer, a second oxide semiconductor layer over the first oxide semiconductor layer, and a third oxide semiconductor layer over the second oxide semiconductor layer. The energy level of a bottom of a conduction band of the second oxide semiconductor layer is lower than those of the first and third oxide semiconductor layers. An end portion of the second oxide semiconductor layer is positioned on an inner side than an end portion of the first oxide semiconductor layer. | 2017-11-09 |
20170323979 | Integrated Structures Having Gallium-Containing Regions - Some embodiments include an integrated structure having a gallium-containing material between a charge-storage region and a semiconductor-containing channel region. Some embodiments include an integrated structure having a charge-storage region under a conductive gate, a tunneling region under the charge-storage region, and a semiconductor-containing channel region under the tunneling region. The tunneling region includes at least one dielectric material directly adjacent a gallium-containing material. Some embodiments include an integrated structure having a charge-trapping region under a conductive gate, a first oxide under the charge-storage region, a gallium-containing material under the first oxide, a second oxide under the gallium-containing material, and a semiconductor-containing channel region under the second oxide. | 2017-11-09 |
20170323980 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching. | 2017-11-09 |
20170323981 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SAME - A semiconductor element capable of adjusting a barrier height φ | 2017-11-09 |
20170323982 | SINGLE-EVENT BURNOUT (SEB) HARDENED POWER SCHOTTKY DIODES, AND METHODS OF MAKING AND USING THE SAME - Under one aspect, a power Schottky diode includes a cathode; a semiconductor disposed over the cathode, the semiconductor including at least a first region and a second region, the second region defining a guard ring; an anode disposed over the first region and at least a portion of the guard ring, the anode including a metal, a junction between the anode and the first region defining a Schottky barrier; and an oxide disposed over the guard ring. Additionally, the power Schottky diode can include a resistive material disposed over at least a portion of the guard ring and at least a portion of the oxide. The resistive material can inhibit a flow of holes from the guard ring to the anode following a heavy ion strike to the guard ring. The anode further can be disposed over at least a portion of, or the entirety of, the resistive material. | 2017-11-09 |
20170323983 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches. | 2017-11-09 |
20170323984 | Layer Structure for a Thin-Film Solar Cell and Production Method - A layer structure for a thin-film solar cell and production method are provided. The layer structure for the thin-film solar cell includes a photovoltaic absorber layer doped, at least in a region which borders a surface of the photovoltaic absorber layer, with at least one alkali metal. The layer structure has an oxidic passivating layer on the surface of the photovoltaic absorber layer, which is designed to protect the photovoltaic absorber layer from corrosion. | 2017-11-09 |
20170323985 | LIFTOFF PROCESS FOR EXFOLIATION OF THIN FILM PHOTOVOLTAIC DEVICES AND BACK CONTACT FORMATION - A method for forming a back contact on an absorber layer in a photovoltaic device includes forming a two dimensional material on a first substrate. An absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) is grown over the first substrate on the two dimensional material. A buffer layer is grown on the absorber layer on a side opposite the two dimensional material. The absorber layer is exfoliated from the two dimensional material to remove the first substrate from a backside of the absorber layer opposite the buffer layer. A back contact is deposited on the absorber layer. | 2017-11-09 |
20170323986 | PHOTOVOLTAIC MODULE - A PV module includes a transparent substrate, a first solar cell unit, a crystalline silicon solar cell, and a spacer. The first solar cell unit is between the transparent substrate and the crystalline silicon solar cell, and the first solar cell unit includes a first electrode, a second electrode, and a I-III-VI semiconductor layer between the first electrode and the second electrode. The I-III-VI semiconductor layer includes at least gallium (Ga) and sulfur (S), and the energy gap thereof is more than that of crystalline silicon. Moreover, the crystalline silicon solar cell and the first solar cell unit are separated by the spacer. | 2017-11-09 |
20170323987 | SELF-BYPASS DIODE FUNCTION FOR GALLIUM ARSENIDE PHOTOVOLTAIC DEVICES - Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect. | 2017-11-09 |
20170323988 | SOLAR CELL MODULE - A solar cell module includes a plurality of cell strings having a plurality of solar cells, each solar cell having a semiconductor substrate, and a first conductivity-type electrode and a second conductivity-type electrode provided on a first surface of the semiconductor substrate, an interconnector electrically connecting a first conductivity-type electrode of a first solar cell, among the plurality of solar cells included in the plurality of cell strings, and a second conductivity-type electrode of a second solar cell adjacent to the first solar cell in a first direction, to connect the first and second solar cells in series, and a first shield positioned on a front surface of the interconnector between the first and second solar cells, and extending in a second direction crossing the first direction. | 2017-11-09 |
20170323989 | SOLAR MODULE STRUCTURES AND ASSEMBLY METHODS FOR THREE-DIMENSIONAL THIN-FILM SOLAR CELLS - A method for assembling a solar module structure comprises patterning a frontside and a backside of a double-sided printed circuit board coated with metallic foils according to desired frontside and backside interconnect layouts; applying a first coating layer to the rear side of a plurality of three-dimensional thin-film solar cells, each three-dimensional thin-film solar cell comprising: a three-dimensional thin-film solar cell substrate comprising emitter junction regions and doped base regions; emitter metallization and base metallization regions; the three-dimensional thin-film solar cell substrate comprising a plurality of single-aperture unit cells; placing the three-dimensional thin-film solar cells on the frontside of the double-sided printed circuit board; preparing a solar module assembly, comprising: a glass layer; a top encapsulant layer; the plurality of three-dimensional thin-film solar cells on the frontside of the double-sided printed circuit board; a rear encapsulant layer; a protective back plate; and sealing and packaging the solar module assembly. | 2017-11-09 |
20170323990 | SCHOTTKY UV SOLAR CELL - Optically transmissive UV solar cells may be coupled to glass substrates, for example windows, in order to generate electricity while still providing suitable optical behavior for the window. The UV solar cells may be utilized to power electrochromic components coupled to the window to adjust or vary the transmissivity of the window. The UV solar cells may utilize a Schottky ZnO/ZnS heterojunction. | 2017-11-09 |
20170323991 | COMPOSITION AND METHOD COMPRISING OVERCOATED QUANTUM DOTS - Disclosed herein are embodiments of a coated type-I quantum dot comprising a core and a shell, and a silica layer, and a method for making the quantum dot. The quantum dot may be a thick-shelled quantum dot. Also disclosed are embodiments of a composition comprising one or more coated quantum dots and a polymer. The composition may be a luminescent solar concentrator. Device comprising the composition are disclosed. The device may comprise the composition, such as a luminescent solar concentrator, applied to a substrate, such as glass. The device may be a window or a solar module. Also disclosed is a method of applying the composition to the substrate to form a thin film luminescent solar concentrator. | 2017-11-09 |
20170323992 | SOLAR POWER GENERATOR - A solar power generator for generating electricity from sunlight in which a photovoltaic panel is provided so as to be oriented for minimising exposure to direct sunlight. A heat absorber is provided, together with a filter for receiving sunlight and filtering ultraviolet and visible light components to the photovoltaic panel and infrared components to the heat absorber. The heat absorber may include a thermoelectric module. | 2017-11-09 |
20170323993 | DUAL LAYER PHOTOVOLTAIC DEVICE - A hybrid photovoltaic device ( | 2017-11-09 |
20170323994 | HETEROJUNCTION SCHOTTKY GATE BIPOLAR TRANSISTOR - Certain embodiments of the present invention may be directed to a transistor structure. The transistor structure may include a semiconductor substrate. The semiconductor substrate may include a drift region, a collector region, an emitter region, and a lightly-doped/undoped region. The lightly-doped/undoped region may be lightly-doped and/or undoped. The transistor structure may also include a heterostructure. The heterostructure forms a heterojunction with the lightly-doped/undoped region. The transistor structure may also include a collector terminal. The collector terminal is in contact with the collector region. The transistor structure may also include a gate terminal. The gate terminal is in contact with the heterostructure. The transistor structure may also include an emitter terminal. The emitter terminal is in contact with the lightly-doped/undoped region and the emitter region. | 2017-11-09 |
20170323995 | APPARATUS FOR MANUFACTURE OF AT LEAST TWO SOLAR CELL ARRANGEMENTS, SYSTEM FOR MANUFACTURE OF AT LEAST TWO SHINGLED SOLAR CELLS, AND METHOD FOR MANUFACTURE OF AT LEAST TWO SOLAR CELL ARRANGEMENTS - An apparatus for the manufacture of at least two arrangements of solar cell pieces is provided. The apparatus includes at least one positioning device configured for positioning two or more solar cell pieces on a support device for forming the at least two arrangements, wherein the apparatus is configured to allocate the two or more solar cell pieces to a respective arrangement of the at least two arrangements based on one or more properties of the two or more solar cell pieces. | 2017-11-09 |
20170323996 | AUTOMATED ASSEMBLY AND MOUNTING OF SOLAR CELLS ON SPACE PANELS - The present disclosure provides methods of fabricating a multijunction solar cell panel in which one or more of the steps are performed using an automated process. In some embodiments, the automated process uses machine vision. | 2017-11-09 |
20170323997 | METHODS OF FORMING THIN-FILM PHOTOVOLTAIC DEVICES WITH DISCONTINUOUS PASSIVATION LAYERS - In various embodiments, photovoltaic devices incorporate discontinuous passivation layers (i) disposed between a thin-film absorber layer and a partner layer, (ii) disposed between the partner layer and a front contact layer, and/or (iii) disposed between a back contact layer and the thin-film absorber layer. | 2017-11-09 |
20170323998 | SEMICONDUCTOR NANOCRYSTAL PROBES FOR BIOLOGICAL APPLICATIONS AND PROCESS FOR MAKING AND USING SUCH PROBES - A semiconductor nanocrystal compound and probe are described. The compound is capable of linking to one or more affinity molecules. The compound comprises (1) one or more semiconductor nanocrystals capable of, in response to exposure to a first energy, providing a second energy, and (2) one or more linking agents, having a first portion linked to the one or more semiconductor nanocrystals and a second portion capable of linking to one or more affinity molecules. One or more semiconductor nanocrystal compounds are linked to one or more affinity molecules to form a semiconductor nanocrystal probe capable of bonding with one or more detectable substances in a material being analyzed, and capable of, in response to exposure to a first energy, providing a second energy. Also described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and treating materials with the probe. | 2017-11-09 |
20170323999 | SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a semiconductor light emitting device including a conductive substrate, a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked. The contact area between the first electrode layer and the first semiconductor layer is 3% to 13% of the total area of the semiconductor light emitting device, and thus high luminous efficiency is achieved. | 2017-11-09 |
20170324000 | Optoelectronic Semiconductor Chip and Method for Producing Optoelectronic Semiconductor Chips - An optoelectronic semiconductor chip has a semiconductor body and a substrate on which the semiconductor body is disposed. The semiconductor body has an active region disposed between a first semiconductor layer of a first conductor type and a second semiconductor layer of a second conductor type. The first semiconductor layer is disposed on the side of the active region facing the substrate. The first semiconductor layer is electrically conductively connected to a first termination layer that is disposed between the substrate and the semiconductor body. An encapsulation layer is disposed between the first termination layer and the substrate and, in plan view of the semiconductor chip, projects at least in some regions over a side face which delimits the semiconductor body. | 2017-11-09 |
20170324001 | Light-Emitting Semiconductor Chip - A semiconductor chip includes a semiconductor body with a semiconductor layer sequence. An active region intended for generating radiation is arranged between an n-conductive multilayer structure and a p-conductive semiconductor layer. A doping profile is formed in the n-conductive multilayer structure which includes at least one doping peak. | 2017-11-09 |
20170324002 | Light Emitting Diode Chip and Fabrication Method - A light-emitting diode chip includes an epitaxial layer with a plurality of recess portions and protrusion portions; and a light transmission layer having a plurality of light transmission portions between top ends of adjacent protrusion portions and forming holes with the recess portions. The light transmission portions have a horizontal dimension larger than a width of the top ends of two adjacent protrusion portions, and serve as current blocking layer. A current spreading layer covers the light transmission layer and the epitaxial layer not masked by the light transmission layer. A refractive index of the light transmission layer is between those of the epitaxial layer and the holes, indicating a difference of refractive index between the light transmission layer and the epitaxial layer. Light scattering probability can therefore be increased, thus avoiding light absorption by electrodes and improving light extraction efficiency. | 2017-11-09 |
20170324003 | LIGHT-EMITTING DEVICE PACKAGE - A light-emitting device package of the embodiments includes a package body; at least one light emitting device above the package body; an adhesive layer between the at least one light emitting device and the package body; and an adhesive-layer-accommodating portion disposed in the package body for accommodating the adhesive layer therein, wherein the adhesive-layer-accommodating portion has a side surface disposed to be inclined at a predetermined angle relative to an imaginary vertical plane that extends in a thickness direction of the package body. | 2017-11-09 |
20170324004 | LIGHT-EMITTING DEVICE AND LIGHTING SYSTEM - Disclosed is a light emitting device according to the embodiment including a conductive semiconductor layer divided into at least two or more light emitting regions; a plurality of light emitting structures on the conductive semiconductor layer; an electrode layer on the plurality of light emitting structures; a second electrode electrically connected to the electrode layer; and a first electrode electrically connected to the conductive semiconductor layer, wherein each of the light emitting structures includes a rod-shaped first conductivity type semiconductor, an active layer configured to surround the first conductivity type semiconductor and a second conductivity type semiconductor configured to surround the active layer, and each of the light emitting structures has at least two or more outer surfaces having different extending directions with respect to an upper surface of the conductive semiconductor layer. | 2017-11-09 |
20170324005 | OPTOELECTRONIC SEMICONDUCTOR CHIP - According to the present disclosure, optoelectronic semiconductor chip includes at least one n-doped semiconductor layer, at least one p-doped semiconductor layer and one active layer arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer. The p-doped semiconductor layer is electrically contacted by means of a first metallic connection layer, and a reflection-enhancing dielectric layer sequence is arranged between the p-doped semiconductor layer and the first connection layer, which dielectric layer sequence includes a plurality of dielectric layers with different refractive indices. | 2017-11-09 |
20170324006 | METHOD OF PRODUCING A CARRIER AND METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT - A method of producing a carrier for an optoelectronic component includes providing a lead frame having an upper side and a lower side; arranging a first film on the lower side of the lead frame; arranging a second film on the upper side of the lead frame; forming a molded body from a molding material, the lead frame being embedded in the molded body; and removing the first film and the second film. | 2017-11-09 |
20170324007 | Optoelectronic Device, Use of a Dual Emitter as Wavelength Conversion Material - An optoelectronic apparatus is disclosed. In an embodiment, the apparatus includes at least one wavelength conversion region which includes at least one dual emitter as wavelength conversion material, wherein the wavelength conversion region converts primary radiation at least in part into secondary radiation, and wherein the dual emitter includes a first electronic base state and a second electronic base state, together with a first electronically excited state and a second electronically excited state which may be reached from the first electronically excited state. The dual emitter further includes emission proceeding from the second electronically excited state into the second base state. | 2017-11-09 |
20170324008 | WAVELENGTH CONVERTING MATERIAL FOR A LIGHT EMITTING DEVICE - Embodiments of the invention include a wavelength-converting material defined by AE | 2017-11-09 |
20170324009 | OPTOELECTRONIC SYSTEM - An embodiment of the invention discloses an optoelectronics system. The optoelectronic system includes an optoelectronic element having a top surface, a bottom surface, a plurality of lateral surfaces arranged between the top surface and the bottom surface, and a first electrode arranged on the bottom surface; a wavelength converting material covering a plurality of lateral surfaces; and a reflecting layer, formed on the wavelength converting material which is arranged on the top surface. | 2017-11-09 |
20170324010 | SMALL LED SOURCE WITH HIGH BRIGHTNESS AND HIGH EFFICIENCY - Small LED sources with high brightness and high efficiency apparatus including the small LED sources and methods of using the small LED sources are disclosed. | 2017-11-09 |
20170324011 | LIGHT-EMITTING DEVICE INCLUDING CHIP-SCALE LENS - A light-emitting device includes a light-emitting structure, a lens, and a reflective layer. The light-emitting structure includes a light-emitting stack structure including a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer, which are stacked, a first electrode layer electrically connected to the first-conductivity-type semiconductor layer, and a second electrode layer electrically connected to the second-conductivity-type semiconductor layer. The lens is located on the light-emitting structure. The reflective layer is located on the lens. | 2017-11-09 |
20170324012 | OPTOELECTRONIC COMPONENT AND METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT - An optoelectronic component includes a first lead frame section and a second lead frame section spaced apart from one another, and having an optoelectronic semiconductor chip arranged on the first lead frame section and the second lead frame section, wherein the first lead frame section and the second lead frame section respectively have an upper side, a lower side and a first side flank extending between the upper side and the lower side, a first lateral solder contact surface of the optoelectronic component is formed on the first side flank of the first lead frame section, and the first lateral solder contact surface is formed by a recess arranged on the first side flank of the first lead frame section and extends from the upper side to the lower side of the first lead frame section. | 2017-11-09 |
20170324013 | LIGHT EMITTING DEVICE AND ADAPTIVE DRIVING BEAM HEADLAMP SYSTEM - A light emitting device includes a substrate, a plurality of first wiring members, a plurality of second wiring members and a plurality of light emitting elements. The first wiring members extend in a first direction. The second wiring members extend in a second direction. Each of the second wiring members is segmented into a plurality of second wiring portions. The light emitting elements are disposed along the second direction. A first electrode of the light emitting element is connected to a corresponding one of the first wiring members. A second electrode of the light emitting element has a first connection part and a second connection part that is linked to the first connection part. The first connection part and the second connection part are connected to a corresponding one of the second wiring members and bridge at least two of the segmented second wiring portions in the second direction. | 2017-11-09 |
20170324014 | VERTICAL SOLID-STATE TRANSDUCERS AND HIGH VOLTAGE SOLID-STATE TRANSDUCERS HAVING BURIED CONTACTS AND ASSOCIATED SYSTEMS AND METHODS - Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials. | 2017-11-09 |
20170324015 | THERMOELECTRIC COOLING USING THROUGH-SILICON VIAS - Structures that include thermoelectric couples and methods for fabricating such structures. A device level and a back-end-of-line (BEOL) interconnect structure are fabricated at a front side of a substrate. A thermoelectric couple is formed that is coupled with the substrate. The thermoelectric couple includes a first through-silicon via extending through the device level and the substrate to a back side of the substrate, a second through-silicon via extending through the device level and the substrate to the back side of the substrate, an n-type thermoelectric pillar coupled with the first through-silicon via, and a p-type thermoelectric pillar coupled with the second through-silicon via. The BEOL interconnect structure includes a wire that couples the first through-silicon via in series with the second through-silicon via. | 2017-11-09 |
20170324016 | HIGHLY-INTEGRATED THERMOELECTRIC COOLER - A method of forming a thermoelectric device structure and the resultant thermoelectric device structure. The method forms a first pattern of epitaxial thermoelectric elements of a first conductivity type on a first semiconductor substrate, forms a second pattern of epitaxial thermoelectric elements of a second conductivity type on a second semiconductor substrate, separates the epitaxial thermoelectric elements of the first conductivity type and places the epitaxial thermoelectric elements of the first conductivity type and the epitaxial thermoelectric elements of the second conductivity type on a heat sink, and integrates the heat sink to a device substrate including an electronic device to be cooled. | 2017-11-09 |
20170324017 | Athletic Activity Monitoring Device with Energy Capture - Aspects relate to an energy harvesting device adapted for use by an athlete while exercising. The device may utilize a mass of phase-change material to store heat energy, the stored heat energy subsequently converted into electrical energy by one or more thermoelectric generator modules. The energy harvesting device may be integrated into an item of clothing, and such that the mass of phase change material may store heat energy as the item of clothing is laundered. | 2017-11-09 |
20170324018 | Athletic Activity Monitoring Device with Energy Capture - Aspects relate to an energy harvesting device adapted for use by an athlete while exercising. The device may utilize a mass of phase-change material to store heat energy, the stored heat energy subsequently converted into electrical energy by one or more thermoelectric generator modules. The energy harvesting device may be integrated into an item of clothing, and such that the mass of phase change material may store heat energy as the item of clothing is laundered. | 2017-11-09 |
20170324019 | DIFFERENTIAL CRYOGENIC TRANSMITTER - In an integrated-circuit component having a signal transmitter receives a transmitter power supply that cycles periodically between power-off and power-on voltage levels to define a sequence of enable intervals during which the signal transmitter is to output voltage levels corresponding to respective transmit data bits onto an external signaling link. The signal transmitter generates, at the start of each output-enable interval, an initial nonzero voltage having a first polarity across conductors of the external signaling link, and then conditionally transitions the initial nonzero voltage to a second nonzero voltage according to whether the transmit data bit corresponding to the output-enable interval has a predetermined one of two binary states, the second nonzero voltage having a polarity opposite the first polarity. | 2017-11-09 |
20170324020 | PIEZOELECTRIC SENSOR, A DEVICE AND A METHOD OF USING A PIEZO CHANNEL - A piezoelectric sensor comprises a microcontroller, a plurality of piezoelectric sensor elements of which at least two are useable for producing a haptic signal by a voltage (HV) generated by a boost converter connected to each piezoelectric sensor element, and connected to a piezo channel of the microcontroller. A multiplexer individually controls each of the switches if an enable a signal is present. The microcontroller is configured to use each of the piezo channels as a sensor channel for reading sensor input from the respective piezoelectric sensor element and in response to detecting a sensor input in at least one of the piezo channels to set the enable signal at the increase voltage pin and/or the enable signal pin, and to set a signal to at least one piezo channel in which the sensor input was detected. | 2017-11-09 |
20170324021 | SERVO VALVE WITH ASYMETRICAL REDUNDANT PIEZOELECTRIC ACTUATOR - A driving stage of a servo valve, including a hydraulic ejector and a hydraulic receiver able to be moved relative to each other, one of the two hydraulic units being integral with a mobile unit, movable relative to a body of the servo valve through actuation means, characterized in that the actuation means comprise two piezoelectric actuators connected in series. Control device comprising a servo valve comprising such a driving stage. | 2017-11-09 |
20170324022 | PIEZOELECTRIC ENERGY HARVESTER - A piezoelectric energy harvester has a box, a plurality of first arc-shaped metal stands and a plurality of arc-shaped piezoelectric elements. The box has an upper portion, a connection base, a buffer element and a lower portion. The connection base situates between the upper portion and the lower portion. The upper portion movably connects with the lower portion through the buffer element. The plurality of first arc-shaped metal stands situated on a side of the connection base in the box. Each of the arc-shaped piezoelectric elements locates on each of the first arc-shaped metal stands. When an external force applied on the box, the plurality of first arc-shaped metal stands deforms due to the compression from the upper portion and consequently causes the deformation of the arc-shaped piezoelectric elements for generating electricity accordingly. | 2017-11-09 |
20170324023 | ELEMENT AND ELECTRIC POWER GENERATOR - An element, including a first electrode, an intermediate layer, and a second electrode, the first electrode, the intermediate layer, and the second electrode being laminated in this order, wherein the intermediate layer has flexibility, and wherein a deformation amount on a side of the first electrode of the intermediate layer is different from a deformation amount on a side of the second electrode of the intermediate layer when a pressure is applied to the intermediate layer in a direction orthogonal to a surface of the intermediate layer. | 2017-11-09 |
20170324024 | CRYSTAL VIBRATOR AND CRYSTAL VIBRATION DEVICE - A crystal vibrator includes an AT-cut crystal substrate with a vibration portion having a principal surface and a peripheral portion surrounding and thinner than the vibration portion. An excitation electrode is formed on the principal surface and an extension electrode is electrically connected to the excitation electrode. The vibration portion has a first short-edge side lateral surface that abuts the peripheral portion at an acute angle and a tapered lateral surface adjacent to the first short-edge side lateral surface and inclined with respect to the X axis in the XZ′ plane. The tapered lateral surface abuts the peripheral portion at an angle that is greater than the angle defined by the first short-edge side lateral surface. The extension electrode extends from the excitation electrode through the tapered lateral surface to a first short-edge side in a longitudinal direction parallel to the Z′ axis. | 2017-11-09 |
20170324025 | DATA STORAGE DEVICES AND METHODS FOR MANUFACTURING THE SAME - A data storage device and a method for manufacturing the data storage device provide a data storage device having a superior reliability and easy fabrication. The data storage device comprises a substrate including cell and peripheral circuit regions, a first conductive line on the peripheral circuit region, a peripheral contact plug between the substrate and the first conductive line, the peripheral contact plug being in contact with the first conductive line, a second conductive line on the cell region, a plurality of data storage structures between the substrate and the second conductive line, and a wiring structure between the substrate and each of the data storage structures and between the substrate and the peripheral contact plug. The first conductive line includes a bottom surface having a position from the substrate that is lower than a position of a bottom surface of the second conductive line. | 2017-11-09 |
20170324026 | STORAGE ELEMENT AND STORAGE APPARATUS - A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween. This configuration may effectively prevent divergence of magnetization reversal time due to directions of magnetization of the storage layer and the magnetization fixed layer being substantially parallel or antiparallel, reduce write errors, and enable writing operation in a short time. | 2017-11-09 |
20170324027 | MAGNETIC RANDOM ACCESS MEMORY WITH PERPENDICULAR ENHANCEMENT LAYER - The present invention is directed to a magnetic tunnel junction (MTJ) memory element including a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; a magnetic fixed layer exchange coupled to the magnetic reference layer structure through an anti-ferromagnetic coupling layer; a magnesium oxide layer formed adjacent to the magnetic fixed layer; and a metal layer comprising nickel and chromium formed adjacent to the magnesium oxide layer. The magnetic reference layer structure includes a first and a second magnetic reference layers with a first perpendicular enhancement layer (PEL) interposed therebetween. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer has a second invariable magnetization direction opposite to the first invariable magnetization direction. The magnetic free layer structure includes one or more magnetic free layers having a variable magnetization direction substantially perpendicular to layer planes thereof. | 2017-11-09 |
20170324028 | COMPONENT WITH REDUCED STRESS FORCES IN THE SUBSTRATE - A component with a magnetic field sensor. The electronic component is located in a semiconductor substrate or on the surface of the semiconductor substrate and is surrounded at least partially, preferably largely, by a trench in the semiconductor substrate. The trench is filled with a filling material. | 2017-11-09 |
20170324029 | MEMORY CELL HAVING MAGNETIC TUNNEL JUNCTION AND THERMAL STABILITY ENHANCEMENT LAYER - A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be comprised of a layer of CoFeB ferromagnetic material. | 2017-11-09 |
20170324030 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY - A magnetoresistance effect element includes a reference layer made of a ferromagnetic material, a recording layer made of a ferromagnetic material, and a barrier layer disposed between the reference layer and the recording layer. The reference layer and the recording layer have an in-plane magnetization direction parallel to a surface of the layers. The recording layer has a shape that has short axis and long axis perpendicular to the short axis in plan view. A first value obtained by dividing a thickness of the recording layer by a length of the short axis of the recording layer is greater than 0.3 and smaller than 1. | 2017-11-09 |
20170324031 | MAGNETIC RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern. | 2017-11-09 |
20170324032 | METHOD, SYSTEM, AND DEVICE FOR L-SHAPED MEMORY COMPONENT - Embodiments disclosed herein may relate to forming reduced size storage components in a cross-point memory array. In an embodiment, a storage cell comprising an L-shaped storage component having an approximately vertical portion extending from a first electrode positioned below the storage material to a second electrode positioned above and/or on the storage component. A storage cell may further comprise a selector material positioned above and/or on the second electrode and a third electrode positioned above and/or on the selector material, wherein the approximately vertical portion of the L-shaped storage component comprises a reduced size storage component in a first dimension. | 2017-11-09 |
20170324033 | DIFFUSED RESISTIVE MEMORY CELL WITH BURIED ACTIVE ZONE - An apparatus for non-volatile memory, and more specifically a ReRAM device with a buried resistive memory cell. The memory cell includes a first contact disposed on a substrate, an active layer, a second contact, a first diffused zone disposed within the active layer, a second diffused zone disposed within the active layer, and an active switching zone disposed within the active layer in between the first diffused zone and the second diffused zone. In one embodiment, the active zone may be doped by diffusion or ion implantation and/or may be fabricated utilizing a self-aligned process. In another embodiment, the memory cell may combine a deep implant and shallow diffusion well to create the active zone. The vertically and laterally isolated buried resistive memory cell concentrates the electric field away from the edges of the device and eliminates the effects of interface impurities and contaminants. | 2017-11-09 |
20170324034 | RESISTIVE MEMORY HAVING CONFINED FILAMENT FORMATION - Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening. | 2017-11-09 |
20170324035 | METHOD, SYSTEM, AND DEVICE FOR PHASE CHANGE MEMORY SWITCH WALL CELL WITH APPROXIMATELY HORIZONTAL ELECTRODE CONTACT CROSS REFERENCES - Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode. | 2017-11-09 |
20170324036 | ORGANIC LIGHT-EMITTING DIODE DEVICE, MANUFACTURING METHOD THEREOF AND EVAPORATION EQUIPMENT - The present disclosure provides an organic light-emitting diode (OLED) device, comprising at least two electron transport layers between a cathode and a light-emitting layer of the device, wherein energy barrier of different electron transport layers successively increase from the cathode to the light-emitting layer. The present disclosure also provides an evaporation equipment and an OLED device manufacturing method, wherein the electron transport layers of the OLED device are formed by an evaporation process using the evaporation equipment. The OLED device of the present disclosure improves the luminescence efficiency of OLED devices, and the evaporation equipment can readily effect a fast switching between different evaporation rates within a same evaporation chamber. | 2017-11-09 |
20170324037 | POLYCYCLIC COMPOUND AND ORGANIC ELETROLUMINESCENCE DEVICE INCLUDING THE SAME - A polycyclic compound according to an embodiment of the inventive concept is represented by the following Formula 1: | 2017-11-09 |
20170324038 | HETEROCYCLIC COMPOUNDS FOR USE IN ELECTRONIC DEVICES - The present invention relates to heterocyclic compounds and to electronic devices, especially organic electroluminescent devices, comprising these compounds. | 2017-11-09 |
20170324039 | COMPOUND, MATERIAL FOR ORGANIC ELECTROLUMINESCENCE ELEMENT, ORGANIC ELECTROLUMINESCENCE ELEMENT, AND ELECTRONIC APPARATUS - A compound is represented by a formula (1) below. | 2017-11-09 |
20170324040 | SURFACE SEALING MATERIAL FOR ORGANIC EL ELEMENTS AND CURED PRODUCT OF SAME - The purpose of the present invention is to provide a surface sealing material which has high storage stability and is capable of forming, on an object to be coated such as an organic EL element, a cured product layer that has less irregularity, cissing and the like, while having high surface smoothness. A surface sealing material for organic EL elements according to the present invention contains (B) a cationically polymerizable compound that comprises a cationically polymerizable functional group in each molecule and has a structure represented by formula (1) —(R—O) | 2017-11-09 |
20170324041 | ORGANIC COMPOUND FOR ELECTROLUMINESCENCE DEVICE - The present invention discloses an organic compound is represented by the following formula(1), the organic EL device employing the organic compound as fluorescent emitting guest shown deep blue color(CIEy=0.09˜0.12)and display good performance. | 2017-11-09 |
20170324042 | ORGANIC LIGHT-EMITTING DEVICE - An organic light-emitting device including a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode, the organic layer including an emission layer, wherein the organic layer includes a first compound represented by Formula 1 and a second compound represented by Formula 2: | 2017-11-09 |
20170324043 | OXYGEN-CONTAINING FUSED RING AMINE COMPOUND, SULFUR-CONTAINING FUSED RING AMINE COMPOUND AND ORGANIC ELECTROLUMINESCENCE DEVICE - A fused amine compound including a furan ring or a thiophene ring and an organic electroluminescence device employing the amine compound. The organic electroluminescence device includes a cathode, an anode, and one or more organic thin film layers which are disposed between the cathode and the anode. The organic thin film layers include a light emitting layer and at least one layer of the organic thin film layers includes at least one amine compound. | 2017-11-09 |
20170324044 | MATERIALS FOR ORGANIC ELECTROLUMINESCENT DEVICES - The present invention relates to compounds which are suitable for use in electronic devices, and to electronic devices, in particular organic electroluminescent devices, comprising these compounds. | 2017-11-09 |
20170324045 | COMPOUND, ORGANIC ELECTROLUMINESCENCE DEVICE AND ELECTRONIC DEVICE - A novel compound capable of producing an organic electroluminescence (EL) device with excellent properties, an organic EL device comprising the compound, and an electronic device comprising the organic EL device are provided. | 2017-11-09 |
20170324046 | HETEROCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING ELEMENT USING SAME - The present specification relates to a novel hetero-cyclic compound and an organic light emitting device using the same. | 2017-11-09 |
20170324047 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light-emitting element including a first semiconductor layer of a first conductivity type; a first light-emitting layer; a second light-emitting layer; and a second semiconductor layer of a conductivity type opposite to the conductivity type of the first semiconductor layer. The first light-emitting layer has a base layer with composition subject to stress strain from the first semiconductor layer and has a plurality of base segments partitioned into a random net shape; and a first quantum well structure layer composed of at least one quantum well layer and at least one barrier layer. The second light-emitting layer has a second quantum well structure layer composed of a plurality of barrier layers that have different compositions from that of the at least one barrier layer of the first quantum well structure layer, and at least one quantum well layer. | 2017-11-09 |
20170324048 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light-emitting element including a first semiconductor layer of a first conductivity type; a light-emitting functional layer that includes first and second light-emitting layers; and a second semiconductor layer of a conductivity type opposite to the conductivity type of the first semiconductor layer. The first light-emitting layer has a first base layer with a composition subject to stress strain from the first semiconductor layer; a first quantum well layer that retains a segment shape of the first base segment; and a first barrier layer that has a flat surface flattened by embedding the first base layer and the first quantum well layer. The second light-emitting layer has a second base layer that has a composition subject to stress strain from the first barrier layer; a second quantum well layer that retains a segment shape of the second base segment; and a second barrier layer. | 2017-11-09 |
20170324049 | Organic Electroluminescent Materials and Devices - The present invention includes a new series of heteroleptic iridium complexes that demonstrate high efficiency in OLED device. | 2017-11-09 |
20170324050 | DIELECTRIC AND DIELECTRIC INK AND CAPACITOR AND TRANSISTOR AND DEVICE - A dielectric and a dielectric ink include a dielectric material. The dielectric material includes ceramide or a ceramide derivative. A capacitor and a transistor may include the dielectric material. A device may include at least one of a capacitor and a transistor that includes the dielectric material. A dielectric that includes ceramide or a ceramide derivative may be configured to provide dielectric performance in a bio field. The effect on a human body by the dielectric may be reduced, based on the dielectric material of the dielectric including ceramide or a ceramide derivative. | 2017-11-09 |
20170324051 | Method for Producing an Organic Field Effect Transistor and an Organic Field Effect Transistor - Methods for producing organic field effect transistors, organic field effect transistors, and electronic switching devices are provided. The methods may include providing a gate electrode and a gate insulator assigned to the gate electrode for electrical insulation on a substrate, depositing a first organic semiconducting layer on the gate insulator, generating a first electrode and an electrode insulator assigned to the first electrode for electrical insulation on the first organic semiconducting layer, depositing a second organic semiconducting layer on the first organic semiconducting layer and the electrode insulator, and generating a second electrode on the second organic semiconducting layer. | 2017-11-09 |
20170324052 | ORGANIC ELECTRIC MEMORY DEVICE BASED ON PHOSPHONIC ACID OR TRICHLOROSILANE-MODIFIED ITO GLASS SUBSTRATE AND PREPARATION METHOD THEREOF - The invention discloses an organic electric memory device based on phosphonic acid or trichlorosilane-modified ITO glass substrate and a preparation method thereof. The preparation method comprises the following steps of 1) cleaning the ITO glass substrate; 2) forming a phosphonic acid or trichlorosilane modified layer; 3) forming an organic coating film layer; and 4) forming an electrode, and finally obtaining the organic electric memory device. By adoption of the method, a series of sandwich-type organic electric memory devices are prepared; meanwhile, the preparation method is simple, convenient, fast, and easy to operate; compared with the conventional device, the turn-on voltage of the organic electric memory device is lowered, the yield of the multi-level system is improved, and the problem of relatively low ternary productivity at present is solved; and therefore, the organic electric memory device has extremely high application value in the future memory fields. | 2017-11-09 |