45th week of 2017 patent applcation highlights part 51 |
Patent application number | Title | Published |
20170323753 | ADJUSTABLE THERMAL TRIP MECHANISM FOR CIRCUIT BREAKER - An adjustable thermal trip mechanism for a circuit breaker is provided which can improve the reliability of over-current tripping by minimizing an influence upon thermal tripping even if an assembly error such as skewing or twisting occurs during assembly of bimetallic strips. The adjustable thermal trip mechanism for the circuit breaker comprises: a crossbar that is rotatable and has at least one power receiving portion for receiving rotary power; a bimetallic strip that can bend towards the power receiving portion when an over current occurs on the circuit; and an adjustment screw installed to face the power receiving portion, wherein the power receiving portion comprises a plurality of planar portions which are at different distances from the adjustment screw. | 2017-11-09 |
20170323754 | Two-Dimensional Graphene Cold Cathode, Anode, and Grid - In an embodiment, a method includes forming a first diamond layer on a substrate and inducing a layer of graphene from the first diamond layer by heating the substrate and the first diamond layer. The method includes forming a second diamond layer on top of the layer of graphene and applying a mask to the second diamond layer. The mask includes a shape of a cathode, an anode, and one or more grids. The method further includes forming a two-dimensional cold cathode, a two-dimensional anode, and one or more two-dimensional grids by reactive-ion electron-beam etching. Each of the two-dimensional cold cathode, the two-dimensional anode, and the one or more two-dimensional grids includes a portion of the first diamond layer, the graphene layer, and the second diamond layer such that the graphene layer is positioned between the first diamond layer and the second diamond layer. | 2017-11-09 |
20170323755 | Applications of Graphene Grids in Vacuum Electronics - Graphene grids are configured for applications in vacuum electronic devices. A multilayer graphene grid is configured as a filter for electrons in a specific energy range, in a field emission device or other vacuum electronic device. A graphene grid can be deformable responsive to an input to vary electric fields proximate to the grid. A mesh can be configured to support a graphene grid. | 2017-11-09 |
20170323756 | PHOSPHORUS DOPED DIAMOND ELECTRODE WITH TUNABLE LOW WORK FUNCTION FOR EMITTER AND COLLECTOR APPLICATIONS - An apparatus includes an emitter electrode including a phosphorus doped diamond layer with low work function. The apparatus further includes a collector electrode and a vacuum gap disposed between the emitter and the collector. The collector has a work function of 0.84 eV or less. | 2017-11-09 |
20170323757 | LASER PLASMA LENS - A device for collimation or focusing of a relativistic electron packet, obtained in particular by laser-plasma acceleration, including a gas cloud and a laser capable of emitting a laser pulse focused in the gas cloud in order to create therein a wave of focusing electric and magnetic fields. The invention also relates to a device for emission of a collimated or focused relativistic electron packet. The invention further relates to a collimation or focusing method for a relativistic electron packet, and to methods for emission of a collimated or focused relativistic electron packet. | 2017-11-09 |
20170323758 | ROTATING ANODE X-RAY TUBE - According to one embodiment, a rotating anode X-ray tube including a rotating cylinder, a rotating shaft fixed to the inside of the rotating cylinder, an anode fixing body arranged between the rotating cylinder and the rotating shaft, extending in the axial direction, and constituted of one of a magnetic substance member formed of a magnetic substance and a heat-transfer enhancing member heat conductivity of which is higher than surrounding members, ball bearings, and an inner member, connected to the anode fixing body by a connecting member, and constituted of one of the magnetic substance member and the heat-transfer enhancing member, one being different from the member constituting the anode fixing body. | 2017-11-09 |
20170323759 | X-ray tube - An X-ray tube includes a cathode, which is configured to generate an electron beam, and a round anode, which is configured to rotate such that the electron beam impinges on a rotating surface of the anode so as to emit at least one X-ray beam. An array of gas pipes is configured to direct gas onto the surface so as to cool the anode. | 2017-11-09 |
20170323760 | MULTICOLUMN CHARGED PARTICLE BEAM EXPOSURE APPARATUS - A multicolumn charged particle beam exposure apparatus includes a plurality of column cells which generate charged particle beams, and the column cell includes a yoke which is made of a magnetic material and generates a magnetic field of a predetermined intensity distribution around an optical axis of the column, and a coil which is wound around the yoke. The coil includes a plurality of divided windings, which are driven by different power sources. | 2017-11-09 |
20170323761 | CHARGED PARTICLE DETECTOR - A charged particle detector with high detection efficiency is presented in this patent. This charged particle detector contains a grid electrode used for attracting charged particles, a convertor with the shape of particle entrance area smaller than the particle exit area, which is used for converging charged particles and converting ions into electrons in the ion detection mode, an electron detection unit used for detecting secondary electrons and amplifying the signal detected, and a metal shielding. This optimized detector has a simple construction, is easy to assemble and has a low manufacturing cost. | 2017-11-09 |
20170323762 | CHARGED PARTICLE BEAM APPARATUS, ELECTRON MICROSCOPE AND SAMPLE OBSERVATION METHOD - An electron microscope includes: a sample holder; a first optical system irradiating and scanning the sample; an electron detection unit detecting secondary electrons discharged from the sample; a first vacuum chamber which holds the sample holder, the first optical system, and the electron detection unit in a vacuum atmosphere; a display unit displaying a microscopic image of the sample; and a control unit which controls the sample holder and the operation of the first optical system. The electron microscope includes a second vacuum chamber different from the first vacuum chamber, and a second optical system in the second vacuum chamber and is different from the first optical system. The second optical system and the control unit are capable of mutual communication, and the second vacuum chamber has a state changing means which changes the state of the sample. | 2017-11-09 |
20170323763 | Charged Particle Beam Device - The purpose of the present invention is to provide a charged particle beam device with which it is possible to minimize the beam irradiation amount while maintaining a high measurement success rate. The present invention is a charged particle beam device provided with a control device for controlling a scan deflector on the basis of selection of a predetermined number n of frames, wherein the control device controls the scan deflector so that a charged particle beam is selectively scanned on a portion on a sample corresponding to a pixel satisfying a predetermined condition or a region including the portion on the sample from an image obtained by scanning the charged particle beam for a number m of frames (m≧1), the number m of frames being smaller than the number n of frames. | 2017-11-09 |
20170323764 | ION BEAM DEVICE - In this invention, vibrations generated by a freezer from a cooling mechanism for cooling an ion source emitter tip are prevented from being transmitted to the emitter tip as much as possible, while the cooling capability of the cooling mechanism is improved widely. The ion beam device ( | 2017-11-09 |
20170323765 | APPARATUS FOR PLASMA TREATING AND PROCESS FOR PRODUCING MODIFIED PROTEIN STRUCTURE - A protein powder is exposed to plasma at a specified temperature and power for a specified time period wherein the plasma treated protein powder includes an increased fluorescence in a melt curve at room temperature in comparison to an untreated protein. | 2017-11-09 |
20170323766 | RF ANTENNA STRUCTURE FOR INDUCTIVELY COUPLED PLASMA PROCESSING APPARATUS - An RF antenna structure of an inductively coupled plasma (ICP) processing apparatus that includes a main container | 2017-11-09 |
20170323767 | DIELECTRIC WINDOW SUPPORTING STRUCTURE FOR INDUCTIVELY COUPLED PLASMA PROCESSING APPARATUS - An Dielectric window of an inductively coupled plasma (ICP) processing apparatus that includes a main container | 2017-11-09 |
20170323768 | PLASMA TREATMENT PROCESS FOR IN-SITU CHAMBER CLEANING EFFICIENCY ENHANCEMNET IN PLASMA PROCESSING CHAMBER - Embodiments of the disclosure include methods for in-situ chamber cleaning efficiency enhancement process for a plasma processing chamber utilized for a semiconductor substrate fabrication process. In one embodiment, a method for performing a plasma treatment process after cleaning a plasma process includes performing a cleaning process in a plasma processing chamber in absent of a substrate disposed thereon, subsequently supplying a plasma treatment gas mixture including at least a hydrogen containing gas and/or an oxygen containing gas into the plasma processing chamber, applying a RF source power to the processing chamber to form a plasma from the plasma treatment gas mixture, and plasma treating an interior surface of the processing chamber. | 2017-11-09 |
20170323769 | DIELECTRIC WINDOW SUPPORTING STRUCTURE FOR INDUCTIVELY COUPLED PLASMA PROCESSING APPARATUS - A dielectric window supporting structure of inductively coupled plasma (ICP) processing apparatus that includes a main container that houses a substrate to perform plasma processing, a substrate mounting unit on which the substrate is mounted, an exhaust system, a plurality of dielectric windows that form an upper window of the main container, a dielectric supporting unit coupled to an upper end of the main container and supports the dielectric window to seal the inside of the main container, and one or more RF antennas installed to correspond to plurality of the dielectric windows outside the main container. The dielectric supporting unit includes a central frame which supports a bottom edge of the dielectric window and an outer frame which supports the central frame. The outer frame is supported by the upper end of the main container. The central frame includes ceramic material and the outer frame includes metallic material. | 2017-11-09 |
20170323770 | DIELECTRIC WINDOW SUPPORTING STRUCTURE FOR INDUCTIVELY COUPLED PLASMA PROCESSING APPARATUS - An Dielectric window of an inductively coupled plasma (ICP) processing apparatus that includes a main container | 2017-11-09 |
20170323771 | Apparatus for Frequency Tuning in a RF Generator - A radio-frequency (RF) generator is provided that includes an exciter, a power amplifier, a filter, a sensor, and a frequency-tuning subsystem. The frequency-tuning subsystem includes a non-transitory, tangible, machine-readable medium containing instructions to perform a method that includes receiving an impedance trajectory of the plasma load; receiving a reference point in a complex-reflection-coefficient plane, the reference point lying on a reference vector passing through the reference point and the origin; receiving, from the sensor, a measured impedance of the plasma load; determining a measurement angle between a reference vector and a line passing through the reference point and a point in the complex-reflection-coefficient plane corresponding to the measured impedance; scaling the measurement angle by a predetermined constant to produce a frequency step; adding the frequency step to the initial frequency to produce an adjusted frequency; and causing the exciter to generate a signal oscillating at the adjusted frequency. | 2017-11-09 |
20170323772 | PROTECTIVE METAL OXY-FLUORIDE COATINGS - An article comprises a body having a protective coating. The protective coating is a thin film that comprises a metal oxy-fluoride. The metal oxy-fluoride has an empirical formula of M | 2017-11-09 |
20170323773 | MASS SPECTROMETER - A high-voltage power source for applying high voltage to a nozzle of an ESI ion source includes a charge release assistant section ( | 2017-11-09 |
20170323774 | WAFER PROCESSING APPARATUS - Disclosed herein is a laser processing apparatus including a condenser having a function of spherical aberration. Since the condenser has a function of spherical aberration, the focal point of a laser beam to be focused by the condenser and applied to a wafer can be continuously changed in position along the thickness of the wafer. Accordingly, a uniform shield tunnel composed of a fine hole and an amorphous region surrounding the fine hole can be formed so as to extend from, the front side of the wafer to the back side thereof, by one shot of the laser beam. | 2017-11-09 |
20170323775 | Methods of Depositing SiCON with C, O and N Compositional Control - Methods of forming SiCON films comprising sequential exposure to a silicon precursor and a mixture of alkanolamine and amine reactants and an optional plasma are described. Methods of forming a silicon-containing film comprising sequential exposure to a silicon precursor and an epoxide with an optional plasma exposure are also described. | 2017-11-09 |
20170323776 | SELECTIVE DEPOSITION USING HYDROPHOBIC PRECURSORS - Vapor deposition processes are provided in which a material is selectively deposited on a first surface of a substrate relative to a second organic surface. In some embodiments a substrate comprising a first surface, such as a metal, semi-metal or oxidized metal or semi-metal is contacted with a first vapor phase hydrophobic reactant and a second vapor phase reactant such that the material is deposited selectively on the first surface relative to the second organic surface. The second organic surface may comprise, for example, a self-assembled monolayer, a directed self-assembled layer, or a polymer, such as a polyimide, polyamide, polyuria or polystyrene. The material that is deposited may be, for example, a metal or metallic material. In some embodiments the material is a metal oxide, such as ZrO | 2017-11-09 |
20170323777 | SELECTIVELY LATERAL GROWTH OF SILICON OXIDE THIN FILM - Implementations disclosed herein generally relate to methods of forming silicon oxide films. The methods can include performing silylation on the surface of the substrate having terminal hydroxyl groups. The hydroxyl groups on the surface of the substrate are then regenerated using a plasma and H | 2017-11-09 |
20170323778 | PLASMA POISONING TO ENABLE SELECTIVE DEPOSITION - Atomic layer deposition in selected zones of a workpiece surface is accomplished by transforming the surfaces outside the selected zones to a hydrophobic state while the materials in the selected zones remain hydrophilic. | 2017-11-09 |
20170323779 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a display apparatus is provided as follows. A substrate having a display portion on an upper surface of the substrate is prepared. A protection film having an opening is attached to a lower surface of the substrate so that the protection film overlaps the display portion. A support film is attached to the lower surface so that the support film is disposed within the opening of the protection film. A driving circuit chip is attached to the upper surface so that the driving chip is spaced apart from the display portion and the opening. At least a part of the support film is removed. The substrate is bent along a longitudinal direction of the opening. | 2017-11-09 |
20170323780 | THERMALLY CONDUCTIVE SHEET AND ELECTRONIC APPARATUS - A thermally conductive sheet includes: a first graphite sheet; a second graphite sheet that is any of a second graphite sheet disposed to entirely overlap the first graphite sheet, a second graphite sheet disposed to partially overlap and to be shifted from the first graphite sheet, and a second graphite sheet disposed such that there is an interval of less than 5 mm between the second graphite sheet and the first graphite sheet; a first adhesive layer configured to adhere facing surfaces of the first graphite sheet and the second graphite sheet which are disposed; metal layers stacked to sandwich the first graphite sheet and the second graphite sheet which are disposed from the top and bottom; and second adhesive layers configured to adhere facing surfaces of the first graphite sheet, the second graphite sheet, and the metal layers which are disposed. | 2017-11-09 |
20170323781 | Selective Deposition Through Formation Of Self-Assembled Monolayers - Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include net chemisorption of a self-assembled monolayer on the second surface to prevent deposition of the film on the second surface. | 2017-11-09 |
20170323782 | FORMATION OF SiOC THIN FILMS - Methods for depositing silicon oxycarbide (SiOC) thin films on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor that does not comprise nitrogen and a second reactant that does not include oxygen. In some embodiments the methods allow for the deposition of SiOC films having improved acid-based wet etch resistance. | 2017-11-09 |
20170323783 | SHORT INORGANIC TRISILYLAMINE-BASED POLYSILAZANES FOR THIN FILM DEPOSITION - Disclosed are Si—C free and volatile silazane precursors for high purity thin film deposition. | 2017-11-09 |
20170323784 | METHOD FOR DEPOSITING A PLANARIZATION LAYER USING POLYMERIZATION CHEMICAL VAPOR DEPOSITION - A method is provided for depositing a planarization layer over features on a substrate using sequential polymerization chemical vapor deposition. According to one embodiment, the method includes providing a substrate containing a plurality of features with gaps between the plurality of features, delivering precursor molecules by gas phase exposure to the substrate, adsorbing the precursor molecules on the substrate to at least substantially fill the gaps with a layer of the adsorbed precursor molecules, and reacting the precursor molecules to form a polymer layer that at least substantially fills the gaps. | 2017-11-09 |
20170323785 | METHOD TO DEPOSIT CONFORMAL AND LOW WET ETCH RATE ENCAPSULATION LAYER USING PECVD - Methods of depositing conformal, dense silicon-containing films having low hydrogen content are provided herein. Methods involve pulsing a plasma while exposing a substrate to a silicon-containing precursor and reactant to facilitate a primarily radical-based pulsed plasma enhanced chemical vapor deposition process for depositing a conformal silicon-containing film. Methods also involve periodically performing a post-treatment operation whereby, for every about 20 Å to about 50 Å of film deposited using pulsed plasma PECVD, the deposited film is exposed to an inert plasma to densify and reduce hydrogen content in the deposited film. | 2017-11-09 |
20170323786 | GAPFILL OF VARIABLE ASPECT RATIO FEATURES WITH A COMPOSITE PEALD AND PECVD METHOD - Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps. | 2017-11-09 |
20170323787 | METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - A method for manufacturing a photoelectric conversion device comprising the steps of fixing a first substrate including a semiconductor layer provided with a photoelectric conversion element, to a second substrate, thinning the first substrate fixed to the second substrate, from the opposite side of the first substrate from the second substrate, fixing the first substrate to a third substrate provided with a semiconductor element such that the third substrate is located on the opposite side of the first substrate from the second substrate, and removing the second substrate after the step of fixing the first substrate to the third substrate. | 2017-11-09 |
20170323788 | METAL BASED NANOWIRE TUNNEL JUNCTIONS - Semiconductor light emitting diodes (LEDs) formed as (Al)GaN-based nanowire structures have a first semiconductor layer, a second semiconductor layer, and a thin metallic layer fabricated therebetween. The structures, operating in the deep ultraviolet (UV) spectral range, exhibit high photoluminescence efficiency at room temperature. The structures may be formed of an epitaxial metal tunnel junction operating as a reflector that enhances carrier transport to and from the semiconductor alloy layers, capable of producing external quantum efficiencies at least one order of magnitude higher than convention devices. | 2017-11-09 |
20170323789 | METHOD FOR FORMING OXIDE SEMICONDUCTOR FILM, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained. | 2017-11-09 |
20170323790 | WAFER BOW REDUCTION - We describe a method for reducing bow in a composite wafer comprising a silicon wafer and a silicon carbide layer grown on the silicon wafer. The method includes applying nitrogen atoms during the growth process of the silicon carbide layer on the silicon wafer so as to generate a compressive stress within the composite wafer. | 2017-11-09 |
20170323791 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND RESIST GLASS - In a method of manufacturing a semiconductor device having an oxide film removing step where an oxide film formed on a surface of a semiconductor substrate is partially removed, the oxide film removing step includes: a first step where a resist glass layer is selectively formed on an upper surface of the oxide film without using an exposure step; a second step where the resist glass layer is densified by baking the resist glass layer; and a third step where the oxide film is partially removed using the resist glass layer as a mask, wherein the resist glass layer is made of resist glass which contains at least SiO | 2017-11-09 |
20170323792 | SiC SUBSTRATE TREATMENT METHOD - Provided is a SiC substrate treatment method for, with respect to a SiC substrate ( | 2017-11-09 |
20170323793 | FABRICATION METHOD OF FAST RECOVERY DIODE - This invention involves a fabrication method of fast recovery diode, which includes following steps: growing a sacrificial oxide layer on a surface of an N− substrate; forming a P type doped field-limiting ring region on the substrate; forming a P type doped anode region on the substrate; removing the sacrificial oxide layer; annealing the substrate to form a PN junction; implanting oxygen into the surface of the substrate by ion implantation; annealing the substrate to form a silicon dioxide layer on the surface of the substrate; removing the silicon dioxide layer; forming an anode electrode and a cathode electrode of the fast recovery diode. The method eliminates the curved parts near the silicon surface of the profile of PN junction, decreases electric field intensity at the surface of the substrate, therefore increases the breakdown voltage and reliability of the fast recovery diode. | 2017-11-09 |
20170323794 | BOTTOM SOURCE/DRAIN SILICIDATION FOR VERTICAL FIELD-EFFECT TRANSISTOR (FET) - A method for manufacturing a semiconductor device includes forming a first active region on a semiconductor substrate, forming a semiconductor layer on the first active region, patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located at bottom ends of the plurality of fins, forming a silicide layer on exposed portions of the first active region, forming an electrically conductive contact on the silicide region, forming a second active region on top ends of each of the plurality of fins, and forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region. | 2017-11-09 |
20170323795 | METHOD OF SELECTIVE ETCHING ON EPITAXIAL FILM ON SOURCE/DRAIN AREA OF TRANSISTOR - Methods for forming transistors are provided. A substrate is placed in a processing chamber, and a plurality of epitaxial features is formed on the substrate. The epitaxial feature has at least a surface having the (110) plane and a surface having the (100) plane. An etchant or a gas mixture including an etchant and an etch enhancer or an etch suppressor is introduced into the processing chamber to remove a portion of the epitaxial feature. Etch selectivity between the surface having the (110) plane and the surface having the (100) plane can be tuned by varying the pressure within the processing chamber, the ratio of the flow rate of the etchant or gas mixture to the flow rate of a carrier gas, and/or the ratio of the flow rate of the etch enhancer or suppressor to the flow rate of the etchant. | 2017-11-09 |
20170323796 | METHOD FOR ETCHING SILICON LAYER AND PLASMA PROCESSING APPARATUS - Disclosed is a method of etching a silicon layer by removing an oxide film formed on a workpiece which includes the silicon layer and a mask provided on the silicon layer. The method includes: (a) forming a denatured region by generating plasma of a first processing gas containing hydrogen, nitrogen, and fluorine within a processing container accommodating the workpiece therein to denature an oxide film formed on a surface of the workpiece; (b1) removing the denatured region by generating plasma of a rare gas within the processing container; and (c) etching the silicon layer by generating plasma of a second processing gas within the processing container. | 2017-11-09 |
20170323797 | ETCHING METHOD FOR SIC SUBSTRATE AND HOLDING CONTAINER - Provided is a method for controlling the rate of etching of a SiC substrate based on a composition of a storing container. The etching method of the present invention is for etching the SiC substrate by heating the SiC substrate under Si vapor pressure, in a state where the SiC substrate is stored in a crucible. The crucible is formed of a tantalum metal, and has a tantalum carbide layer provided on an internal space side of the tantalum metal, and a tantalum silicide layer provided on the side further toward the internal space side than the tantalum carbide layer. The rate of etching of the SiC substrate is controlled based on difference in a composition of the tantalum silicide layer. | 2017-11-09 |
20170323798 | METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES - A method of manufacturing a vertical memory device includes forming a preliminary first mold structure on a substrate, which includes main and edge regions, and the first preliminary mold structure including alternating insulation and sacrificial layers, forming a first mask on the preliminary first mold structure to expose the preliminary first mold structure between a boundary of the substrate and a first target position, partially etching the insulation and sacrificial layers using the first mask to form a preliminary second mold structure, forming a second mask on the preliminary second mold structure to expose the preliminary second mold structure between the boundary of the substrate and a second target position different from the first target position, and partially etching the insulation layers and the sacrificial layers using the second mask. | 2017-11-09 |
20170323799 | LEADFRAME AND THE METHOD TO FABRICATE THEREOF - The present invention discloses a leadframe in which two conductive pillars with a high aspect ratio and the corresponding two leads of the leadframe form a 3D space for accommodating at least one device. A first lead and a second lead are spaced apart from each other. A first conductive pillar is formed on the first lead by disposing a first via on the first lead, wherein at least one first conductive material is filled inside the first via to form the first conductive pillar. A second conductive pillar is formed on the second lead by disposing a second via on the second lead, wherein at least one second conductive material is filled inside the second via to form the second conductive pillar. The first lead, the second lead, the first conductive pillar, and the second conductive pillar form a 3D space for accommodating at least one device, wherein the at least one device is electrically connected to the first conductive pillar and the second conductive pillar. | 2017-11-09 |
20170323800 | POWER MOSFET - A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a back surface, a source region and a gate region on the active surface, and a drain region on the back surface. The first patterned-metal layer disposed on the active surface includes a source electrode, a gate electrode, a drain electrode and a connecting trace. The source and gate electrodes electrically connect the source and gate regions. The connecting trace located at an edge of the substrate electrically connects the drain electrode. The dielectric layer disposed on the active surface exposes the first patterned-metal layer. The second patterned-metal layer includes UBM layers covering the source, gate and drain electrodes and a connecting metal layer covering the connecting trace and extending to the edge to electrically connect the drain region. The solder balls are disposed on the UBM layers. | 2017-11-09 |
20170323801 | METHOD OF GENERATING A POWER SEMICONDUCTOR MODULE - The present application relates to a method of generating a power semiconductor module including a carrier layer and a substrate having a terminal connection area, the method comprising: soldering the substrate to the carrier layer by forming a solder layer; wherein the solder layer is formed such, that a pre-defined cavity is provided in the solder layer adjacent to the substrate and located opposite to the terminal connection area; and welding a terminal to the terminal connection area of the substrate. | 2017-11-09 |
20170323802 | SEMICONDUCTOR DIE ASSEMBLIES WITH HEAT SINK AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface. | 2017-11-09 |
20170323803 | METHODS OF ENCAPSULATION - Methods and apparatuses suitable for depositing low hydrogen content, hermetic, thin encapsulation layers at temperatures less than about 300° C. are provided herein. Methods involve pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300° C. | 2017-11-09 |
20170323804 | MICROELECTRONICS PACKAGE WITH INDUCTIVE ELEMENT AND MAGNETICALLY ENHANCED MOLD COMPOUND COMPONENT - The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for making the same. The disclosed microelectronics package includes a module substrate, a thinned flip-chip die with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, the magnetically enhanced mold compound component, and a mold compound component. The thinned flip-chip die is attached to the module substrate and includes a device layer with an inductive element embedded therein. Herein, the inductive element is underlying the first surface portion and not underlying the second surface portion. The magnetically enhanced mold compound component is formed over the first surface portion. The mold compound component is formed over the second surface portion, not over the first surface portion, and surrounding the magnetically enhanced mold compound component. | 2017-11-09 |
20170323805 | FILM, METHOD FOR ITS PRODUCTION, AND METHOD FOR PRODUCING SEMICONDUCTOR ELEMENT USING THE FILM - To provide a film which is excellent in releasing property with respect to a resin sealed portion and excellent in low migration property and peeling property with respect to a semiconductor chip, a source electrode or a sealing glass and which is suitable as a mold release film for producing a semiconductor element having a part of the surface of a semiconductor chip, source electrode or sealing glass exposed. A film | 2017-11-09 |
20170323806 | WAFER PROFILING FOR ETCHING SYSTEM - A substrate etching system includes a support to hold a wafer in a face-up orientation, a dispenser arm movable laterally across the wafer on the support, the dispenser arm supporting a delivery port to selectively dispense a liquid etchant onto a portion of a top face of the wafer, and a monitoring system comprising a probe movable laterally across the wafer on the support. | 2017-11-09 |
20170323807 | SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE PROCESSING METHOD - Provided is a substrate processing system and a substrate processing method. The substrate processing system includes a polishing part for performing a Chemical Mechanical Polishing (CMP) process on a substrate, a cleaning part for cleaning the substrate on which the polishing process is performed, and a substrate transferring part for transferring the substrate to the cleaning part before polishing the substrate in the polishing part. The substrate may be preparatorily cleaned in the cleaning part before the polishing process, and then enters the polishing part. | 2017-11-09 |
20170323808 | APPARATUS FOR MANUFACTURE OF AT LEAST TWO SOLAR CELL ARRANGEMENTS, SYSTEM FOR MANUFACTURE OF AT LEAST TWO SHINGLED SOLAR CELLS, AND METHOD FOR MANUFACTURE OF AT LEAST TWO SOLAR CELL ARRANGEMENTS - The present disclosure provides a support device for conveying at least one solar cell element in a transport direction, wherein the support device comprises a support element configured for supporting the at least one solar cell element and an electric arrangement configured for providing an electrostatic force for holding the at least one solar cell element on the support element. | 2017-11-09 |
20170323809 | SUBSTRATE WASHING DEVICE - A substrate washing device includes a substrate holding mechanism | 2017-11-09 |
20170323810 | SINGLE USE RINSE IN A LINEAR MARANGONI DRIER - An apparatus for drying of wet substrates in a post CMP cleaning apparatus is provided. The apparatus provides a waterfall or shallow reservoir of rinsing solution, such as DIW, through which a substrate may be lifted. A solvent vapor may be provided at the rinsing solution interface on the substrate, such as in a Marangoni process. In certain embodiments, the volume of solution through which the substrate is lifted is reduced, which may provide for reduced or eliminated particle reattachment to the substrate. | 2017-11-09 |
20170323811 | SUBSTRATE PROCESSING APPARATUS AND TEMPERATURE ADJUSTMENT METHOD - Provided is a substrate processing apparatus including: a chamber in which plasma processing is performed on a substrate; a susceptor disposed in the chamber and on which the substrate is held; a shower head provided to face the susceptor with a processing space therebetween; a high frequency power source which generates plasma by applying high frequency power to the processing space; water spray devices which form a surface wet with water on a rear surface of a surface of the susceptor as a temperature adjustment surface; an evaporation chamber which isolates the wet surface from an atmosphere around the wet surface; and a pressure adjustment device which adjusts a pressure in the evaporation chamber, wherein the pressure in the evaporation chamber is adjusted by using the pressure adjustment device such that the water which forms the wet surface is evaporated, thereby controlling a temperature of the surface of the susceptor by using latent heat of evaporation of the water. | 2017-11-09 |
20170323812 | Decapsulation System - A decapsulation apparatus has an etch plate, an off-center etch head having an opening, a cover sealing to the etch plate forming an etching chamber, a gasket surrounding the opening, a ram sealed through the cover, a pressure-controlled source of Nitrogen or inert gas continuously purging the etching chamber at a low gas pressure, a f toggle mechanism mounted to a metal plate t, an etchant supply subsystem comprising sources of etchant solutions, an etchant solution pump, supply passages and controls to select etchants and etchant ratios, and a heat exchanger heating or cooling the etchant solution, etchant waste passages f conducting used etchant away. Etchants are mixed in the passages to the reaction region, and turbulence in the reaction region is promoted by impinging etchant solution on the encapsulated device. | 2017-11-09 |
20170323813 | ADVANCED TEMPERATURE CONTROL FOR WAFER CARRIER IN PLASMA PROCESSING CHAMBER - An advanced temperature control system and method are described for a wafer carrier in a plasma processing chamber. In one example a heat exchanger provides a temperature controlled thermal fluid to a fluid channel of a workpiece carrier and receives the thermal fluid from the fluid channel. A proportional valve is between the heat exchanger and the fluid channel to control the rate of flow of thermal fluid from the heat exchanger to the fluid channel. A pneumatic valve is also between the heat exchanger and the fluid channel also to control the rate of flow of thermal fluid from the heat exchanger and the fluid channel. A temperature controller receives a measured temperature from a thermal sensor of the carrier and controls the proportional valve and the pneumatic valve in response to the measured temperature to adjust the rate of flow of the thermal fluid. | 2017-11-09 |
20170323814 | WAFER LOADING APPARATUS OF WAFER POLISHING EQUIPMENT AND METHOD FOR ADJUSTING WAFER LOADING POSITION - An embodiment relates to a wafer loading apparatus of wafer polishing equipment. Provided is the wafer loading apparatus of wafer polishing equipment, comprising: a wafer polisher that includes a polishing carrier having a wafer hole formed therein in which a wafer is loaded, wherein both sides of the wafer are polished by top and bottom boards; a wafer transferrer that includes a transfer arm disposed above the polishing carrier to transfer the wafer, wherein a transfer plate corresponding to a shape of the wafer is connected to one end the transfer arm; a wafer position detector mounted on a bottom surface of the transfer plate to detect a position of the wafer hole; a plurality of wafer attachment/detachment units formed on an edge portion of the transfer plate; a wafer aligner mounted on a top surface of the transfer plate to align the wafer; and a controller to which data on the position of the wafer hole, which is detected by the wafer position detector, is transmitted and which calculates a position where the wafer is to be loaded by the wafer attachment/detachment unit and the wafer aligner. | 2017-11-09 |
20170323815 | SUBSTRATE HOLDING DEVICE, SUBSTRATE TRANSPORT DEVICE, PROCESSING ARRANGEMENT AND METHOD FOR PROCESSING A SUBSTRATE - In accordance with various embodiments, provision is made of a substrate holding device, wherein the latter may comprise a carrier plate with a recess, the recess extending from an upper side of the carrier plate to a lower side of the carrier plate through the carrier plate, a holding frame, which has a frame opening and a support area, surrounding the frame opening, for holding a substrate in the recess, wherein the holding frame inserted into the recess lies on the carrier plate in sections. | 2017-11-09 |
20170323816 | SUBSTRATE PROCESSING APPARATUS AND ARTICLE MANUFACTURING METHOD - A substrate processing apparatus including a plurality of processing devices each of which processes a substrate is provided. The apparatus comprises a conveying device including a conveyance path and conveys, to one of the plurality of processing devices, a substrate conveyed into one end of the conveyance path from an outside of the substrate processing apparatus, and an adjusting device configured to perform adjustment of a pre-alignment state of the substrate conveyed from the one end and to be conveyed into one of the plurality of processing devices, wherein the adjusting device is arranged on the conveyance path and between a processing devices of the plurality of processing devices, farthest from the one end, and a processing device, of the plurality of processing devices, closest to the one end. | 2017-11-09 |
20170323817 | TRANSPORT DEVICE - A transport device is capable of reliably determining a presence or absence of a lid provided on a container and/or determining detachment of the lid, with a simple configuration. The transport device transports a container that includes a lid on a side surface. The transport device includes a lid fall preventive member disposed so as to face an upper end of the lid of the container located in a transport position, and a lid detector that is disposed in the lid fall preventive member and detects the presence or absence of the upper end of the lid. | 2017-11-09 |
20170323818 | ROTATING AND HOLDING APPARATUS FOR SEMICONDUCTOR SUBSTRATE AND CONVEYING APPARATUS OF ROTATING AND HOLDING APPARATUS FOR SEMICONDUCTOR SUBSTRATE - A holding apparatus for a semiconductor substrate and a conveying apparatus for a semiconductor substrate. | 2017-11-09 |
20170323819 | ELECTROSTATIC CHUCKING DEVICE - Provided is an electrostatic chucking device having high heat resistance. The electrostatic chucking device of the present invention includes a first ceramic plate which includes a first surface on which a substrate is able to be placed and a second surface on the opposite side thereof, and in which an internal electrode for electrostatic adsorption is embedded; a heating member fixed to the second surface; a second ceramic plate adhered to the first ceramic plate and the heating member via a first adhesive layer; and a cooling base portion adhered to the second ceramic plate via a second adhesive layer and cools at least the second ceramic plate. The first adhesive layer has a higher heat resistance than the second adhesive layer. The second adhesive layer has a smaller Young's modulus than the first adhesive layer. | 2017-11-09 |
20170323820 | Surface Protective Sheet - A surface protective sheet is used when grinding the rear surface of a semiconductor wafer having a circuit formed on the front surface, and is provided with: a base material comprising a support film and an antistatic coating layer which includes an inorganic conductive filler and a cured product of a curable resin (A); and an adhesive layer. The stress relaxation percentage of the base material after 1 minute at 10% elongation is at least 60%. The Young's modulus of the base material is 100-2000 MPa. | 2017-11-09 |
20170323821 | ROBOT SUBASSEMBLIES, END EFFECTOR ASSEMBLIES, AND METHODS WITH REDUCED CRACKING - A robot subassembly including roll, pitch, and/or vertical orientation adjustability capability of a ceramic or glass end effector. The robot subassembly includes a robot component, a mounting plate coupled to the robot component, wherein the mounting plate includes adjustable orientation relative to the robot component, and a brittle ceramic or glass end effector coupled to the mounting plate. Methods of adjusting orientation between a robot component and the end effector, as well as numerous other aspects are disclosed. | 2017-11-09 |
20170323822 | SYSTEMS, APPARATUS, AND METHODS FOR AN IMPROVED SUBSTRATE HANDLING ASSEMBLY - Embodiments of the present invention provide systems, apparatus, and methods for an improved substrate handling assembly. Embodiments include a pair of actuated arms; a pair of substrate capture tips, each capture tip formed in a different distal end of each actuated arm; an actuator coupled to a proximate end of the actuated arms and operative to actuate the actuated arms; and a hard stop positioned to prevent the actuator from closing the actuated arms more than a predefined amount so that in a closed position, the actuated arms do not contact a substrate positioned to be picked up by the substrate handing assembly. Numerous additional aspects are disclosed. | 2017-11-09 |
20170323823 | METHOD AND APPARATUS FOR PROCESSING WAFER-SHAPED ARTICLES - In an apparatus for treating a wafer-shaped article, a spin chuck is configured to hold a wafer-shaped article of a predetermined diameter. A non-rotating plate is positioned relative to the spin chuck such that the non-rotating plate is beneath and parallel to a wafer-shaped article when positioned on the spin chuck. A fluid dispensing nozzle passes through the non-rotating plate and terminates in a discharge end positioned above and adjacent to the non-rotating plate. The discharge end comprises a horizontal gas discharge nozzle configured to distribute gas radially outwardly across an upper surface of the non-rotating plate. | 2017-11-09 |
20170323824 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer. | 2017-11-09 |
20170323825 | ETCHING METHOD - A method includes performing one or more times of a sequence and reducing a film thickness of a fluorocarbon-containing film formed by performing one or more times of the sequence. Each of the one or more times of the sequence includes forming the fluorocarbon-containing film on a processing target object by generating plasma of a processing gas containing a fluorocarbon gas and not containing an oxygen gas; and etching a first region with radicals of fluorocarbon contained in the fluorocarbon-containing film. In the method, an alternating repetition in which the one or more times of the sequence and the reducing of the film thickness of the fluorocarbon-containing film are alternately repeated is performed. | 2017-11-09 |
20170323826 | SINGLE LAYER INTEGRATED CIRCUIT PACKAGE - An integrated circuit packaging is described, including a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein an electrical circuit is formed by using a masking material, and an interconnection is developed between the electrical circuits, where the interconnection is disposed on at least one side of the first patterned conductive layer and masking material, in which the interconnection is enclosed with a second masking material to form the integrated circuit packaging. | 2017-11-09 |
20170323827 | Method for Forming Interconnect Structure - An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material. | 2017-11-09 |
20170323828 | MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES - Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate. | 2017-11-09 |
20170323829 | INTEGRATED CIRCUIT PACKAGE HAVING I-SHAPED INTERCONNECT - An integrated circuit packaging is described and includes a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein the electrical circuit is formed by using a masking material, and a stud conductive layer disposed on at least one side of the first patterned conductive layer developed by a second layer photo-resist material on the masking material, in which the second layer photo-resist material includes a first line layer with a smaller exposed area than the surface of the conductive layer disposed on one side of the first patterned conductive layer and a second line layer with a larger exposed area than the first line layer disposed on the first layer, such that the exposed area forms an “I” shaped connection of the conductive layer and the stud conductive layer. | 2017-11-09 |
20170323830 | INTEGRATED CIRCUIT PACKAGE HAVING PIN UP INTERCONNECT - An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer. | 2017-11-09 |
20170323831 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming first gate stacks on a first region of a substrate to be spaced apart by a first distance, forming second gate stacks on a second region of the substrate to be spaced apart by a second distance greater than the first distance, forming a first blocking film along the first gate stacks and the substrate, a thickness of the first blocking film between the first gate stacks being a first thickness, forming a second blocking film along the second gate stacks and the substrate, a thickness of the second blocking film between the second gate stacks being a second thickness different from the first thickness, and removing the first blocking film, the second blocking film, and the substrate to form a first recess between the first gate stacks and a second recess between the second gate stacks. | 2017-11-09 |
20170323832 | DUMMY MOL REMOVAL FOR PERFORMANCE ENHANCEMENT - The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an associated method of formation. In some embodiments, the integrated chip has a well region with a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch having a first pitch that is larger than the regular pitch. Since the MOL structures have an irregular pitch with a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a space that reduces parasitic capacitance. | 2017-11-09 |
20170323833 | MINIMIZE MIDDLE-OF-LINE CONTACT LINE SHORTS - Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact. | 2017-11-09 |
20170323834 | SEMICONDUCTOR PACKAGE WITH ELECTRICAL TEST PADS - One or more embodiments are directed to semiconductor packages that include conductive test pads that are electrically coupled to, but distinct from, the leads of the package. In one embodiment the test pads are located on the plastic packaging material, such as encapsulation material, of the package and are electrically coupled to the leads of the package by traces. The traces may also be located on the packaging material and portions of the leads. In one embodiment, all of the test pads are located on a single surface of the packaging material of the package, which may allow for ease of electrical testing of the package. | 2017-11-09 |
20170323835 | DIE EDGE CRACK AND DELAMINATION DETECTION - A die edge crack and delamination detection device includes a semiconductor device including an IC active area surrounded by at least one mechanical protection barrier (MPB); one or more metallization layers stacked on the IC active area; a plurality of passive electronic devices placed within the metallization layers at respective predetermined distances from the MPB; and a detection circuit having circuitry. The circuitry is configured to determine a specific metallization layer in which a crack or a delamination is encroaching from an edge of the semiconductor device, determine a lateral distance of a lead end of the crack or the delamination from the MPB, and determine a rate of approach of the crack or the delamination encroaching towards the MPB, via a nominal change in an electrical measurement of at least one of the passive electronic devices. | 2017-11-09 |
20170323836 | ELECTRONIC COMPONENT CONTAINING PACKAGE AND ELECTRONIC DEVICE - An electronic component containing package includes a substrate including a placement region for placing an electronic component in an upper face thereof; a frame disposed on the upper face of the substrate surrounding the placement region, and including a penetration part opening; and an input/output member disposed in the frame closing the penetration part, including a plurality of wiring conductors which extend inward and outward of the frame and are electrically connected to the electronic component. The input/output member includes via conductors which are connected to the wiring conductors and embedded at sites overlapping with the wiring conductors within a region surrounded by the frame in the input/output member, and a ground layer disposed in a surrounding of lower ends of the via conductors being spaced from the via conductors. Improved high frequency characteristics can be achieved. | 2017-11-09 |
20170323837 | AIR CAVITY PACKAGE - An air cavity package includes a dielectric frame that is formed from an alumina ceramic, a polyimide, or a semi-crystalline thermoplastic. The dielectric frame is joined to a flange using a high temperature silicone adhesive. Leads may be bonded to the dielectric frame using a high temperature organic adhesive, a direct bond, or by brazing. | 2017-11-09 |
20170323838 | ELECTRONIC CIRCUIT MODULE - An electronic circuit module includes a circuit board, electronic components, an embedding layer, and a conductive film. The circuit board has a first principal surface, a second principal surface and a side surface, and includes a pattern conductor and a via conductor. The conductive film is connected to a conduction path to a ground electrode. The side surface includes a first region, a second region having a longer circumferential length than the first region, and a connection region connecting the first region and the second regions. The conductive film is formed on a region including at least part of each of an outer surface of the embedding layer, the first region, and the connection region. The conductive film formed on at least part of the connection region is connected to an exposed portion in the connection region of the via conductor included in the conduction path to the ground electrode. | 2017-11-09 |
20170323839 | MOLDED PACKAGE - A molded package includes an IC chip mounted on a first surface of a lead frame, and a molded resin encapsulating the lead frame together with the IC chip. The molded resin has a second surface-side opening portion that is formed to expose a chip correspondence portion of a second surface of the lead frame corresponding to the IC chip. A filler material is filled in the second surface-side opening portion. The filler material has a thermal conductivity equal to or greater than that of the molded resin and is softer than the molded resin. The chip correspondence portion has a rough surface with fine splits so as to increase a contact area with the filler material, and the filler material is in contact with the external member. | 2017-11-09 |
20170323840 | Package with Tilted Interface between Device Die and Encapsulating Material - A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via. | 2017-11-09 |
20170323841 | ELECTRONIC DEVICE PROVIDED WITH AN INTEGRAL CONDUCTIVE WIRE AND METHOD OF MANUFACTURE - An electronic device includes a supporting substrate having a front mounting face and an electrical connection network. An integrated circuit chip is mounted to the mounting face and is electrically connected to the electrical connection network. A primary encapsulation block embeds the integrated circuit chip and extends above and around the integrated circuit chip on the mounting face of the supporting substrate. An opening is provided in the primary encapsulation block to at least partially uncover an electrical contact. An additional wire made from an electrically conductive material has an end that is electrically connected to the electrical contact. An additional encapsulation block above the primary encapsulation block embeds the additional wire. | 2017-11-09 |
20170323842 | BONDED SUBSTRATE AND METHOD FOR MANUFACTURING BONDED SUBSTRATE - Provided is a bonded substrate mainly for mounting a power semiconductor in which the reliability to a thermal cycle has been enhanced as compared with a conventional one. In a bonded substrate in which a copper plate is bonded to one or both main surface(s) of a nitride ceramic substrate, a bonding layer consisting of TiN intervenes between the nitride ceramic substrate and the copper plate and is adjacent at least to the copper plate, and an Ag distribution region in which Ag atoms are distributed is set to be present in the copper plate. Preferably, an Ag-rich phase is set to be present discretely at an interface between the bonding layer and the copper plate. | 2017-11-09 |
20170323843 | Gas-Cooled 3D IC with Wireless Interconnects - A three-dimensional integrated circuit includes two or more stacks of one or more active layers; a gas-cooling layer separating the two or more stacks and a wireless interconnect between the two or more stacks enabling communication between the two or more stacks and system including a gas-cooled three-dimensional integrated circuit having wireless data interconnects is disclosed. | 2017-11-09 |
20170323844 | Strain-Tolerant Die Attach with Improved Thermal Conductivity, and Method of Fabrication - A mechanically-stable and thermally-conductive interface device between a semiconductor die and a package for the die, and related method of fabrication, comprising: a semiconductor die; a package for the die; a surface area-enhancing pattern on the package and/or the die; and die attach materials between the die and the package, the die attach materials attaching the die to the package through an interface provided by the die attach materials; wherein: an effective bonding area between the die attach materials and the package and/or the die is greater with the pattern than without the pattern; and the increase of the effective bonding area simultaneously increases the surface area for thermal transport between the package and/or the die, and the die attach materials; and increases the surface area for stably attaching the at least one of the package and the die to the die attach materials. | 2017-11-09 |
20170323845 | ELECTRONIC PACKAGE - The disclosed embodiments of electronic packages include electrical contact pad features present on all sides of the package that facilitate simple and low cost electrical connections to the package made through a mechanical contacting scheme. In an embodiment, an electronic package comprises: a metal leadframe having a first leadframe portion having a first thickness and a second leadframe portion having a second thickness that is less than the first thickness, the second leadframe portion defining electrical contact pads; a silicon die attached to the second leadframe portion and overlying a space formed in the leadframe by the first and second leadframe portions; and wirebonds coupling the silicon die to the electrical contact pads. A method of fabricating the electronic package is also disclosed. | 2017-11-09 |
20170323846 | ELECTRONIC POWER DEVICE WITH FLAT ELECTRONIC INTERCONNECTION STRUCTURE - Electronic power device comprising:
| 2017-11-09 |
20170323847 | DOUBLE-FACED COOLING-TYPE POWER MODULE - A double-facing cooling-type power module has coolers on both sides. The power module includes: a first switch having the coolers on both sides; a second switch disposed independently from the first switch and having the coolers on both sides; and a common electrode coupled to both the first switch and the second switch. | 2017-11-09 |
20170323848 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1. | 2017-11-09 |
20170323849 | ADAPTER PANEL AND MANUFACTURING METHOD AND ENCAPSULATION STRUCTURE THEREOF AND BONDING METHOD FOR THE ADAPTER PANEL - Disclosed is an adapter panel and a method of manufacturing the same comprising a panel body having a first surface and an opposing second surface, wherein a through-hole in a frustrum shape is formed through the panel body and filled by a conical electrical conductor between the first and second surface. The conical electrical conductor has a plane end flush with the first surface and a tip end protruding from the second surface. The panel body further comprises a wiring structure on the first surface electrically connected to the plane end of the conical electrical conductor. Bonding to a dielectric plate can be achieved by directly inserting the tip end of the conical electrical conductor into a solder ball. | 2017-11-09 |
20170323850 | SEMICONDUCTOR DEVICES HAVING STAGGERED AIR GAPS - A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween. | 2017-11-09 |
20170323851 | MULTILAYER INDUCTOR AND THE FABRICATION METHOD THEREOF - A multilayer electrical component is disclosed, wherein the multilayer electrical component comprises: a plurality of magnetic layers stacked over one another, wherein each magnetic layer is made of a first magnetic material, and wherein for each magnetic layer, a trench is formed in the magnetic layer, the bottom surface of the trench being located higher than the bottom surface of the magnetic layer; a second material that is different from the first material is disposed in the trench in the magnetic layer; and a conductive layer is disposed over the trench for forming a conductive element of the electrical component. | 2017-11-09 |
20170323852 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate. | 2017-11-09 |