45th week of 2018 patent applcation highlights part 58 |
Patent application number | Title | Published |
20180323079 | METHODS FOR PROCESSING SEMICONDUCTOR WAFERS HAVING A POLYCRYSTALLINE FINISH | 2018-11-08 |
20180323080 | GETTERING LAYER FORMING METHOD | 2018-11-08 |
20180323081 | GETTERING LAYER FORMING METHOD | 2018-11-08 |
20180323082 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 2018-11-08 |
20180323083 | Sensor Device With Media Channel Between Substrates | 2018-11-08 |
20180323084 | FIRST PROTECTIVE FILM-FORMING SHEET, METHOD FOR FORMING FIRST PROTECTIVE FILM, AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP | 2018-11-08 |
20180323085 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD FOR DISCHARGE OF PROCESSING LIQUID FROM NOZZLE | 2018-11-08 |
20180323086 | ROBOT TRANSPORT DEVICE | 2018-11-08 |
20180323087 | HIGH-THROUGHPUT BATCH POROUS SILICON MANUFACTURING EQUIPMENT DESIGN AND PROCESSING METHODS | 2018-11-08 |
20180323088 | DIE PLACEMENT HEAD WITH TURRET | 2018-11-08 |
20180323089 | BONDING APPARATUS AND BONDING METHOD | 2018-11-08 |
20180323090 | MEDICAL INSTRUMENT FOR IN VIVO HEAT SOURCE | 2018-11-08 |
20180323091 | METHOD AND APPARATUS FOR UNIFORM THERMAL DISTRIBUTION IN A MICROWAVE CAVITY DURING SEMICONDUCTOR PROCESSING | 2018-11-08 |
20180323092 | FLUORESCENCE BASED THERMOMETRY FOR PACKAGING APPLICATIONS | 2018-11-08 |
20180323093 | INTEGRATED SUBSTRATE TEMPERATURE MEASUREMENT ON HIGH TEMPERATURE CERAMIC HEATER | 2018-11-08 |
20180323094 | CHUCK STAGE PARTICLE DETECTION DEVICE | 2018-11-08 |
20180323095 | IMAGE BASED SUBSTRATE MAPPER | 2018-11-08 |
20180323096 | SYSTEMS AND METHODS FOR PASSIVE ALIGNMENT OF SEMICONDUCTOR WAFERS | 2018-11-08 |
20180323097 | EXPANSION METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE | 2018-11-08 |
20180323098 | WAFER POSITIONING PEDESTAL FOR SEMICONDUCTOR PROCESSING | 2018-11-08 |
20180323099 | FDSOI CHANNEL CONTROL BY IMPLANTED HIGH-K BURIED OXIDE | 2018-11-08 |
20180323100 | METAL VIA PROCESSING SCHEMES WITH VIA CRITICAL DIMENSION (CD) CONTROL FOR BACK END OF LINE (BEOL) INTERCONNECTS AND THE RESULTING STRUCTURES | 2018-11-08 |
20180323101 | FORMING INTERCONNECTS WITH SELF-ASSEMBLED MONOLAYERS | 2018-11-08 |
20180323102 | Selective Deposition of Dielectric Materials | 2018-11-08 |
20180323103 | METHODS AND APPARATUS FOR FILLING A FEATURE DISPOSED IN A SUBSTRATE | 2018-11-08 |
20180323104 | TRIBLOCK COPOLYMERS FOR SELF-ALIGNING VIAS OR CONTACTS | 2018-11-08 |
20180323105 | Simultaneous Break and Expansion System for Integrated Circuit Wafers | 2018-11-08 |
20180323106 | CO-PLANAR P-CHANNEL AND N-CHANNEL GALLIUM NITRIDE-BASED TRANSISTORS ON SILICON AND TECHNIQUES FOR FORMING SAME | 2018-11-08 |
20180323107 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF | 2018-11-08 |
20180323108 | Methods for Forming Fin Field-Effect Transistors | 2018-11-08 |
20180323109 | MINIMIZE MIDDLE-OF-LINE CONTACT LINE SHORTS | 2018-11-08 |
20180323110 | HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE | 2018-11-08 |
20180323111 | FORMING A HYBRID CHANNEL NANOSHEET SEMICONDUCTOR STRUCTURE | 2018-11-08 |
20180323112 | STRUCTURE AND FORMATION METHOD OF FIN-LIKE FIELD EFFECT TRANSISTOR | 2018-11-08 |
20180323113 | INTEGRATION SCHEME FOR GATE HEIGHT CONTROL AND VOID FREE RMG FILL | 2018-11-08 |
20180323114 | Bulk CMOS RF Switch With Reduced Parasitic Capacitance | 2018-11-08 |
20180323115 | Bulk CMOS RF Switch With Reduced Parasitic Capacitance | 2018-11-08 |
20180323116 | BOTTOM EMISSION MICROLED DISPLAY AND A REPAIR METHOD THEREOF | 2018-11-08 |
20180323117 | IN-KERF TEST STRUCTURE AND TESTING METHOD FOR A MEMORY ARRAY | 2018-11-08 |
20180323118 | Dam for Three-Dimensional Integrated Circuit | 2018-11-08 |
20180323119 | FAN-OUT SEMICONDUCTOR PACKAGE | 2018-11-08 |
20180323120 | POWER MODULE | 2018-11-08 |
20180323121 | Multi-Layer Substrate For Semiconductor Packaging | 2018-11-08 |
20180323122 | CERAMIC-ALUMINUM CONJUGATE, POWER MODULE SUBSTRATE, AND POWER MODULE | 2018-11-08 |
20180323123 | THIOUREA ORGANIC COMPOUND FOR GALLIUM ARSENIDE BASED OPTOELECTRONICS SURFACE PASSIVATION | 2018-11-08 |
20180323124 | CURABLE SILICONE RESIN COMPOSITION, SILICONE RESIN COMPOSITE, PHOTOSEMICONDUCTOR LIGHT EMITTING DEVICE, LUMINAIRE AND LIQUID CRYSTAL IMAGING DEVICE | 2018-11-08 |
20180323125 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME | 2018-11-08 |
20180323126 | PACKAGE STRUCTURE | 2018-11-08 |
20180323127 | STACKED FAN-OUT PACKAGE STRUCTURE | 2018-11-08 |
20180323128 | SEMICONDUCTOR PACKAGE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING | 2018-11-08 |
20180323129 | SEMICONDUCTOR PACKAGE HAVING ROUTABLE ENCAPSULATED CONDUCTIVE SUBSTRATE AND METHOD | 2018-11-08 |
20180323130 | ADHESIVE POLYMER THERMAL INTERFACE MATERIAL WITH SINTERED FILLERS FOR THERMAL CONDUCTIVITY IN MICRO-ELECTRONIC PACKAGING | 2018-11-08 |
20180323131 | POWER ELECTRONICS ASSEMBLIES HAVING A SEMICONDUCTOR COOLING CHIP AND AN INTEGRATED FLUID CHANNEL SYSTEM | 2018-11-08 |
20180323132 | DISTRIBUTION AND STABILIZATION OF FLUID FLOW FOR INTERLAYER CHIP COOLING | 2018-11-08 |
20180323133 | SEMICONDUCTOR DEVICES WITH BACK-SIDE COILS FOR WIRELESS SIGNAL AND POWER COUPLING | 2018-11-08 |
20180323134 | ELECTRIC CONDUCTOR TRACK, METHOD, AND USE | 2018-11-08 |
20180323135 | Method And System For Improved Matching For On-Chip Capacitors | 2018-11-08 |
20180323136 | CHIP PACKAGE WITH SIDEWALL METALLIZATION | 2018-11-08 |
20180323137 | INTEGRATED CIRCUIT (IC) PACKAGE AND PACKAGE SUBSTRATE COMPRISING STACKED VIAS | 2018-11-08 |
20180323138 | REDUNDANT THROUGH-HOLE INTERCONNECT STRUCTURES | 2018-11-08 |
20180323139 | METHOD FOR MANUFACTURING A DEVICE WITH INTEGRATED-CIRCUIT CHIP BY DIRECT DEPOSIT OF CONDUCTIVE MATERIAL | 2018-11-08 |
20180323140 | ELECTRONIC DEVICE WITH DELAMINATION RESISTANT WIRING BOARD | 2018-11-08 |
20180323141 | LOW-DISPERSION COMPONENT IN AN ELECTRONIC CHIP | 2018-11-08 |
20180323142 | Structure Of Integrated Circuitry And A Method Of Forming A Conductive Via | 2018-11-08 |
20180323143 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME | 2018-11-08 |
20180323144 | MULTI-DIE INDUCTORS WITH COUPLED THROUGH-SUBSTRATE VIA CORES | 2018-11-08 |
20180323145 | 3D INTERCONNECT MULTI-DIE INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES | 2018-11-08 |
20180323146 | MULTI-DIE INDUCTORS WITH COUPLED THROUGH-SUBSTRATE VIA CORES | 2018-11-08 |
20180323147 | 3D INTERCONNECT MULTI-DIE INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES | 2018-11-08 |
20180323148 | SEMICONDUCTOR DEVICE AND IO-CELL | 2018-11-08 |
20180323149 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 2018-11-08 |
20180323150 | Multi-Stacked Package-on-Package Structures | 2018-11-08 |
20180323151 | WET ETCH REMOVAL OF Ru SELECTIVE TO OTHER METALS | 2018-11-08 |
20180323152 | SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF | 2018-11-08 |
20180323153 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING BACKSIDE OPENINGS FOR AN ULTRA-THIN SEMICONDUCTOR DIE | 2018-11-08 |
20180323154 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF | 2018-11-08 |
20180323155 | TRENCH MOSFET DEVICE AND THE PREPARATION METHOD THEREOF | 2018-11-08 |
20180323156 | BREAKABLE SUBSTRATE FOR SEMICONDUCTOR DIE | 2018-11-08 |
20180323157 | SECURITY ARRANGEMENT FOR INTEGRATED CIRCUITS USING MICROCAPSULES IN DIELECTRIC LAYER | 2018-11-08 |
20180323158 | MAGNETIC INDUCTOR STACK INCLUDING INSULATING MATERIAL HAVING MULTIPLE THICKNESSES | 2018-11-08 |
20180323159 | MICROELECTRONIC DEVICES DESIGNED WITH HIGH FREQUENCY COMMUNICATION DEVICES INCLUDING COMPOUND SEMICONDUCTOR DEVICES INTEGRATED ON AN INTER DIE FABRIC ON PACKAGE | 2018-11-08 |
20180323160 | METHODS OF FORMING AND OPERATING SEMICONDUCTOR DEVICES INCLUDING DUMMY CHIPS | 2018-11-08 |
20180323161 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF | 2018-11-08 |
20180323162 | SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES | 2018-11-08 |
20180323163 | Protrusion Bump Pads for Bond-on-Trace Processing | 2018-11-08 |
20180323164 | SEMI-CONDUCTOR PACKAGE STRUCTURE | 2018-11-08 |
20180323165 | VERTICALLY DIE-STACKED BONDER AND METHOD USING THE SAME | 2018-11-08 |
20180323166 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME | 2018-11-08 |
20180323167 | METHODS OF OPERATING A WIRE BONDING MACHINE TO IMPROVE CLAMPING OF A SUBSTRATE, AND WIRE BONDING MACHINES | 2018-11-08 |
20180323168 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 2018-11-08 |
20180323169 | DUAL-SIDED MEMORY MODULE WITH CHANNELS ALIGNED IN OPPOSITION | 2018-11-08 |
20180323170 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF | 2018-11-08 |
20180323171 | DEFORMABLE CLOSED-LOOP MULTI-LAYERED MICROELECTRONIC DEVICE | 2018-11-08 |
20180323172 | ELIMINATING DIE SHADOW EFFECTS BY DUMMY DIE BEAMS FOR SOLDER JOINT RELIABILITY IMPROVEMENT | 2018-11-08 |
20180323173 | CONNECTION PADS FOR LOW CROSS-TALK VERTICAL WIREBONDS | 2018-11-08 |
20180323174 | FABRICATION AND USE OF THROUGH SILICON VIAS ON DOUBLE SIDED INTERCONNECT DEVICE | 2018-11-08 |
20180323175 | SEMICONDUCTOR MODULE | 2018-11-08 |
20180323176 | SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME | 2018-11-08 |
20180323177 | 3DIC Formation with Dies Bonded to Formed RDLs | 2018-11-08 |
20180323178 | STRUCTURES AND METHODS FOR ELECTRICAL CONNECTION OF MICRO-DEVICES AND SUBSTRATES | 2018-11-08 |