45th week of 2013 patent applcation highlights part 45 |
Patent application number | Title | Published |
20130295675 | METHOD FOR INSERTING GENETIC MATERIAL INTO GENOMIC DNA - The present invention provides reagents and methods for improved homologous recombination. | 2013-11-07 |
20130295676 | Method of Modifying Target Region in Host DNA and Selectable Marker Casette - A method of modifying a target region in a host DNA using a donor DNA: wherein the donor DNA having regions homologous to a 5′-side region outside of the target region in the host DNA, a 3′-side region outside of the target region in the host DNA and a first homologous recombination region inside of the target region in the host DNA, respectively, in this order, and further having a first selectable marker gene, an expression-inducing promoter and a second selectable marker gene expressed under the control of the expression-inducing promoter between the region homologous to the 3′-side region and the region homologous to the first homologous recombination region; which method has the steps of: a first step of performing homologous recombination between the donor DNA and the host DNA at the regions of the 5′-side region and the first homologous recombination region, to conduct selection of a host integrated with the donor DNA based on expression of the first selectable marker gene; and a second step of performing homologous recombination, within the host DNA integrated with the donor DNA by the first step, between two regions of the 3′-side region derived from the host DNA and the 3′-side region derived from the donor DNA, to conduct selection of a host whose target region is modified based on expression of the second selectable marker gene under an expression-inducing condition for the expression-inducing promoter; and a selectable marker cassette for use in the method. | 2013-11-07 |
20130295677 | METHOD AND APPARATUS FOR DETERMINING FORMATION FLUID COMPOSITION - In some embodiments, apparatus and systems, as well as methods, may operate to draw a formation fluid sample into a sampling port included in a down hole tool, to vaporize some part of the fluid sample to substantially fill an injection port with a gas phase, to differentiate gas components in the gas phase to provide differentiated gas components along a concentration gradient, to detect the differentiated gas components, and to determine a fingerprint of the differentiated gas components. Other apparatus, systems, and methods are disclosed. | 2013-11-07 |
20130295678 | SYSTEMS AND METHODS FOR NON-FASTING LDL CHOLESTEROL ASSAYS - In one embodiment, a test strip for testing for cholesterol-related blood analytes in whole blood includes a red blood cell separation layer, the red blood cell separation layer separating red blood cells from a blood sample applied to the test strip as the blood sample flows downward through the red blood cell separation layer. The test strip further includes a reaction layer receiving the blood sample from the red blood cell separation layer, the reaction layer including POE-POP-POE block copolymer, a surfactant, and a reflectivity changing reactant, the POE-POP-POE block copolymers solubilizing essentially only non-LDL cholesterol analytes, the non-LDL cholesterol analytes reacting with the reflectivity changing reactant in order to change a reflectivity of the blood sample. | 2013-11-07 |
20130295679 | PREDICTION OF A SMALL-FOR-GESTATIONAL AGE (SGA) INFANT - A method of predicting a SGA infant in a patient at a pre-symptomatic gestational stage is described. The method comprises a step of assaying a biological sample from the patient for an abundance of a plurality of metabolite biomarkers selected from the 19 metabolite biomarkers of Table IV, correlating the abundance of the plurality of metabolite biomarkers with a metabolite fingerprint of SGA shown in Table IV, and predicting SGA based on the level of correlation between the abundance of the plurality of metabolite biomarkers and the metabolite fingerprint of Table IV. | 2013-11-07 |
20130295680 | GAS SENSOR INCORPORATING A POROUS FRAMEWORK - The disclosure provides sensor for gas sensing including CO | 2013-11-07 |
20130295681 | DEVICE, SYSTEM AND METHOD FOR MEASURING HOMEOSTASIS, VITALITY, ENERGY AND STRESS IN AN INDIVIDUAL OR SUBSTANCE - The present invention relates to a device, system and a method for evaluating, measuring and assessing vitality, energy and stress levels in an individual and/or substance, and in particular, to such a device, system and method in which personal assessment and decision support is provided based on the measured levels of vitality, energy and stress. | 2013-11-07 |
20130295682 | METHOD OF OPERATING AN OPTOCHEMICAL SENSOR - An optochemical sensing device has source that emits radiation of a first and a second predetermined intensity, a detector, and a sensitive element that comprises a signal substance. To measure an analyte in a measurement medium, the sensitive element is contacted with the analyte. A first raw signal, which is dependent on the analyte content is obtained by exciting the signal substance with radiation of the first predetermined intensity. At a later time, a second raw signal is also obtained. A comparison of the raw signals yields a comparison value, which is compared against a predetermined limit value. If the comparison value exceeds the limit value, the radiation source is set at the first intensity. If the comparison value is smaller than the limit value, the radiation source is set at the lower second intensity. Using the lower radiation intensity prolongs the life of the sensitive element. | 2013-11-07 |
20130295683 | DEVICE AND METHOD FOR HOLDING AND ANALYZING A SAMPLE - A device for holding a sample for optical fingerprinting analysis comprises a carrier, and a distribution of non-specific interacting surfaces extending across said carrier. At least one fluidic channel allows a fluid sample to flow through at least a part of said carrier to get in touch with one or more of said non-specific interacting surfaces. One or more optical windows adjacent to said non-specific interacting surfaces enable optical analysis of results of said sample getting in touch with said non-specific interacting surfaces at multiple locations of the carrier. | 2013-11-07 |
20130295684 | CONJUGATED POLYMERS FOR USE IN HOMOGENEOUS AND SOLID STATE ASSAYS - Disclosed are multichromophores, and methods, articles and compositions employing them. Disclosed are methods, articles and compositions for the detection and analysis of biomolecules in a sample. Provided assays include those determining the presence of a target biomolecule in a sample or its relative amount, or the assays may be quantitative or semi-quantitative. The methods can be performed on a substrate or in an array format on a substrate. Disclosed are detection assays employing sensor biomolecules that do not comprise a fluorophore that can exchange energy with the cationic multichromophore. Disclosed are biological assays in which energy is transferred between one or more of the multichromophore, a label on the target biomolecule, a label on the sensor biomolecule, and/or a fluorescent dye specific for a polynucleotide, in all permutations. | 2013-11-07 |
20130295685 | MOBILITY SHIFT ASSAYS FOR DETECTING ANTI-TNF ALPHA DRUGS AND AUTOANTIBODIES - The present invention provides assays for detecting and measuring the presence or level of anti-TNFα drugs and/or the autoantibodies to anti-TNFα drugs in a sample. The present invention is useful for optimizing therapy and monitoring patients receiving anti-TNFα drug therapeutics to detect the presence or level of autoantibodies against the drug. The present invention also provides methods for selecting therapy, optimizing therapy, and/or reducing toxicity in subjects receiving anti-TNFα drugs for the treatment of TNFα-mediated disease or disorders. | 2013-11-07 |
20130295686 | INTERCALATION METHODS AND DEVICES - The invention provides devices and methods for improving labeling of nucleic acids including intercalation of nucleic acids using for example mono intercalators such as mono cyanine intercalators. | 2013-11-07 |
20130295687 | Novel Method of Isolation of TLR4 from Cell Lysates of Mononuclear Cells - A novel method of isolation of TLR4 from cell lysates of mononuclear cells is provided. The method includes: collecting bovine adult filarial parasites ( | 2013-11-07 |
20130295688 | OPTICAL ANALYTE DETECTION SYSTEMS AND METHODS OF USE - Various embodiments are drawn to systems and methods for detecting an analyte of interest in a sample including an optical sensor, a capture probe attached to a surface of the optical sensor wherein the capture probe is capable of binding to the analyte to form a duplex or complex, and an antibody capable of binding to the analyte, duplex, or complex. In several embodiments, systems and methods further include a particle attached to the antibody or capable of binding to the antibody. In several embodiments, systems and methods for analyte detection feature one or more of the following: high detection sensitivity and specificity, scalability and multiplex capacity, ability to analyze large analytes, and ability to detect or measure multiple individual binding events in real-time. | 2013-11-07 |
20130295689 | METHOD FOR DETECTION OF BASIC PEPTIDE AND REAGENT FOR DETECTION OF BASIC PEPTIDE - The present invention provides a method for detection of a basic peptide by mixing a sample suspected to contain the basic peptide and a reagent containing denatured albumin and detecting turbidness due to a complex of the basic peptide and denatured albumin. | 2013-11-07 |
20130295690 | VERSATILE DRUG TESTING DEVICE - A versatile drug testing device (a lateral flow diagnostic testing device) includes a flat transparent carrier with a top and a bottom with the carrier having a series of independent parallel grooves formed therein running from adjacent to the top to adjacent to the bottom of the carrier, each groove having a first opening and a second opening above the first opening therein adjacent to the bottom of the carrier, at least one drug test strip installed in one of said grooves with its absorbent pad contiguous to the openings and a cover layer attached to the carrier operable to sealing close each of said grooves whereby the bottom of the device can be immersed in a specimen of urine, body fluid, or other biological specimen to wet the pad of the at least one test strip though the ingress of the specimen though the associated openings and the test results on the test strip can be easily viewed through the transparent carrier. Because of the unique construction the device will give accurate reading if temporarily immersed in the specimen or left in the specimen for an extended period of time, making it very user friendly. | 2013-11-07 |
20130295691 | Method of Attaching a Ligand to a Test Strip - The invention features a method of attaching a ligand that has a free carboxyl group to a solid support by adding an amino group to the ligand to form a ligand-amino derivative, converting the ligand amino derivative to a ligand sulfhydryl derivative, attaching the ligand sulfhydryl derivative to a protein to form a ligand-linker-protein conjugate, and applying the ligand-linker-protein conjugate to the solid support. The method is particularly useful for immobilizing small molecule ligands having a free carboxyl group, such as cloxicillin, to a lateral-flow test strip, in order to make a detection zone on the test strip that exhibits a clear signal and enhanced sensitivity. | 2013-11-07 |
20130295692 | MEANS AND METHODS FOR PREDICTING DIABETES - A method for diagnosing diabetes or a predisposition for diabetes is provided, which comprises determining the amount of glyoxylate in a test sample of a subject suspected to suffer from diabetes or to have a predisposition for diabetes and comparing said amount to a references, whereby diabetes or a predisposition for diabetes is to be diagnosed. Further, the use of glyoxylate or a detection agent for glyoxylate for diagnosing diabetes or a predisposition for diabetes is provided. Moreover, a device and a kit for diagnosing diabetes or a predisposition for diabetes are also provided. | 2013-11-07 |
20130295693 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SEMICONDUCTOR DEVICE - A semiconductor device with a functional element including an upper electrode composed of an electrically conductive metal oxide and being configured to store information; an interlayer insulating film covering the functional element; a contact hole formed in the interlayer insulating film, the contact hole including a side wall surface and a bottom and exposing an upper surface of the upper electrode at the bottom; an electrically conductive barrier film covering the bottom and the side wall surface of the contact hole; and a tungsten film formed on the electrically conductive barrier film, the tungsten film filling at least part of the contact hole, wherein a layer in which silicon atoms are concentrated is formed at the interface between the tungsten film and the electrically conductive barrier film. | 2013-11-07 |
20130295694 | CIRCUIT PROTECTION DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a circuit protection device and a method of manufacturing the same. The circuit protection device includes a common mode noise filter having a plurality of sheets, each of the sheets being formed to optionally include a coil pattern, an internal electrode, a hole filled with a conductive material, and a hole filled with a magnetic material; and an electrostatic discharge (ESD) protection device having a plurality of sheets, each of the sheets being formed to optionally include an internal electrode and a hole filled with an ESD protection material. | 2013-11-07 |
20130295695 | System and Method for Rejuvenating an Imaging Sensor Degraded by Exposure to Extreme Ultraviolet or Deep Ultraviolet Light - The present invention for imaging sensor rejuvenation may include a rejuvenation illumination system configured to selectably illuminate a portion of an imaging sensor of an imaging system with illumination suitable for at least partially rejuvenating the imaging sensor degraded by exposure to at least one of extreme ultraviolet light or deep ultraviolet light; and a controller communicatively coupled to the rejuvenation illumination system and configured to direct the rejuvenation illumination system to illuminate the imaging sensor for one or more illumination cycles during a non-imaging state of the imaging sensor. | 2013-11-07 |
20130295696 | METHOD FOR TRANSFERRING A LAYER FROM A DONOR SUBSTRATE ONTO A HANDLE SUBSTRATE - The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions which are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs. | 2013-11-07 |
20130295697 | Tj TEMPERATURE CALIBRATION, MEASUREMENT AND CONTROL OF SEMICONDUCTOR DEVICES - A semiconductor device, such as a semiconductor die, is disclosed including embedded temperature sensors for scanning the junction temperature, Tj, at one or more locations of the semiconductor die while the die is operating. Once a temperature of a hot spot is detected that is above a temperature specified for the die or package containing the die, the die/package may be discarded. Alternatively, the functionality of the die may be altered in a way that reduces the temperature of the hot spots. | 2013-11-07 |
20130295698 | LITHOGRAPHIC TARGETS FOR UNIFORMITY CONTROL - A photo mask having a first set of patterns and a second set of patterns is provided in which the first set of patterns correspond to a circuit pattern to be fabricated on a wafer, and the second set of patterns have dimensions such that the second set of patterns do not contribute to the circuit pattern that is produced using a lithography process based on the first set of patterns under a first exposure condition. The critical dimension distribution of the photo mask is determined based on the second set of patterns that do not contribute to the circuit pattern produced using the lithography process based on the first set of patterns under the first exposure condition. | 2013-11-07 |
20130295699 | METHOD FOR TESTING THROUGH-SILICON-VIA (TSV) STRUCTURES - A method for testing TSV structures includes providing a wafer having a front side and a back side, the wafer further comprising a plurality of TSV structures formed therein; thinning the wafer from the back side of the wafer; forming a first under bump metallization layer on the back side of the wafer blanketly; providing a probing card to the front side of the wafer to test the TSV structures; and patterning the first UBM layer. | 2013-11-07 |
20130295700 | METHOD FOR INTEGRATED CIRCUIT DIAGNOSIS - A method provides a mechanism to examine physical properties and/or diagnose problems at a selected location of an integrated circuit. Such a method can include creating a layer of a reactive material a selected distance above and in proximity with a surface of the integrated circuit so that the reactive material can be evaluated to form chemical radicals above and in proximity to the surface of the integrated circuit. A portion of the reactive material can be excited. A portion of the surface of the integrated circuit can be removed to a selected level to evaluate an exposed electrical structure of the integrated circuit. The exposed electrical structure can be evaluated to determine a potential problem in the integrated circuit. | 2013-11-07 |
20130295701 | LIQUID CRYSTAL DISPLAY OF HORIZONTAL ELECTRONIC FIELD APPLYING TYPE AND FABRICATING METHOD THEREOF - A liquid crystal display (LCD) device of a horizontal electric field type is disclosed. The LCD device is fabricated by a three-mask process, and has gate pad, common pad and data pad electrodes, each including a upper electrode formed of a transparent conductive material. With a lift-off process, these upper electrodes are formed within contact holes. | 2013-11-07 |
20130295702 | LIQUID CRYSTAL DISPLAY DEVICE COMPRISING FIRST AND SECOND DATA LINK LINES ELECTRICALLY CONNECTED TO ODD AND EVEN DATA LINES RESPECTIVELY AND CROSSING EACH OTHER TO CONNECT EVEN AND ODD DATA PAD ELECTRODES RESPECTIVELY - A liquid crystal display device includes a gate line on a substrate including a display region and a non-display region; odd and even data lines crossing the gate line to define a pixel region in the display region; a thin film transistor connected to the gate line and one of the odd and even data lines; a pixel electrode in the pixel region and connected to the thin film transistor; first and second data link lines electrically connected to the odd and even data lines, respectively, and formed with a gate insulating layer therebetween; and first and second data pad electrodes at one ends of the first and second data link lines, respectively. | 2013-11-07 |
20130295703 | METHOD FOR MANUFACTURING MULTI-DIMENSIONAL TARGET WAVEGUIDE GRATING AND VOLUME GRATING WITH MICRO-STRUCTURE QUASI-PHASE-MATCHING - A method for manufacturing a multi-dimensional target waveguide grating and volume grating with micro-structure quasi-phase-matching. An ordinary waveguide grating is used as a seed grating, and on this basis, a two-dimensional or three-dimensional sampling structure modulated with a refractive index, that is, a sampling grating, is formed. The sampling grating comprises multiple shadow gratings, and one of the shadow gratings is selected as a target equivalent grating. A sampled grating comprises Fourier components in many orders, that is, shadow gratings, a corresponding grating wave vector is [Formula 1], and the grating profile of all the shadow gratings changes with the sampling structure [Formula 2]. In a case where a seed grating wave vector [Formula 3] and a required two-dimensional or three-dimensional grating wave vector do not match, a certain Fourier periodic structure component of the Fourier components of the sampling structure is used to compensate for the wave vector mismatch. The manufacturing method may be applied to design and manufacture a multi-dimensional target waveguide grating and volume grating for any grating profile, and may simplify the grating manufacturing process and also make possible a variety of grating-based photon devices. | 2013-11-07 |
20130295704 | GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE, AND METHOD FOR FABRICATING GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE - Provided is a group-III nitride semiconductor laser device with a laser cavity of high lasing yield, on a semipolar surface of a support base in which the c-axis of a hexagonal group-III nitride is tilted toward the m-axis. First and second fractured faces to form the laser cavity intersect with an m-n plane. The group-III nitride semiconductor laser device has a laser waveguide extending in a direction of an intersecting line between the m-n plane and the semipolar surface. In a laser structure, a first surface is opposite to a second surface. The first and second fractured faces extend from an edge of the first surface to an edge of the second surface. The fractured faces are not formed by dry etching and are different from conventionally-employed cleaved facets such as c-planes, m-planes, or a-planes. | 2013-11-07 |
20130295705 | METHOD FOR FORMING DEPOSITION FILM, AND METHOD FOR PRODUCING DISPLAY DEVICE - A masking film ( | 2013-11-07 |
20130295706 | Organic Electroluminescent Element and Manufacturing Method Thereof, and Phosphorus-Containing Organic Compound and Manufacturing Method Thereof - An organic electroluminescent element comprising an anode, a cathode and a plurality of organic compound layers sandwiched between the anode and cathode, the organic compound layers including: a hole-transporting layer made of an organic compound insoluble in alcohols; and an electron-transporting layer formed on the hole-transporting layer by a wet method, the electron-transporting layer being made of a phosphorus-containing organic compound soluble in the alcohols. | 2013-11-07 |
20130295707 | METHOD FOR THE PRODUCTION OF AN ORGANIC LIGHT EMITTING ILLUMINANT - In a method for producing an organic light emitting illuminant, a base electrode layer is formed over a substrate, an organic light emitting layer is formed over at least one portion of the base electrode layer, and a top electrode layer is formed over at least one portion of the organic light emitting layer, the layers being formed in the shape of strips. The strip-shaped formation of the layers is carried out in a coating process in an in-line vacuum coating system having stationary shadowing masks on the advancing substrate such that at least one area of the base electrode layer remains uncoated once the layers have been formed. | 2013-11-07 |
20130295708 | METHODS FOR FORMING SEMICONDUCTOR MATERIALS BY ATOMIC LAYER DEPOSITION USING HALIDE PRECURSORS - Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns. | 2013-11-07 |
20130295709 | METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION ELEMENTS - “The invention provides a photoelectric conversion element manufacturing apparatus that forms a semiconductor stack film on a substrate by using microwave plasma CVD. The apparatus includes a chamber which is a enclosed space containing a base, on which the a subject substrate for thin-film formation is mounted, a first gas supply unit which supplies plasma excitation gas to a plasma excitation region in the chamber, a pressure regulation unit which regulates pressure in the chamber, a second gas supply unit which supplies raw gas to a plasma diffusion region in the chamber, a microwave application unit which applies microwaves into the chamber, and a bias voltage application unit which selects and applies a substrate bias voltage to the substrate according to the type of gas.” | 2013-11-07 |
20130295710 | PHOTOVOLTAIC MODULES AND METHODS FOR MANUFACTURING PHOTOVOLTAIC MODULES HAVING TANDEM SEMICONDUCTOR LAYER STACKS - Methods of manufacturing photovoltaic modules are provided. One method includes providing a substrate and depositing a lower electrode above the substrate. The method also includes depositing a lower stack of microcrystalline silicon layers above the lower electrode, depositing an upper stack of amorphous silicon layers above the lower stack of microcrystalline silicon layers, and depositing an upper electrode above the upper stack of amorphous silicon layers. At least one of the lower stack and the upper stack includes an N-I-P stack of silicon layers having an n-doped silicon layer, an intrinsic silicon layer, and a p-doped silicon layer. The intrinsic silicon layer has an energy band gap that is reduced by depositing the intrinsic silicon layer at a temperature of at least 250 degrees Celsius. | 2013-11-07 |
20130295711 | SELF-POWERED INTEGRATED CIRCUIT WITH MULTI-JUNCTION PHOTOVOLTAIC CELL - A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion. | 2013-11-07 |
20130295712 | METHODS OF TEXTURING SURFACES FOR CONTROLLED REFLECTION - Novel methods for the texturing of photovoltaic cells is described, wherein texturing minimizes reflectance losses and hence increases solar cell efficiency. In one aspect, a microstamp with the mirror inverse of the optimum surface structure is described. The photovoltaic cell substrate to be etched and the microstamp are immersed in a bath and pressed together to yield the optimum surface structure. In another aspect, micro and nanoscale structures are introduced to the surface of a photovoltaic cell by wet etching and depositing nanoparticles or introducing metal induced pitting to a substrate surface. In still another aspect, remote plasma source (RPS) or reactive ion etching (RIE), is used to etch nanoscale features into a silicon-containing substrate. | 2013-11-07 |
20130295713 | Modification and Optimization of a Light Management Area - A method for manufacturing an optoelectronic device is provided. The method includes providing a substrate. Thereafter, the method includes providing a lacquer layer on the substrate. The method further includes providing light management texture in the lacquer layer. Providing light management texture in the lacquer layer includes providing a replication substrate having a negative texture and imprinting the negative texture into the lacquer layer using the replication substrate, such that the light management texture is created in the lacquer layer. Furthermore, the method includes providing a first electrode layer on the lacquer layer. The method further includes etching, prior to deposition of first electrode layer, to enable formation of less steep light management texture in the lacquer layer and subsequently less steep texture on first electrode layer by etching at least one of the textures in the production of the negative texture on the replication substrate, or the light management texture on the lacquer layer itself. | 2013-11-07 |
20130295714 | SYSTEMS AND METHODS FOR SITE CONTROLLED CRYSTALLIZATION - Systems and methods for site controlled crystallization are disclosed. According to one aspect, a method for forming a composite film is disclosed. In one example embodiment, the method includes forming a layer of amorphous material. The method also includes forming a layer of metal material on each of a plurality of selected regions of the layer of amorphous material to form a structure including the layer of metal material on the layer of amorphous material, and annealing the structure to generate metal-induced crystallization at the interface of the layer of metal material and each of the selected regions of the layer of amorphous material such that crystalline structures are formed. | 2013-11-07 |
20130295715 | METHOD FOR ETCHING MICRO-ELECTRICAL FILMS USING A LASER BEAM - A method for etching with a laser beam having a predetermined wavelength an area of a layer of a first material, said area being deposited at the surface of at least two second materials, includes: depositing a layer of a third material on the layer of the first material, the first and the third materials having a chemical affinity on application of the laser beam greater than the chemical affinity during said application between the first material and each of said at least two second materials; and applying the laser beam to an area of a free surface of the layer of third material vertically above the area of the layer of first material with a fluence of said laser beam causing the separation of said area. | 2013-11-07 |
20130295716 | VAPOR DEPOSITION DEVICE, VAPOR DEPOSITION METHOD, ORGANIC EL ELEMENT AND ORGANIC EL DISPLAY DEVICE - First and second vapor deposition particles ( | 2013-11-07 |
20130295717 | Methods Of Depositing Antimony-Comprising Phase Change Material Onto A Substrate And Methods Of Forming Phase Change Memory Circuitry - A method of depositing an antimony-comprising phase change material onto a substrate includes providing a reducing agent and vaporized Sb(OR) | 2013-11-07 |
20130295718 | THIN-FILM TRANSISTOR, METHOD OF FABRICATING THE THIN-FILM TRANSISTOR, AND DISPLAY SUBSTRATE USING THE THIN-FILM TRANSISTOR - An oxide thin-film transistor (TFT) substrate that includes: a substrate, a gate line, a data line, an oxide TFT, and a pixel electrode. An oxide layer of the oxide TFT includes a first region that has semiconductor characteristics and a channel, and a second region that is conductive and surrounds the first region. A portion of the first region is electrically connected to the pixel electrode, and the second region is electrically connected to the data line. | 2013-11-07 |
20130295719 | GRADED METAL OXIDE RESISTANCE BASED SEMICONDUCTOR MEMORY DEVICE - Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells. | 2013-11-07 |
20130295720 | METHODS FOR MANUFACTURING A CHIP PACKAGE - A method for manufacturing a chip package is provided. The method including: arranging a plurality of dies over a carrier; depositing encapsulation material over the carrier wherein the plurality of dies are covered by the encapsulation material thereby forming a structure including the encapsulation material and the plurality of dies; and removing encapsulation material thereby forming a thinned portion of the structure and a further portion of the structure including encapsulation material thicker than the thinned portion. | 2013-11-07 |
20130295721 | APPARATUS TO FABRICATE FLIP-CHIP PACKAGES AND METHOD OF FABRICATING FLIP-CHIP PACKAGES USING THE SAME - An apparatus to fabricate a flip-chip package (FCP), and a method of fabricating an FCP using the same. The method includes providing a semiconductor chip such that an active surface on which a bump is formed faces upward, picking up the semiconductor chip using a pickup transfer and rotating the semiconductor chip such that the active surface of the semiconductor chip faces downward, directly transferring the semiconductor chip from the pickup transfer to a mount transfer, and mounting the semiconductor chip on a transfer unit using the mount transfer such that the active surface faces downward. | 2013-11-07 |
20130295722 | Method of Forming an Integrated Circuit Package Including a Direct Connect Pad, A Blind Via, and a Bond Pad Electrically Coupled to the Direct Connect Pad - A method for forming an integrated circuit package is disclosed. A flex circuit is form by forming a direct connect pad on a first side of a dielectric layer. After forming the direct connect pad, an opening from a second side of the dielectric layer is formed to expose the direct connect pad. A blind via is formed within the opening in the dielectric layer. A first conductor is formed within the opening. A bond pad of a semiconductor die is electrically coupled with the direct connect pad using a second conductor, wherein the bond pad and the second conductor directly overlie the direct connect pad. | 2013-11-07 |
20130295723 | Package 3D Interconnection and Method of Making Same - A method of manufacturing an integrated circuit (IC) package is provided. The method includes mounting a fast plurality of contact members on a surface of a package member, and coupling a second plurality of contact members located on a first surface of an interposer substrate to corresponding ones of the first plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the first plurality of contact members. | 2013-11-07 |
20130295724 | Power Semiconductor Chip Package - A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad. | 2013-11-07 |
20130295725 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - The inventive concept provides semiconductor packages and methods of forming the same. The semiconductor package includes a buffer layer covering at least one sidewall of the semiconductor chip. The buffer layer is covered by a molding layer. Thus, reliability of the semiconductor package may be improved. | 2013-11-07 |
20130295726 | Integrated Memory Arrays, And Methods Of Forming Memory Arrays - Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry. | 2013-11-07 |
20130295727 | Programmable Semiconductor Interposer for Electronic Package and Method of Forming - Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated. | 2013-11-07 |
20130295728 | Semiconductor Structure and Manufacturing Method for the Same - A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type. | 2013-11-07 |
20130295729 | METHOD FOR MANUFACTURING REVERSE-BLOCKING SEMICONDUCTOR ELEMENT - In a method of manufacturing a reverse-blocking semiconductor element, a tapered groove is formed and ions are implanted into a rear surface and the tapered groove. Then, a furnace annealing process and a laser annealing process are performed to form a rear collector layer and a separation layer on the side surface of the tapered groove. In this way, it is possible to ensure a reverse breakdown voltage and reduce a leakage current when a reverse bias applied, even in a manufacturing method including a process of manufacturing a diffusion layer formed by forming a tapered groove and performing ion implantation and an annealing process for the side surface of the tapered groove as the separation layer for bending the termination of a reverse breakdown voltage pn junction to extend to the surface. | 2013-11-07 |
20130295730 | SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES - A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device. | 2013-11-07 |
20130295731 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode. | 2013-11-07 |
20130295732 | METHOD FOR MAKING FIELD EFFECT TRANSISTOR - The present invention provides a method for making a field effect transistor, comprising of the following steps: providing a silicon substrate with a first type, forming a shallow trench by photolithography and etching processes, and forming silicon dioxide shallow trench isolations inside the shallow trench; forming by deposition a high-K gate dielectric layer and a metal gate electrode layer on the substrate and the shallow trench isolations; forming a gate structure by photolithography and etching processes; forming source/drain extension regions by ion implantation of dopants of a second type; depositing an insulating layer to form sidewalls tightly adhered to the sides of the gate; forming source/drain regions and PN junction interfaces between the source/drain region and the silicon substrate by ion implantation of dopants of the second type; and performing microwave annealing to activate implanted ions. The novel process of making a field effect transistor in the present invention can achieve impurity activation in the source/drain area at a low temperature and can reduce the influence of source/drain annealing on high-K gate dielectric and metal gate electrode. | 2013-11-07 |
20130295733 | Si-Ge-Si SEMICONDUCTOR STRUCTURE HAVING DOUBLE COMPOSITIONALLY-GRADED HETERO-STRUCTURES AND METHOD FOR FORMING THE SAME - A Si—Ge—Si semiconductor structure having double compositionally-graded hetero-structures is provided, comprising: a substrate; a buffer layer or an insulation layer formed on the substrate; a strained SiGe layer formed on the buffer layer or the insulation layer, wherein a Ge content in a central portion of the strained SiGe layer is higher than the Ge content in an upper surface or in a lower surface of the strained SiGe layer, and the Ge content presents a compositionally-graded distribution from the central portion to the upper surface and to the lower surface respectively. According to the present disclosure, a compositionally-graded hetero-structure replaces an abrupt hetero-structure so as to form a triangular hole carrier potential well, so that most of hole carriers may be distributed in the strained SiGe layer with high Ge content and a reduction of the carrier mobility caused by interface scattering may be avoided, thus further improving a performance of a device. | 2013-11-07 |
20130295734 | METHOD FOR FORMING GATE, SOURCE, AND DRAIN CONTACTS ON A MOS TRANSISTOR - A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer. | 2013-11-07 |
20130295735 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A first structure and a second structure are formed on a substrate. An oxide layer is entirely formed to cover the first structure and the second structure. A nitride layer is formed to entirely cover the oxide layer. A dry etching process is performed to remove a part of the nitride layer on the first structure. A wet etching process is performed to entirely remove the nitride layer and the oxide layer on the first structure and the second structure. | 2013-11-07 |
20130295736 | FABRICATION METHOD OF TRENCH POWER SEMICONDUCTOR STRUCTURE - A fabrication method of a trench power semiconductor structure is provided. First, a substrate with a first epitaxial layer is provided. Then, a dielectric layer is formed on the first epitaxial layer. A shielding layer is formed on the dielectric layer. Next, a portion of the shielding and the dielectric layers are removed to form a shielding structure and a dielectric structure on the first epitaxial layer, wherein the shielding structure is stacked on the dielectric structure. A selective epitaxial growth technique is utilized to form a second epitaxial layer surrounding the dielectric and the shielding structures on the exposed surface of the first epitaxial layer and the second epitaxial layer. Afterward, the shielding structure is removed to form a trench on the dielectric structure. A gate oxide layer is further formed on the inner surface of the trench. Lastly, a conducting structure is formed in the trench. | 2013-11-07 |
20130295737 | Semiconductor Cells, Arrays, Devices and Systems Having a Buried Conductive Line and Methods for Forming the Same - Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device. | 2013-11-07 |
20130295738 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A fin-shaped structure is formed on a substrate. A gate structure and a cap layer are formed, wherein the gate structure is disposed across parts of the fin-shaped structure and parts of the substrate, the cap layer is on the gate structure, and the cap layer includes a first cap layer on the gate structure and a second cap layer on the first cap layer. A spacer material is formed to entirely cover the second cap layer, the fin-shaped structure and the substrate. The spacer material is etched, so that the sidewalls of the second cap layer are exposed and a spacer is formed beside the gate structure. The second cap layer is removed. | 2013-11-07 |
20130295739 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a source/drain feature is formed over a substrate. A Si-containing layer is formed over the source/drain feature. A metal layer is formed over the Si-containing layer. A metal silicide layer is formed from the metal layer and Si in the Si-containing layer. | 2013-11-07 |
20130295740 | FORMING CMOS WITH CLOSE PROXIMITY STRESSORS - A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses. | 2013-11-07 |
20130295741 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate. | 2013-11-07 |
20130295742 | METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE - A method to enhance the programmability of a prompt-shift device is provided, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. In one embodiment, no additional masks are employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer. | 2013-11-07 |
20130295743 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide. | 2013-11-07 |
20130295744 | INTERFACE CONTROL FOR IMPROVED SWITCHING IN RRAM - A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell. | 2013-11-07 |
20130295745 | METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE - A method of manufacturing a nonvolatile memory device includes: forming a tantalum oxide material layer including an oxygen-deficient transition metal oxide; forming a tantalum oxide material layer including a transition metal oxide and having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the tantalum oxide material layer; and exposing, after the forming of a tantalum oxide material layer, the tantalum oxide material layer to plasma generated from a noble gas. | 2013-11-07 |
20130295746 | COMBINATION OF A SUBSTRATE AND A WAFER - The invention pertains to a combination of a substrate and a wafer, wherein the substrate and the wafer are arranged parallel to one another and bonded together with the aid of an adhesive layer situated between the substrate and the wafer, and wherein the adhesive is chosen such that its adhesive properties are neutralized or at least diminished when a predetermined temperature is exceeded. According to the invention, the adhesive layer is only applied annularly between the substrate and the wafer in the edge region of the wafer. | 2013-11-07 |
20130295747 | ADHESIVE COMPOSITION FOR A WAFER PROCESSING FILM - The present invention relates to an adhesive composition for a wafer processing film, a wafer processing film, and a semiconductor wafer processing method. In the semiconductor wafer processing process such as a dicing process or a back grinding process, a delaminating force with respect to a wafer to be attached may be effectively reduced to improve process efficiency and prevent the wafer from being warped or cracked. | 2013-11-07 |
20130295748 | METHOD OF UNIFORM SELENIZATION AND SULFERIZATION IN A TUBE FURNACE - A method for high temperature selenization of Cu—In—Ga metal precursor films comprises ramping the precursor film to a temperature between about 350 C and about 450 C in an inert gas and at a pressure between about 1 atmosphere and about 2 atmospheres. A partial selenization is performed at a temperature between about 350 C and about 450 C in a Se-containing atmosphere. The film is then ramped to a temperature between about 450 C and about 550 C in an inert gas and at a pressure between about 1 atmosphere and about 2 atmospheres, followed by an additional selenization step at a temperature between about 450 C and about 550 C in a Se-containing atmosphere. The film is then annealed at a temperature between about 550 C and about 650 C in an inert gas. | 2013-11-07 |
20130295749 | Apparatus for vapor condensation and recovery - Methods and apparatus for recovery of precursor vapor from a gas and precursor vapor mixture used in a deposition process. The gas and precursor vapor mixture is passed through a multitude of heat transfer surfaces in a heat conducting housing causing the precursor vapor to condense. The precursor vapor in liquid form is then collected after condensation. | 2013-11-07 |
20130295750 | HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE - A method of removing a plurality of semiconductor device layers from an underlying base substrate. A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. Each successive sacrificial material layer that is formed is thicker than the previously formed sacrificial material layer. An etch is then performed that first removes the thickest sacrificial material layer of the multilayered stack. The uppermost semiconductor device layer within the multilayered stack is accordingly first released. As the etch continues, the other sacrificial material layers are removed sequentially, in the order of decreasing thickness, and the other semiconductor device layers are removed sequentially. | 2013-11-07 |
20130295751 | THIN FILM FORMING DEVICE FOR SOLAR CELL AND THIN FILM FORMING METHOD - This thin film forming method for a solar cell forms a thin film that contains a plurality of elements on the surface of an object to be processed. A raw material solution that contains the elements is dispersed in a processing space and microparticles by an electric field, and the microparticles that are dispersed form a thin film that adheres to the surface of the object to be processed. Thus, a thin film for a solar cell element with preferable crystallinity can be formed even in an atmosphere at atmospheric pressure. | 2013-11-07 |
20130295752 | METHODS FOR CHEMICAL MECHANICAL PLANARIZATION OF PATTERNED WAFERS - Methods for chemical mechanical planarization of patterned wafers are provided herein. In some embodiments, methods of processing a substrate having a first surface and a plurality of recesses disposed within the first surface may include: depositing a first material into the plurality of recesses to predominantly fill the plurality of recesses with the first material; depositing a second material different from the first material into the plurality of recesses and atop the substrate to fill the plurality of recesses and to form a layer atop the first surface; and planarizing the second material using a first slurry in a chemical mechanical polishing tool until the first surface is reached. In some embodiments, a second slurry, different than the first slurry, is used to planarize the substrate to a first level. | 2013-11-07 |
20130295753 | ION BEAM DIMENSION CONTROL FOR ION IMPLANTATION PROCESS AND APPARATUS, AND ADVANCED PROCESS CONTROL - A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate. | 2013-11-07 |
20130295754 | DOPING OF SEMICONDUCTOR SUBSTRATE THROUGH CARBONLESS PHOSPHOROUS-CONTAINING LAYER - A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant. | 2013-11-07 |
20130295755 | METHODS FOR FORMING TRENCHES - Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask. | 2013-11-07 |
20130295756 | METHODS OF FORMING CONTACTS FOR SEMICONDUCTOR DEVICES USING A LOCAL INTERCONNECT PROCESSING SCHEME - One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess. | 2013-11-07 |
20130295757 | SHORT GATE-LENGTH HIGH ELECTRON-MOBILITY TRANSISTORS WITH ASYMMETRIC RECESS AND SELF-ALIGNED OHMIC ELECTRODES - A method for fabricating InP-based high electron-mobility transistors (HEMTs) and GaAs-based metamorphic electron-mobility transistors (MHEMTs) by utilizing asymmetrically recessed Γ-gates and self-aligned ohmic electrodes is disclosed. The fabrication starts with mesa isolation, followed by gate recess and gate metal deposition, in which the gate foot is placed asymmetrically in the recess groove, with the offset towards the source. It is important to use Γ-gates as the shadow mask for ohmic metal deposition, because it allows a source-gate spacing as small as 0.1 micron, greatly reducing the critical source resistance, and it retains a relatively large gate-drain spacing, enabling a decent breakdown voltage when coupled with the asymmetric gate recess. It is also critical to maintain a large stem height of the Γ-gates to assure a sufficient gap between the top of the gates and the ohmic metal after its deposition to reduce the parasitic capacitance. The uniqueness of this technology would best fit the applications that require low voltage and/or low DC power consumption. | 2013-11-07 |
20130295758 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern. | 2013-11-07 |
20130295759 | Methods For Manufacturing Metal Gates - Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first. | 2013-11-07 |
20130295760 | INCORPORATING IMPURITIES USING A MASK - Methods of incorporating impurities into materials can be useful in non-volatile memory devices as well as other integrated circuit devices. Various embodiments provide for incorporating impurities into a material using a mask. | 2013-11-07 |
20130295761 | Three-Dimensional Semiconductor Device and Method for Fabricating the Same - Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes. | 2013-11-07 |
20130295762 | CU PILLAR BUMP WITH ELECTROLYTIC METAL SIDEWALL PROTECTION - A method of forming a bump structure includes providing a semiconductor substrate and forming an under-bump-metallurgy (UBM) layer on the semiconductor substrate. The method further includes forming a mask layer on the UBM layer, wherein the mask layer has an opening exposing a portion of the UBM layer. The method further includes forming a copper layer in the opening of the mask layer and removing a portion of the mask layer to form a space between the copper layer and the mask layer. The method further includes performing an electrolytic process to fill the space with a metal layer and removing the mask layer. | 2013-11-07 |
20130295763 | LOW TEMPERATURE THIN WAFER BACKSIDE VACUUM PROCESS WITH BACKGRINDING TAPE - Vacuum processing, such as a backside metallization (BSM) deposition, is performed on a taped wafer after a gas escape path is formed between a base film of the tape and the wafer frontside surface following backgrind. Venting provided by the gas escape path reduces formation of bubbles under the tape. The gas escape path may be provided, for example, by a selective pre-curing of tape adhesive, to breach an edge seal and place the wafer frontside surface internal to the edge seal in fluid communication with an environment external to the edge seal. With the thinned wafer supported by the pre-cured tape, BSM is then deposited while the wafer and tape are cooled, for example, via a cooled electrostatic chuck. | 2013-11-07 |
20130295764 | METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES - A method is provided that includes forming conductive or semiconductive features above a first dielectric material, depositing a second dielectric material above the conductive or semiconductive features, etching a void in the second dielectric material, wherein the etch stops on the first dielectric material, and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided | 2013-11-07 |
20130295765 | TWO-STEP SILICIDE FORMATION - One embodiment of the present invention comprises a transistor having a source/drain region within a substrate, an extension region within the substrate adjoining the source/drain region and extending toward a gate on the substrate, and a dielectric spacer against the gate wherein the dielectric spacer covers at least part of the extension region. A silicide intermix layer is formed over both the source/drain region and a portion of the extension region. A silicide contact is formed through the silicide intermix layer over the source/drain region. | 2013-11-07 |
20130295766 | THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS - A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths. | 2013-11-07 |
20130295767 | INCREASED TRANSISTOR PERFORMANCE BY IMPLEMENTING AN ADDITIONAL CLEANING PROCESS IN A STRESS LINER APPROACH - When forming sophisticated transistors on the basis of a highly stressed dielectric material formed above a transistor, the stress transfer efficiency may be increased by reducing the size of the spacer structure of the gate electrode structure prior to depositing the highly stressed material. Prior to the deposition of the highly stressed material, an additional cleaning process may be implemented in order to reduce the presence of any metal contaminants, in particular in the vicinity of the gate electrode structure, which would otherwise result in an increased fringing capacitance. | 2013-11-07 |
20130295768 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A process chamber is provided into which a substrate is carried, wherein a chlorine atom-containing metal nitride film, in which a natural oxide film is formed on a top side thereof, is formed on the substrate; a substrate support unit configured to support and heat the substrate within the process chamber; a gas supply unit configured to supply either or both of nitrogen atom-containing gas and hydrogen atom-containing gas to an inside of the process chamber; a gas exhaust unit configured to exhaust the gas from the inside of the process chamber; a plasma generation unit configured to excite the nitrogen atom-containing gas and the hydrogen atom-containing gas supplied to the inside of the process chamber; and a control unit configured to control the substrate support unit, the gas supply unit, and the plasma generation unit. | 2013-11-07 |
20130295769 | METHODS OF PATTERNING SMALL VIA PITCH DIMENSIONS - Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask. | 2013-11-07 |
20130295770 | METHODS FOR INTEGRATED CIRCUIT FABRICATION WITH PROTECTIVE COATING FOR PLANARIZATION - Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane. | 2013-11-07 |
20130295771 | METHODS AND SYSTEMS FOR POLISHING PHASE CHANGE MATERIALS - A slurry for polishing a phase change material, such as Ge—Sb—Te, or germanium-antimony-tellurium (GST), includes abrasive particles of sizes that minimize at least one of damage to (e.g., scratching of) a polished surface of phase change material, an amount of force to be applied during polishing, and a static etch rate of the phase change material, while optionally providing selectivity for the phase change material over adjacent dielectric materials. A polishing method includes applying a slurry with one or more of the above-noted properties to a phase change material, as well as bringing the polishing pad into frictional contact with the phase change material. Polishing systems are disclosed that include a plurality of sources of solids (e.g., abrasive particles) and provide for selectivity in the solids that are applied to a substrate or polishing pad. | 2013-11-07 |
20130295772 | METHOD OF FORMING PATTERNS - A method of forming patterns includes forming a photoresist film on a substrate. The photoresist film is exposed with a first dose of light to form a first area and a second area in the photoresist film. A first hole and a second hole are formed by removing the first area and the second area with a first developer. The photoresist film is re-exposed with a second dose of the light to form a third area in the photoresist film between the first hole and the second hole. A third hole is formed between the first hole and the second hole by removing the third area with a second developer. | 2013-11-07 |
20130295773 | Method for Simultaneously Forming Features of Different Depths in a Semiconductor Substrate - Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen. | 2013-11-07 |
20130295774 | PLASMA ETCHING METHOD - A plasma etching method performs a plasma etching on a substrate W by irradiating plasma containing charged particles and neutral particles to the substrate W. The method includes controlling a distribution of reaction amounts between the substrate W and the neutral particles in a surface of the substrate W by adjusting a temperature distribution in the surface of the substrate W supported by a support, and controlling a distribution of irradiation amounts of the charged particles in the surface of the substrate W by adjusting a gap between the substrate W supported by the support and an electrode provided so as to face the support. | 2013-11-07 |