45th week of 2013 patent applcation highlights part 29 |
Patent application number | Title | Published |
20130294072 | LIGHT FIXTURE WITH THERMAL MANAGEMENT PROPERTIES - A light fixture including an electronic housing and at least one optical chamber positioned on each side of the electronic housing. In some embodiments, the optical chambers are positioned a distance from the electronic housing so as to avoid creation of a thermal path between the optical chambers and the electronic housing. Each optical chamber includes a heat sink and a plurality of LEDs mounted on a PCB that is, in turn, mounted on the heat sink. A reflector is positioned over at least a portion of the PCB. In some embodiments, vents extend through the heat sink and a fin extends upwardly from the heat sink and angles at least partially over at least some of the vents. In use, air enters the optical chambers and exits the fixture through the top vents in the heat sink. The air circulates over the reflector, carrying heat from the reflectors during the process. Heat is also conducted to the air from the heat sink. The angled fins extending over the top vents provide additional surface area for contact with the air and thus facilitate additional heat transfer from the heat sink. | 2013-11-07 |
20130294073 | LIGHT-EMITTING DIODE WORK LIGHT INCLUDING ADJUSTABLE LENS - In accordance with various embodiments, there is provided a light-emitting diode work light, which includes a housing, a light source comprising a light-emitting diode, and a light focusing assembly comprising a lens and a focusing knob. The light focusing assembly is configured to adjust a focal distance of light emitted from the light source. The focusing knob is configured to adjust a distance between the light source and the lens. In accordance with certain embodiments, the light-emitting diode work light includes a plurality of lights sources and a plurality of light focusing assemblies. Each light focusing assembly includes a lens and a focusing knob, and is configured to adjust a focal distance of light emitted from a respective light source. | 2013-11-07 |
20130294074 | LAMP - A lamp having a housing for the reception of a plurality of illuminants, as well as a scattered light disc held in a frame are described, which is characterized in that the frame, designed in a closed manner, comprises a surrounding guide limb part, which can be received substantially in a form fitting manner in the housing, and an inwardly directed support limb part extending perpendicular to the guide limb part; and in that a light permeable, surrounding strip of predefinable color differing from the color of the scattered light disc, is arranged in an edge holding fixture formed by the guide limb part and the support limb part; and the scattered light disc, on whose full area lights is incident, being supported on this strip. | 2013-11-07 |
20130294075 | Lighting system and method of manufacture - A lighting system comprises a circuit board ( | 2013-11-07 |
20130294076 | Light fixture - A light fixture, such as a laminar light fixture to illuminate a workstation with an effective anti-glare feature comprising a number of LEDs as light sources, and an anti-glare grid with a number of adjacently located, anti-glare channels going through and a number of webs separating the anti-glare channels. Each anti-glare channel has a first end and a second end that is opposite to the first end. The light fixture further comprises a light-guiding panel with a number of adjacently located cup-like light-guiding elements. Each light-guiding element provides a light-guiding channel going through that has a first end and a second end that is located opposite to the first end. Further, at least one LED is located at the first end of the light-guiding channel of each light-guiding element. One light-guiding element is located in each anti-glare channel. | 2013-11-07 |
20130294077 | LIGHT ENGINE - A light engine that includes light emitting diodes mounted on a printed circuit board, which in turn is attached to a heat sink. An optic assembly is positioned over the printed circuit board to direct the emitted light as desired. The light engine can be positioned. within the ceiling within the opening of a mounting frame. In some embodiments, the light engine is retained on the mounting frame such that it can be moved clear of the mounting frame opening. | 2013-11-07 |
20130294078 | MODULAR LED ILLUMINATING DEVICE - The invention relates to a modular LED illuminating device that includes a case, multiple LED units and a power wire. The case has a front cover and a rear cover. Multiple holding holes are formed through the front cover, and a wire groove is formed on the rear cover. The multiple LED units are held by the multiple holding holes. The power wire is partially mounted in the wire groove and electrically connected to the multiple LED units. Compared with conventional fluorescent lamps, the modular LED illuminating device has long lifetime and saves more energy. | 2013-11-07 |
20130294079 | TWO-DIMENSION CONFIGURABLE LIGHTING SYSTEM WITH ENHANCED LIGHT SOURCE PLACEMENT CAPABILITIES - A lighting system having neural hubs that connect to other neural hubs in a manner that allows a lighting system to be configured in a two dimensional pattern that can propagate out from a single neural hub. Straight sections can be provided for use in connection with the neural hubs to enhance the configurability of the lighting system. | 2013-11-07 |
20130294080 | Light Effect System For Forming A Light Beam - The present invention relates to a light effect system for forming a light beam. The light effect system comprises a first light forming means adapted to form at least a part of the light beam where at least a first actuator is adapted to rotate the first light forming means around a first rotational point and around an first axis substantially parallel to the central axis of the light beam. At least a second actuator is adapted to move the first light forming means in relation to the light beam, such that first rotational point is moved in an area outside the light beam and radially in relation to the central axis of the light beam. | 2013-11-07 |
20130294081 | SECURE SYSTEM FOR ENERGY CONSUMING DEVICE - A support structure includes a groove and a channel. The grove can be defined by a wall and a lip. An energy consumption device includes a housing that supports a magnet and a first and second terminal and the magnet helps couple the energy consumption device to the support structure. The housing is positioned in the groove and the groove helps retain the housing in the support structure while the channel allows the energy consumption device to be visible. To help secure the energy consuming device, a header can be provided on both ends of the support structure so that the housing can be translated along the groove but cannot be removed from the support structure. | 2013-11-07 |
20130294082 | LIGHT BULB SHAPED LAMP AND LIGHTING APPARATUS - A light bulb shaped lamp according to the present invention includes: a hollow globe having an opening; a plurality of light-emitting modules housed in the globe, each of the light-emitting modules having a semiconductor light-emitting device that is a light source; and a stem extending from the opening of the globe to an inside of the globe, the stem supporting the light-emitting modules, in which the stem penetrates at least one of the light-emitting modules, and the light-emitting modules are spaced a predetermined distance apart along an axis of the stem. | 2013-11-07 |
20130294083 | LED Street Lamp with Improved Heat Dissipation - An LED street lamp has a lamp body, at least one LED module and a power supply. The lamp body includes at least one heat dissipating portion and a connecting portion. Each of the at least one heat dissipating portion has two main fins. The main fins are crossed to divide each of the at least one heat dissipating portion into four fan-shaped regions. Each fan-shaped region has multiple auxiliary fins and multiple ventilation channels. Each of the at least one LED module is secured to one of the at least one heat dissipating portion of the lamp body. The power supply is mounted on the connecting portion of the lamp body. With the above-mentioned structure, the LED street lamp can provide improved heat dissipation and dust does not easily accumulate in the ventilation channels. | 2013-11-07 |
20130294084 | Reflectors and Reflector Orientation Feature to Prevent Non-Qualified Trim - The luminaire includes a light emitting diode (LED) module that includes a heat sink with an outer wall defining a top cavity and a bottom cavity and a mounting flange generally positioned along the bottom of the outer wall. A LED light source is positioned within the bottom cavity and in thermal communication with the heat sink. The bottom surface of the mounting flange includes one or more alignment features or keys extending out from the bottom surface. A trim having a corresponding alignment aperture is matingly engaged by positioning all or a portion of the alignment feature into the alignment aperture to ensure proper orientation of the trim with the LED module and to provide sufficient surface area for good thermal transfer between the heat sink and the trim. | 2013-11-07 |
20130294085 | LIGHTING DEVICE AND METHOD MANUFACTURING HOLDER OF LIGHTING DEVICE - A lighting device ( | 2013-11-07 |
20130294086 | REFLECTOR AND LAMP COMPRISED THEREOF - Embodiments of a reflector and a lamp that utilizes the reflector and light-emitting diode (LED) devices to generate an optical intensity distribution substantially similar to that of a conventional incandescent light bulb. The lamp can include a heat dissipating assembly with one or more heat dissipating elements disposed annularly about the envelope and spaced apart from the envelope in order to promote convective airflow. In one embodiment, the reflector operates as a total internal reflection (TIR) lens. | 2013-11-07 |
20130294087 | LUMINAIRE WITH PRISMATIC OPTIC - A luminaire with a prismatic optic permits the nearly uniform distribution of light about the luminaire. The prismatic optic permits the use of directional light sources, such as light emitting diodes, while maintaining the uniform light distribution. Furthermore, a concave shape of the optic further enables uniform light distribution. When light emitting diodes are used, the luminaire further includes a heat sink to maintain a desirable operational temperature without negatively affecting the light distribution properties of the luminaire. | 2013-11-07 |
20130294088 | SELF-LOCKING TRIM RING AND CHANNEL FOR OPTIC LENS - A lamp comprises an optical lens. The lamp further comprises a self-locking trim ring including a plurality of teeth. The self-locking trim ring is disposed over the optical lens. The lamp further comprises a heat sink. The heat sink has an inner chamber wherein the optical lens is disposed in the inner chamber. The heat sink also has an outer chamber disposed radially outwardly from the inner chamber. The outer chamber has a recess that engages the plurality of teeth. The self-locking trim ring secures the optical lens to the heat sink. | 2013-11-07 |
20130294089 | PATTERN PROJECTION USING MICRO-LENSES - An illumination assembly includes a light source, which is configured to emit optical radiation. A transparency containing a plurality of micro-lenses, which are arranged in a non-uniform pattern and are configured to focus the optical radiation to form, at a focal plane, respective focal spots in the non-uniform pattern. Optics are configured to project the non-uniform pattern of the focal spots from the focal plane onto an object. | 2013-11-07 |
20130294090 | DOOR ASSEMBLY FOR A LIGHT FIXTURE - A door assembly for a lighting fixture. Embodiments of the door assembly include a door frame defined by two frame sides and two frame ends that define a frame opening. A diffuser panel is positioned within the door frame to span the frame opening and a refractor extends along the length of the door frame. The refractor is retained on the door assembly at its ends. More specifically, in some embodiments an aperture having the profile of the refractor is provided in the end plate on each frame end. The ends of the refractor are inserted into the apertures of the end plates to retain the refractor on the door assembly by its ends. | 2013-11-07 |
20130294091 | LAMP HOLDER ASSEMBLY HAVING A REMOVABLE SHADE UNIT - A lamp holder assembly includes a holder and a light transmissive shade unit. The holder includes a plurality of connecting slots each having a wide slot section and a narrow slot section. The shade unit is provided with a plurality of connecting rods each having a rod body and a barb-like distal end. The rod bodies of the connecting rods extend respectively and movably through the narrow hole sections, and are movable into the wide slot sections, respectively. The barb-like distal end of each of the connecting rods is sized so as to allow movement through the wide slot section of a corresponding one of the connecting slots, while preventing movement through the narrow slot section of the corresponding one of the connecting slots. | 2013-11-07 |
20130294092 | LED LAMP - A lamp has an optically transmissive enclosure and a base defining a longitudinal axis of the lamp extending from the base to the free end of the enclosure. A heat sink is at least partially located in the enclosure and includes a tower that extends along the longitudinal axis of the lamp. An LED assembly is positioned in the optically transmissive enclosure. The LED assembly comprises a lead frame circuit or a flex circuit where LEDs are attached to the circuits. The lead frame and flex circuit are formed into a three-dimensional shape and are thermally coupled to the tower. | 2013-11-07 |
20130294093 | LIGHTING APPARATUS - A lighting apparatus as disclosed herein may include a body, a light emitting unit having at least one LED provided over the body, an enclosure provided over the body to enclose the light emitting unit, and an electric module provided in the body and electrically connected to the light emitting unit. The body may include a first heat sink having a first cavity and a second heat sink having a second cavity. The first heat sink may be positioned in the second cavity such that an outer surface of the first heat sink is adjacent to an inner surface of the second heat sink. The first heat sink and the second heat sink are formed of different materials and a conductivity of the first heat sink may be different than a conductivity of the second heat sink. | 2013-11-07 |
20130294094 | LAMP - A lamp including the following elements is provided. A housing has an assembling opening and an electrical base on two ends thereof, wherein the housing has an inner wall and a portion of the inner wall adjacent to the assembling opening is an air-guiding wall. A cooling fan has a casing disposed at the assembling opening and forming an air channel, a fan wheel rotatably arranged in the air channel, and at least one partitioning board between the air-guiding wall and the air channel so as to define at least one first air-guiding opening and at least one second air-guiding opening. A light-emitting module is arranged in the housing and opposite to the fan wheel. Accordingly, the present lamp does not require forming any air inlet or air outlet on the housing, and thus provides a simplifier structure. | 2013-11-07 |
20130294095 | Thermal Management for Light Emitting Diode Fixture - A recessed light fixture includes an LED module, which includes a single LED package that is configured to generate all light emitted by the recessed light fixture. For example, the LED package can include multiple LEDs mounted to a common substrate. The LED package can be coupled to a heat sink for dissipating heat from the LEDs. The heat sink can include a core member. A reflector housing may be coupled to the heat sink and configured to receive a reflector. The reflector can have any geometry, such as a bell-shaped geometry including two radii of curvature that join together at an inflection point. An optic coupler can be coupled to the reflector housing and configured to cover electrical connections at the substrate and to guide light emitted by the LED package. | 2013-11-07 |
20130294096 | Thermal Bridge for LED Luminaires - A luminaire includes two housing halves, movable relative to each other between an open and closed configuration. The bottom housing half includes disposed therein a substrate which itself carries at least one LED which transmits light through a window in the bottom housing half. A thermal bridge made of at least one layer of anisotropic thermally conductive graphite is in thermal contact with the substrate and the top housing half when the housing is in the closed configuration, but its disengaged from either the substrate or top housing half when the housing is in the open configuration. | 2013-11-07 |
20130294097 | LAMP HEAT SINK - A lamp heat sink includes a plurality of heat dissipating fins disposed around a body and extending away from the body. The lamp heat sink further comprises a heat dissipating circumferent skirt surrounding the body and disposed between the plurality of heat dissipating fins. The lamp heat sink further comprises a plurality of channels disposed around the body, formed by the plurality of heat dissipating fins and the heat dissipating circumferent skirt. The plurality of channels each include an intake opening configured to receive cold air and an exhaust opening configured to release warm air. | 2013-11-07 |
20130294098 | Adjustable Lamp Socket Extender - Disclosed herein is a lamp socket extender, generally comprising a base section, an extendable body, and a head section. The base section connects to a light socket, such as an Edison style light socket. The head section attaches to a lamp adapter, which holds a lamp. The extendable body is capable of extending to create more or less distance between the head section and the base section. In a preferred embodiment, the extendable body is comprised of a core covering and a telescopic covering. There may be a wiring harness utilized to more easily attach and detach the wiring from the lamp to the lamp socket extender. | 2013-11-07 |
20130294099 | FLEXIBLE TUBE AND LAMP HAVING THE SAME - A flexible tube is adapted to be sleeved on a power cable, and includes a flexible tube body and at least one flexible wire. The flexible tube body is adapted to be sleeved on the power cable, is made of a plastic material, and is formed with a central hole and at least one through hole that are formed therethrough, that extend along the length thereof, and that are spaced apart from each other. The central hole is adapted to permit extension of the power cable therethrough. The flexible wire extends through and is secured within the through hole in the flexible tube body. | 2013-11-07 |
20130294100 | LIGHT DISTRIBUTION-CONTROLLING DEVICE OF VEHICLE HEADLIGHT - A light distribution-controlling device of a vehicle headlight includes headlight lamp bodies, light distribution operation switches, a front detection unit, a manual mode control unit that controls the light distribution of the headlight lamp body based on a signal outputting from the light distribution operation switch, an auto mode control unit that controls the light distribution of the headlight lamp body based on a signal output from the front detection unit, an auto mode changeover switch that switches control of the light distribution of the headlight lamp body to control by the auto mode control unit, a passing continuation-determining unit that determines whether a continuation time of an ON operation of a passing switch is more than or equal to a threshold continuation time, and an auto mode-returning unit that returns the control of the light distribution to the control by the auto mode control unit. | 2013-11-07 |
20130294101 | LIGHT MODULE - A light module comprises a light-exit section, a base light source that exhibits at least one LED with a light-emitting surface limited by an edge, a reflector open to the light-exit section for collimating light on a meridional plane, and a cylinder lens for collimating the light on a sagittal plane running perpendicular to the meridional plane. The reflector on the sagittal plane is free of curvature and is curved on the meridional plane such that a focal line is defined. The base light source is arranged such that the edge runs on the focal line, and the light-emitting surface proceeds from the focal line extending in a direction of the light-exit section so that the light radiated from the light module exhibits a basic light distribution with a “light/dark” boundary. | 2013-11-07 |
20130294102 | VEHICLE LAMP FITTING - A vehicle lamp fitting comprises a semiconductor light source and a lens adapted to radiate light from the semiconductor light source with both a main light distribution pattern and an overhead sign light distribution pattern. The lens includes a first surface of incidence adapted to form the main light distribution pattern, and a second surface of incidence adapted to form the overhead sign light distribution pattern. The second surface of incidence is located further to a side of the lens adjacent to the semiconductor light source than an imaginary first surface of incidence. | 2013-11-07 |
20130294103 | COLOR TEMPERATURE TUNABLE LED-BASED LAMP MODULE - A light mixing and folding lamp includes an LED assembly with two or more LED chips that direct light into the ingress end of a light mixing rod. The light mixing rod is positioned to pass through an aperture in a concave second reflecting element, and mixed light emerges from the egress end of the light mixing rod, where it is directed toward a first reflecting element positioned near a focal point of the second reflecting element. The first reflecting element reflects mixed light emerging from the egress end of the light mixing rod, folding the mixed light back toward a concave reflecting surface of the second reflecting element. The second reflecting element reflects light from the first reflecting element forward, where the light emerges from the lamp directed toward a subject to be illuminated. | 2013-11-07 |
20130294104 | Lighting Device - The disclosed embodiments relate to functional and decorative lighting. A transparent body ( | 2013-11-07 |
20130294105 | LIGHT ELEMENT HAVING A TARGETED INFLUENCE ON EDGE OPTICS - A light element for ambient illumination, having a light distribution plane and a main scatter plane, wherein an angle between a surface normal of the main scatter plane and a surface normal of the light distribution plane is between 10° and 80°. | 2013-11-07 |
20130294106 | LIGHT-COUPLING OPTICAL SYSTEMS AND METHODS EMPLOYING LIGHT-DIFFUSING OPTICAL FIBER - Light-coupling systems and methods that employ light-diffusing optical fiber are disclosed. The systems include a light source and a light-diffusing optical fiber optically coupled thereto. The light-diffusing optical fiber has a core, a cladding and a length. At least a portion of the core comprises randomly arranged voids configured to provide substantially spatially continuous light emission from the core and out of the cladding along at least a portion of the length. A portion of the light-diffusing optical is embedded in an index-matching layer disposed adjacent a lower surface of a transparent sheet. Light emitted by the light-diffusing optical fiber is trapped within the transparent sheet and index-matching layer by total internal reflection and is scattered out of the upper surface of the transparent sheet by at least one scattering feature thereon. | 2013-11-07 |
20130294107 | LIGHT EMITTING UNIT, DISPLAY, AND LIGHTING APPARATUS - There are provided a light emitting unit that enhances the uniformity of in-plane colors, as well as a display and a lighting apparatus that include such a light emitting unit thereon. The light emitting unit includes: a plurality of light emitting sections each having a light source and a wavelength conversion member, the wavelength conversion member converting a wavelength of light emitted from the light source; an optical component having a light incident surface in opposition to the plurality of light emitting sections; and a color unevenness prevention structure suppressing direct entering of light from the light source into the optical component. | 2013-11-07 |
20130294108 | OPTICAL FILM AND BACKLIGHT MODULE USING THE SAME - An optical film applied in a backlight module is provided. The optical film includes a basic layer, a plurality of periodically arranged reflective convex-parts and a plurality of periodically arranged collimating parts. The reflective convex-parts are disposed on the first surface of the basic layer. The reflective convex-part includes at least one reflective side surface and an incident bottom surface contacting a light guide plate. The collimating parts are disposed on the second surface of the basic layer. The reflective convex-parts are respectively corresponded to the collimating parts. In each corresponding pair of the reflective convex-part and the collimating part, a central axis of the reflective convex-part is substantially coincided with a central axis of the collimating part. In addition, a backlight module using the optical film is also provided. | 2013-11-07 |
20130294109 | SOLID STATE LIGHTING APPARATUS WITH ELECTRICAL CONNECTORS INCLUDING PORTIONS OF DRIVER CIRCUITS - A solid state lighting apparatus can include an electrical connector that is configured to releasably couple to a standardized electrical fixture having ac voltage provided thereat, where the electrical connector includes an opening that is configured to provide a recess in the electrical connector including an interior contact to provide the ac voltage in the recess when connected to the standardized electrical fixture. A protective circuit stage of a solid state lighting driver circuit can be in the recess to electrically coupled to the interior contact. An electrical wire can include a first portion that can be electrically coupled to the protective circuit stage in the recess and a second portion that is outside the recess. A solid state lighting housing can be configured to releasably couple to the second portion of the electrical wire. | 2013-11-07 |
20130294110 | ELECTROMAGNETIC ENERGY-FLUX REACTOR - Systems and methods for providing power to a load are provided. One system includes a first reactor including a first plurality of coils. A first coil of the first plurality of coils is configured to generate a first magnetic field, and a plurality of second coils of the first plurality of coils are configured to generate a plurality of second magnetic fields that vary an intensity of the first magnetic field. The system further comprises a second reactor comprising a second plurality of coils, wherein the second plurality of coils are configured to tune the first reactor to the load. The first reactor is configured to provide the power to the load, and the second reactor is configured to increase the power provided to the load by increasing an intensity of the second magnetic fields generated by the second coils and tuning the first reactor to the load. | 2013-11-07 |
20130294111 | OVERLOAD DETECTION IN A SWITCHED MODE POWER SUPPLY - A switched mode power supply includes a switching device, the switched mode power supply being operable to convert an input voltage (V | 2013-11-07 |
20130294112 | Regulating Controller for Controlled Self-Oscillating Converters Using Bipolar Junction Transistors - A power converter controller and methods for its operation are provided that can control a self-oscillating power converter that uses a Bipolar Junction Transistor (BJT) as a switch by manipulating the current flowing in a control winding. The controller is able to determine the optimum time to remove a short circuit applied to the control winding, as well as being able to determine the optimum time to pass current through the control winding. The controller can further draw power from the power converter using the control winding. The controller is capable of maintaining the midpoint voltage of the power converter in the case that the converter has more than one switch. The controller estimates the output power of the converter without requiring a connection to the secondary side of the converter transformer. The controller further controls entry and exit into a low-power mode in which converter oscillations are suppressed. | 2013-11-07 |
20130294113 | LLC RESONANT POWER CONVERTER WITH CURRENT-CIRCULATING CIRCUIT FOR ENABLING LIGHT-LOAD REGULATION - The present invention is to provide a power converter, which includes a half-bridge circuit parallel-connected to an input voltage and having two series-connected power switches, an LLC resonant circuit formed by a resonant inductor, magnetic inductance of a primary winding and a resonant capacitor, a current-circulating circuit parallel-connected to the half-bridge circuit and having two series-connected rectifiers, and a full-wave rectification circuit connected to a secondary winding for generating an output voltage across an output capacitor. The LLC resonant circuit is parallel-connected to one of the power switches, and the line between the two rectifiers is cross-connected to the line between the resonant inductor and the primary winding. Thus, since the current-circulating circuit is able to guide current through the resonant inductor into circulation in switching moment of the power switches, parasitic capacitance of the primary winding is prevented from being overcharged by the current through the resonant inductor accordingly. | 2013-11-07 |
20130294114 | Direct-Current Converter - A direct-current converter comprises: a first series circuit, which is connected in parallel with a smoothing capacitor and in which a first switching element and a second switching element are connected in series; a second series circuit, which is connected in parallel between main electrodes of the first switching element and in which a resonance capacitor, a resonance reactor and a primary winding of a transformer are connected in series; a half wave rectification smoothing circuit, which rectifies and smoothes a voltage of a secondary winding of the transformer; a control circuit configured to alternately turn on and off the first switching element and second switching element, based on art output voltage of the rectification smoothing circuit; and a third series circuit, which is connected in parallel with the second switching element and in which a boost reactor and a direct-current power supply are connected in series. | 2013-11-07 |
20130294115 | CONTROL DRIVEN SYNCHRONOUS RECTIFIER SCHEME FOR ISOLATED ACTIVE CLAMP FORWARD POWER CONVERTERS - A synchronous rectification circuit includes a transformer receiving an input voltage at a primary side and outputting an output voltage at a secondary side and a controller arranged and programmed to operate independently from the input and output voltages. The controller preferably outputs control signals to switching logic devices, the switching logic devices being arranged to output timing signals to drive individual synchronous rectifiers included in the secondary side of the transformer. The synchronous rectification circuit includes at least one logic gate which receives the control signals output from the controller and supplies clock signals to the switching logic devices, the clock signals being generated by the at least one logic gate based on the control signal and driving devices arranged to receive the timing signals from a respective one of the switching logic devices, the driving devices driving the synchronous rectifiers in accordance with the timing signals. | 2013-11-07 |
20130294116 | AUTOMATIC ADJUSTING DEVICE FOR OUTPUT POWER - An automatic adjusting device is provided, which is used for adjusting an output power of a power supply and comprises an automatic adjusting circuit. The automatic adjusting circuit includes a comparing unit and a programmable signal generating unit. The comparing unit compares a limiting level and a protection level and produces a comparison signal. The protection level limits the output power provided by the power supply. The programmable signal generating unit generates the protection level and adjusts the protection level according to the comparison signal for adjusting the output power. The programmable signal generating unit will adjust the protection level according to the limiting level. Thereby, the output power can be adjusted automatically without manual adjustment. Consequently, the cost can be reduced and the adjusting accuracy can enhanced. | 2013-11-07 |
20130294117 | METHOD AND APPARATUS FOR CONTROLLING THE MAXIMUM OUPUT POWER OF A POWER CONVERTER - An example control circuit for use in a power converter includes an input voltage sensor, a current sensor, and a drive signal generator. The input voltage sensor generates a first signal representative of an input voltage (Vin) of the power converter. The current sensor generates a second signal representative of a switch current through a power switch of the power converter. The drive signal generator generates a drive signal to control switching of the power switch in response to the first and second signals. The drive signal generator sets a switching frequency of the drive signal based on a product K×Vin×t to control a maximum output power of the power converter, where K is a fixed number and t is a time it takes the second signal to change between two values of the switch current when the power switch is in an on state. | 2013-11-07 |
20130294118 | Output Current Estimation for an Isolated Flyback Converter With Variable Switching Frequency Control and Duty Cycle Adjustment for Both PWM and PFM Modes - A fly-back power converter has a current-estimating control loop that senses the primary output current in a transformer to control the secondary output. A primary-side control circuit switches primary current through the transformer on and off. A discharge time when a secondary current through an auxiliary winding of the transformer is flowing is generated by sampling a voltage divider on an auxiliary loop for a knee-point. A normalized duty cycle is calculated by multiplying the discharge time by a current that is proportional to the switching frequency and comparing to a sawtooth signal having the switching frequency. The peak of a primary-side voltage is sensed from the primary current loop and converted to a current and multiplied by the normalized duty cycle to generate an estimated current. An error amp compares the estimated current to a reference to adjust the oscillator frequency and peak current to control primary switching. | 2013-11-07 |
20130294119 | PHOTOVOLTAIC SYSTEM AND POWER SUPPLY SYSTEM - According to one embodiment, a system includes modules to detect a node voltage and an output current of a converter, a detector to obtain an effective power value, a system condition detector to detect a power supply condition in the electric system or the operating conditions of devices included in the electric system and then output a first signal, a setting unit to switch a set value to a preset first or second value and then output the set value, a unit to calculate an angular frequency of an output voltage of the converter on the basis of an output of the detector, the value, and an output of the system condition detector, and a unit to calculate a target value of the converter. | 2013-11-07 |
20130294120 | SWITCHING CONVERTER - A switching converter in which deterioration and breakage can be suppressed is provided. A switching converter whose area can be reduced is provided. The switching converter includes a switch connected to a power supply portion; a transformer connected to the power supply portion; a first rectifying and smoothing circuit and a second rectifying and smoothing circuit each connected to at least the transformer; and a switching control circuit which is connected to the first rectifying and smoothing circuit and the second rectifying and smoothing circuit and which controls operation of the switch. The switching control circuit includes a control circuit controlling on/off of the switch and operation of a starter circuit; and the starter circuit controlling startup of the control circuit. The starter circuit includes a transistor and a resistor each including a wide-gap semiconductor. | 2013-11-07 |
20130294121 | SYSTEM AND METHOD PROVIDING OVER CURRENT AND OVER POWER PROTECTION FOR POWER CONVERTER - System and method for protecting a power converter. A system includes a threshold generator configured to generate a threshold signal, and a first comparator configured to receive the threshold signal and a first signal and to generate a comparison signal. The first signal is associated with an input current for a power converter. Additionally, the system includes a pulse-width-modulation generator configured to receive the comparison signal and generate a modulation signal in response to the comparison signal, and a switch configured to receive the modulation signal and adjust the input current for the power converter. The threshold signal is associated with a threshold magnitude as a function of time. The threshold magnitude increases with time at a first slope during a first period, and the threshold magnitude increases with time at a second slope during a second period. The first slope and the second slope are different. | 2013-11-07 |
20130294122 | POWER SUPPLY DEVICE - A power supply device includes a converter, a rectifier circuit, a voltage cycle detection circuit, and a power supply cutoff signal output unit. The converter converts an AC voltage inputted from an external power supply to a DC voltage and outputs the DC voltage. The rectifier circuit rectifies the AC voltage inputted from the external power supply and outputs a rectified waveform voltage. The voltage cycle detection circuit detects a voltage cycle in which the rectified waveform voltage reaches a predetermined threshold value and, when the voltage cycle is detected to be longer than a predetermined cycle, outputs a voltage cycle abnormality signal. The power supply cutoff signal output unit outputs a power supply cutoff signal when the voltage cycle abnormality signal is inputted. | 2013-11-07 |
20130294123 | CHARGE PUMP - A charge pump includes a timing signal generator for generating complementary first and second timing signals, and a voltage booster including a plurality of voltage boosting circuits. Each of the voltage boosting circuits includes input and output terminals, first and second capacitors each having first and second ends, and a switch module. The switch module is controllable to make or break electrical connection between the second end of the first capacitor and each of the input and output terminals and between the second end of the second capacitor and each of the input and output terminals. The first end of each of the first and second capacitors of a first one of the voltage boosting circuits receives a respective one of the first and second timing signals. | 2013-11-07 |
20130294124 | POWER CONVERSION DEVICE - Aspects of the invention include a step-up/step-down chopper unit, an inverter unit, a rectifier unit, first to third voltage detection means, and a drive control unit. Voltage regulation means of the drive control unit, in accordance with a detected voltage value detected by the voltage detection means, generates control signals for keeping the effective voltage value of a capacitor constant. In some aspects of the invention, the effective voltage value of the capacitor is controlled to be constant by the switching elements of the step-up/step-down chopper unit and inverter unit being driven by the control signals. The rectifier unit can suppress a surge voltage by causing energy stored in a inductor to be absorbed by storage elements when bidirectional switching elements are turned off. | 2013-11-07 |
20130294125 | CONTROL CIRCUIT OF POWER SUPPLY SYSTEM - Aspects of the invention provide an error amplifier that can compare a feedback voltage of an output voltage with a reference voltage to produce a resulting error signal in cooperation with a phase compensating circuit. In some aspects of the invention, an AC detecting circuit makes a decision as to whether a detected input voltage signal is that of a 100 Vac system or that of a 200 Vac system to change the gain of the error amplifier according to the result of the decision. When the voltage signal Vis is lower than the threshold voltage established beforehand, for making the transient response speed of the phase compensating circuit faster, the AC detecting circuit increases the gain of the error amplifier. When the voltage signal is higher than the threshold voltage established beforehand, for making a power factor higher, the AC detecting circuit decreases the gain of the error amplifier. | 2013-11-07 |
20130294126 | Photovoltaic Power Conditioning Units - We describe a photovoltaic (PV) panel system comprising a PV panel with multiple sub-strings of connected solar cells in combination with a power conditioning unit (microinverter). The power conditioning unit comprises a set of input power converters, one connected to each sub-string, and a common output power conversion stage, to provide power to an ac mains power supply output. Integration of the micro-inverter into the solar PV module in this way provides many advantages, including greater efficiency and reliability. Additionally, embodiments of the invention avoid the need for bypass diodes, a component with a high failure rate in PV panels, providing lower power loss and higher reliability. | 2013-11-07 |
20130294127 | SINGLE-PHASE VOLTAGE SOURCE DC-AC POWER CONVERTER AND THREE-PHASE VOLTAGE SOURCE DC-AC POWER CONVERTER - A single-phase voltage source DC-AC power converter includes (a) a single-phase voltage source DC-AC power converting circuit having a gate signal generator that detects a single-phase AC output current at an AC terminal and that generates gate signals for making values of a PWM command and the single-phase AC output current identical, and (b) target current producing means that produces the PWM command such that a DC component included in the single-phase AC output voltage at the AC terminal becomes zero. | 2013-11-07 |
20130294128 | INVERTER CIRCUIT HAVING A JUNCTION GATE FIELD-EFFECT TRANSISTOR - An example inverter circuit assembly includes at least one first transistor device and at least one second transistor device. The second transistor device comprises a silicon carbide junction gate field-effect transistor. The at least one second transistor device is an inner transistor device relative to the at least one first transistor device. | 2013-11-07 |
20130294129 | COMPOSITE MATERIAL, REACTOR-USE CORE, REACTOR, CONVERTER, AND POWER CONVERTER APPARATUS | 2013-11-07 |
20130294130 | FUEL CELL SYSTEM - A fuel cell system including: a hydrogen generator for causing a reforming reaction of a material gas to generate a hydrogen-containing fuel gas; a fuel cell configured to cause a reaction between the fuel gas generated by the hydrogen generator and an oxygen-containing oxidizing gas; a combustor configured to combust at least one of the material gas and an off fuel gas discharged from the fuel cell; a casing configured to accommodate the hydrogen generator, the fuel cell, and the combustor; a first exhaust port, formed on the casing and through which the flue gas from the combustor is discharged to an outside of the casing; a first intake port formed on the casing; suction units configured to suction air through the first intake port into the casing; and a CO detector configured to detect carbon monoxide contained in the air suctioned through the first intake port. | 2013-11-07 |
20130294131 | MAGNETIC MEMORY DEVICES AND SYSTEMS - A method of storing one or more bits of information comprising: forming a magnetic bubble; and storing a said bit of information encoded in a typology of a domain wall of said magnetic bubble. Preferably a bit is encoded using a symmetric topological state of the domain wall and a topological state including at least one winding rotation of a magnetisation vector of the domain wall. Preferably the magnetic bubble is confined in an island of magnetic material, preferably of maximum dimension less than 1 μm. | 2013-11-07 |
20130294132 | Memory Arrays - Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F | 2013-11-07 |
20130294133 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an I/O circuit configured to input/output a data signal; a plurality of internal circuits configured to transmit and receive the data signal to/from the I/O circuit; and a path provider configured to select one of a direct path to a target internal circuit or an indirect path to the target internal circuit that is longer than the direct path in response to one or more path control signals and use the selected path when the data signal is transmitted between the I/O circuit and the plurality of internal circuits. | 2013-11-07 |
20130294134 | STACKED LAYER TYPE SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A stacked layer type semiconductor device includes N memories each including at least one main via and (N−1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1. | 2013-11-07 |
20130294135 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A system includes a first circuit, a second circuit including a logic circuit, and a bus interconnecting the first and second circuits to each other so that the second circuit accesses the first circuit to perform a data transfer therebetween, wherein the first circuit includes a first sense amplifier array including a plurality of first sense amplifiers that are arranged in a first direction, each of the first sense amplifiers including first and second nodes; and a plurality of first global bit lines each extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that each of the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers. | 2013-11-07 |
20130294136 | GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS - A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation. | 2013-11-07 |
20130294137 | SEMICONDUCTOR DEVICE HAVING BIT LINE HIERARCHICALLY STRUCTURED - Disclosed herein is a semiconductor device that includes a plurality of memory cells; a local bit line coupled to the memory cells; a global bit line; and a first switch circuit coupled between the global bit line and the local bit line, the first switch circuit electrically connecting the local bit line to the global bit line when at least one of first and second control signals is in an active state, and the first switch circuit electrically disconnecting the local bit line to the global bit line when both of the first and second control signals are in an inactive state. | 2013-11-07 |
20130294138 | SHIFT REGISTER MEMORY DEVICE, SHIFT REGISTER, AND DATA STORAGE METHOD - A shift register memory device includes a shift register, program/read element, and rotating force application unit. The shift register includes plural rotors arranged along a direction with uniaxial anisotropy. Each rotor has a characteristic direction rotatable around a rotational axis extending in the direction. The program/read element can program data to the shift register by matching the characteristic direction of one of the rotors to one selected from two directions conforming to the uniaxial anisotropy and to read data by detecting the characteristic direction. The rotating force application unit can apply a rotating force to the shift register to urge the characteristic direction to rotate. The rotors are organized into plural pairs of every two adjacent rotors. Respective first and second forces urge the characteristic directions to be opposingly parallel for two rotors of the same pair and for two mutually adjacent rotors of mutually adjacent pairs. | 2013-11-07 |
20130294139 | CIRCUITS CONFIGURED TO REMAIN IN A NON-PROGRAM STATE DURING A POWER-DOWN EVENT - In a particular embodiment, an apparatus includes a one-time programmable (OTP) memory circuit configured to be responsive to a programming voltage. The OTP memory circuit includes an OTP memory array including OTP memory cells, a first power switch configured to decouple the OTP memory array from the programming voltage, and a second power switch configured to decouple a subset of the OTP memory cells from the programming voltage. | 2013-11-07 |
20130294140 | ANTI-FUSE CIRCUIT IN WHICH ANTI-FUSE CELL DATA IS MONITORED, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells and the anti-fuse array is configured to store anti-fuse program data. The data storage circuit is configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses. The first selecting circuit is configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal. | 2013-11-07 |
20130294141 | MEMORY DEVICE INCLUDING ANTIFUSE MEMORY CELL ARRAY AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE - A memory device includes a memory cell array, a column decoder, and a row decoder. The row decoder includes a first word line driver and a second word line driver. The first word line driver is configured to electrically coupled to a first set of antifuse memory cells coupled to a first word line. The second word line driver is configured to electrically coupled to a second set of antifuse memory cells coupled to a second word line. The first set of antifuse memory cells are arranged in first and third rows of the memory cell array, and the second set of antifuse memory cells are arranged in second and fourth rows of the memory cell array. The second row is arranged between the first and third rows. | 2013-11-07 |
20130294142 | METHOD FOR CONTROLLING THE BREAKDOWN OF AN ANTIFUSE MEMORY CELL - A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time. | 2013-11-07 |
20130294143 | Built-In Self Test for One-Time-Programmable Memory - An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The method also reads each memory location to verify that the memory location is unprogrammed and activates the programming circuitry for each memory location, which applies a test current to the programming circuitry. The test current is less than a threshold current needed to permanently change the state of the circuit element. The method then determines whether the programming circuitry is functioning properly. | 2013-11-07 |
20130294144 | Method for Bit-Error Rate Testing of Resistance-based RAM Cells Using a Reflected Signal - A testing method is described for performing a fast bit-error rate (BER) measurement on resistance-based RAM cells, such MTJ cells, at the wafer or chip level. Embodiments use one or more specially designed test memory cells fabricated with direct electrical connections between the two electrodes of the cell and external contact pads (or points) on the surface of the wafer (or chip). In the test setup the memory cell is connected an impedance mismatched transmission line through a probe for un-buffered, fast switching of the cell between the high and low resistance states without the need for CMOS logic to select and drive the cell. The unbalanced transmission line is used generate signal reflections from the cell that are a function of the resistance state. The reflected signal is used to detect whether the test cell has switched as expected. | 2013-11-07 |
20130294145 | SWITCHING DEVICE STRUCTURES AND METHODS - Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a second electrode. The switching device can further include a third electrode coupled to the vertical stack and configured to receive a voltage applied thereto to control a formation state of a conductive pathway in the material between the first and the second electrode, wherein the formation state of the conductive pathway is switchable between an on state and an off state. | 2013-11-07 |
20130294146 | RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A resistive memory device according to an embodiment includes a plurality of word lines extended and formed in a first direction; a global word line signal line extended substantially in the first direction, formed substantially in a layer substantially identical with the word lines, and interposed substantially between a designated number of the word lines; a plurality of bit lines extended and formed in a second direction tilted at an angle with the first direction; a plurality of normal cells connected substantially between the word line and the bit line; and a plurality of dummy cells connected substantially between the global word line signal line and the bit line. | 2013-11-07 |
20130294147 | RESISTANCE CHANGE MEMORY - A memory includes memory cells each includes a resistance change element and a diode, and each memory cell between one of row lines and one of column lines, a first decoder which selects one of the row lines as a selected row line, a second decoder which selects one of the column lines as a selected column line, a voltage pulse generating circuit which generates a voltage pulse, a voltage pulse shaping circuit which makes a rise time and a fall time of the voltage pulse longer, and a control circuit which applies the voltage pulse outputting from the voltage pulse shaping circuit to unselected column lines except the selected column line, and which applies a fixed potential to unselected row lines except the selected row line, in a data writing to a memory cell which is provided between the selected row line and the selected column line. | 2013-11-07 |
20130294148 | RESISTIVE MEMORY SENSING METHODS AND DEVICES - The present disclosure includes resistive memory sensing methods and devices. One such method includes performing a voltage based multiple pass sensing operation on a group of cells coupled to a selected conductive line of an array of resistive memory cells. The voltage based multiple pass sensing operation can include providing an indication of those cells of the group that conduct at least a threshold amount of current responsive to one of a number of different sense voltages successively applied to the selected conductive line during each of a corresponding number of the multiple passes, and for each successive pass of the multiple passes, disabling data lines corresponding to those cells determined to have conducted the threshold amount of current in association with a previous one of the multiple passes. | 2013-11-07 |
20130294149 | REDUCING POWER IN SRAM USING SUPPLY VOLTAGE CONTROL - An embodiment of the invention provides a method for decreasing power in a static random access memory (SRAM). A first voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are column addressed during a read cycle. A second voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are not column addressed during a read cycle. Because the second voltage is less than the first voltage, power in the SRAM is reduced. In this embodiment, a memory cell in the SRAM includes at least one read buffer and a latch connected between the latch sourcing and latch sinking supply lines. | 2013-11-07 |
20130294150 | METHOD AND APPARATUS FOR TESTING A RESISTIVE MEMORY ELEMENT - Methods and apparatus for testing a resistive memory element are provided. In an example, an initial test resistor in a resistance network coupled to a first input of a sense amplifier is selected, where the resistive memory element is coupled. to a second input of the sense amplifier and an output of the sense amplifier is measured. Another test resistor is selected based on the output of the sense amplifier and both the measuring the output step and the selecting another test resistor step are repeated until the output of the sense amplifier changes. A resistance of the resistive memory element is estimated based on the last test resistor selected, where the selected test resistors and the resistive memory element pass respective currents having substantially similar amplitudes and are coupled to respective access transistors having substantially similar properties. | 2013-11-07 |
20130294151 | MAGNETIC MEMORY DEVICES AND METHODS OF OPERATING THE SAME - A magnetic memory device includes: a free layer for storing information; and a reference layer disposed on a first surface of the free layer. The reference layer includes at least two magnetic domains and a magnetic domain wall between the at least two magnetic domains. The reference layer extends past both ends of the free layer. The magnetic memory device further includes a switching element connected to a second surface of the free layer. Another magnetic memory device includes: a first reference layer having a first magnetic domain wall; a second reference layer having a second magnetic domain wall; and a memory structure between the first and second reference layers. The memory structure includes: a first free layer adjacent to the first reference layer; a second free layer adjacent to the second reference layer; and a switching element between the first and second free layers. | 2013-11-07 |
20130294152 | APPARATUSES AND METHODS INCLUDING MEMORY ACCESS IN CROSS POINT MEMORY - Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described. | 2013-11-07 |
20130294153 | APPARATUSES AND METHODS INCLUDING SUPPLY CURRENT IN MEMORY - Some embodiments include apparatuses and methods having first conductive lines, second conductive lines, a memory array including memory cells, each of the memory cells coupled between one of the first conductive lines and one of the second conductive lines. At least one of such apparatuses and methods can include a module configured to cause a first current from a first current source and a second current from a second current source to flow through a selected memory cell among the memory cells during an operation of storing information in the selected memory cell. Other embodiments including additional apparatuses and methods are described. | 2013-11-07 |
20130294154 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is disclosed, which relates to a technology for a serial cell structure of a phase change memory (PCM). The semiconductor memory device includes a plurality of unit cells stacked with a plurality of layers, and a single bit line formed to have a vertical structure and shared by the plurality of unit cells. Each unit cell includes a switching element including a source region, a drain region, and a channel region, and a phase change resistor (PCR) element formed over the switching element. | 2013-11-07 |
20130294155 | PLURAL OPERATION OF MEMORY DEVICE - An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm. | 2013-11-07 |
20130294156 | MEMORY KINK CHECKING - This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell. | 2013-11-07 |
20130294157 | READING DATA FROM MULTI-LEVEL CELL MEMORY - A method at a data storage device includes determining a first hard bit of a first logical page, the first hard bit corresponding to a particular cell of the MLC memory. A second hard bit of a second logical page is sensed. The second hard bit corresponds to the particular cell. The first hard bit is used as a soft bit of the second logical page to provide reliability information during a decode operation of the second logical page. | 2013-11-07 |
20130294158 | MULTI-LEVEL CELL MEMORY DEVICES AND METHODS OF STORING DATA IN AND READING DATA FROM THE MEMORY DEVICES - A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream. | 2013-11-07 |
20130294159 | DATA PATH FOR MULTI-LEVEL CELL MEMORY, METHODS FOR STORING AND METHODS FOR UTILIZING A MEMORY ARRAY - Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array. | 2013-11-07 |
20130294160 | SEMICONDUCTOR MEMORY DEVICE USING ONLY SINGLE-CHANNEL TRANSISTOR TO APPLY VOLTAGE TO SELECTED WORD LINE - A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other. | 2013-11-07 |
20130294161 | LOW-VOLTAGE FAST-WRITE NVSRAM CELL - This invention discloses several embodiments of a low-voltage fast-write NVSRAM cells, made of either of a 2-poly floating-gate type flash cell or a 1-poly charge-trapping SONOS or MONOS flash cell with improvement by adding a Bridge circuit. This Bridge circuit is preferably inserted between each LV 6T SRAM cell and each HV Flash cell that comprises one paired complementary Flash strings. The Flash strings can be made of either 2T or 3T Flash strings. The tradeoff of using either a 2T or a 3T Flash string is subject to the gate area penalty and required design specs. One improvement for adding the Bridge circuit into the NVSRAM cell is to ensure the data writing between Flash cell and SRAM cell with the same polarity and to allow the operation down to low 1.2V Vdd. | 2013-11-07 |
20130294162 | Column Redundancy Circuitry for Non-Volatile Memory - In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns. | 2013-11-07 |
20130294163 | FLASH-BASED MEMORY SYSTEM WITH ROBUST BACKUP AND RESTART FEATURES AND REMOVABLE MODULES - A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit. | 2013-11-07 |
20130294164 | NONVOLATILE SEMICONDUCTOR MEMORY HAVING A WORD LINE BENT TOWARDS A SELECT GATE LINE SIDE - A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line. | 2013-11-07 |
20130294165 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND CONTROL METHOD THEREOF - A semiconductor memory device includes first cell strings connected to first bit lines and second cell strings connected to second bit lines corresponding to the first bit lines, respectively. Data is stored in memory cells of the first cell strings, and the second cell strings are configured as a data non-storage region. At least one memory cell of each of the second cell strings is in a programmed state. | 2013-11-07 |
20130294166 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A non-volatile memory device and a method for driving the same are disclosed. During a precharge operation, the bit line is precharged on the basis of a voltage applied to a common source line. The bit line is precharged or not precharged based on whether or not a selected memory cell is in an erased state or a program state. | 2013-11-07 |
20130294167 | Erase Inhibit For 3D Non-Volatile Memory - An erase process for a 3D stacked memory device performs a two-sided erase of NAND strings until one of more of the NAND strings passes an erase-verify test, then a one-sided erase of the remaining NAND strings is performed. The two-sided erase charges up the body of a NAND string from the source-side and drain-side ends, while the one-sided erase charges up the body of the NAND string from the drain-side end. The NAND strings associated with one bit line form a set. The switch to the one-sided erase can occur when the set meets a set erase-verify condition, such as one, all, or some specified portion of the NAND strings of the set passing the erase-verify test. The erase operation can end when no more than a specified number of NAND strings have not met the erase-verify test. As a result, erase degradation of the memory cells is reduced. | 2013-11-07 |
20130294168 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality of physical blocks. Each of the plurality of physical blocks includes a plurality of string units. Each string unit has a plurality of NAND strings that shares a plurality of word lines connected to a plurality of memory cells, respectively. The memory region is disposed to one of the plurality of physical blocks. Each of the plurality of string units configures a first logical block, and when the first logical block is failed, information of the first failed logical block is stored in a first region of the memory region. | 2013-11-07 |
20130294169 | SIMULTANEOUS MULTI-LEVEL BINARY SEARCH IN NON-VOLATILE STORAGE - Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time. A binary search may be performed. | 2013-11-07 |
20130294170 | SWITCH AND SEMICONDUCTOR DEVICE INCLUDING THE SWITCH - A device includes a first transistor coupled between first and second nodes, and including a control gate supplied with a first control signal, a second transistor coupled between the first node and a third node, and including a control gate supplied with the first control signal, a third transistor coupled between the third node and a fourth node, and including a control gate supplied with a second control signal, a fourth transistor coupled between the fourth node and a fifth node, and including a control gate supplied with the second control signal, and a fifth transistor coupled between the fifth node and the second nodes, and including a control gate supplied with the first control signal. Each of the second and fifth transistors is smaller in threshold voltage than the first transistor. | 2013-11-07 |
20130294171 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR PHYSICAL QUANTITY SENSOR DEVICE - In aspects of the invention, an auxiliary memory circuit includes a shift register wherein a plurality of flip-flops are cascade-connected and a plurality of inversion circuits that invert and output outputs of each D flip-flop. A main memory circuit includes a switch, which acts in accordance with a signal from the auxiliary memory circuit, and an EPROM connected in series to the switch and driven by a writing voltage. A variable resistance circuit includes a switch, which acts in accordance with a signal from the auxiliary memory circuit, and a resistor connected in series to the switch. With aspects of the invention, it is possible for terminals of the writing voltage and a writing voltage to be commonized. Also, it is possible to provide a low-cost semiconductor physical quantity sensor device that can carry out electrical trimming with the voltage when writing into the EPROM kept constant. | 2013-11-07 |