45th week of 2013 patent applcation highlights part 16 |
Patent application number | Title | Published |
20130292771 | METHOD AND APPARATUS FOR INTEGRATED CIRCUIT PROTECTION - In certain examples an integrated circuit protection circuit can include a circuit module, and an isolation device. The isolation device can be configured to couple a ground node of the circuit module to a power ground in an on state, and to isolate the ground node of the circuit module from the power ground in an off state, wherein the isolation module is configured to enter the off state when the IC receives a negative input voltage. | 2013-11-07 |
20130292772 | LAYOUT DESIGNS WITH VIA ROUTING STRUCTURES - An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure. | 2013-11-07 |
20130292773 | CROSS-COUPLING-BASED DESIGN USING DIFFUSION CONTACT STRUCTURES - An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a gate cut region across the first gate structure, the second gate structure, or a combination thereof; providing a first gate contact over the first gate structure; providing a second gate contact over the second gate structure; and providing a diffusion contact structure coupling the first gate contact to the second gate contact, the diffusion contact structure having vertices within the gate cut region. | 2013-11-07 |
20130292774 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING RAISED DRAIN AND SOURCE REGIONS AND CORRESPONDING SEMICONDUCTOR DEVICE - A semiconductor device having raised source and drain regions is formed by forming a gate electrode structure on a semiconductor substrate, forming a first spacer structure laterally to the gate electrode structure, forming a semiconductor layer over an exposed surface of the semiconductor substrate at both sides of the gate electrode structure such that a layer portion is formed which is beveled towards the gate electrode with regard to the exposed surface of the semiconductor substrate, and forming a second spacer structure over the first spacer structure, wherein the second spacer structure covers at least a portion of the beveled layer portion. | 2013-11-07 |
20130292775 | STRAINED SILICON STRUCTURE - A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance. | 2013-11-07 |
20130292776 | SEMICONDUCTOR DEVICE EMPLOYING FIN-TYPE GATE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises an active region having an upper portion and a sidewall portion which are protruded from the top surface of a device isolation region, and a silicide film disposed in the upper portion and the sidewall portion of the active region, thereby effectively reducing resistance in a source/drain region of the semiconductor device. As a result, the entire resistance of the semiconductor device comprising a fin-type gate can be reduced to improve characteristics of the semiconductor device. | 2013-11-07 |
20130292777 | Structure for FinFETs - An SRAM array is formed by a plurality of FinFETs formed by fin lines. Each fin line is formed in a substrate, wherein a bottom portion of the fin line is enclosed by an isolation region and an upper portion of the fin line protrudes above a top surface of the isolation region. From a first cross sectional view of the SRAM array, each fin line is of a rectangular shape. From a second cross sectional view of the SRAM array, the terminals of each fin line is of a tapered shape. | 2013-11-07 |
20130292778 | Techniques for the Fabrication of Thick Gate Dielectric - A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided. | 2013-11-07 |
20130292779 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCTION PROCESS - A semiconductor device includes a first p-channel FET, the first p-channel FET includes: a first fin-type semiconductor region; a first gate electrode crossing the first fin-type semiconductor region and defining a first p-channel region at an intersection of the first fin-type semiconductor region and the first gate electrode; p-type first source/drain regions, each formed on either side of the first gate electrode in the first fin-type semiconductor region; and first and second compressive stress generating regions formed by oxidizing regions located outside the p-type first source/drain regions in the first fin-type semiconductor region. | 2013-11-07 |
20130292780 | INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIENTATION TECHNOLOGY (HOT) USING DIRECT SILICON BONDED (DSB) SUBSTRATES - Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed. | 2013-11-07 |
20130292781 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a gate structure disposed on a substrate. At least one lightly doped region adjoins the gate structure in the substrate. The at least one lightly doped region has a first conductivity type. A source feature and a drain feature are on opposite sides of the gate structure in the substrate. The source feature and the drain feature have the first conductivity type. The source feature is in the at least one lightly doped region. A buck pick-up region adjoins the source feature in the at least one lightly doped region. The buck pick-up region has a second conductivity type. | 2013-11-07 |
20130292782 | MEMORY DEVICE HAVING A DIELECTRIC CONTAINING DYSPROSIUM DOPED HAFNIUM OXIDE - The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition, to form a dielectric layer of hafnium oxide doped with dysprosium and a method of fabricating such a combination produces a reliable structure for use in a variety of electronic devices. The dielectric structure can include hafnium oxide on a substrate surface followed by dysprosium oxide, and repeating to form a thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices. | 2013-11-07 |
20130292783 | MEMS ELEMENT AND METHOD FOR MANUFACTURING SAME - An acceleration sensor is formed using an etched layer sandwiched between first and second substrates. In this case, a structure including a movable portion which is displaceable in the thickness direction of the substrates, and a support frame are formed in the etched layer. In addition, first and second fixed electrodes are formed on the first and second substrates, respectively, at a position facing the movable portion. Further, a remaining sacrificial layer is provided on the substrate by leaving a portion of a second sacrificial layer when a first sacrificial layer is entirely etched away. Therefore, when the first sacrificial layer is etched away, corrosion of the structure and the support beams is prevented because the second sacrificial layer is preferentially corroded as compared to the structure. | 2013-11-07 |
20130292784 | Magnetic Memory Element with Multi-Domain Storage Layer - An apparatus and method for enhancing data writing and retention to a magnetic memory element, such as in a non-volatile data storage array. In accordance with various embodiments, a programmable memory element has a reference layer and a storage layer. The reference layer is provided with a fixed magnetic orientation. The storage layer is programmed to have a first region with a magnetic orientation antiparallel to said fixed magnetic orientation, and a second region with a magnetic orientation parallel to said fixed magnetic orientation. A thermal assist layer may be incorporated into the memory element to enhance localized heating of the storage layer to aid in the transition of the first region from parallel to antiparallel magnetic orientation during a write operation. | 2013-11-07 |
20130292785 | PERPENDICULAR MAGNETIC RANDOM ACCESS MEMORY (MRAM) DEVICE WITH A STABLE REFERENCE CELL - A magnetic random access memory (MRAM) element is configured to store a state when electric current flows therethrough. The MRAM element includes a first magnetic tunnel junction (MTJ) for storing a data bit and a reference bit MTJ for storing a reference bit. The data bit MTJ and reference bit MTJ are preferred to be of identical structure that includes a magnetic free layer (FL) having a switchable magnetization with a direction that is perpendicular to a film plane. The direction of magnetization of the FL is determinative of the data bit stored in the at least one MTJ. The identical structure further includes a magnetic reference layer (RL) having a magnetization with a direction that is perpendicular to the film plane, and a magnetic pinned layer (PL) having a magnetization with a direction that is perpendicular to the film plane. The direction of magnetization of the RL and the PL are anti-parallel relative to each other in the data bit MTJ for storing data bit, wherein when electric current is applied to the first MTJ, the magnetization orientation of the FL switches during a write operation, whereas, the direction of magnetization the RL and the PL remain the same. The direction of magnetization of the FL, the RL and the PL are parallel relative to each other in the reference bit MTJ for storing reference bit, the magnetization orientation of the FL does not switch under normal read operations. | 2013-11-07 |
20130292786 | INTEGRATED OPTICAL SENSOR MODULE - An integrated optical sensor module includes an optical sensor die having an optical sensing area on its first surface, and an application-specific integrated circuit (ASIC) die arranged over the first surface of the optical sensor die. A hole in the ASIC die is at least partially aligned with the optical sensing area such that at least some of the light passing through the hole may contact the optical sensing area. The hole through the ASIC die can be configured to receive an optical fiber, lens structure, or other optical element therein. | 2013-11-07 |
20130292787 | LOW COST BACKSIDE ILLUMINATED CMOS IMAGE SENSOR PACKAGE WITH HIGH INTEGRATION - This invention discloses a backside illuminated image sensor without the need to involve a mechanical grinding process or a chemical-mechanical planarization process in fabrication, and a fabricating method thereof. In one embodiment, an image sensor comprises a semiconductor substrate, a plurality of light sensing elements in the semiconductor substrate, and a cavity formed in the semiconductor substrate. The light sensing elements are arranged in a substantially planar manner. The cavity has a base surface overlying the light sensing elements. The presence of the cavity allows the image to reach the light sensing elements through the cavity base surface. The cavity can be fabricated by etching the semiconductor substrate. Agitation may also be used when carrying out the etching. | 2013-11-07 |
20130292788 | Self-aligned Semiconductor Ridges in Metallic Slits as a Platform for Planar Tunable Nanoscale Resonant Photodetectors - A photodetector having a ridge-in-slit geometry is provided, where a semiconductor ridge is laterally sandwiched in a metallic slit. This assembly is disposed on a layer of semiconducting material, which in turn is disposed on an insulating substrate. These structures can provide efficient resonant detectors having the wavelength of peak response set by the ridge width. Thus a lateral feature defines the wavelength of peak responsivity, as opposed to a vertical feature. | 2013-11-07 |
20130292789 | Optically Transitioning Thermal Detector Structures - A thermal absorption structure of a radiation thermal detector element may include an optically transitioning material configured such that optical conductivity of the thermal absorption structure is temperature sensitive and such that the detector element absorbs radiation less efficiently as its temperature increases, thus reducing its ultimate maximum temperature. | 2013-11-07 |
20130292790 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor layer and a Schottky electrode, a Schottky junction being formed between the semiconductor layer and the Schottky electrode. The Schottky electrode includes a metal part containing a metal, a Schottky junction being formed between the semiconductor layer and the metal part; and a nitride part around the metal part, the nitride part containing a nitride of the metal, and a Schottky junction being formed between the semiconductor layer and the nitride part. | 2013-11-07 |
20130292791 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - In order to prevent formation of voids in STI film, after a second buried insulating layer is filled and planarized, a high density cap is formed embedded in the center region of the second buried insulating layer of the STI trench. The high density cap shields and protects the weaker center region of the second buried insulating layer of the STI trench from the subsequent processing steps and prevents formation of voids in the second buried insulating layer. | 2013-11-07 |
20130292792 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes active regions separated by a trench, a separation layer dividing the trench, and buried bit lines buried in the trench with the separation layer interposed between the buried bit lines. | 2013-11-07 |
20130292793 | LOCALIZED STRAIN RELIEF FOR AN INTEGRATED CIRCUIT - An integrated circuit may include a semiconductor die having a trench formed in a surface of the semiconductor die. One or more circuit components may be formed on the surface of the semiconductor die. The trench can extend into the semiconductor die next to at least one circuit component. The trench may surround the circuit component partially or wholly. The trench may be filled with a material having a lower bulk modulus than the semiconductor die in which the trench is formed. | 2013-11-07 |
20130292794 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING - A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces. | 2013-11-07 |
20130292795 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first conductive layer on the substrate and including a main pattern, and substantially symmetrical auxiliary patterns extending from two sides of the main pattern, an insulating layer on the substrate and the first conductive layer, and a second conductive layer on the insulating layer and overlapping at least a portion of the main pattern and the auxiliary patterns. | 2013-11-07 |
20130292796 | SEMICONDUCTOR DEVICES INCLUDING CAPACITOR SUPPORT PADS - A semiconductor device may include a semiconductor substrate and a plurality of first capacitor electrodes arranged in a plurality of parallel lines on the semiconductor substrate with each of the first capacitor electrodes extending away from the semiconductor substrate. A plurality of capacitor support pads may be provided with each capacitor support pad being connected to first capacitor electrodes of at least two adjacent parallel lines of the first capacitor electrodes and with adjacent capacitor support pads being spaced apart. A dielectric layer may be provided on each of the first capacitor electrodes, and a second capacitor electrode may be provided on the dielectric layer so that the dielectric layer is between the second capacitor electrode and each of the first capacitor electrodes. Related methods are also discussed. | 2013-11-07 |
20130292797 | FULLY ENCAPSULATED CONDUCTIVE LINES - Fully encapsulated conductive lines are generally described. For example, a first dielectric layer is formed on a substrate. Copper wiring is disposed below a top surface of the first dielectric layer. A barrier metal layer is formed over the copper wiring, the barrier metal layer flush with the top surface of the first dielectric layer, and a second dielectric layer is formed on the barrier metal layer and the top surface of the first dielectric layer. Other embodiments are also disclosed and claimed. | 2013-11-07 |
20130292798 | DUAL CONTACT TRENCH RESISTOR AND CAPACITOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE - A resistor and capacitor are provided in respective shallow trench isolation structures. The method includes forming a first and second trench in a substrate and forming a first insulator layer within the first and second trench. The method includes forming a first electrode material within the first and second trench, on the first insulator layer, and forming a second insulator layer within the first and second trench and on the first electrode material. The method includes forming a second electrode material within the first and second trench, on the second insulator layer. The second electrode material pinches off the second trench. The method includes removing a portion of the second electrode material and the second insulator layer at a bottom portion of the first trench, and filling in the first trench with additional second electrode material. The additional second electrode material is in electrical contact with the first electrode material. | 2013-11-07 |
20130292799 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer. | 2013-11-07 |
20130292800 | PROCESSES FOR PREPARING COPPER INDIUM GALLIUM SULFIDE/SELENIDE FILMS - This invention relates to processes for preparing films of copper indium gallium sulfide/selenides (CIGS/Se) on substrates via inks comprising CIGS/Se microparticles and a plurality of particles. This invention relates to inks, coated layers, and film compositions. Such films are useful in the preparation of photovoltaic devices. This invention also relates to processes for preparing coated substrates and for making photovoltaic devices. | 2013-11-07 |
20130292801 | HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE - A semiconductor structure is provided that includes a base substrate, and a multilayered stack located on the base substrate. The multilayered stack includes, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness. | 2013-11-07 |
20130292802 | NITRIDE CRYSTAL, NITRIDE CRYSTAL SUBSTRATE, EPILAYER-CONTAINING NITRIDE CRYSTAL SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d | 2013-11-07 |
20130292803 | CHIP STRUCTURE AND WAFER STRUCTURE - A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate. | 2013-11-07 |
20130292804 | Semiconductor Device and Method of Forming a Shielding Layer over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded Through the Die TSV - A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die. | 2013-11-07 |
20130292805 | METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure. | 2013-11-07 |
20130292806 | Methods For Manganese Nitride Integration - Described are methods of forming a semiconductor device. Certain methods comprises depositing a film comprising manganese nitride over a dielectric; depositing a copper seed layer over the film; and depositing a copper fill layer over the copper seed layer. Also described are semiconductor devices. Certain semiconductor devices comprise a low-k dielectric layer; a manganese nitride layer overlying the low-k dielectric layer; a seed layer selected from a copper seed layer or electrochemical deposition seed layer overlying the manganese nitride layer; a copper layer overlying the copper seed layer. | 2013-11-07 |
20130292807 | Semiconductor Device Dielectric Interface Layer - Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break. | 2013-11-07 |
20130292808 | SEMICONDUCTOR PACKAGE INTEGRATED WITH CONFORMAL SHIELD AND ANTENNA - A semiconductor package includes a substrate, a semiconductor die, a package body, an electromagnetic interference shield, a dielectric structure and an antenna element. The substrate comprises a grounding segment and a feeding point. The semiconductor die is disposed on the substrate. The package body encapsulates the semiconductor die. The electromagnetic interference shield is formed on the package body. The dielectric structure encapsulates the electromagnetic interference shield. The antenna element is formed on the dielectric structure and electrically connecting the grounding segment of the substrate and the feeding point. | 2013-11-07 |
20130292809 | SEMICONDUCTOR PACKAGE - A semiconductor package including an antenna formed integrally therewith. The semiconductor package includes: a semiconductor chip; a sealing part sealing the semiconductor chip; a substrate part formed on at least one surface of the sealing part; and an antenna part formed on the sealing part and electrically connected to the semiconductor chip. | 2013-11-07 |
20130292810 | REDISTRIBUTION ELEMENTS AND SEMICONDUCTOR DEVICE PACKAGES INCLUDING SEMICONDUCTOR DEVICES AND REDISTRIBUTION ELEMENTS - A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane. | 2013-11-07 |
20130292811 | LEADFRAME HAVING SELECTIVE PLANISHING - A metal leadframe strip ( | 2013-11-07 |
20130292812 | LEAD FRAME FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE USING THE LEAD FRAME - A lead frame for a semiconductor device and a semiconductor device package using the lead frame. The lead frame includes a package body having an internal space configured to mount a semiconductor device, and a lead unit disposed so as to apply voltages to the semiconductor device. The lead unit includes internal leads embedded in the package body and having an area in which the semiconductor device is to be mounted, and external leads each being connected to the internal leads, respectively . Each external lead protrudes from the package body and each has a contact portion that contacts a printed circuit board (PCB). The lead frame also includes and a support structure disposed on external sides of the package body and supporting the external leads. | 2013-11-07 |
20130292813 | MULTI-CHIP FLIP CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A multi-chip flip chip package includes multiple dies. Each die comprises several pads for coupling with pads of the other die and for coupling with pins of the multi-chip flip chip package through conducting elements. A dielectric element is positioned between the dies and the conducting elements, and positioned between the dies for providing the electrical insulation. The dies and the conducting elements between the dies are coated with a packaging element for preventing physical damage and corrosion. | 2013-11-07 |
20130292814 | INTEGRATED POWER CONVERTER PACKAGE WITH DIE STACKING - An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry. | 2013-11-07 |
20130292815 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire. | 2013-11-07 |
20130292816 | CLAD MATERIAL FOR INSULATING SUBSTRATES - A clad material | 2013-11-07 |
20130292817 | STRUCTURE AND METHOD FOR MONITORING STRESS INDUCED FAILURES IN INTERLEVEL DIELECTRIC LAYERS OF SOLDER BUMP INTEGRATED CIRCUITS - A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density. | 2013-11-07 |
20130292818 | SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE HAVING THE SAME, AND STACKED SEMICONDUCTOR PACKAGE USING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip having a front surface and a back surface; through electrode formed in the semiconductor chip to pass through the front surface and the back surface and having a first end which is disposed on the front surface and a second end which is disposed on the back surface; and back-side bump formed over the second end of the through electrode and including an embedded pattern which is formed over a portion of the second end of the through electrode and a conductive pattern which is formed over the embedded pattern and a remaining portion of the second end of the through is electrode and having a convex sectional shape. | 2013-11-07 |
20130292819 | CHIP-ON-FILM DEVICE - A chip-on-film device including a flexible circuit film having a wire, a passivation layer having a hole, an adhesive layer, a pad, an interconnection, and a bump is provided. A part of the adhesive layer is disposed in the hole. The pad is disposed under the passivation layer, and a part of the pad is disposed under the hole. A part of the interconnection is disposed under the passivation layer, and disposed at a side of the pad, wherein the interconnection does not touch the pad. A part of the bump is disposed on the adhesive layer. The bump is electrically connected to the pad via the adhesive layer. The bump is welded on the wire. A part of a first part of the bump overlaps the pad, and a second part of the bump extends to an outside of the pad and at least partially overlaps the interconnection. | 2013-11-07 |
20130292820 | ELECTRONIC DEVICE PACKAGES INCLUDING BUMP BUFFER SPRING PADS AND METHODS OF MANUFACTURING THE SAME - Electronic device packages and related methods are provided. The electronic device package includes a first substrate having a first contact portion disposed thereon, a bump having a first contact surface connected to the first contact portion and a second contact surface disposed opposite to the first contact surface, and a buffer spring pad portion between the first contact portion of the first substrate and the first contact surface of the bump. The buffer spring pad portion includes at least two different conductive material layers which are stacked. | 2013-11-07 |
20130292821 | CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SAME - A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a plurality of first pads and second pads. The pad area is defined with a first area, a second area and a third area, wherein the first area is located between the second area and the third area. Each of the first pads and the second pads are interlaced to each other on the first area. The conductive structure comprises a plurality of conductive bumps formed on each of the first pads and the second pads respectively to electrically connect with each of the first pads and the second pads. Each of the conductive bumps has a first bump-width disposed on the first area and a second bump-width disposed on one of the second and third areas in which the first bump-width is shorter than the second bump-width. | 2013-11-07 |
20130292822 | BUMP STRUCTURE, SEMICONDUCTOR PACKAGE HAVING THE BUMP STRUCTURE, AND METHOD OF FORMING THE BUMP STRUCTURE - A bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of a substrate. The first bump includes a lower portion having a first width, a middle portion having a second width smaller than the first width, and an upper portion having a third width greater than the second width. The second bump is disposed on the upper portion of the first bump. | 2013-11-07 |
20130292823 | STACK OF SEMICONDUCTOR STRUCTURES AND CORRESPONDING MANUFACTURING METHOD - A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar. | 2013-11-07 |
20130292824 | CONNECTION OF A CHIP PROVIDED WITH THROUGH VIAS - A chip provided with through vias wherein the vias are formed of an opening with insulated walls coated with a conductive material and filled with an easily deformable insulating material, elements of connection to another chip being arranged in front of the easily deformable insulating material. | 2013-11-07 |
20130292825 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure located in the dielectric layer and electrically connected to the device region, wherein the conducting pad structure comprises a stacked structure of a plurality of conducting pad layers; a support layer disposed on a top surface of the conducting pad structure; and a protection layer disposed on the second surface of the semiconductor substrate. | 2013-11-07 |
20130292826 | METHOD OF MAKING SEMICONDUCTOR ASSEMBLY WITH BUILT-IN STIFFENER AND SEMICONDUCTOR ASSEMBLY MANUFACTURED THEREBY - The present invention relates to a method of making a semiconductor assembly. In accordance with a preferred embodiment, the method includes: preparing a dielectric layer and a supporting board including a stiffener, a bump/flange sacrificial carrier and an adhesive, wherein the adhesive bonds the stiffener to the sacrificial carrier and the dielectric layer covers the supporting board; then removing the bump and a portion of the flange to form a cavity and expose the dielectric layer; then mounting a semiconductor device into the cavity; and then forming a build-up circuitry that includes a first conductive via in direct contact with the semiconductor device and provides signal routing for the semiconductor device. Accordingly, the direct electrical connection between the semiconductor device and the build-up circuitry is advantageous to high I/O and high performance, and the stiffener can provide adequate mechanical support for the build-up circuitry and the semiconductor device. | 2013-11-07 |
20130292827 | Pillar Structure having a Non-Planar Surface for Semiconductor Devices - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 2013-11-07 |
20130292828 | STACKED SEMICONDUCTOR PACKAGES - An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound. | 2013-11-07 |
20130292829 | Semiconductor Package with Embedded Die - A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration. | 2013-11-07 |
20130292830 | Interposer Having a Defined Through Via Pattern - A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone. | 2013-11-07 |
20130292831 | Methods and Apparatus for Package on Package Devices - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package. | 2013-11-07 |
20130292832 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a first insulating layer; a plurality of first conductive elements disposed in the first insulating layer; a first circuit layer formed on the first insulating layer; a semiconductor chip disposed on the first insulating layer; and an encapsulant formed on the first insulating layer and encapsulating the semiconductor chip. The first conductive elements that are bonding wires have a small diameter and thus occupy desired limited space on the first insulating layer. Therefore, more space is available for the first circuit layer. | 2013-11-07 |
20130292833 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a lower semiconductor package including at least one lower semiconductor chip, at least one upper semiconductor package mounted on the lower semiconductor package to include at least one upper semiconductor chip, a molding layer provided between the lower and upper semiconductor packages, and connection solder balls provided in the molding layer to electrically connect the lower and upper semiconductor packages to each other. Each of the connection solder balls may include a portion protruding upward from the molding layer, and there may be no gap between the connection solder balls and the molding layer. | 2013-11-07 |
20130292834 | MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE - First and second bond elements, e.g., wire bonds, electrically connect a chip contact with one or more substrate contacts of a substrate, and can be arranged so that the second bond element is joined to the first bond element at each end and so that the second bond element does not touch the chip contact or one or more substrate contacts. A third bond element can be joined to ends of the first and second bond elements. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact. | 2013-11-07 |
20130292835 | CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERS - Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density. | 2013-11-07 |
20130292836 | VIA-FREE INTERCONNECT STRUCTURE WITH SELF-ALIGNED METAL LINE INTERCONNECTIONS - The present disclosure provides a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer. | 2013-11-07 |
20130292837 | PASSIVATION FOR WAFER LEVEL - CHIP-SCALE PACKAGE DEVICES - Aspects of the disclosure are directed towards an efficient wafer level chip-scale package, and methods or producing the packages. Various aspects are directed to protecting against humidity, contamination, mechanical damage, and current leakage while maintaining isolation and manufacturability of the plastic package and a ratio of active die size to package size. | 2013-11-07 |
20130292838 | PACKAGE-ON-PACKAGE INTERCONNECT STIFFENER - Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package. | 2013-11-07 |
20130292839 | POROUS SILICON MATERIAL - Provided are a method for producing a porous silicon material filled with a metal, the method including the steps of rendering hydrophobic a porous silicon substrate having pores from 1 to 5 nm in diameter, and depositing a metal into the pores of the porous silicon substrate by the electrodeposition of the porous silicon substrate; a method for producing a metallic nanoparticle or a nanofiber, the method including the steps of producing a porous silicon material filled with a metal, dissolving the silicon contained in the porous silicon material filled with a metal; a metallic nanoparticle or a nanofiber obtained by using the method for producing a metallic nanoparticle or a nanofiber: and a porous silicon material formed from a porous silicon substrate having pores from 1 to 5 nm in diameter and a resistivity of 5 to 20 Ω·cm, the pores of which are filled with a metal. | 2013-11-07 |
20130292840 | STACKED MEMORY ALLOWING VARIANCE IN DEVICE INTERCONNECTS - A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack. | 2013-11-07 |
20130292841 | SEMICONDUCTOR INTERCONNECT STRUCTURE - The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer. | 2013-11-07 |
20130292842 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package includes a plurality of semiconductor chips each including a substrate having one surface, the other surface which faces away from the one surface and side surfaces which connect the one surface and the other surface, through-silicon vias which pass through the one surface and the other surface of the substrate, repair pads which are exposed on the side surfaces of the substrate, and wiring lines which electrically connect the through-silicon vias with the repair pads, the plurality of semiconductor chips being stacked such that through-silicon vias of the semiconductor chips are connected with one another; and interconnections electrically connecting the repair pads of the semiconductor chips. | 2013-11-07 |
20130292843 | SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a substrate having one surface and an other surface which substantially faces away from the one surface; at least two alignment bumps formed on the one surface of the substrate and having different diameters; and at least two alignment grooves defined on the other surface of the substrate and having different diameters. | 2013-11-07 |
20130292844 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first interposer; first and second semiconductor chips horizontally mounted over the first interposer and electrically connected with the first interposer; and a second interposer disposed over the first and second semiconductor chips and electrically connected with the first and second semiconductor chips, wherein the first semiconductor chip includes a plurality of first through electrodes, and the second semiconductor chip includes a plurality of second through electrodes, and wherein the first through electrodes of the first semiconductor chip and the second through electrodes of the second semiconductor chip are electrically connected with each other through the first and second interposers. | 2013-11-07 |
20130292845 | STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip. | 2013-11-07 |
20130292846 | SEMICONDUCTOR PACKAGE - Provided is a semiconductor package including a first semiconductor chip and a second semiconductor chip respectively disposed at a bottom and at a top so that active surfaces thereof face each other. Further includes is a first molding member for sealing the first semiconductor chip and exposing the active surface of the first semiconductor chip through a top surface, a first rewiring formed on the top surface of the first molding member and the active surface of the first semiconductor chip, a second rewiring formed on a bottom surface of the first molding member, a through-via for penetrating through the first molding member and electrically connecting the first and second rewirings, and a first connection member disposed between the first and second semiconductor chips. Also provided are various systems including same and various methods for making same. | 2013-11-07 |
20130292847 | Semiconductor Devices and Methods of Manufacturing the Same - A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad. | 2013-11-07 |
20130292848 | SEMICONDUCTOR PACKAGES INCLUDING MOLDING LAYERS - Semiconductor packages including molding layer and methods of fabricating the same are provided. The method may include forming a bare package including a semiconductor chip on a package substrate and forming a molding layer surrounding the semiconductor chip on the package substrate while contacting an upper surface of the molding layer with a lower surface of a release film. The lower surface of the release film and the upper surface of the molding layer comprising uneven surfaces and the molding layer may expose an upper surface of the semiconductor chip. | 2013-11-07 |
20130292849 | SYSTEM-IN PACKAGES - System-in packages, or multichip modules, are described which can include multi-layer chips and multi-layer dummy substrates over a carrier, multiple through vias blindly or completely through the multi-layer chips and completely through the multi-layer dummy substrates, multiple metal plugs in the through vias, and multiple metal interconnects, connected to the metal plugs, between the multi-layer chips. The multi-layer chips can be connected to each other or to an external circuit or structure, such as mother board, ball grid array (BGA) substrate, printed circuit board, metal substrate, glass substrate, or ceramic substrate, through the metal plugs and the metal interconnects. | 2013-11-07 |
20130292850 | Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant - A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die. | 2013-11-07 |
20130292851 | Semiconductor Device and Method of Forming TSV Semiconductor Wafer with Embedded Semiconductor Die - A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die. | 2013-11-07 |
20130292852 | CHIP EMBEDDED PACKAGES AND METHODS FOR FORMING A CHIP EMBEDDED PACKAGE - A chip embedded package is provided, the chip embedded package including: a plurality of dies; wherein a first die of the plurality of dies is a chip implementing a first sensor technology, and wherein a second die of the plurality of dies is a chip implementing a second sensor technology; and wherein the plurality of dies are molded with an encapsulation material; wherein at least one of the first die and the second die includes a film interconnect. | 2013-11-07 |
20130292853 | MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die. | 2013-11-07 |
20130292854 | STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING STACKED MICROELECTRONIC DEVICES - Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on a front side of a first microelectronic die, and attaching a back-side surface of a second microelectronic die to individual metal spacers. In another embodiment, the method of manufacturing the microelectronic device may further include forming top-tier spacer elements on front-side wire bonds of the first die. | 2013-11-07 |
20130292855 | Method for Housing an Electronic Component in a Device Package and an Electronic Component Housed in the Device Package - A method for housing an electronic component in a device package includes providing a first substrate, wherein the electronic component is arranged in a component area on a first main surface of the first substrate, and wherein first contact pads are arranged outside of the component area, forming an open top frame structure around the component area on the first main surface of the first substrate, providing a second substrate having second contact pads, arranged symmetrically to the first contact pads and electrically and mechanically connecting the first main surface of the first substrate with the first main surface of the second substrate, so that the frame structure and the second substrate from a cavity or recess around the electronic component on the first substrate. | 2013-11-07 |
20130292856 | METHOD FOR THE WAFER-LEVEL INTEGRATION OF SHAPE MEMORY ALLOY WIRES - The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. | 2013-11-07 |
20130292857 | GAS DIFFUSION APPARATUS FOR LIQUID AERATION AND CARBONATED LIQUIDS - A wine and spirit aerator includes a tube, a diffuser and an air pump attached to opposing ends of the tube. The aerator may include a stopper sized and shaped to be inserted into a lip of a wine or spirit bottle. The tube and diffuser can extend to the bottom of the bottle. The tube can have telescoping sections or be sized for single glass operation where the pump can be set on a structure between uses. The diffuser can be porous or sintered metal. The pump can be removed and replaced with a carbon dioxide injector to turn the aerator into a carbonated beverage preparation apparatus or a plant feeding apparatus. A method of marketing wine and spirits is also provided in which videos of same aerated by the disclosed aerators are posted to a website that offers both the aerators and the wine or spirit for purchase. | 2013-11-07 |
20130292858 | Combination Submersible and Floating Aerator - An aeration system may have a submersible aerator that may be located on the bottom of a body of water and a floating aerator that may operate directly above the submersible aerator. The submersible aerator may create a laminar column of bubbles and may be powered by an air compressor. The floating aerator may use a motor driven propeller to agitate water on the water surface. A controller may determine when to operate the aerators, and may operate them separately or together in some instances. Some embodiments may have a controller that operates the aerators differently based on energy supply, which may vary in solar powered systems with a battery bank. | 2013-11-07 |
20130292859 | OPTICAL FIBER END PROCESSING METHOD AND OPTICAL FIBER END PROCESSING APPARATUS - There is provide an optical fiber end processing method, for processing an end portion of an optical fiber having a core and a clad surrounding the core, comprising: fixing two places of the optical fiber; firstly heating a part at a tip end side of the optical fiber between fixed parts fixed at two places, thereby melting the optical fiber at the heated part at the tip end side; secondly heating a part at a base end side of the optical fiber between the fixed parts away from the heated part at the tip end side in a state that the optical fiber is fixed at two places, thereby forming an expanded core region which is formed by expanding a diameter of the core by diffusing the dopant included in the optical fiber; and removing at least the heated part at the tip end side. | 2013-11-07 |
20130292860 | HOLLOW FIBER MEMBRANE SPINNING NOZZLE, AND METHOD FOR MANUFACTURING HOLLOW FIBER MEMBRANE - A hollow fiber membrane-spinning nozzle that spins a hollow fiber membrane having a porous membrane layer and a support is provided in which the nozzle includes a resin flow channel through which a membrane-forming resin solution forming the porous membrane layer flows, the resin flow channel includes a liquid storage section that stores the membrane-forming resin solution and a shaping section that shapes the membrane-forming resin solution in a cylindrical shape and satisfies at least one of conditions (a) to (c): (a) the resin flow channel is disposed to cause the membrane-forming resin solution to branch and merge; (b) a delay means for delaying the flow of the membrane-forming resin solution is disposed in the resin flow channel; and (c) the liquid storage section or the shaping section includes branching and merging means for the membrane-forming resin solution therein. | 2013-11-07 |
20130292861 | COMPOSITE MATERIAL PART MANUFACTURING PROCESS USING REMOVABLE AND RETAINABLE MATERIAL - A system for changing a dimension of manufactured composite material parts may comprise a male tool, a female tool, a removable material, and a retainable material. The male tool may include a convex outer surface configured to receive composite material placed thereon to form a new part. The female tool may include a concave inner surface configured to receive the male tool such that the outer surface of the male tool faces the inner surface. The removable material may be placed on the composite material in a first area corresponding to a wide area on a previously manufactured part where an outer dimension was measured to be greater than a designed value. The retainable material may be placed on the composite material in a second area corresponding to a narrow area on the previously manufactured part where the outer dimension was measured to be less than the designed value. | 2013-11-07 |
20130292862 | Solid Image Apparatus With Improved Part Separation From The Image Plate - Devices, methods, and computer program products for facilitating the assembly of three-dimensional parts in a layer-wise fashion are disclosed, wherein separation forces between the assembler device and the parts are minimized at certain interfaces. Parts may be produced from polymers, photopolymers, metals, or other materials. In some aspects of the present disclosure, separation forces are minimized via the utilization of a cure inhibiting layer on a top surface of the image plate and via sliding the part from contact with a portion of the image plate having high elevation to above a portion of the image plate with low elevation. In some aspects, the assembler device further comprises a sweeper configured to expose the cure inhibiting layer to a source of cure inhibitor after a cure cycle. | 2013-11-07 |
20130292863 | METHODS AND SYSTEMS FOR ADJUSTING THE COMPOSITION OF A BINDER SYSTEM FOR USE IN MAKING FIBERGLASS PRODUCTS - Methods and systems for preparing a binder system for use in producing fiberglass products are provided. The method can include combining at least a first resin and a component to produce a first binder system. The component can include a second resin, an additive, or a combination thereof. At least a portion of the first binder system can be applied to a first plurality of fibers. One or more process variables can be monitored. The one or more process variables can be evaluated. An amount of the first resin, the component, or both combined with one another can be adjusted in response to the evaluation of the one or more monitored process variables to produce a second binder system. | 2013-11-07 |
20130292864 | METHODS AND SYSTEMS FOR ADJUSTING THE COMPOSITION OF A BINDER SYSTEM CONTAINING TWO OR MORE RESINS - Methods and systems for preparing a binder system are provided. The method can include combining a first resin and a second resin to produce a first binder system. The first binder system can be applied to a first plurality of lignocellulose substrates and at least partially cured to produce a first composite product. The method can also include monitoring one or more process variables. The one or more monitored process variables can be evaluated. An amount of the first resin, the second resin, or both combined with one another can be adjusted in response to the evaluation of the one or more monitored process variables to produce a second binder system. | 2013-11-07 |
20130292865 | TEMPLATE SYSTEM AND NANO-IMPRINT METHOD USING THE SAME - A template system, and a nano-imprint method using the same, include a template having a nano-pattern and configured to transfer the nano-pattern to a resin material on a substrate, and a pressure controlling apparatus configured to change a pressure of the template with respect to the substrate according to an intensity of bubbles captured between the substrate and the template. | 2013-11-07 |
20130292866 | POROUS MEMBRANE, PROCESS FOR PRODUCING POROUS MEMBRANE, PROCESS FOR PRODUCING CLARIFIED LIQUID, AND POROUS-MEMBRANE MODULE - A porous membrane with the membrane wall constructed of a hydrophobic polymer and a hydrophilic polymer, wherein when the membrane wall is divided into 3 sections in the film thickness direction to form region “a” containing one wall surface A of the membrane wall, region “c” containing the other wall surface C and region “b” between region “a” and region “c”, the hydrophilic polymer content ratio C | 2013-11-07 |
20130292867 | WASHING APPARATUS, AND PROCESS FOR PRODUCING POROUS MEMBRANE - The present invention relates to a method of producing a porous membrane, including a coagulation step of coagulating a membrane-forming raw material solution to form a porous membrane; a washing step of washing the porous membrane to remove material remaining in the porous membrane; a removal step of removing a hydrophilic polymer remaining in the porous membrane, in which the washing step includes transporting a porous membrane so as to contact with a falling washing solution. According to the present invention, it is possible to provide a method of producing a porous membrane capable of efficiently removing a solvent from a porous membrane within a short period of time at a low cost without large facilities; and a washing apparatus used for the production process. | 2013-11-07 |
20130292868 | SOLVENT-CAST MICROPROTRUSION ARRAYS CONTAINING ACTIVE INGREDIENT - In an aspect of the invention, an array of microprotrusions is formed by providing a mold with cavities corresponding to the negative of the microprotrusions, casting atop the mold a first solution comprising a biocompatible material and a solvent, removing the solvent, casting a second solution atop the first cast solution, removing the solvent from the second solution, and demolding the resulting array from the mold. The first solution preferably contains an active ingredient. | 2013-11-07 |
20130292869 | MEDICAL DEVICES AND METHODS INCLUDING POLYMERS HAVING BIOLOGICALLY ACTIVE AGENTS THEREIN - The implant design is a drug loaded polymer device, such as a rod, designed to control the release of a biologically active agent, such as clonidine or its derivatives, such as clonidine HCl for a prolonged period of time, such as 2 months, 3 months, 4 months, and even 4.5 months. The polymer is preferably a biodegradable polymer, such as poly(lactide-co-glycolide) or polylactic acid/polylactide. The challenge in using the HCl salt forms of drugs such as clonidine, is controlling the release of the highly water soluble drug for up to 4.5 months. It has been found that by controlling the particle size distribution of the drug powder, the drug distribution within the polymer matrix is more uniform and can be controlled. Therefore, the large aggregates, which cause rapid drug release can be eliminated. | 2013-11-07 |
20130292870 | METHODS FOR MANUFACTURING CUSTOM CUTTING GUIDES IN ORTHOPEDIC APPLICATIONS - A patient specific system for joint replacement surgery that includes a custom cutting guide having an inner surface shaped to match the anatomy of a surface of a patient's joint to be resected. The custom cutting guide is designed for use with a corresponding prosthesis. A slot and guide holes are formed in the custom cutting guide corresponding to features protruding outwardly from a positive physical bone model. The slot guides a tool during resection of the femur to produce a first resected surface on the femur for mounting the prosthesis. The guide is formed from the positive physical model by applying a polymeric composition to the outer surface of the positive physical model including the features corresponding to the slot and guide holes of the custom cutting guide. | 2013-11-07 |