45th week of 2008 patent applcation highlights part 49 |
Patent application number | Title | Published |
20080276031 | Method and apparatus for a federation control plane in an orthogonal system - A method of and architecture for controlling board elements in an orthogonal system architecture is provided. The method and architecture preferably utilize an internal bus architecture between control boards, such that a first control board can access board elements in its stack via I/O on a second control board and the second control board can access board elements in its stack via I/O on the first control board. Most preferably the internal bus architecture is a HyperTransport bus architecture. | 2008-11-06 |
20080276032 | ARRANGEMENTS WHICH WRITE SAME DATA AS DATA STORED IN A FIRST CACHE MEMORY MODULE, TO A SECOND CACHE MEMORY MODULE - A storage device control apparatus including first and second systematic memory module groups, each of which is composed of a plurality of memory modules, a memory controller for controlling memory access to the memory modules belonging to each of the first systematic and second systematic memory module groups. When the memory controller detects failure in one of the other memory systems, the memory system performs memory access to the memory modules belonging to its own systematic memory module groups. | 2008-11-06 |
20080276033 | MULTIPATH REDUNDANT STORAGE SYSTEM ARCHITECTURE AND METHOD - Disclosed is a storage system and method that provides multi-path bus and component interconnection and isolation in a data storage system. A plurality of data storage devices in a removable assembly are connected to a fabric that is configurable to connect some or all of the data storage devices (or “drives”) to a drive controller and configurable to isolate one or more data storage devices from the drive controller. Multiple controllers, fabrics, and interconnecting buses may be employed to provide redundancy in the event of a connector, bus, or controller failure. Computer program code operating in a host, interface controller, and/or drive controller configures the fabric to isolate failed devices and may be employed to optimize data transfer rates. Data storage devices may be multi-ported. The fabric may comprise any device or devices capable of configurably interconnecting data storage devices to one or more controllers and may comprise multiplexers, cross point switches, port bypass controllers. Fabrics may also provide translation or conversion of one bus or interface format to another format. | 2008-11-06 |
20080276034 | Design Structure for Transmitting Data in an Integrated Circuit - A design structure, which may be generated by a fabless design company, for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores. | 2008-11-06 |
20080276035 | Wear Leveling - A reference memory location can be designated in a memory device. A memory location can be designated in response to storing data in the memory device. If the identified memory location is associated with the reference memory location then an allocated memory location can be designated relative to the reference memory location, and the allocated memory location can be leveled. | 2008-11-06 |
20080276036 | Memory with Block-Erasable Location - A non-volatile main memory ( | 2008-11-06 |
20080276037 | Method to Access Storage Device Through Universal Serial Bus - A method accessing a flash memory storage device through universal serial bus (USB) of the present invention includes a flash controller and a flash memory, wherein the method includes connecting the storage device to a USB interface of an electronic device; outputting a plurality of accessing instructions to the flash controller via the electronic device; deciding which data is needed to be temporarily saved in a cache memory and a priority of the accessing instructions according to the characteristic of the file system and the content of preceding instructions of the flash controller; and writing the data temporarily saved in the cache memory into the flash memory according to the priority of the flash controller. The objective of the method of the present invention is to enhance the operation efficiency of the storage device. | 2008-11-06 |
20080276038 | Storage system using flash memory modules logically grouped for wear-leveling and raid - A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group. | 2008-11-06 |
20080276039 | Method and System for Emulating Content-Addressable Memory Primitives - A method and system for emulating content-addressable memory (CAM) primitives (e.g., a read operation) is disclosed. According to one embodiment, a method is provided for emulating a read operation on a plurality of CAM elements utilizing a read input including match input data and a CAM element selection index. In the described method, match reference data is distributed among a plurality of random-access memory (RAM) elements by storing match reference data corresponding to each of the plurality of CAM elements within a first RAM element of the plurality. Thereafter, a first record is identified within the first RAM element utilizing a first portion of the match input data and the CAM element selection index. A read operation result is then generated utilizing the first record. | 2008-11-06 |
20080276040 | STORAGE APPARATUS AND DATA MANAGEMENT METHOD IN STORAGE APPARATUS - Provided are a storage apparatus and its data management method capable of preventing the loss of data retained in a volatile cache memory even during an unexpected power shutdown. This storage apparatus includes a cache memory configured from a volatile and nonvolatile memory. The volatile cache memory caches data according to a write request from a host system and data staged from a disk drive, and the nonvolatile cache memory only caches data staged from a disk drive. Upon an unexpected power shutdown, the storage apparatus immediately backs up the dirty data and other information cached in the volatile cache memory to the nonvolatile cache memory. | 2008-11-06 |
20080276041 | DATA STORAGE ARRAY SCALING METHOD AND SYSTEM WITH MINIMAL DATA MOVEMENT - A method for rearranging data blocks in a data storage system when adding new storage devices to create an expanded data storage system. A temporary configuration is selected for which the exchange of one or more data blocks between the temporary configuration and the source configuration produces the destination configuration before identifying and exchanging data blocks between the temporary configuration and the source configuration to produce the destination configuration. A single data element transfer chain embodiment provides superior performance in an embodiment that maintains (does not reduce) the source array data storage efficiency at the destination array after scaling. When adding a single new device to an existing array, the required data movement is minimized and does not exceed the capacity of the new device. | 2008-11-06 |
20080276042 | DATA STORAGE SYSTEM AND METHOD - Disclosed are a redundant data storage system (e.g., a RAID system) and a method of operating such a redundant data storage system that provides significant power savings with minimal reduction in reliability. The system and method allow up to half of the memory devices in any of the memory arrays in the system to be placed in standby without significantly impacting the read accesses. The system and method further designate reserved areas in the active memory devices as write-journals, which have at least the same level of protection as the main arrays. The write-journals allow data to be written without powering up a standby memory device. Thus, power consumption is minimized without impacting reliability. | 2008-11-06 |
20080276043 | DATA STORAGE SYSTEM AND METHOD - Disclosed are a redundant data storage system (e.g., a RAID system) and a method of operating such a redundant data storage system that provides significant power savings with minimal reduction in reliability. The system and method allow up to half of the memory devices in any of the memory arrays in the system to be placed in standby without significantly impacting the read accesses. The system and method further designate reserved areas in the active memory devices as write-journals, which have at least the same level of protection as the main arrays. The write-journals allow data to be written without powering up a standby memory device. Thus, power consumption is minimized without impacting reliability. | 2008-11-06 |
20080276044 | PROCESSING APPARATUS - A processing apparatus which executes a program and performs processes of the program, includes an execution circuit including a plurality of central processing units, each having a respective cache memory, and each of the respective cache memories has an N-way set-associative structure with N-ways in which one line is made up of plural words. Each of the respective cache memories includes a data memory array which is simultaneously read-out in multiple-word-widths, and can be read-out using one of a type one read-out and a type two read-out. In the type one read-out, plural words in the same word positions within respective lines are simultaneously read-out from corresponding lines belonging to different ways, and in the type two read out, plural words making up one line of one way are simultaneously read-out. The cache memory has a first read-out mode and a second read-out mode. In the first read-out mode, a word belonging to a way which is hit by a memory access is selected from among the plural words read-out using the type-one read out, and the selected word is outputted, and in the second read-out mode, plural words are read-out from a way which is hit, using the type-two read out, and read-out plural words are outputted. | 2008-11-06 |
20080276045 | Apparatus and Method for Dynamic Cache Management - The apparatus of the present invention improves performance of computing systems by enabling a multi-core or multi-processor system to deterministically identify cache memory ( | 2008-11-06 |
20080276046 | Architecture for a Multi-Port Cache Memory - A multi-port cache memory ( | 2008-11-06 |
20080276047 | APPARATUS, SYSTEM, AND METHOD FOR EFFICIENTLY VERIFYING WRITES - An apparatus, system, and method are disclosed for efficiently verifying writes. A storage module stores a plurality of data sets in a storage controller memory. A write module writes the plurality of data sets through a first write channel to a hard disk drive. A verification module verifies whether a representative data set of the plurality of data sets is successfully written to the first write channel or not. A mitigation module rewrites the plurality of data sets in response to an unsuccessful write of the representative data set. | 2008-11-06 |
20080276048 | Addressing and Command Protocols for Non-Volatile Memories Utilized in Recording Usage Counts - Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be assigned an address through a set of discrete voltages. One, multiple, or all of the memory modules may be addressed with a single command, which may be an increment counter command, a write command, or a punch out bit field. The status of the memory modules may be determined by sampling a single signal that may be at a low, high, or intermediate voltage level. | 2008-11-06 |
20080276049 | Semiconductor memory apparatus, memory access control system and data reading method - In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to the read data storing portion while maintaining a corresponding relationship between the priority information and the data read; and a priority operation control portion which chooses and outputs the data with a highest priority among the priority information and the data that are stored in the read data storing portion while maintaining a corresponding relationship between the priority information and the data. | 2008-11-06 |
20080276050 | ERASE HANDLING METHOD FOR NON-VOLATILE MEMORY AND ELECTRONIC APPARATUS THEREOF - For an electronic apparatus with a sleep mode and an operation mode, an erasing command is issued to a memory controller that controls a non-volatile memory device before the electronic apparatus is entering the sleeping mode. Preferably, an estimated sleeping time is compared with a predetermined threshold for determining whether to activate erase operations to release space from the non-volatile memory device. Further, when the electronic apparatus returns from the sleep mode to the operation mode, the erase operations are checked whether they are complete. If the erase operations are not completed, another erase command is issued to the memory controller next time when the electronic apparatus is going to the sleep mode again. | 2008-11-06 |
20080276051 | Configurable Memory Protection - A method can include receiving a signal associated with an attempted access to data that is stored at a specific location in memory; obtaining a selection value that selects which memory protection register of multiple alternative memory protection registers is to provide a memory protection attribute for the specific location in memory; obtaining, from the selected memory protection register, a memory protection attribute; and controlling access to the specific location in memory based on the obtained memory protection attribute. | 2008-11-06 |
20080276052 | METHOD FOR ACCESSING MEMORY - A method for accessing a memory is provided. The method includes entering a memory accessing mode for updating a top of low memory (TOLM) value stored in a TOLM register in a chipset of a system with a highest memory address when a memory accessing command is received. The memory accessing command requests the utilization of a memory block in a memory of the system corresponding to an address space occupied by a memory-mapped input output (MMIO) function. The system then accesses the corresponding memory block in the memory according to the address space recorded in the memory accessing command. After the access is completed, the memory accessing mode is closed and the original TOLM value is written back to the TOLM register. Therefore, the present invention can access the “MMIO memory block” to prevent a waste of the memory. | 2008-11-06 |
20080276053 | Portable Device and Method for Controlling Deep Power Down Mode of Shared Memory - The memory device may include a first determination unit for determining whether entry into a DPD mode is to be made by interpreting signals received from a first processor, and generating and outputting a corresponding first DPD entry signal; a second determination unit for determining whether entry into the DPD mode is to be made by interpreting signals received from a second processor, and generating and outputting a corresponding second DPD entry signal; and a DPD determination unit for performing control for operation in the DPD mode only when the first DPD entry signal and the second DPD entry signal are respectively received from the first determination unit and the second determination unit. In accordance with the present invention, a single piece of memory operates in the DPD mode even when a plurality of processors shares the memory, so that power consumption can be minimized. | 2008-11-06 |
20080276054 | MONITORING PERFORMANCE OF A STORAGE AREA NETWORK - A performance monitor reports SAN performance so that issues within the SAN are not masked from the client. Accesses to the SAN may be grouped into the categories of SAN logical or SAN physical. In one specific embodiment, the ranges of service times for accesses to the SAN are determined by monitoring service times of accesses to the SAN from the client perspective. In another specific embodiment, the ranges of service times for the SAN are determined by the SAN returning data with each request that indicates the service time from the SAN perspective. This allows reporting not only SAN logical and SAN physical accesses, but also allows reporting SAN service time. By specifying SAN service time, the client is able to better determine network delays. In yet another embodiment, information is returned by the SAN to indicate whether the access is SAN logical or SAN physical. | 2008-11-06 |
20080276055 | SYSTEMS AND METHODS FOR ALLOCATING CONTROL OF STORAGE MEDIA IN A NETWORK ENVIRONMENT - A method for dynamically allocating control of a storage device, the method comprising receiving an access request from a first computer requesting access to a storage device; directing, based upon the access request, a first storage controller computer to assume an inactive state with respect to control of the storage device; and directing, based upon the access request, a second storage controller computer to assume an active state with respect to control of the storage device. | 2008-11-06 |
20080276056 | Efficient Point-To-Point Enqueue And Dequeue Communications - Systems and methods for writing and/or reading data to a point-to-point shared memory communication mechanism are provided according to embodiments disclosed herein. According to one embodiment, a determination may be made whether a first memory location in the cache of a general purpose multi-core processor includes an empty symbol. If the first memory location includes the empty symbol, then data may be placed in the first memory location in the cache. If the first memory location does not include the empty symbol, then waiting until it does. In another embodiment, a determination may be made whether a first memory location of a general purpose multi-core processor includes the empty symbol. If it does not, then data may be read from the first memory location and/or the empty symbol may be written into the first memory location. If the first memory location does include the empty symbol, then pausing. | 2008-11-06 |
20080276057 | DATA STORAGE ARRAY SCALING METHOD AND SYSTEM WITH MINIMAL DATA MOVEMENT - A method for rearranging data blocks in a data storage system when adding new storage devices to create an expanded data storage system. A temporary configuration is selected for which the exchange of one or more data blocks between the temporary configuration and the source configuration produces the destination configuration before identifying and exchanging data blocks between the temporary configuration and the source configuration to produce the destination configuration. A single data element transfer chain embodiment provides superior performance in an embodiment that maintains (does not reduce) the source array data storage efficiency at the destination array after scaling. When adding a single new device to an existing array, the required data movement is minimized and does not exceed the capacity of the new device. | 2008-11-06 |
20080276058 | Storage Device For Data-Smuggling - A computer-readable storage medium having computer-readable code embodied thereon including: program code for restricting access, by a file system running on a host system, to a restricted area of a storage area of a storage device; and program code for enabling at least one application to access the restricted area via the file system. Preferably, the computer-readable code further includes: program code for enabling the storage device to copy data from a non-restricted area to the restricted area. Preferably, the computer-readable code further includes: program code for directing the storage device to route host-system read-requests, directed to addresses in the restricted area, to addresses in a non-restricted area. Preferably, the computer-readable code further includes: program code for applying access commands of the host system to restricted data residing in the restricted area when the host system requests access to non-restricted data addressed to a non-restricted area. | 2008-11-06 |
20080276059 | APPARATUS AND METHODS FOR SETTING SECURITY TO STORAGE UNIT AND COMPUTER - Methods and apparatus are provided for inhibiting data writing to an optical disc drive connected to a computer. A BIOS confirms presence of a security function of an optical disc drive. When the optical disc drive possesses the security function, the BIOS delivers a command to the optical disc drive to set it to a read-only mode. The optical disc drive that has received the command sets the drive per se to operate in the read-only mode. Since a command for setting it to the read-only mode and a command for releasing it are delivered to the optical disc drive only by the BIOS, when a control is transferred to an Operating System (OS), setting of the read-only mode cannot be released by the OS and other OS's, or application software. | 2008-11-06 |
20080276060 | Pre-Configured Partitions With Use-Rights Limitations - A computer system comprising includes an inactive partition with a bootable operating system installed and a license manager for obtaining a license that allows the partition to be activated. | 2008-11-06 |
20080276061 | METHOD AND COMPUTER FOR DETERMINING STORAGE DEVICE - A computer specifies the configuration of a first storage device by referencing first configuration information relating to the configuration of a first storage system including the first storage devices, specifies one or more storage medium access performances corresponding to the first storage device by referencing the storage medium performance information, and calculates a first access performance index of the first storage device based on one or more specified storage medium access performances. The computer then references storage medium performance information and second configuration information relating to the configuration of a second storage system including a second storage device, and determines a second storage device having an access performance index that is at least equal to the calculated first storage access performance index. | 2008-11-06 |
20080276062 | MEMORY MANAGEMENT FOR A MOBILE MULTIMEDIA PROCESSOR - Certain embodiments of the invention may be found in a method for memory management for a mobile multimedia processor. The method may comprise receiving within a mobile multimedia processor chip a plurality of memory requests. The plurality of memory requests may be handled by allocating memory from at least one on-chip memory block and/or at least one off-chip memory block. The memory may be allocated based on a priority level of each of the plurality of memory requests and at least one dynamically settable global memory allocation priority threshold. A new dynamically settable memory allocation priority threshold may be dynamically determined based on a new application and/or by monitoring at least one software process in at least one present application. Additionally, new memory request priority level may be dynamically determined for each memory request in at least one software process in a new application. | 2008-11-06 |
20080276063 | DYNAMIC STACK ALLOCATING METHOD IN MULTI-THREADED OPERATING SYSTEMS - Provided is a method of dynamically reallocating a thread stack in a multi-threaded operating system, and more particularly, a method of dynamically allocating a thread stack of a multi-threaded operating system in an embedded system for wireless sensor nodes. The method includes the steps of: measuring sizes of data and non-data sections of a stack with respect to each thread; determining a new size of the non-data section of each stack based on the size of the data section of the stack measured with respect to each thread; and adjusting the size of the non-data section of each stack to the determined new size. According to the method, even without the source code analysis, an amount of memory spaces to be used can be reduced compared to that of a conventional static stack allocation method. | 2008-11-06 |
20080276064 | Shared stream memory on multiple processors - A method and an apparatus that allocate a stream memory and/or a local memory for a variable in an executable loaded from a host processor to the compute processor according to whether a compute processor supports a storage capability are described. The compute processor may be a graphics processing unit (GPU) or a central processing unit (CPU). Alternatively, an application running in a host processor configures storage capabilities in a compute processor, such as CPU or GPU, to determine a memory location for accessing a variable in an executable executed by a plurality of threads in the compute processor. The configuration and allocation are based on API calls in the host processor. | 2008-11-06 |
20080276065 | METHOD OF PARTITIONING STORAGE AREA OF RECORDING MEDIUM AND RECORDING MEDIUM USING THE METHOD, AND METHOD OF ACCESSING RECORDING MEDIUM AND RECORDING DEVICE USING THE METHOD - Provided is a method of partitioning a storage area of a recording medium and a recording medium using the method, and a method of accessing a recording medium and a recording device using the method, capable of storing partition information used for partitioning a predetermined storage area included in the recording medium into a number of storage sub-areas in a first storage sub-area of the recording medium, and storing authority information which indicates whether an access instruction for accessing one of the partitioned storage sub-areas has authority to access the storage sub-area in a second storage sub-area. Accordingly, on a user's point, a read-only memory (ROM) area and a random access memory (RAM) area may be simultaneously provided to a NAND flash memory. On a content provider's point, desired contents are prevented from being deleted, and an additional space for storing added contents can be guaranteed. | 2008-11-06 |
20080276066 | Virtual memory translation with pre-fetch prediction - A system to facilitate virtual page translation. An embodiment of the system includes a processing device, a front end unit, and address translation logic. The processing device is configured to process data of a current block of data. The front end unit is coupled to the processing device. The front end unit is configured to access the current block of data in an electronic memory device and to send the current block of data to the processor for processing. The address translation logic is coupled to the front end unit and the electronic memory device. The address translation logic is configured to pre-fetch a virtual address translation for a predicted virtual address based on a virtual address of the current block of data. Embodiments of the system increase address translation performance of computer systems including graphic rendering operations. | 2008-11-06 |
20080276067 | Method and Apparatus for Page Table Pre-Fetching in Zero Frame Display Channel - A method for a graphics processing unit (“GPU”) to maintain a local cache to minimize system memory reads is provided. A display read request and a logical address are received. The GPU determines whether a local cache contains a physical address corresponding to the logical address. If not, a cache fetch command is generated, and a number of cache lines is retrieved from a table, which may be a GART table, in the system memory. The logical address is converted to a corresponding physical address of the memory when the cache lines are retrieved from the table so that data in memory may be accessed by the GPU. When a cache line in the local cache is consumed, a next line cache fetch request is generated to retrieve a next cache line from the table so that the local cache maintains a predetermined amount of cache lines. | 2008-11-06 |
20080276068 | IMS network architecture with integrated network elements - An IP multimedia subsystem (IMS) network includes (i) a plurality of network elements that are directly or indirectly interconnected for carrying out communications and (ii) an integrated IMS network control unit interfaced with the other network elements. The control unit integrates three IMS network functions into one network node: a multimedia resource function (MRF) module, which incorporates a multimedia resource function controller (MRFC) and/or one or more multimedia resource function processors (MRFP), e.g., media servers; a media gateway control function (MGCF); and a media gateway (MGW). The external physical interface of the control unit mimics the typical interfaces of the MRF/MRFC, MGCF, and MGW, were they to be provided as separate network elements/nodes. As such, the control unit is both physically and logically transparent to the rest of the network, as relating to the integrated MRF, MGCF, and MGW functions. | 2008-11-06 |
20080276069 | METHOD AND APPARATUS FOR PREDICTIVE DECODING - Predictive decoding is achieved by fetching an instruction, accessing a predictor containing predictor information including prior instruction execution characteristics, obtaining predictor information for the fetched instruction from the predictor; and generating a selected one of a plurality of decode operation streams corresponding to the fetched instruction. The decode operation stream is selected based on the predictor information. | 2008-11-06 |
20080276070 | REDUCING THE FETCH TIME OF TARGET INSTRUCTIONS OF A PREDICTED TAKEN BRANCH INSTRUCTION - A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced. | 2008-11-06 |
20080276071 | REDUCING THE FETCH TIME OF TARGET INSTRUCTIONS OF A PREDICTED TAKEN BRANCH INSTRUCTION - A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced. | 2008-11-06 |
20080276072 | System and Method for using a Local Condition Code Register for Accelerating Conditional Instruction Execution in a Pipeline Processor - A method of executing a conditional instruction within a pipeline processor having a plurality of pipelines, the processor having a first condition code register associated with a first pipeline and a second condition code register associated with a second pipeline is disclosed. The method saves a most recent condition code value to either the first condition code register or the second condition code register. The method further sets an indicator indicating whether the second condition code register has the most recent condition code value and retrieves the most recent condition code value from either the first or second condition code register based on the indicator. The method uses the most recent condition code value to determine if the conditional instruction should be executed. | 2008-11-06 |
20080276073 | Apparatus for and method of distributing instructions - An apparatus is provided for buffering instructions. An instruction store has memory locations for storing instructions. Each instruction can be associated with a timer such that an instruction dispatcher causes the instruction to be sent when the timer indicates that the instruction should be sent. | 2008-11-06 |
20080276074 | SIMPLE LOAD AND STORE DISAMBIGUATION AND SCHEDULING AT PREDECODE - Embodiments of the invention provide a processor for executing instructions. In one embodiment, the processor includes circuitry to receive a load instruction and a store instruction to be executed in the processor and detect a conflict between the load instruction and the store instruction. Detecting the conflict includes determining if load-store conflict information indicates that the load instruction previously conflicted with the store instruction. The load-store conflict information is stored for both the load instruction and the store instruction. The processor further includes circuitry to schedule execution of the load instruction and the store instruction so that execution of the load instruction and the store instruction do not result in a conflict. | 2008-11-06 |
20080276075 | SIMPLE LOAD AND STORE DISAMBIGUATION AND SCHEDULING AT PREDECODE - Embodiments of the invention provide a method and processor for executing instructions. In one embodiment, the method includes receiving a load instruction and a store instruction to be executed in the processor and detecting a conflict between the load instruction and the store instruction. Detecting the conflict includes determining if load-store conflict information indicates that the load instruction previously conflicted with the store instruction. The load-store conflict information is stored for both the load instruction and the store instruction. The method further includes scheduling execution of the load instruction and the store instruction so that execution of the load instruction and the store instruction do not result in a conflict. | 2008-11-06 |
20080276076 | METHOD AND APPARATUS FOR REGISTER RENAMING - A method and apparatus for register renaming are provides in the illustrative embodiments. A mapper receives a request for a data in a logical register. The mapper searches an in-flight map table and a set of architected map tables for the data in the logical register. The mapper identifies an entry in one of the in-flight map table and an architected map table in the set of architected map tables that corresponds with the logical register in the request. The mapper returns a location of a physical register, which holds the requested data. | 2008-11-06 |
20080276077 | Method To Reduce The Number Of Load Instructions Searched By Stores And Snoops In An Out-Of-Order Processor - A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load instructions; inserting the load instructions in the LRQ in program order; clearing a load received data field; executing the load instructions; checking load reorder queue (LRQ) entries; re-executing the load instruction of the matching LRQ entry; continuing execution; getting the load data; setting the load received data field; comparing a load sequence number (LSQN) of each load instruction to a snoop_safe register contents; ANDing all the load received data bits if the LSQN is greater in magnitude to the snoop_safe; setting the snoop_safe register to the LSQN of the load instruction; searching the LRQ entry; and setting a load_peril_snoop register to the LRQ index value where the first load instruction younger to the snoop_safe was found. | 2008-11-06 |
20080276078 | Method and Apparatus for Context Address Generation for Motion Vectors and Coefficients - A method for high/low usage is provided. The method receives a macroblock data structure and a syntax element at a digital signal processing engine. Further, the method classifies the syntax element as high use or low use. In addition, the method sends the syntax element from the digital signal processing engine to a logic unit, distinct from the digital processing engine, for binarization if the syntax element is high use. | 2008-11-06 |
20080276079 | MECHANISM TO MINIMIZE UNSCHEDULED D-CACHE MISS PIPELINE STALLS - A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The method includes receiving an issue group of instructions, determining if a first instruction in the issue group is a load instruction, and if so, scheduling the first instruction to be executed in a pipeline in which execution is not delayed with respect to another pipeline in the cascaded delayed execution pipeline unit. | 2008-11-06 |
20080276080 | METHODS FOR STORING BRANCH INFORMATION IN AN ADDRESS TABLE OF A PROCESSOR - Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information. | 2008-11-06 |
20080276081 | COMPACT REPRESENTATION OF INSTRUCTION EXECUTION PATH HISTORY - A method of representing instruction execution path history is provided. The method in one aspect may include gathering information associated with a current instruction, the information including at least a target address. Previously computed bits representing execution path history is modified and hashed based on the target address, to compute current execution path history. | 2008-11-06 |
20080276082 | COMPARING CHRACTERISTICS PRIOR TO BOOTING DEVICES - A system that comprises a first electronic device comprising a non-volatile memory. The system also comprises another electronic device in communication with the first electronic device and comprising a second non-volatile memory. The system further comprises a control logic coupled to the first and second electronic devices. Each of the non-volatile memories stores electrical characteristics associated with a corresponding electronic device. Prior to booting up the first or second electronic device, the control logic obtains and compares at least some of the electrical characteristics and disables the communication as a result of the comparison. | 2008-11-06 |
20080276083 | Method for Transmitting a Message Containing a Description of an Action to be Executed in a Receiver Equipment - The invention relates to a method for transmitting a message to a reception equipment by an operator, the message containing a description of an action to be executed in the said equipment at a time chosen by the operator. | 2008-11-06 |
20080276084 | Anonymity Revocation - Methods and systems for anonymity revocation, enabling a trusted entity to identify a user computer within an anonymous system. A system comprises an attester computer providing attestation value cert from a security module public key and an identifying value. The user computer having a module providing the module public key and a security module attestation value, the user computer providing a user public key, a user attestation-signature value derived from the attestation value cert, and an encryption computable under use of a trusted-entity public key and a module-generated-identifier value, the module-generated-identifier value relating to the identifying value; a verification computer verifying validity of received user attestation-signature value and the encryption; and a trusted entity having a trusted entity secret key, wherein the trusted entity is able to derive the module-generated-identifier value from the encryption, the module-generated-identifier value being usable to identify the user computer with the security module. | 2008-11-06 |
20080276085 | Allowing differential processing of encrypted tunnels - In one embodiment, a method can include: (i) receiving an outbound packet in a network device, where the outbound packet includes a packet header; (ii) modifying the outbound packet by adding a service identifier to a cleartext portion of the packet header; (iii) when the outbound packet represents an event boundary, adding an event delimiter to the packet header; and (iv) passing the outbound packet to an encryption process for packaging and transmitting across a tunnel. | 2008-11-06 |
20080276086 | Method of controlling the processing of data - A method of controlling the processing of data, is provided comprising defining security controls for a plurality of data items, and applying individualised security rules to each of the data items based on a measurement of integrity of a computing entity to which the data items are to be made available. | 2008-11-06 |
20080276087 | Peripheral Device for Programmable Logic Controller - The invention aims to provide, in order to prevent dishonest operations associated with leakage of authentication data, and leakage of data that is information assets, a peripheral device for a programmable logic controller, that does not require to give out the content of data and authentication data to a user of the peripheral device. | 2008-11-06 |
20080276088 | Continuous isochronous read access and measurement of data stored in non-volatile memory - A measurement and authentication engine in a nonvolatile memory computes an original hash value on data read from the nonvolatile memory. A measurement and authentication engine in a host processor recomputes the hash value on the data received from nonvolatile memory and checks that the computed hash value matches the hash value generated and transferred from the nonvolatile memory. | 2008-11-06 |
20080276089 | Content Authentication and Recovery Using Digital Watermarks - The disclosure describes methods for using digital watermarking to authenticate digital media signals, such as images, audio and video signals. It also describes techniques for using embedded watermarks to repair altered parts of a media signal when alteration is detected. Alteration is detected using hashes, digital watermarks, and a combination of hashes and digital watermarks. | 2008-11-06 |
20080276090 | System for Allocating a Chip Card to a Network Operator - A chip card needs to be allocated in a secured manner to a network operator via a personalization center in order to determine a final authentication key which is attributed to a subscriber of the operator without its being transmitted via a network. The following is loaded into a card by a module: an algorithm and an allocation key; an algorithm for determination of the authentication key and at least one intermediate authentication key. A module transmits an allocation message which includes a final identity number, a random number and an allocation signature from the center to the card. The card authenticates the message by means of the allocation algorithm as a function of the allocation key and the allocation signature, and determines the final authentication key as a function of the intermediate key and the random number. | 2008-11-06 |
20080276091 | Mobile Device File Sharing Method and Apparatus - File sharing between mobile devices is enabled using a hierarchical Distributed Hash Table (DHT) based message routing system. According to one embodiment, mobile device electronic content is shared via an overlay network of computer nodes arranged according to a hierarchical DHT by a mobile device generating a message. The message includes a key configured to identify mobile device electronic content and to enable routing of the message based on the hierarchical DHT through the overlay network upon reception of the message at any of the computer nodes. The message is transmitted to a packet-switched radio access network, the packet-switched radio access network configured to send the message to one or more of the computer nodes. The message is eventually routed to the computer node responsible for the key. The responsible computer node processes the message, e.g., by registering electronic content, deregistering electronic content or responding to an electronic content request. | 2008-11-06 |
20080276092 | Method for Authentication of Sensor Data, and an Associated Sensor - A method for authentication of sensor data (D) which is interchanged between at least one sensor (S | 2008-11-06 |
20080276093 | SERVICE MOBILITY MANAGEMENT SYSTEM USING XML SECURITY AND THE METHOD THEREOF - A system for managing service mobility using an extensible Markup Language (XML) electronic signature. A mobility interface stops and stores the operation of a service being currently performed. Before the service is moved, a service serializer serializes service state information and converts it into an XML form which is attachable to an electronic signature. An XML security manager creates an XML electronic signature for the Manifest file of the Java ARchive (JAR) file of a service bundle, attaches the serialized service state information to the XML electronic signature, and records it. A service installer transmits the signed JAR file to an Open Service Gateway initiative (OSGi) framework that has requested that the service be moved. | 2008-11-06 |
20080276094 | COMMUNICATION TERMINAL DEVICE, SERVER APPARATUS, DATA MANAGEMENT METHOD AND RECORDING MEDIUM - A response is made to delivery data received by a communication terminal (cellular phone or the like) through a network (public network), the delivery data and the response action are traced and the delivery data during a predetermined time including the time at which the response action occurs and the data representing the response action are extracted, which is recorded as the traced data (TD). The traced data is transferred to a server device (signature server) through the network, and the data with the signature is transferred to the communication terminal and stored as the signed data. | 2008-11-06 |
20080276095 | Data Processing Apparatus and Its Method - A verification information generation system comprises a first and a second data processing apparatuses. The first data processing apparatus comprises a holding unit adapted to hold a first secret information which is set in advance, a reception unit adapted to receive information associated with the second secret information from the second data processing apparatus, a key information generation unit adapted to generate key information on the basis of the first secret information and the information associated with the second secret information, a key derivation auxiliary information generation unit adapted to generate key derivation auxiliary information which allows the key information to be derived from the second secret information, a verification information generation unit adapted to generate verification information on the basis of information to be verified and the key information, and an output unit adapted to output the information to be verified, the verification information, and the key derivation auxiliary information. The second secret information is information which is set in advance in the second data processing apparatus. | 2008-11-06 |
20080276096 | Method and apparatus for protecting external call references - The present invention is generally directed to a method, system, and article of manufacture that ensures the integrity of programs having variable portions. One aspect of this invention is a method for protecting software products having variant portions. This method includes identifying a reference to an external target in a software product, creating an identifier for the external target, and adding the identifier to the reference. In some embodiments, the unique identifier is a digital signature and the reference to an external target is a call to an external library. | 2008-11-06 |
20080276097 | Alternate to email for messages of general interest - This invention is an online system to forward and discuss messages of common interest among members of the system. The system is based on a central server that manages all member accounts, messages and message flow among the members. The system introduces the concept of private comments on a public message. While the message is open to all members of the system, each comment on the message is restricted to be viewed only by members to whom the comment is sent to. This allows an email like interface to forward and discuss the same message among different groups of people. The system also provides metrics related to the overall reach and popularity of the message. | 2008-11-06 |
20080276098 | ONE-TIME PASSWORD ACCESS TO PASSWORD-PROTECTED ACCOUNTS - Systems and methods facilitate secure one-time-password access to an account in a remote server from an untrusted client. The system consists of an intermediary component whose salient components are a proxy component, a webserver component, and an encryption/decryption component, and it preserves the characteristics of both the server and client. In a man-in-the-middle fashion, the proxy substitutes a one-time password entered at a login interface with a true password, and forwards it to the remote login server. True passwords are encrypted using a seed associated with user identifiers, and a list of one-time passwords is generated/updated and stored on media or transmitted to an electronic device. Substitution takes place by decrypting the one-time password with the seed used for encryption, ensuring the proxy avoids storing the true password. | 2008-11-06 |
20080276099 | Universal Serial Bus (USB) Flash Drive Having Locking Pins and Locking Grooves for Locking Swivel Cap - In one embodiment of the present invention a Universal Serial Bus (USB) flash drive with locking swivel cap includes a USB device, a swivel cap having a top swivel cap face and a bottom swivel cap face. The swivel cap is connectably attached to the USB device, four locking pins, two of which disposed on the top swivel cap face and two of which disposed on the bottom swivel cap face, two top locking grooves disposed on a top surface of the USB device, and two bottom locking grooves disposed on a bottom surface of the USB device, wherein the locking pins disposed on top swivel cap face coupled with the two top locking grooves and the locking pins disposed on the bottom swivel cap face couple with the two bottom locking grooves allowing the swivel cap to lock in fully open (180 degrees) and fully closed (0 degree). A USB connector is connected to the USB device to couple the USB flash drive to a host device. A fingerprint sensor area is disposed on the top side of the USB device, the fingerprint sensor scans fingerprints of a user of the portable flash drive with swivel cap and optional fingerprint verification capability, and allowing access to data stored on the portable flash drive with swivel cap and optional fingerprint verification capability. | 2008-11-06 |
20080276100 | Virtual Machine or Hardware Processor for Ic-Card Portable Electronic Devices - A virtual machine or hardware processor for an IC-card portable electronic device includes a non-volatile memory unit, a remote decryption unit, and associated objects for storing an executable program in an encrypted format in the non-volatile memory. The IC-card stores a licence key to encrypt and decrypt the executable program through an IC-card interface. The IC-card interface extracts and encrypts the operands of the plain executable program into encrypted operands so as to not limit performance. The remote decryption unit detects if an instruction contains encrypted operands, and queries a decryption to the IC-card interface. The IC-card interface decrypts the encrypted operands and re-encrypts the just decrypted operands into obscured operands through a dynamic obscuration key. | 2008-11-06 |
20080276101 | DIGITAL DATA RECORDING APPARATUS, DIGITAL DATA RECORDING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - A data communication unit receives encrypted digital data via a network and records the digital data on a primary recording medium. The digital data, having been encrypted in different encryption methods according to the distributors, include attribute information indicating the encryption methods. The encryption method of the digital data is determined and the encrypted data is decrypted by an appropriate decryption unit. Identification information of a secondary recording medium or a playback apparatus is obtained according to whether the secondary recording medium is removable from the playback apparatus. A controller selects an encryption unit among a plurality of encryption units according to the obtained identification information. The selected encryption unit creates an encryption key according to the identification information and re-encrypts the digital data. A recording unit records the digital data on the secondary recording medium. An accounting unit charges according to accounting information in the attribute information. | 2008-11-06 |
20080276102 | Data Protection Systems and Methods - Systems and methods are provided for protecting electronic content from the time it is packaged through the time it is experienced by an end user. Protection against content misuse is accomplished using a combination of encryption, watermark screening, detection of invalid content processing software and hardware, and/or detection of invalid content flows. Encryption protects the secrecy of content while it is being transferred or stored. Watermark screening protects against the unauthorized use of content. Watermark screening is provided by invoking a filter module to examine content for the presence of a watermark before the content is delivered to output hardware or software. The filter module is operable to prevent delivery of the content to the output hardware or software if it detects a predefined protection mark. Invalid content processing software is detected by a monitoring mechanism that validates the software involved in processing protected electronic content. Invalid content flows can be detected by scanning the information passed across system interfaces for the attempted transfer of bit patterns that were released from an application and/or a piece of content management software. | 2008-11-06 |
20080276103 | Universal serial bus assembly structure - A USB (Universal Serial Bus) assembly structure is composed of a power supply device, a lead wire, an electromagnetic wave elimination device, a power adapter, and a plug, wherein a side of the lead wire is provided with a USB power supply device, such that when a computer is not turned on or is hibernated, power can be still supplied by the USB power supply device. In addition, when a computer is not provided with enough USB slots, it is still convenient to supply the USB power. | 2008-11-06 |
20080276104 | Power source equiment for power over ethernet system with increased cable length - Increased cable length Power over Ethernet (PoE) systems are provided. Embodiments can be designed for compliance with IEEE 802.3af, IEEE 802.3at, or legacy PoE standards. Embodiments include PSE and PD designs enabled for increased length PoE. Embodiments include example modifications of IEEE 802.3af PSE system rules, including example modifications of PSE port voltage ranges to support IEEE 802.3af compliant PDs across increased cable lengths. Embodiments include example modifications of IEEE 802.3af PD system rules, including example modifications of PD port voltage ranges to enable current IEEE compliant PSEs to support increased cable length PoE. Embodiments include PDs having increased voltage process and/or added voltage protection circuitry to support increased length PoE. Modifications of PSE system rules and PD system rules can be performed independently of each others, so that modified PSEs can be made to work with existing PDs, or vice versa. | 2008-11-06 |
20080276105 | POWER MANAGERS FOR AN INTEGRATED CIRCUIT - A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands. | 2008-11-06 |
20080276106 | Data Conversion Apparatus and Data Conversion Method - It is aimed, for example, to reduce an amount of power consumption of an operation concerning data encryption or decryption and to make it difficult to perform a power analysis. In the case an exclusive OR operation between 32-bit input data and a 32-bit key is performed to obtain output data of 32 bits, the input data is kept in an input shift register | 2008-11-06 |
20080276107 | Method and Device to Wake-Up Nodes in a Serial Data Bus - A method of communication comprising sending communication signals switched between dominant and recessive values at clock intervals in frames over a serial data bus from at least one of a plurality of sending nodes to a plurality of receiving nodes. The receiving nodes have an operational state and a standby state in which the current consumption of the node is reduced compared to the operational state. The receiving nodes include wake-up trigger means for triggering transition from the standby state to the operational state in response to the communication signals. The frames of the transmitted signals include an identifier field during which the communication signal alternates between the dominant and recessive values in successive clock intervals with at least one significant occurrence during which the communication signal remains at one of the dominant and recessive values during at least two successive clock intervals, and the trigger means is selectively responsive to the position of the occurrence within the identifier field for triggering the transition from the standby state to the operational state. | 2008-11-06 |
20080276108 | METHOD AND SYSTEM FOR IMPLEMENTING GENERALIZED SYSTEM STUTTER - A method and system for implementing a generalized system stutter are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of blocking a first request received from a first of a plurality of bus masters during a low power state of a computing device for as long as permissible by the timing requirements of the computing device, wherein the first request is capable of triggering the computing device to transition out of the low power state, and during an active state of the computing device, servicing the first request along with other pending requests from the rest of the plurality of bus masters before the computing device transitions back to the low power state. | 2008-11-06 |
20080276109 | IMAGE DISPLAY DEVICE HAVING BACKLIGHT - An image display device | 2008-11-06 |
20080276110 | DISTRIBUTED POWER MANAGEMENT - A power management bus for controlling power over multiple device subsystems includes a master power bus controller which transmits power management information to control one or more power resources through a transmit interface. The transmitted information is received at one or more receive interfaces. A broadcast message can be transmitted to control multiple power resources by subsystem, resource group and resource type. A single address message can be transmitted to control a single power resource. A power down can be initiated at any of the receive interfaces. | 2008-11-06 |
20080276111 | Detecting Software Attacks By Monitoring Electric Power Consumption Patterns - Software attacks such as worms and viruses are detected in an electronic device by monitoring power consumption patterns. In a first embodiment, software attacks are detected by an increase in power consumption. The increased power consumption can be caused by increased network traffic, or by increased activity in the microprocessor. Monitoring power consumption is particularly effective for detecting DOS/flooding attacks when the electronic device is in an idle state. In a second embodiment, a power consumption signal is converted to the frequency domain (e.g., by fast Fourier transform). The highest amplitude frequencies are identified. Specific software attacks produce characteristic frequencies in the power consumption signal. Software attacks are therefore detected by matching the highest amplitude frequencies with frequencies associated with specific worms and viruses. Identification of a particular software attack typically requires matching of 3 or more of the highest amplitude frequencies, and, optionally, amplitude information. | 2008-11-06 |
20080276112 | SEMICONDUCTOR INTEGRATED CIRCUIT - A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay. | 2008-11-06 |
20080276113 | ELECTRONIC APPARATUS AND METHOD FOR CONTROLLING SAME - An electronic apparatus with a wireless unit includes a multiplier to receive a clock signal at a predetermined frequency. The electronic apparatus further includes a modulator configured to modulate the frequency of the clock signal generated by the multiplier, and a controller configured to change the frequency of the clock signal generated by the multiplier and a modulation rate of the modulation performed by the modulator according to a state of the electronic apparatus. | 2008-11-06 |
20080276114 | Micro-controller having USB control unit, MC unit and oscillating circuit commonly used by the USB control unit and the MC unit - A micro-controller includes a USB control unit, an MC unit having an operation mode and a stop mode and an oscillating circuit, which is commonly used by the USB control unit and the MC unit. The USB control unit includes a watching circuit for watching a condition of a first data and a second data, which is complement data of the first data. The operation of the oscillating circuit is controlled in response to an operation control signal, which is generated by a watching result, and an oscillation control signal whose voltage level is changed in response to the mode of the MC unit. | 2008-11-06 |
20080276115 | Power Optimization When Using External Clock Sources - Logic circuits of a digital device may be biased to operate over specific external clock frequency ranges by programming a desired clock oscillator frequency range into a configuration memory of the digital device. In addition, clock source selection may also be programmed into the configuration register. Bias circuits are then configured so that the internal logic of the digital device will operate over the desired clock oscillator frequency range. Non-volatile memory may be used to store the contents of the configuration memory so as to retain the configuration during power down of the digital device. The non-volatile memory may be programmable fuse links, electrically erasable and programmable memory (EEPROM), FLASH memory, etc. | 2008-11-06 |
20080276116 | Method and an Apparatus for Providing Timing Signals to a Number of Circuits, an Integrated Circuit and a Node - A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal before having received a timing signal from at least two nodes. In this manner, the direction of the timing skew between nodes and circuits is known and data transport between the circuits made easier. | 2008-11-06 |
20080276117 | END-TO-END TRANSACTIONAL PROTECTION FOR REQUESTS IN A WEB APPLICATION - Various embodiments of a system and method for processing a request in a distributed software application are disclosed. In response to a client request, one or more server computers may modify a plurality of different portions of state information. The system may operate to ensure that the portions of state information are all modified atomically. The system may also operate to provide transparent connection failover functionality for the network connection between the client computer and the one or more server computers. | 2008-11-06 |
20080276118 | AUTONOMICALLY ADJUSTING CONFIGURATION PARAMETERS FOR A SERVER WHEN A DIFFERENT SERVER FAILS - A load balancer detects a server failure, and sends a failure notification message to the remaining servers. In response, one or more of the remaining servers may autonomically adjust their configuration parameters, thereby allowing the remaining servers to better handle the increased load caused by the server failure. One or more of the servers may also include a performance measurement mechanism that measures performance before and after an autonomic adjustment of the configuration parameters to determine whether and how much the autonomic adjustments improved the system performance. In this manner server computer systems may autonomically compensate for the failure of another server computer system that was sharing the workload. | 2008-11-06 |
20080276119 | AUTONOMICALLY ADJUSTING CONFIGURATION PARAMETERS FOR A SERVER WHEN A DIFFERENT SERVER FAILS - A load balancer detects a server failure, and sends a failure notification message to the remaining servers. In response, one or more of the remaining servers may autonomically adjust their configuration parameters, thereby allowing the remaining servers to better handle the increased load caused by the server failure. One or more of the servers may also include a performance measurement mechanism that measures performance before and after an autonomic adjustment of the configuration parameters to determine whether and how much the autonomic adjustments improved the system performance. In this manner server computer systems may autonomically compensate for the failure of another server computer system that was sharing the workload. | 2008-11-06 |
20080276120 | Volume and failure management method on a network having a storage device - A SAN manager acquires configuration information from devices constituting a SAN and produces a corresponding relationship between a host computer and a virtual volume (virtual volume mapping) and a corresponding relationship between the host computer and a real volume (real volume mapping). Based on those pieces of mapping information, the SAN manager outputs a corresponding relationship between virtual and real volumes. Meanwhile, the failure notification messages received from the in-SAN devices are construed to detect and output an influence of the failure upon the access to a real or virtual volume. Furthermore, when receiving a plurality of failure notifications from the devices connected to the SAN, the plurality of failure notifications are outputted with an association based on the corresponding relationship between real and virtual volumes. | 2008-11-06 |
20080276121 | METHOD AND INFRASTRUCTURE FOR RECOGNITION OF THE RESOURCES OF A DEFECTIVE HARDWARE UNIT - A system and method of recognizing resources of a computer comprising a system serial number and a broken hardware unit comprising a non-volatile memory unit and enablement definition data relating to functions of the broken hardware unit, wherein the method comprises starting the computer; entering a serial number in a read/write non-volatile memory field of the non-volatile memory unit; reading the read/write non-volatile memory field; and matching the serial number of the read/write non-volatile memory field with the system serial number. The method may further comprise detecting failure of the broken hardware unit after the starting of the computer. Preferably, a reading that the serial number of the read/write non-volatile memory field matches with the system serial number permits acceptance of the enablement definition data of the broken hardware unit. | 2008-11-06 |
20080276122 | RESTORING THE FIRMWARE AND ALL PROGRAMMABLE CONTENT OF AN OPTICAL DRIVE - After an update of an optical drive with a new firmware or after any other event that changed content of non-volatile memory means of the optical drive it is possible that the user for any reason wants to restore the original operational condition of the optical drive. However, even after a re-flash with the old firmware there may arise the problem, that the original operational condition is not successfully restored. This in many cases is due to the fact, that a new firmware can also reprogram other programmable content in the optical drive which remains in the updated state, even after a re-flash. | 2008-11-06 |
20080276123 | AUTOMATION OF BARE METAL RECOVERIES - Completely recovering data stored on a hard disk or other computer-readable media of a computing system from scratch in an automated manner. Recovery information and post-restore customization data are stored on the backup medium that stores the backup of the computer-readable media of the computing system (e.g., operating system, application programs, user data, application data, etc.). The computing system is rebooted into a recovery environment where a recovery script automates the recovery of the backup. The recovery information and post-restore customization data are applied to the offline, recovered backup to ensure continuity. The computing system is rebooted into the recovered backup. | 2008-11-06 |
20080276124 | INCOMPLETE WRITE PROTECTION FOR DISK ARRAY - The embodiments of the invention provide methods of protecting data blocks while writing to a storage array, wherein storage units in the storage array include write logs. The data protection level of the write logs is equal to or greater than the data protection level of the storage units. Moreover, the write logs have metadata describing contents of the write logs, wherein the metadata include a sequence number identifying the age of the metadata. Each of the data blocks is a member of a parity group having addressable data blocks and first parity blocks. The addressable data blocks have at least one host data block and at least one associated data block. | 2008-11-06 |
20080276125 | Data Processing Method - The invention relates to a data processing method comprising generating meta-data for each data file stored by back-up servers of a set of back-up servers on a storage medium of a plurality of storage media. The meta-data of a data file comprises the file name of the data file, a content-specific identifier and an access path for the data file. The content-specific identifier relates to the data content comprised in the data file and the access path specifies on which storage medium on the plurality of storage media the data file is stored. The method further comprises storing the meta-data of each data file in a database, wherein the database enables the identification of data files having the same data content by use of the content-specific identifiers of the data files as these data files have identical content-specific identifiers. | 2008-11-06 |
20080276126 | Methods and Apparatus for Measuring Performance in Processing System - Techniques are disclosed for measuring performance in processing systems such as communications systems and computing systems. For example, a method of measuring performance in a processing system having a plurality of processing devices includes the following steps. A measurement system coupled to the plurality of processing devices generates an interrupt signal. The measurement system applies the interrupt signal to a set of processing devices under test, wherein the set of processing devices under test is selected from the plurality of processing devices, such that each processing device of the set under test makes data available to the measurement system. The available data represents data associated with the execution of at least one function performed by each processing device of the set under test. The measurement system obtains the available data and utilizes at least a portion of the available data to determine a measure of performance associated with each of the processing devices of the set under test. | 2008-11-06 |
20080276127 | Diagnostic and Trouble-Shooting Methods in a Wireless Control and Sensor Network - A method of performing diagnostics on a first hierarchical device operable within a building automation system is disclosed. The method includes compiling application code configured to control the first hierarchical device such that the application code includes a plurality of internal variables, providing a diagnostic module configured to monitor the plurality of internal variables, collecting internal variable diagnostic data related to the monitored plurality of internal variables, uploading the collected internal variable diagnostic data to a second hierarchical device, performing, at the second first hierarchical device, a layered diagnostic analysis on the internal variable diagnostic data, and identifying a first hierarchical device problem based on the analyzed internal variable diagnostic data. | 2008-11-06 |
20080276128 | Metrics independent and recipe independent fault classes - A method and apparatus for diagnosing faults. Process data is analyzed using a first metric to identify a fault. The process data was obtained from a manufacturing machine running a first recipe. A fault signature that matches the fault is identified. The identified fault signature was generated using a second metric and/or a second recipe. At least one fault class that is associated with the fault signature is identified. | 2008-11-06 |
20080276129 | SOFTWARE TRACING - Trace information is selectively generated for a software routine based on the perceived reliability of the software routine. The software routine includes at least one trace point having an active state and an inactive state. A previously-established reliability indicator for the software routine is read before the routine is executed. The reliability indicator is based on criteria such as age, prior level of testing, source, number or previously detected faults and/or number of prior successful executions. If the reliability indicator meets a predetermined threshold, the active state is selected for the trace point. If the reliability indicator does not meet the predetermined threshold, the inactive state is selected for the trace point. | 2008-11-06 |
20080276130 | DISTRIBUTED LOGGING APPARATUS SYSTEM AND METHOD - An apparatus, system, and method are disclosed for distributed logging. Operating entities and associations between operating entities are registered in a registry by a logging entity registrar. An event notification monitor recognizes operating errors in operating entities. An aggregation module aggregates operating logs from sets of associated entities, which are then stored by a log set recorder. | 2008-11-06 |