45th week of 2020 patent applcation highlights part 51 |
Patent application number | Title | Published |
20200349961 | SYSTEMS AND METHODS FOR ADJUSTING DUBBED SPEECH BASED ON CONTEXT OF A SCENE - Systems and methods are disclosed herein for detecting dubbed speech in a media asset and receiving metadata corresponding to the media asset. The systems and methods may determine a plurality of scenes in the media asset based on the metadata, retrieve a portion of the dubbed speech corresponding to the first scene, and process the retrieved portion of the dubbed speech corresponding to the first scene to identify a speech characteristic of a character featured in the first scene. Further, the systems and methods may determine whether the speech characteristic of the character featured in the first scene matches the context of the first scene, and if the match fails, perform a function to adjust the portion of the dubbed speech so that the speech characteristic of the character featured in the first scene matches the context of the first scene. | 2020-11-05 |
20200349962 | AUDIO SIGNAL PROCESSING FOR NOISE REDUCTION - A headphone, headphone system, and speech enhancing method is provided to enhance speech pick-up from the user of a headphone and includes receiving a plurality of signals from a set of microphones and generating a primary signal by array processing the microphone signals to steer a beam toward the user's mouth. A noise reference signal is also derived from one or more microphones via a delay-and-sum technique, and a voice estimate signal is generated by filtering the primary signal to remove components that are correlated to the noise reference signal. | 2020-11-05 |
20200349963 | ECHO CANCELLATION SYSTEM AND METHOD OF MULTICHANNEL SOUND MIXING - The invention provides an echo cancellation system and method of a multichannel sound mixing. The echo cancellation system comprises a voice assistant module and at least one signal generating device for respectively outputting first audio data and second audio data adapted to the configuration of a loudspeaker; a copying module for copying the first audio data and the second audio data to obtain corresponding third audio data and fourth audio data; a first sound mixing module for mixing and converting the first audio data and the second audio data to obtain two-channel first sound mixing data; a second sound mixing module for mixing the third audio data and the fourth audio data to obtain second sound mixing data; an echo cancellation module for echo cancellation according to the first sound mixing data; and a playing module for receiving and playing the second sound mixing data. | 2020-11-05 |
20200349964 | DETECTION AND SUPPRESSION OF KEYBOARD TRANSIENT NOISE IN AUDIO STREAMS WITH AUX KEYBED MICROPHONE - Provided are methods and systems for enhancing speech when corrupted by transient noise (e.g., keyboard typing noise). The methods and systems utilize a reference microphone input signal for the transient noise in a signal restoration process used for the voice part of the signal. A robust Bayesian statistical model is used to regress the voice microphone on the reference microphone, which allows for direct inference about the desired voice signal while marginalizing the unwanted power spectral values of the voice and transient noise. Also provided is a straightforward and efficient Expectation-maximization (EM) procedure far fast enhancement of the corrupted signal. The methods and systems are designed to operate easily in real-time on standard hardware, and have very low latency so that there is no irritating delay in speaker response. | 2020-11-05 |
20200349965 | AUDIO ENHANCEMENT THROUGH SUPERVISED LATENT VARIABLE REPRESENTATION OF TARGET SPEECH AND NOISE - Systems and methods for generating an enhanced audio signal comprise a trained neural network configured to receive an input audio signal and generate an enhanced target signal, the trained neural network comprising a pre-processing neural network configured to receive a segment of the input audio signal and output an audio classification, the pre-processing neural network including at least one hidden layer comprising an embedding vector, and a noise reduction neural network configured to receive the segment of the input audio signal, and the embedding vector and generate the enhanced target signal. The pre-processing neural network may comprise a target signal pre-processing neural network configured to output a target signal classification and comprising at least one hidden layer comprising a target embedding vector. The pre-processing neural network may comprise a noise pre-processing neural network configured output a noise classification and comprising at least one hidden layer comprising a noise embedding vector. | 2020-11-05 |
20200349966 | HOT-WORD FREE ADAPTATION OF AUTOMATED ASSISTANT FUNCTION(S) - Hot-word free adaptation of one or more function(s) of an automated assistant. Sensor data, from one or more sensor components of an assistant device that provides an automated assistant interface (graphical and/or audible), is processed to determine occurrence and/or confidence metric(s) of various attributes of a user that is proximal to the assistant device. Whether to adapt each of one or more of the function(s) of the automated assistant is based on the occurrence and/or the confidence of one or more of the various attributes. For example, certain processing of at least some of the sensor data can be initiated, such as initiating previously dormant local processing of at least some of the sensor data and/or initiating transmission of at least some of the audio data to remote automated assistant component(s). | 2020-11-05 |
20200349967 | MAGNETIC RECORDING DEVICES AND METHODS USING A WRITE-FIELD-ENHANCEMENT STRUCTURE AND BIAS CURRENT WITH OFFSET PULSES - Disclosed herein are magnetic recording devices and methods of using them. A magnetic recording device comprises a main pole extending to an air-bearing surface (ABS), a trailing shield extending to the ABS, a write-field-enhancing structure disposed between and coupled to the main pole and the trailing shield at the ABS, a write coil configured to magnetize the main pole, a write current control circuit coupled to the write coil and configured to apply a write current to the write coil, wherein the write current comprises a write pulse, and a bias current control circuit coupled to the write-field-enhancing structure and configured to apply a bias current to the write-field-enhancing structure, wherein the bias current comprises a driving pulse offset in time from the write pulse by a delay, wherein the delay substantially coincides with an expected magnetization switch-time lag of a free layer of the write-field-enhancing structure. | 2020-11-05 |
20200349968 | MAMR Writer With Low Resistance MAMR Stack - The present disclosure generally relates to a magnetic media drive employing a magnetic recording head. The head includes a main pole at a media facing surface (MFS), a trailing shield at the MFS, and a MAMR stack disposed between the main pole and the trailing shield at the MFS. The MAMR stack includes a seed layer and at least one magnetic layer. The seed layer is fabricated from a thermally conductive material having electrical resistivity lower than that of the main pole. The seed layer has a stripe height greater than a stripe height of the at least one magnetic layer. With the extended seed layer, the bias current from the trailing shield to the main pole spreads further away from the MFS along the extended seed layer before flowing into the main pole, reducing temperature rise at or near the MAMR stack, leading to improved write head reliability. | 2020-11-05 |
20200349969 | DATA STORAGE DEVICES WITH INTEGRATED SLIDER VOLTAGE POTENTIAL CONTROL - Disclosed herein is a data storage device comprising a recording media, a slider comprising a write head having a write-field enhancement structure for recording data to the recording media, an electronics module, and a plurality of lines disposed between and coupled to the slider and the electronics module, wherein at least one line of the plurality of lines is configured to both couple a bias voltage to a body of the slider, and carry a bias current for the write-field enhancement structure. Also disclosed herein is a data storage device comprising a slider with an embedded contact sensor, an electronics module, and a plurality of lines disposed between and coupled to the slider and the electronics module, wherein at least one line of the plurality of lines is configured to both couple a bias voltage to a body of the slider, and provide a signal to the embedded contact sensor. | 2020-11-05 |
20200349970 | Multi-Layer Microactuators For Hard Disk Drive Suspensions - A multi-layer microactuator for a hard disk drive suspension includes a piezoelectric (“PZT”) layer, a constraining layer, a lower electrode layer, a middle electrode layer, and an upper electrode layer. The lower electrode layer is on a bottom surface of the PZT layer and includes a first lower electrode island, a second lower electrode island, and a third lower electrode island. The second lower electrode island includes a finger extending from a main body portion towards a first end of the PZT layer. The middle electrode layer is disposed between a top surface of the PZT layer and a bottom surface of the constraining layer. The middle electrode layer including a first middle electrode island and a second middle electrode island, the second middle electrode island including a finger extending from a main body portion towards the first end of the PZT layer. | 2020-11-05 |
20200349971 | MAGNETIC HEADS FOR USE IN DIFFERENT FLUID ATMOSPHERES, AND RELATED METHODS - Described are magnetic recording heads that include an air-bearing surface and that are designed to be useful or potentially useful in two or more different types of fluid atmospheres; also described are related methods of testing the magnetic recording heads and installing the magnetic recording heads in a hard disk drive, as well as hard disk drives that contain a magnetic recording head as described. | 2020-11-05 |
20200349972 | GENERATION OF MEDIA DIFF FILES - A method is disclosed in which first payload data included in a first file container and second payload data included in a second file container are determined. The first payload data is decoded to determine first un-encoded data representing first content, and the second payload data is decoded to determine second un-encoded data representing second content. At least one difference is determined between the first un-encoded data and the second un-encoded data, and third un-encoded data corresponding to the at least one difference is determined. The third un-encoded data is encoded to generate third payload data representing third content, and a third file container is generated that includes the third payload data. | 2020-11-05 |
20200349973 | SYSTEM FOR GENERATING AN OUTPUT FILE - A system for creating an output comprises a processing unit, a user input module operably connected to the processing unit, and a video monitor operably connected to the processing unit. The processing unit provides on the video monitor: a grid image comprising multiple cells, each cell representing a duration of time; and a selection area comprising multiple select icons, each select icon representing a source data file. The processing unit is configured such that a user can create a grid layout representing the correlation between individual selected source data files and one or more of the multiple cells. The processing unit produces the output based on the correlation. | 2020-11-05 |
20200349974 | SYSTEMS AND METHODS FOR EDITING A VIDEO - The present disclosure relates to systems and methods for editing a video. The method may include obtaining a video document including audio information. The method may also include processing the audio information to identify at least one desired audio segment of the audio information that has at least one desired acoustic feature representation. Further, the method may include editing the video document to generate a video abstraction at least based on the identified at least one desired audio segment of the audio information. | 2020-11-05 |
20200349975 | VIDEO TAGGING BY CORRELATING VISUAL FEATURES TO SOUND TAGS - Automatically recommending sound effects based on visual scenes enables sound engineers during video production of computer simulations, such as movies and video games. This recommendation engine may be accomplished by classifying SFX and using a machine learning engine to output a first of the classified SFX for a first computer simulation based on learned correlations between video attributes of the first computer simulation and the classified SFX. | 2020-11-05 |
20200349976 | MOVIES WITH USER DEFINED ALTERNATE ENDINGS - User engagement with movies is increased by enabling users to use their own vision, imagination, and creativity to generate user created alternate endings and/or sequences. In the context of movies presented through computer simulation consoles, the simulation community activity can be enhanced by providing the option of sharing user-customized creations as well as watching (and possibly rating) other user's creations. | 2020-11-05 |
20200349977 | POINT OF VIEW VIDEO PROCESSING AND CURATION PLATFORM - Embodiments of the present disclosure may provide methods and systems enabled to perform the following stages: receiving a plurality of content streams; retrieving metadata associated with each of the plurality of content streams; processing the metadata to detect at least one target annotation within at least one target content stream; retrieving telemetry data associated with the at least one target content stream; processing the telemetry data and the metadata associated with a plurality of frames in the at least one target content stream to ascertain vector motion data; and mapping a spatial relationship associated with at least one capturing device associated with at least one target content source. | 2020-11-05 |
20200349978 | SYSTEM AND METHODS FOR CONCATENATING VIDEO SEQUENCES USING FACE DETECTION - There are provided methods and devices for media processing, comprising: providing at least one media asset source selected from a media asset sources library, the at least one media asset source comprising at least one source video, via a network or client device; receiving via the network or the client device a media recording comprising a client video recorded by a user of the client device; parsing the client video and the source video, respectively, to a plurality of client video frames and a plurality of source video frames; identifying at least one face in at least one frame of the plurality of source video frames and at least another face in at least one frame of the plurality of client video frames by face detection; superposing one or more markers on the identified at least one face of the plurality of source video frames; processing said client video frames to fit the size or shape of said source video frames by using said one or more markers; concatenating said processed client video frames with said source video frames, wherein said concatenation comprises matching the frame rate and resolution of the processed client video frames to the frame rate and resolution of the plurality of client video frames to yield a mixed media asset. | 2020-11-05 |
20200349979 | SYSTEMS AND METHODS FOR PRODUCING ANNOTATED CLASS DISCUSSION VIDEOS INCLUDING RESPONSIVE POST-PRODUCTION CONTENT - Video production systems and methods are provided for generating annotated class discussion videos, which contain real-time student commentary post-production annotations responsive to such student commentary, or a combination thereof. In an embodiment, the video production system includes a display device, a dedicated video input source, and a video processing device. The video processing device contains, in turn, a wireless receiver configured to receive wireless input signals from the dedicated video input source and a plurality of devices executing a student commentary capture application during a presentation, a controller operably coupled to the wireless receiver, and a memory storing computer-readable instructions. When executed by the controller, the computer-readable instructions cause the video processing device to generate an output video containing student commentary synchronized with the presentation as captured, at least in part, utilizing the dedicated video input source. The output video is then presented on the display device. | 2020-11-05 |
20200349980 | Audio Sample Playback Unit - Disclosed herein are a number of example embodiments for an improved audio sample playback unit. For example, multi-dimensional mapping of triggers to audio samples is disclosed. Also disclosed is low latency retrieval and playback of audio samples via pre-loading of sample heads into high speed memory. Furthermore, disclosed herein is a multi-threaded control operation for generating audio frames in response to trigger inputs, as well as the use of multiple pipes from which audio data can be generated. Further still, an example embodiment provides for multi-level control of audio properties, including voice-specific controls, pipe-specific controls, and global controls. | 2020-11-05 |
20200349981 | ELECTRONIC DEVICE AND METHOD FOR REPRODUCING A HUMAN PERCEPTUAL SIGNAL - The method of reproducing a human perceptual signal comprises the steps of selecting ( | 2020-11-05 |
20200349982 | HAPTIC EFFECT GENERATION FOR SPACE-DEPENDENT CONTENT - Systems and methods for authoring and encoding haptic effects are provided for space-dependent content, such as 360-degree videos, three-dimensional videos, or virtual or augmented reality contents. The systems and methods can generate one or more haptic layers for encoding or modifying haptic effects for the content. | 2020-11-05 |
20200349983 | MULTI-COLUMN INTERLEAVED DIMM PLACEMENT AND ROUTING TOPOLOGY - In one embodiment, a printed circuit board (PCB) has a first central processing unit (CPU) socket and a second CPU socket substantially in line with the first CPU socket, and also has a first plurality of dual in-line memory module (DIMM) sockets interconnected with the first CPU socket and a second plurality of DIMM sockets interconnected with the second CPU socket (in a direction parallel to the first plurality of DIMM sockets). The first plurality of DIMM sockets are arranged on the PCB in at least a first column and a second column of DIMM sockets, and the second plurality of DIMM sockets are arranged on the PCB in at least the second column and a third column of DIMM sockets, such that the second column of DIMM sockets contains interleaved DIMM sockets from each of the first plurality of DIMM sockets and the second plurality of DIMM sockets. | 2020-11-05 |
20200349984 | SEMICONDUCTOR PACKAGE CONFIGURATION FOR REDUCED VIA AND ROUTING LAYER REQUIREMENTS - Semiconductor packages are mounted opposite one another across a printed circuit board, where one of the packages is configured with a mirrored pin assignment of the other. | 2020-11-05 |
20200349985 | PAGE BUFFER AND MEMORY DEVICE INCLUDING THE SAME - A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer. | 2020-11-05 |
20200349986 | NON-VOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME - A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal. | 2020-11-05 |
20200349987 | MEMORY SYSTEM AND METHOD OF OPERATING THE MEMORY SYSTEM - The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller configured to generate a command for controlling the memory device and output the command to the memory device. The interface circuit receives the command, transmits the received command to the semiconductor memory when the received command corresponds to the semiconductor memory, and performs a training operation of the interface circuit when the received command corresponds to the interface circuit and the received command is a specific command. | 2020-11-05 |
20200349988 | DATA TRANSMISSION CODE AND INTERFACE - A data transmission interface for use in a first integrated circuit, for encoding and sending a data packet from the first IC to a second IC via a data bus having three data wires, the data transmission interface being arranged to generate three time-dependent binary signals which jointly encode the data packet, each of the signals being associated with a unique data wire of the data bus and spanning a temporal cycle T within which are defined six consecutive time stamps T | 2020-11-05 |
20200349989 | SEMICONDUCTOR DEVICE AND MEMORY SYSTEM - According to one embodiment, in a semiconductor device, the first pull-up circuit is connected to a third node and to a fourth node. The third node is a node between a drain of the first transistor with a first conductivity type and a source of the second transistor with the first conductivity type. The fourth node is a node between a drain of the third transistor with the first conductivity type, and a source of the fourth transistor with the first conductivity type and a source of the fifth transistor with the first conductivity type. The first pull-down circuit is connected to a fifth node and to a sixth node. The fifth node is a node between a drain of the first transistor with a second conductivity type and a source of the second transistor with the second conductivity type. The sixth node is a node between a drain of the third transistor with the second conductivity type and a source of the fourth transistor with the second conductivity type and a source of the fifth transistor with the second conductivity type. | 2020-11-05 |
20200349990 | FX DRIVER CIRCUIT - A FX phase driver for a memory device having a first driver circuit including a first pull-up circuit configured to drive a first phase signal to a first high state value and a first pull-down circuit configured to drive the first phase signal to a first low state value. The phase driver also including a second driver circuit including a second pull-up circuit configured to drive a second phase signal to a second high state value that is higher than an active state voltage level of a word line in the memory device and a second pull-down circuit configured to drive the second phase signal to a second low state value. The second pull-down circuit includes a stabilization circuit configured to provide a resistive path for a leakage current in the second pull-down circuit when the second pull-up circuit drives the second phase signal to the second high state value. | 2020-11-05 |
20200349991 | MEMORY CONTROL COMPONENT WITH INTER-RANK SKEW TOLERANCE - In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends. | 2020-11-05 |
20200349992 | NARROW ETCHED GAPS OR FEATURES IN MULTI-PERIOD THIN-FILM STRUCTURES - Multi-period thin-film structures exhibiting giant magnetoresistance (GMR) are described. Techniques are also described by which narrow spacing and/or feature size may be achieved for such structures and other thin-film structures having an arbitrary number of periods. | 2020-11-05 |
20200349993 | SEMICONDUCTOR DEVICE - A semiconductor device of the present disclosure includes: a first gate electrode that includes a first main line section and one or a plurality of first sub line sections, in which the first main line section extends in a first direction in a first active region of a semiconductor substrate, and segments the first active region into a first region and a second region, and the one or the plurality of first sub line sections extends from the first main line section in a second direction intersecting the first direction in the first region, and segments the first region into a plurality of sub regions including a first sub region and a second sub region; a first memory element that includes a first terminal, and a second terminal coupled to the first sub region of the semiconductor substrate, and is configured to be set in a first resistive state or a second resistive state; and a second memory element that includes a first terminal, and a second terminal coupled to the second sub region of the semiconductor substrate, and is configured to be set in the first resistive state or the second resistive state. | 2020-11-05 |
20200349994 | SEMICONDUCTOR STRUCTURES, MEMORY CELLS AND DEVICES COMPRISING FERROELECTRIC MATERIALS, SYSTEMS INCLUDING SAME, AND RELATED METHODS - A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed. | 2020-11-05 |
20200349995 | APPARATUSES AND METHODS FOR MANAGING ROW ACCESS COUNTS - Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells. | 2020-11-05 |
20200349996 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. | 2020-11-05 |
20200349997 | MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT - An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path. | 2020-11-05 |
20200349998 | MAIN WORD LINE DRIVER CIRCUIT - A main word line circuit provides a first and second row factor signals. The main word line circuit includes a pull-up circuit to drive a global word line to follow a first decoded address signal when the first row factor signal is at a first value. The main word line circuit includes an intermediate voltage circuit to drive the global word line to follow a value of the second row factor signal. A processing device drives the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drives the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state. | 2020-11-05 |
20200349999 | DRAM ARRAY ARCHITECTURE WITH ROW HAMMER STRESS MITIGATION - An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line. | 2020-11-05 |
20200350000 | EFUSE MEMORY CELL AND EFUSE MEMORY, AND WRITE/READ METHODS THEREOF - The present disclosure provides an efuse memory cell, an efuse memory, and their write/read methods. The efuse memory cell has a write bit line terminal, a read bit line terminal, a read word line terminal, and a write word line terminal. The efuse memory cell further includes: an electric fuse, having a first terminal connecting to the write bit line terminal and a second terminal; a first control transistor, having a first terminal connecting to the second terminal of the electric fuse, a second terminal connecting to the read bit line terminal, and a control terminal connecting to the read word line terminal; and a second control transistor, having a first terminal connecting to the second terminal of the electric fuse, a second terminal which is a ground terminal, and a control terminal connecting to the write word line terminal. | 2020-11-05 |
20200350001 | SEMICONDUCTOR DEVICES - A semiconductor device includes a command decoder and a period signal generation circuit. The command decoder generates a first entry command and a first exit command based on a first internal chip selection signal and a first internal control signal and generates a second entry command and a second exit command based on a second internal chip selection signal and a second internal control signal. The period signal generation circuit generates a period signal based on the first entry command, the second entry command, the first exit command, the second exit command, and the period signal. | 2020-11-05 |
20200350002 | Static Power Reduction in SRAM - A circuit for reducing static power in SRAM and methods for using the same are disclosed. In one embodiment, a circuit for reducing static power in SRAM includes a plurality of memory blocks, where a memory block in the plurality of memory blocks includes a plurality memory banks, where a memory bank in the plurality of memory banks includes a plurality bit cells. The circuit further includes a bias circuit configured to produce a bias voltage to a row of bit cells, where the bias circuit is coupled to a circuit ground terminal of the row of bit cells in the plurality of bit cells, and a controller configured to control the bias circuit to produce a first set of bias settings in an access mode and control the bias circuit to produce a second set of bias settings in a standby mode of the SRAM. | 2020-11-05 |
20200350003 | Signal Communication Circuit Implementing Receiver and Trasmitter Circuits - A signal communication circuit and methods for using the same are disclosed. In one embodiment, a circuit for signal communication includes a signal line configured to transmit signals, a transmitter circuit configured to drive a transmitted signal onto the signal line, a receiver circuit configured to detect the transmitted signal based on a deviation of a received signal from a reference signal on the signal line, and the receiver circuit is further configured to use the received signal to communicate the transmitted signal. | 2020-11-05 |
20200350004 | Dynamic Power Reduction in SRAM - A circuit for reducing dynamic power in SRAM and methods for using the same are disclosed. In one embodiment, a circuit for reducing dynamic power in SRAM includes a plurality of memory blocks, which includes a plurality memory banks, which in turn includes a plurality bit cells; a set of memory bank signal lines; a set of memory block signal lines shared across the plurality of memory banks in the memory block; a bridge circuit couple between the set of memory bank signal lines and the set of memory block signal lines; a set of sense amplifiers corresponding to the set of memory block signal lines, where the set of sense amplifiers are shared among the plurality of memory banks in the memory block; and a controller configured to control an access of one or more bit cells in the plurality bit cells. | 2020-11-05 |
20200350005 | SERIALIZED SRAM ACCESS TO REDUCE CONGESTION - A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A memory array is configured to receive each of the plurality of serialized input signals. The memory array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width. | 2020-11-05 |
20200350006 | JOSEPHSON MEMORY AND LOGIC CIRCUITS USING QUASI-LONG-JUNCTION INTERCONNECT - A Josephson memory array and logic circuits use quasi-long-Josephson-junction interconnects to propagate signals at fast speeds and low energy expense, while permitting for memory arrays as dense fabrics of relatively simple unit cell sub-circuits, which include π Josephson junctions, connected together by the interconnects. Each of the unit cell sub-circuits can be configured as a looped or linear arrangement. The unit cell sub-circuits and interconnects provide a fast, dense memory technology for reciprocal quantum logic (RQL), suitable for low-level caches and other memories collocated with an RQL processor. | 2020-11-05 |
20200350007 | Multi-State Programming for Memory Devices - Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device. | 2020-11-05 |
20200350008 | ELECTRONIC DEVICE AND OPERATING METHOD OF ELECTRONIC DEVICE - A semiconductor memory includes bit lines, word lines, memory cells coupled between the bit lines and the word lines, and a sensing circuit configured to sense a state of a selected memory cell. During a read operation of the selected memory cell, the electronic device is configured to precharge a selected word line to a first voltage, to precharge an unselected word line to a second voltage, to float the selected word line and the unselected word line, to apply a bit line voltage a selected bit line, to adjust a voltage level of the unselected word line using a first leakage current that flows between an unselected bit line and the unselected word line, to couple the selected word line and the unselected word line to the sensing circuit, and to compare a voltage level of the selected word line with the voltage level of the unselected word line. | 2020-11-05 |
20200350009 | ELECTRONIC DEVICE AND METHOD OF OPERATING THE ELECTRONIC DEVICE - An electronic device includes a semiconductor memory. The semiconductor memory includes a bit line, a word line crossing the bit line, and a memory cell coupled to and disposed between the bit line and the word line. In a read operation, when the word line, which is in a precharged state, is floated, the bit line is driven to increase a voltage level of the bit line, and stopped when the memory cell is turned on. | 2020-11-05 |
20200350010 | RESISTIVE MEMORY DEVICE WITH TRIMMABLE DRIVER AND SINKER AND METHOD OF OPERATIONS THEREOF - A device is disclosed. The device includes a first memory cell, a second memory cell, a first pair of a driver and a sinker, and a second pair of a driver and a sinker. The first memory cell is coupled between the first pair of the driver and the sinker through a first line and a second line. The second memory cell is coupled between the second pair of the driver and the sinker through a third line and a fourth line. The first pair of the driver and the sinker are configured to be controlled to have resistances depending on a row location of the first memory cell in a memory column. | 2020-11-05 |
20200350011 | SUB-WORD LINE DRIVER CIRCUIT - A sub-word line circuit having a phase driver circuit to provide a first phase signal and a second phase signal. The sub-word line circuit includes a sub-word line driver circuit having a pull-up circuit configured to receive the first phase signal and a global word line signal. The pull-circuit is further configured to drive a local word line to follow the global word line signal when the first phase signal is at a first value and isolate the local word line from the global word line signal when the first phase signal is at a second value. The sub-word line circuit also includes a processing device that sets the first phase signal to the first value prior to the global word line signal entering an active state and sets the first phase signal to the second value only after the global word line signal has entered a pre-charge state. | 2020-11-05 |
20200350012 | NON-VOLATILE MEMORY DEVICE AND METHOD OF WRITING TO NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes: a memory group of a plurality of variable resistance memory cells in which digital data is recorded according to a magnitude of a resistance value, the memory group including at least one data cell and at least one dummy cell which are associated with each other; and a read circuit which performs, in parallel, a read operation on each of the plurality of memory cells included in the memory group. Dummy data, for reducing a correlation between a side-channel leakage generated when the read operation is performed by the read circuit and information data recorded in the at least one data cell, is recorded in the at least one dummy cell. | 2020-11-05 |
20200350013 | RESISTIVE MEMORY APPARATUS AND OPERATING METHOD THEREOF - A resistive memory apparatus and an operating method thereof are provided. In the method, a set operation having a first enhanced bias is performed on at least one memory cell in a resistive memory array of the resistive memory apparatus, in which the first enhanced bias is larger than a bias used in a normal execution of the set operation. A heat process is performed on the memory cell. A set operation having a second enhanced bias is performed on the memory cell, in which the second enhanced bias is larger than or equal to the first enhanced bias. | 2020-11-05 |
20200350014 | THREE-DIMENSIONAL MEMORY DEVICE WITH EMBEDDED DYNAMIC RANDOM-ACCESS MEMORY - Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including a peripheral circuit, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also further includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. The 3D memory device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface. | 2020-11-05 |
20200350015 | TEMPERATURE COMPENSATION FOR MEMORY CELLS IN AN ANALOG NEURAL MEMORY SYSTEM USED IN A DEEP LEARNING NEURAL NETWORK - Numerous embodiments are disclosed for providing temperature compensation in a an analog memory array. The analog memory array optionally is a vector-by-matrix multiplier in an analog neuromorphic memory system used in a deep learning neural network. One embodiment comprises measuring an operating temperature within a memory array and applying, by a temperature compensation block, a bias voltage to a terminal of a memory cell in the array, wherein the bias voltage is a function of the operating temperature. | 2020-11-05 |
20200350016 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring. | 2020-11-05 |
20200350017 | STORAGE DEVICE, CONTROLLER AND METHOD FOR OPERATING CONTROLLER - The disclosure relates to a storage device, a controller and a method for operating a controller. The controller described in embodiments of the disclosure may include a word line grouping circuit configured to group a plurality of word lines in a semiconductor memory device into a plurality of word line groups based on program time information on program times of the respective word lines. Also, the controller may include a super page configuration circuit configured to configure a plurality of super pages including some of the word lines, based on word line group information on the word line groups. Embodiments of the disclosure may provide a storage device, a controller and a method for operating a controller, capable of minimizing program performance degradation that may occur due to deviations in program time among word lines. | 2020-11-05 |
20200350018 | NON-VOLATILE MEMORY DEVICE - A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage. | 2020-11-05 |
20200350019 | NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop. | 2020-11-05 |
20200350020 | MEMORY DEVICE HAVING IMPROVED DATA RELIABILITY AND METHOD OF OPERATING THE SAME - A memory device includes: a memory cell region; a peripheral circuit region; a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline. | 2020-11-05 |
20200350021 | APPARATUS AND METHODS FOR PROGRAMMING MEMORY CELLS USING MULTI-STEP PROGRAMMING PULSES - Memories having a controller configured to apply a particular multi-step programming pulse to a selected access line of a programming operation, enable for programming memory cells that have a particular desired data state for the programming operation and are deemed to have a threshold voltage lower than a first threshold voltage level while applying a first step of a multi-step programming pulse to the selected access line, and enable for programming memory cells that have the particular desired data state for the programming operation and are deemed to have a threshold voltage lower than a second threshold voltage level and higher than the first threshold voltage level while applying a second step of the multi-step programming pulse, lower than the first step of the multi-step programming pulse, to the selected access line. | 2020-11-05 |
20200350022 | STORAGE DEVICE AND METHOD OF OPERATING THE SAME - Provided herein is a method of operating a memory device configured to perform a program operation on a first memory cell coupled to a selected word line. The method includes determining, after the program operation on the first memory cell has been performed, whether a threshold voltage of a second memory cell coupled to a same bit line to which the first memory cell is coupled and coupled to a word line adjacent to the selected word line corresponds to an erased status. The method also includes applying to the first memory cell, when the threshold voltage of the second memory cell corresponds to the erased status, an additional program voltage higher by a preset voltage than a program voltage last applied during the program operation. | 2020-11-05 |
20200350023 | MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME - The memory controller may include a command generator generating and outputting first and second read commands to a memory device so that respective first and second read operations are performed using a first read voltage, a calculator receiving first and second read data in response to the read commands, comparing the first and second read data each other, and calculating a number of first inverted cells and a number of second inverted cells based on a result of the comparing, each of the first inverted cells having a bit value that inverted from a first bit value to a second bit value, and each of the second inverted cells having a bit value that inverted from the second bit value to the first bit value, and a read voltage determiner changing the first read voltage depending on the number of first inverted cells and the number of second inverted cells. | 2020-11-05 |
20200350024 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater. | 2020-11-05 |
20200350025 | Data Storage Systems and Methods for Improved Recovery After a Write Abort Event - Apparatus, media, methods, and systems for data storage systems and methods for improved recovery after a write abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device. | 2020-11-05 |
20200350026 | PEAK CURRENT MANAGEMENT IN A MEMORY ARRAY - An electronic device comprises a multi-chip package including multiple memory dice that include a memory array, charging circuitry, polling circuitry and a control unit. The charging circuitry is configured to perform one or more memory events in a high current mode using a high current level or in a low current mode using a lower current level. The polling circuitry is configured to poll a power status node common to the multiple memory dice to determine availability of the high current mode. The control unit is configured to operate the charging circuitry in the high current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is available, and operate the charging circuitry in the low current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is unavailable. | 2020-11-05 |
20200350027 | MEMORY SYSTEM CAPABLE OF REDUCING THE READING TIME - A bias circuit includes a charging current reproduce unit, a cell current reproduce unit, a current comparator, and a bit line bias generator. The charging current reproduce unit generates a charging reference voltage according to a charging current flowing through a voltage bias transistor. The cell current reproduce unit generates a cell reference voltage according to a cell current flowing through a common source transistor. The current comparator includes a first current generator for generating a replica charging current according to the charging reference voltage, and a second current generator for generating a replica cell current according to the cell reference voltage. The bit line bias generator generates a bit line bias voltage to control a page buffer for charging a bit line according to a difference between the replica charging current and the replica cell current. | 2020-11-05 |
20200350028 | METHOD AND SYSTEM FOR REDUCING PROGRAM DISTURB DEGRADATION IN FLASH MEMORY - Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates. | 2020-11-05 |
20200350029 | NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition. | 2020-11-05 |
20200350030 | Multi-Bit-Per-Cell Three-Dimensional Resistive Random-Access Memory (3D-RRAM) - The present invention discloses a multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAM | 2020-11-05 |
20200350031 | ONE-TIME PROGRAMMABLE MEMORIES WITH LOW POWER READ OPERATION AND NOVEL SENSING SCHEME - A time-based sensing circuit to convert resistance of a one-time programmable (OTP) element into logic states is disclosed. A one-time programmable (OTP) memory has a plurality of OTP devices. At least one of the OTP devices can have at least one OTP element that is selectively accessible via a wordline and a bitline. The bitline can be coupled a capacitor and the capacitor can be precharged and discharged. By comparing the discharge rate of the capacitor to discharge rate of a reference capacitor in a reference unit (e.g., reference cell, reference resistance, reference selector, etc.), the PRE resistance can be determined larger or smaller than a reference resistance and then converting the OTP element resistance into a logic state. | 2020-11-05 |
20200350032 | DATA AND MEMORY REORGANIZATION - A method and system for improving data and memory reorganization and storage technology is provided. The method includes configuring data capture and analysis settings of a database system resulting in configured data capture settings. A data and associated memory analysis request is received and specified test code is selected. A specified portion of data and associated memory is selected and the specified analysis code is executed resulting in execution of said specified type of analysis with respect to the specified portion of said data and associated memory. The specified portion of said data and associated memory is modified and stored. | 2020-11-05 |
20200350033 | MEMORY CONTROLLER AND MEMORY SYSTEM HAVING THE SAME - There are provided a memory controller and a memory system having the same. A memory controller includes: an internal memory for storing error injection information for an error test operation and error test information that is a result of the error test operation; and a central processing unit for receiving first sector data from a host, and performing an error test operation on a memory device according to the error injection information, when the error injection information is included in the first sector data. | 2020-11-05 |
20200350034 | Method for Non-Invasive Prenatal Testing Using Parental Mosaicism Data - Provided herein are methods for determining the ploidy state of one or more chromosome in a developing fetus. The subject methods provide for increase accuracy by utilizing information about the mosaicism level of one or more chromosomes of interest in the mother of fetus. The mosaicism level of one or more chromosomes of interest is determine for the maternal tissue that is used as the source of nucleic acid for genetic analysis that are used to determine the ploidy state of the fetal chromosome or chromosomes of interest. For example, if 5% white blood cells of mother are missing a copy of the X chromosome, this information can be used when determining fetal ploidy level, rather than operating under the assumption that the maternal X chromosome are present in two copies. Utilization of the mosaicism data can be used to increase the reliability and accuracy of the determination of the ploidy state of a chromosome of interest. | 2020-11-05 |
20200350035 | GENE ANALYSIS METHOD, GENE ANALYSIS APPARATUS, MANAGEMENT SERVER, GENE ANALYSIS SYSTEM, PROGRAM, AND STORAGE MEDIUM - For analyzing gene sequences by use of various gene panels, convenience for a user is improved. A gene analysis apparatus ( | 2020-11-05 |
20200350036 | DEVICE-AGNOSTIC SYSTEM FOR PLANNING AND EXECUTING HIGH-THROUGHPUT GENOMIC MANUFACTURING OPERATIONS - High-throughput production of modified microbes is achieved through optimization of directed build graph data structures representing biological workflows. Portions of otherwise unrelated workflows may be combined where they share common biological reaction steps, and processed by a genetic manufacturing facility to take advantage of operational efficiencies. Workflows may be mapped to physical laboratory equipment in a manner that optimizes material transfers. Different automated platforms running different machines in different languages are coordinated in a device-agnostic and language-agnostic manner. | 2020-11-05 |
20200350037 | SYSTEM, METHOD AND COMPUTER ACCESSIBLE-MEDIUM FOR MULTIPLEXING BASE CALLING AND/OR ALIGNMENT - An exemplary system, method and computer-accessible medium for multiplexing base-calling of a plurality of nucleic acid molecules in the same flow cell is provided. When multiplexing for just two nucleic acid molecules, it can operate by selecting a first base call for a first nucleic acid molecule and a second base call for a second nucleic acid molecule, after having placed them in the same flow cell and obtaining the combined raw intensity output. It can use as prior the appropriate reference genome sequences from which the nucleic acid molecules can be derived in order to create a score function, which can additionally be constrained by various penalty functions. It can derive accuracy and speed by using a branch and bound strategy as well as by performing alignment and base-calling in one step per cycle. | 2020-11-05 |
20200350038 | Bioinformatics Systems, Apparatuses, and Methods Executed on an Integrated Circuit Processing Platform - A system, method and apparatus for executing a bioinformatics analysis on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit that may be connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits may be arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the bioinformatics analysis on the reads of genomic data. Each subset of the hardwired digital logic circuits may be formed in a wired configuration to perform the one or more steps in the bioinformatics analysis. | 2020-11-05 |
20200350039 | TECHNIQUES FOR GENERATING ENCODED REPRESENTATIONS OF COMPOUNDS - Techniques and apparatus for generating encoded representations of compounds are described. In one embodiment, for example, an apparatus may include at least one memory, and logic coupled to the at least one memory. The logic may be configured receive analytical information associated with at least one compound, generate at least one encoded representation of the at least one compound, the encoded representation comprising at least one segment representing at least one property of the at least one compound using a plurality of symbols. Other embodiments are described. | 2020-11-05 |
20200350040 | ELECTRONIC DATA DOCUMENT FOR USE IN CLINICAL TRIAL VERIFICATION SYSTEM AND METHOD - The present invention provides an electronic data document (EDD) and related system and method for use in a computerized clinical trial verification system. In an exemplary embodiment, the EDD is authenticated by the creator and validated by the receiver, and comprises an image of a source document (SD) that comprises a masked record of at least one interaction between a clinical trial investigator and a patient enrolled in a clinical trial, at least one revealed portion of the SD that includes evidence relevant to at least one question in a clinical trial questionnaire, and at least one annotation connecting the revealed portion to the at least one question. The present invention provides a computerized system and method for allowing a clinical trial investigator to answer questions from a clinical trial questionnaire pertinent to a clinical trial of a medical treatment using encrypted and partially masked electronic documents comprising images of original patient records. The process of creating and viewing the partially masked electronic documents preferably does not create local copies that can be recalled later. | 2020-11-05 |
20200350041 | METHODS OF FORECASTING ENROLLMENT RATE IN CLINICAL TRIAL - In one embodiment, the present invention provides a method of designing a clinical trial enrollment plan, comprising the use of non-linear regression analysis to model the relationship between the number of investigator sites and the site enrollment rates, or the relationship between the number of investigator sites and the trial enrollment rates. One or more parameters such as the number of investigator sites, site enrollment rates, and/or trial enrollment rates can then be extrapolated from said regression analysis, wherein said extrapolated parameters are used in the design of one or more clinical trial enrollment plans | 2020-11-05 |
20200350042 | AUTOMATED SYSTEM AND METHOD OF RECORDING CONTENTS OF MEDICATION PACKAGES VENDED FROM A PLURALITY OF VENDING MACHINES IN AN ELECTRONIC RECORD THAT STORES RECORDS FOR A PLURALITY OF PATIENTS ASSOCIATED WITH RESPECTIVE VENDING MACHINES - An automated method is provided for recording contents of medication packages vended from a plurality of vending machines in electronic records, such as an electronic medication administration record (eMAR), that store records for a plurality of patients who are associated with respective vending machines. A vending event causes the electronic record to be populated. The contents of the medication packages vended from the vending machines are recorded in electronic records without communicating patient names or vended medications in the electronic message sent from the vending machines. | 2020-11-05 |
20200350043 | Records Access and Management - An electronic device for aggregating electronic medical records, in which electronic medical records are aggregated from multiple electronic repositories and displayed as a single set of records. The multiple electronic repositories may store records for a particular patient using varying identifying/access information to facilitate anonymous access to the electronic medical records. Emergency medical services providers may be able to access medical records for a patient using the electronic device after being authenticated as a valid/licensed medical services provider. | 2020-11-05 |
20200350044 | SYSTEM AND METHOD FOR HEALTH CARE DATA INTEGRATION AND MANAGEMENT - In an exemplary embodiment, a method creates an electronic health record and analyzes that record to present a summary report. The report may optionally include treatment opportunities, strategies, and plans for the physician and patient. Data processing steps used to create and analyze the record and deliver the summary data may include aggregation, integration, internal validation, clinical validation, inspection, prediction, and communication. | 2020-11-05 |
20200350045 | Systems, Devices, and Methods for Identification and Tracking of Objects - The concept disclosed is referred is a temporary identification device, or, “TID.” The TID comprises essentially, different embodiments of a reproducible layer, the reproducible layer being a pictographic rendering of data, information, colors, and visualization codes pertaining to a specific subject, the subject being animate or inanimate. The medium of the reproducible layer may be, but is not limited to, paper, fabric, synthetic material, or an inked imprint/impression of the data and information integral to the TID. The medium of the reproducible layer is encompassed within, or incorporated onto the TID. In some embodiments, the information embodied within or upon the TID may be transferred directly onto the skin or surface of a subject. | 2020-11-05 |
20200350046 | INVENTORY TRACKING AND CONTROL SYSTEM - An automatic inventory tracking and control system tracks the inventory of medical articles in an enclosure by providing a robust electromagnetic (EM) field within the enclosure. The enclosure has electrically-conductive walls. Wireless identification devices such as RFID tags, attached to each medical article respond to the electromagnetic field by transmitting unique data identified with each medical article. A probe or probes are used to generate transverse electromagnetic modes in the enclosure. | 2020-11-05 |
20200350047 | SYSTEMS AND METHODS FOR ADJUSTING MEDICAL TREATMENT TO REDUCE LIKELIHOOD OF PRESCRIPTION CASCADE - There is provided a method for generating instructions for adjusting a medical treatment of a patient, comprising: detecting an indication of a new symptom appearing in a patient being treated with medications for medical condition(s), computing a value indicative of risk of the new symptom being an adverse drug reaction (ADR) of one or a combination of the medications, detecting an indication of another new medication for treating the patient, computing likelihood of PC when the new medication is for treating the new symptom and the value is according to a requirement, generating a request for substitute medication(s) for the one or combination of medications when likelihood of PC is detected, and generating instructions for adjusting treatment of the patient by substituting the one or combination of medications with the substitute medication(s), and for terminating administration of the new medication or avoiding administration of the new medication. | 2020-11-05 |
20200350048 | SYSTEM AND METHOD FOR THE VERIFICATION OF MEDICATION - A system for verifying proper possession of a medication where a reader device scans a code printed on the medication to extract an embedded serial number. A first server queries a prescription database, which retrieves patient information associated with the embedded serial number. The patient information is returned to the reader device and a match determination is made. The patient information may include a name and photograph. | 2020-11-05 |
20200350049 | SYSTEMS AND METHODS FOR DISTRIBUTING CELL THERAPIES - The disclosure relates to delivery systems, and corresponding methods, for selecting and delivering an allogeneic T-cell line for administration to a patient, e.g., according to the HLA profile of the patient's somatic or diseased cells. | 2020-11-05 |
20200350050 | SYSTEM AND METHOD FOR MANAGING INVENTORY AT DISPENSING UNITS - Dispensing units or stations for dispensing items, such as in a healthcare facility, are linked in a network. The dispensing stations are arranged in groups. Inventory data for all the stations in a group is combined together, and displayed at a graphical view or widget. Multiple widgets may be displayed on a dashboard screen of a user system, for use in managing inventory. | 2020-11-05 |
20200350051 | METHOD, SYSTEM AND APPARATUS FOR GUIDING AND TRACKING MEDICATION USAGE - Methods and systems are provided for tracking and guiding a patient's clinically directed medication usage. Medicaments are placed in secure passive packaging that must be unlocked to enable dispensing of a dose or a set of doses. This packaging is designed to be difficult to open manually, and instead is designed to dispense only when used in combination with an unlocking device. The unlocking device is a separate device containing electronics, mechatronics or both, to unlock and dispense from the packaging and to track and guide usage. Together, the secure container and the unlocking device track medication usage, deter an excessive rate of patient usage, and deter unauthorized access to medication. | 2020-11-05 |
20200350052 | INTELLIGENT MEDICATION DELIVERY SYSTEMS AND METHODS FOR DOSE RECOMMENDATION AND MANAGEMENT - Systems, devices, and techniques are disclosed for administering and tracking medicine to patients and providing health management capabilities for patients and caregivers. In some aspects, a method includes receiving one or more analyte values associated with a health condition of the patient user; receiving contextual data associated with the patient user obtained by the mobile computing device, where the obtained contextual data includes information associated with a meal; determining a medicine metric value associated with an amount of medicine active in the body of the patient user; autonomously calculating a dose of the medicine without input from the user based at least on the one or more analyte values, the medicine metric value, and the information associated with a meal; and continuously displaying the calculated dose of the medicine. | 2020-11-05 |
20200350053 | DIAGNOSTIC COMMUNICATION SYSTEMS, DIAGNOSTIC DATA COLLECTION KITS, AND METHODS FOR GENERATING AND CONVEYING ORAL CONDITION DATA SETS AND TREATMENT PLANS - Diagnostic communication systems, diagnostic data collection kits, and methods for generating and conveying oral condition data sets and treatment plans. A method of developing a treatment plan to treat an oral condition of a patient includes receiving an oral condition data set, analyzing the oral condition data set, and generating the treatment plan based on the analysis of the oral condition data set. The oral condition data set is at least partially generated by a patient representative utilizing a data collection kit. A data collection kit for generating an oral condition data set includes at least one diagnostic instrument, instructions describing a method of generating at least a portion of the oral condition data set, and/or packaging that contains the at least one diagnostic instrument. The instructions include instructions for delivering the oral condition data set to a service provider and/or a centralized service. | 2020-11-05 |
20200350054 | MONITORING SYSTEM FOR A DIALYSIS MACHINE - The invention relates to a monitoring system for at least one dialysis machine (e.g. a peritoneal dialysis machine), wherein the monitoring system receives data from a dialysis machine to be monitored via a first data communication network, wherein the data are selected from a group comprising machine data, error codes, operational data, environmental data, consumables data, network data, treatment data, wherein the data received are stored in a manner which is specific to the respective peritoneal dialysis machine, wherein for each machine, at least individual components of the stored data are analyzed wherein, on the basis of the analysis, an action selected from informing a patient, informing a medical professional, informing service personnel, informing a quality management representative is carried out via a second data communication network. | 2020-11-05 |
20200350055 | NORMALIZED STANDARD DEVIATION TRANSITION BASED DOSIMETRY MONITORING FOR LASER TREATMENT - Technologies are generally described for normalized standard deviation transition based dosimetry monitoring for laser treatment. In some examples, a response signal may be generated based on a physical response to a laser pulse detected through acoustic or optical means. Each response signal may be a time series of data with a number of points. Standard deviation may be determined for each response signal and normalized using a mean or comparable normalization factor. Thus, a robust distribution may be computed from the response to each laser pulse. A change in the normalized standard deviation from each single pulse's time domain response data may be used to determine how many laser pulses remain before completion of the treatment (similar to event onset response). Thus, laser treatment may be continued based on an estimation of remaining pulses for completion or ceased if completion is reached. | 2020-11-05 |
20200350056 | AUTOMATED ASSESSMENT OF MEDICAL CONDITIONS - Systems and methods are provided for patient evaluation. The systems may include a mobile device and a central server. The mobile device can conduct an automated assessment that detects at least one of traumatic brain injury or concussion in a patient. The automated assessment can include in part displaying a clinical condition questionnaire and receiving responses to the clinical condition questionnaire from the patient. The mobile device can provide a record of the automated assessment of the patient to the central server. The central server can receive the record of the automated assessment of the patient, receive a request to determine a clinical state of a patient, diagnose the clinical state of the patient based on the received record of the automated assessment and stored records of prior automated assessments, and provide an indication of the clinical state of the patient. | 2020-11-05 |
20200350057 | REMOTE COMPUTING ANALYSIS FOR COGNITIVE STATE DATA METRICS - Remote computing analysis for cognitive state data metrics is performed. Cognitive state data from a plurality of people is collected as they interact with a rendering. The cognitive state data includes video facial data collected on one or more local devices from the plurality of people. Information is uploaded to a remote server. The information includes the cognitive state data. A facial expression metric based on a plurality of image classifiers is calculated for each individual within the plurality of people. Cognitive state information is generated for each individual, based on the facial expression metric for each individual. The cognitive state information for each individual within the plurality of people who interacted with the rendering is aggregated. The aggregation is based on the facial expression metric for each individual. The cognitive state information that was aggregated is displayed on at least one of the one or more local devices. | 2020-11-05 |
20200350058 | CHINESE MEDICINE PRODUCTION PROCESS KNOWLEDGE SYSTEM - A process knowledge system for traditional Chinese medicine production includes a database module having production data acquisition and storage units. The production data acquisition unit acquires process parameter data in production. The parameter data includes quality and process data and is stored in the storage unit. A capability evaluation module evaluates the process capability of the system according to the quality data to obtain a process capability evaluation result. A monitoring feedback module enters a whole-process monitoring mode the process capability is found sufficient. A design space searching module enters a design space searching mode when the process capability is found insufficient. Release parameters are determined or a design space is searched for through process capability evaluation, so that a production process knowledge system stepwise regresses into a knowledge process system capable of realizing intelligent regulation and feedback of the traditional Chinese medicine production process. | 2020-11-05 |
20200350059 | METHOD AND SYSTEM OF TEETH ALIGNMENT BASED ON SIMULATING OF CROWN AND ROOT MOVEMENT - The present disclosure relates to a dental image processing protocol for the design of dental aligners. Specifically, the dental image processing protocol aids in the determination of tooth movements during realignment, based on an initial position and a final position, and on characteristics of the periodontal environment. Therefore, planned tooth movements reflect both crown movement and root movement within biological structures of the alveolar process. | 2020-11-05 |
20200350060 | METHOD AND SYSTEM FOR DELIVERING MEDICAL CARE TO PATIENTS - A method for delivering medical care to a patient is provided. A first set of doctors is identified for performing a medical procedure on the patient based on a first location of the patient. An availability request is communicated to a subset of the first set of doctors, requesting an availability confirmation of each doctor of the subset of doctors for performing the medical procedure. One or more availability responses of one or more doctors are received from one or more doctor devices. Each availability response is indicative of an availability of a corresponding doctor for performing the medical procedure. A first doctor is selected, from the one or more doctors, for performing the medical procedure. The first doctor is selected based on a response time of the availability response of the first doctor to the availability request. | 2020-11-05 |