45th week of 2009 patent applcation highlights part 33 |
Patent application number | Title | Published |
20090275107 | Scalable Production Method for AAV - A method for producing AAV, without requiring cell lysis, is described. The method involves harvesting AAV from the supernatant. For AAV having capsids with a heparin binding site, the method involves modifying the AAV capsids and/or the culture conditions to ablate the binding between the AAV heparin binding site and the cells, thereby allowing the AAV to pass into the supernatant, i.e., media. Thus, the method of the invention provides supernatant containing high yields of AAV which have a higher degree of purity from cell membranes and intracellular materials, as compared to AAV produced using methods using a cell lysis step. | 2009-11-05 |
20090275108 | BACILLUS PUMILUS STRAIN FOR HIGH YIELD OF TETRAMETHYLPYRAZINE - This invention provides a high-yield bacterial strain for producing tetramethylpyrazine named | 2009-11-05 |
20090275109 | BACILLUS STRAINS USEFUL FOR ANIMAL ODOR CONTROL - A composition is provided that includes | 2009-11-05 |
20090275110 | Microorganism that Displays Biotin on Cell Surface - Provided is a microorganism that can display, on the cell surface, any molecules other than a molecule comprising amino acids, more specifically, a microorganism that displays biotin on a cell surface. The microorganism is capable of co-expressing a biotinylating enzyme and an acceptor peptide having a sequence recognized by the biotinylating enzyme, wherein the acceptor peptide is expressed on the cell surface, so that lysine of the acceptor peptide is biotinylated to display biotin on the cell surface. Also provided is a method for displaying an intended molecule, including not only a molecule comprising amino acids but also any molecules, on a cell surface of a microorganism. | 2009-11-05 |
20090275111 | Anaerobically Compostable Polymeric Compositions, Articles and Landfill Biodegradation - Compostable hydrocarbon polymers, composites, and articles anaerobically biodegrade in landfills in a relatively short time. Composite polymeric articles and sheets such as indoor or outdoor signs, billboards, banners, images, protective barriers, backdrops and wall coverings have very useful service durations and yet are landfill biodegradable. | 2009-11-05 |
20090275112 | NUTRIENT ADDITIVES FOR START-UP AND SUSTAINED OPERATION OF A BIOLOGICAL FILTER APPARATUS - A biological filter apparatus for biological degradation of contaminants in an air stream is operated by passing the air stream through a filter chamber containing a structure supporting a population of microbes and collecting water that drains from the structure and spraying the collected water onto the structure, whereby the sprayed water is recirculated. Upon start up or re-start of the filter apparatus, a nutrient composition is added to the recirculating water. The nutrient composition contains a buffering agent, sources of nitrogen and phosphorus, and sources of trace elements selected from manganese, calcium, iron and sodium. | 2009-11-05 |
20090275113 | Thermal cycling apparatus - This invention provides an apparatus for providing heating and cooling of samples in sample vessels having uniform temperature profiles. The apparatus can be used for performing PCR, and real time PCR in particular, with control and uniformity. The system employs a heat block containing a liquid composition to efficiently transfer heat to and from reaction vessels. | 2009-11-05 |
20090275114 | VIBRATORY MIXER - To simplify mixing systems without stirrer systems and to minimize cleaning and validation operations, it is proposed that a vibratory mixer with a vibratory mechanism should have a container. Into this container is inserted a bag which, after use, need not be cleaned and is instead replaced by a new one. This bag is equipped with the connections and sensors required and presterilized. The bag is placed into an angled container. The container serves as a stabilization casing. As a result of the vibration of the container, there is liquid displacement over the angle range, which improves the mixing operation. | 2009-11-05 |
20090275115 | MICROREACTOR - Chemical and biological reactors, including microreactors, are provided. Exemplary reactors include a plurality of reactors operable in parallel, where each reactor has a small volume and, together, the reactors produce a large volume of product. Reaction systems can include mixing chambers, heating/dispersion units, reaction chambers, and separation units. Components of the reactors can be readily formed from a variety of materials. For example, they can be etched from silicon. Components are connectable to and separable from each other to form a variety of types of reactors, and the reactors can be attachable to and separable from each other to add significant flexibility in parallel and/or series reactor operation. | 2009-11-05 |
20090275116 | Metallic PCR frames - The present invention is represented by a two part PCR well plate. Part one, the outer shell, is constructed from a thin metal.. Part two, the tubes, are thermoformed in an array of 96/384 or formed individually and inserted or welded into each tube cell location. The use of a rigid metal frame for the PCR array virtually eliminates all warping problems associated with temperature cycling. | 2009-11-05 |
20090275117 | SLIP COVER FOR HEATED PLATEN ASSEMBLY - A heated platen assembly for use in a biological testing device is disclosed having a heated platen defining a plurality of optical openings configured to permit radiation to pass through the heated platen, a light transmissive slip cover configured to cover at least one of the plurality of optical openings, and means for retaining the slip cover over the at least one of the plurality of optical openings. | 2009-11-05 |
20090275118 | Bacteria Detecting Instrument, Bacteria Detecting Method, and Bacteria Detecting Kit - A micro array instrument is used in which an oligonucleotide based on a species- or genus-specific nucleotide sequence of subject bacteria is immobilized on a surface of a substrate. By confirming whether the oligonucleotide immobilized on the substrate has hybridized with a probe prepared from a test sample, bacteria contained in the test sample can be detected and identified easily, quickly, and accurately. | 2009-11-05 |
20090275119 | Liquid Chromatograph - The present invention relates to a liquid chromatography apparatus X, which is provided with a deaerator | 2009-11-05 |
20090275120 | EXTRACTION OF CO2 GAS FROM ENGINE EXHAUST - A photo-bioreactor is used for extraction of carbon dioxide from exhaust gases of an engine used for compression of natural gas by providing a series of vessels and in each contacting the gases with a labyrinthine flow of water containing photo-synthetic organisms. Each vessel receives the gases in series and is controlled to manage the temperature and dwell time to take into account the reducing CO | 2009-11-05 |
20090275121 | Vibrational Mixer - A vibrational mixer ( | 2009-11-05 |
20090275122 | POLYPEPTIDES HAVING COLANIC ACID-DEGRADING ACTIVITY - The present disclosure generally relates to polypeptides having colanic acid-degrading activity and methods of using the same. Polynucleotides encoding such polypeptides are also described. The polypeptides may be used, for example, in processes for degrading colanic acid, processes for the removal of endotoxins from biological samples, and processes for purifying plasmid DNA. | 2009-11-05 |
20090275123 | MODIFIED VITAMIN K-DEPENDENT POLYPEPTIDES - The invention provides vitamin K-dependent polypeptides with enhanced membrane binding affinity. These polypeptides can be used to modulate clot formation in mammals. Methods of modulating clot formation in mammals are also described. | 2009-11-05 |
20090275124 | Methods and Compositions Comprising Anti-Idiotypic Antibodies to Anti-MMP-14 Antibodies - Provided are anti-idiotypic antibodies specific for a CDR of an anti-MMP-14 antibody for use as reagents in novel assays for anti-MMP-14 antibodies, pharmaceutical compositions and vaccines. | 2009-11-05 |
20090275125 | Human T1R2 Taste Receptor Nucleic Acids and Cells Containing These Nucleic Acids - Newly identified mammalian taste-cell-specific G protein-coupled receptors, and the genes and cDNA encoding said receptors are described. Specifically, T1R G protein-coupled receptors active in taste signaling, and the genes and cDNA encoding the same, are described, along with methods for isolating such genes and for isolating and expressing such receptors. Methods for representing taste perception of a particular taste stimulus in a mammal are also described, as are methods for generating novel molecules or combinations of molecules that elicit a predetermined taste perception in a mammal, and methods for simulating one or more tastes. Further, methods for stimulating or blocking taste perception in a mammal are also disclosed. | 2009-11-05 |
20090275126 | ANTIBODIES AGAINST INSULIN-LIKE GROWTH FACTOR I RECEPTOR AND USES THEREOF - Antibodies against insulin like growth factor I receptor (IGF-IR), methods for their production, pharmaceutical compositions containing said antibodies, and uses for such antibodies are disclosed. Such antibodies are implicated in antitumor therapy. | 2009-11-05 |
20090275127 | VIABLE CELLS FROM FROZEN UMBILICAL CORD TISSUE - Viable progenitor cells are extracted from frozen umbilical cord tissue. In embodiments, the umbilical cord tissue is a blood vessel bearing perivascular Wharton's jelly, and the extracted progenitor cells are HUCPVCs. | 2009-11-05 |
20090275128 | MEDIUM AND CULTURE OF EMBRYONIC STEM CELLS - Previous methods for culturing human embryonic stem cells have required either fibroblast feeder cells or a medium which has been exposed to fibroblast feeder cells in order to maintain the stem cells in an undifferentiated state. It has now been found that if high levels of fibroblast growth factor, gamma amino butyric acid, pipecholic acid, lithium and transforming growth factor beta are added to the medium in which the stem cells are cultured, the stem cells will remain undifferentiated indefinitely through multiple passages, even without feeder cells or conditioned medium. | 2009-11-05 |
20090275129 | TISSUE ENGINEERED BLOOD VESSELS - Compositions and methods of using tissue engineered blood vessels to repair and regenerate blood vessels of patients with vascular disease are disclosed. | 2009-11-05 |
20090275130 | BIOMIMETIC NUCLEIC ACIDS - The present invention is directed to nucleic acids with biomimetic properties and methods for producing said nucleic acids. In particular, this invention relates to nucleic acids exhibiting biomimetic properties in relation to proteins such as growth factors, hormones and/or other cell signaling proteins. Biomimetic properties may generally be defined as interactive ability in the same and/or similar manner as another biological molecule. This may, for example, include interacting with a ligand-binding biomolecule, such as a cell signaling receptor, in a manner similar to a native ligand. In the case of a signaling receptor, such biomimetic nucleic acids may in general act as an agonist or an antagonist to the given receptor. They may further act in competition to a native ligand. | 2009-11-05 |
20090275131 | METHOD FOR PRODUCTION OF MAST CELLS FROM STEM CELLS - Provided are methods for generating mast cells from pluripotent stem cells in vitro. Methods are disclosed for the differentiation of pluripotent cells, such as iPS cells and/or human embryonic stem cells, into mast cells. The resulting mast cells may be used for various purposes including screening cells for drug development and research. Growth factors which may be included in culture media according to the present invention include stem cell factor (SCF), FLT-3 ligand, thrombopoietin (TPO), interleukin-3 (IL-3), and/or interleukin-6 (IL-6). | 2009-11-05 |
20090275132 | METHOD FOR PURIFYING CARDIOMYOCYTES OR PROGRAMMED CARDIOMYOCYTES DERIVED FROM STEM CELLS OR FETUSES - An object of the present invention is to develop a method for purify cardiomyocytes at a high degree of purification and at a high yield from a cell mixture comprising cardiomyocytes derived from fetuses and stem cells using various features which have not been previously expected to be used for purification of cardiomyocytes or which are newly found, wherein said method is carried out without undergoing any genetic modification or without adding any special proteins or biologically active agents. | 2009-11-05 |
20090275133 | ANTISENSE MODULATION OF C-REACTIVE PROTEIN EXPRESSION - Antisense compounds, compositions and methods are provided for modulating the expression of C-reactive protein. The compositions comprise antisense compounds, particularly antisense oligonucleotides, targeted to nucleic acids encoding C-reactive protein. Methods of using these compounds for modulation of C-reactive protein expression and for treatment of diseases associated with expression of C-reactive protein are provided. | 2009-11-05 |
20090275134 | COMPOSITIONS OF ACTIVE WNT PROTEIN - Compositions of purified biologically active Wnt proteins are provided. Wnt proteins are found to be hydrophobic and post-translationally modified by addition of a lipid moiety at a conserved cysteine residue. Methods for isolation of Wnt utilize detergents that maintain the solubility of the modified protein. | 2009-11-05 |
20090275135 | MAMMALIAN CYTOKINES; RECEPTORS; RELATED REAGENTS AND METHODS - Nucleic acids encoding mammalian cytokine receptor, e.g., for cytokine IL-B50, purified proteins and fragments thereof. Antibodies, both polyclonal and monoclonal, are also provided. Methods of using the compositions for both diagnostic and therapeutic utilities are described. | 2009-11-05 |
20090275136 | Nuclear Targeting Sequence - The present provides nuclear localization signaling (NLS) sequences derived from titin, comprised of amino acids 181-220: SVGRATSTAE LLVQGEEEVP AKKTKTIVST AQISESRQTR and fragments thereof, such as amino acids 193-208: VQGEEEVP AKKTKTIV; amino acids 199-208: VPAKKTKTIV; and amino acids 200-206: PAKKTKT. The NLS sequences can be linked to agents, such as peptides, proteins or nucleotides, for transporting the agents into the nucleus of cells, and the NLS-agent complex can be further linked to antibodies or ligands for specific binding to cells. Also provided is a method for constructing cDNAs comprising combining a NLS sequence with a nucleic acid sequence for a target protein for expression and entry of the target protein into the nucleus of cells, which then can perform specific functions therein. | 2009-11-05 |
20090275137 | HIGH AFFINITY TCR PROTEINS AND METHODS - T cell receptors (TCRS) that have higher affinity for a ligand than wild type TCRs are provided. These high affinity TCRs are formed by mutagenizing a T cell receptor protein coding sequence to generate a variegated population of mutants of the T cell receptor protein coding sequence; transforming the T cell receptor mutant coding sequence into yeast cells; inducing expression of the T cell receptor mutant coding sequence on the surface of yeast cells; and selecting those cells expressing T cell receptor mutants that have higher affinity for the peptide/MHC ligand than the wild type T cell receptor protein. The high affinity TCRs can be used in place of an antibody or single chain antibody. | 2009-11-05 |
20090275138 | PRODUCTION OF rAAV IN VERO CELLS USING PARTICULAR ADENOVIRUS HELPERS - The present invention relates to methods and materials for recombinant adeno-associated virus production. More particularly, in some embodiments the invention contemplates the use of an adenovirus known as Simian Adenovirus 13 (SAdV-13) and Vero cells for production of recombinant adeno-associated virus (rAAV). | 2009-11-05 |
20090275139 | MATERIALS AND METHODS RELATING TO THE PRODUCTION AND MAINTENANCE OF CELL LINES - The invention provides methods for maintaining cell lines from primary cells, i.e., non-transformed cells, using expression of the signal transducer of activation and transcription (STAT). The methods are particularly suitable for maintenance of B-cells. | 2009-11-05 |
20090275140 | Hemoglobin Based Bilirubin Reference Material - What is described is a single reference material and method of making useful for calibrating or qualifying instruments that are diagnostic spectroscopically for bilirubin, hemoglobin, and hemoglobin fractions, and, optionally, diagnostic for other blood analytes by sensor means. | 2009-11-05 |
20090275141 | Affinity Adsorbents for Factor VIII and Von Willebrand's Factor - For the separation, removal, isolation, purification, characterisation, identification or quantification of Factor VIII, von Willebrand's Factor or a protein that is a analogue of either, an affinity adsorbent is used that is a compound of formula (II) wherein one X is N and the other is N, C—Cl or C—CN; A is a support matrix, optionally linked to the triazine ring by a spacer; Y is O, S or NR | 2009-11-05 |
20090275142 | COMPOSITIONS AND METHODS FOR BIODETECTION BY NUCLEIC ACID-TEMPLATED CHEMISTRY - The invention provides compositions and methods for the detection of biological targets, (e.g. nucleic acids and proteins) by nucleic acid-templated chemistry, for example, by generating fluorescent polymethine dyes. | 2009-11-05 |
20090275143 | NANOSTRUCTURE ARRAY AND METHODS OF USE FOR EXPLOSIVE DETECTION - In various embodiments, the present disclosure provides a method of detecting triacetone triperoxide. In a particular implementation, the method includes providing an array of titanium nanostructures that include a sensitizing agent. The array is contacted with a fluid sample, such as vapor sample. The resistance of the array is measured. The measured resistance of the array can be used to determine whether the sample includes triacetone triperoxide. The nanostructures are, in some cases, titania nanotubes. The sensitizing agent is, in a specific example, zinc. The present disclosure also provides a triacetone triperoxide sensor that includes an array of nanostructures, at least a portion of which are sensitized with a sensitizer, such as one or more of Li | 2009-11-05 |
20090275144 | System and Method for Colorimetric Titration Measurements - A system for colorimetric titration, comprising a container ( | 2009-11-05 |
20090275145 | METAL-ENHANCED FLUORESCENCE FOR POLARIZATION-BASED AFFINITY ASSAYS - A method and kit for determining the quantity of an analyte include providing a functionalized substrate and a reagent. The functionalized substrate includes metallic nanoparticles and a plurality of substantively identical bioactive target molecules affixed to a substrate. The bioactive target molecule binds to a particular analyte. The reagent includes identical detection molecules. Each detection molecule includes a fluorophore, and binds to a particular analyte or competes with a particular analyte for binding to the target molecule. The functionalized substrate is contacted to a test sample and the reagent. The functionalized substrate and a covering solution are exposed to polarized electromagnetic waves that excite the fluorophore. A quantity of the particular analyte in the test sample is determined based on measuring polarization anisotropy of fluorescent emissions from the substrate and the covering solution. | 2009-11-05 |
20090275146 | METHOD AND APPARATUS FOR MANUFACTURING DEVICE - A method for manufacturing a device, includes: (A) forming a first electrode layer on a substrate; (B) forming a ferroelectric layer on the first electrode layer; (C) forming a second electrode layer on the ferroelectric layer; (D) forming a mask having a predetermined pattern on the second electrode layer; (E) forming a memory element by selectively removing the first electrode layer, the ferroelectric layer, and the second electrode layer using the mask; and (F) removing the mask, where at least, the processes (D) and (E), or the processes (E) and (F) are continuously performed under a reduced pressure. | 2009-11-05 |
20090275147 | MITIGATION OF EDGE DEGRADATION IN FERROELECTRIC MEMORY DEVICES THROUGH PLASMA ETCH CLEAN - A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed. | 2009-11-05 |
20090275148 | MITIGATION OF EDGE DEGRADATION IN FERROELECTRIC MEMORY DEVICES THROUGH PLASMA ETCH CLEAN - A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed. | 2009-11-05 |
20090275149 | METHODS AND SYSTEMS FOR CONTROLLING CRITICAL DIMENSIONS IN TRACK LITHOGRAPHY TOOLS - A method of controlling wafer critical dimension (CD) uniformity on a track lithography tool includes obtaining a CD map for a wafer. The CD map includes a plurality of CD data points correlated with a multi-zone heater geometry map. The multi-zone heater includes a plurality of heater zones. The method also includes determining a CD value for a first heater zone of the plurality of heater zones based on one or more of the CD data points and computing a difference between the determined CD value for the first heater zone and a target CD value for the first heater zone. The method further includes determining a temperature variation for the first heater zone based, in part, on the computed difference and a temperature sensitivity of a photoresist deposited on the wafer and modifying a temperature of the first heater zone based, in part, on the temperature variation. | 2009-11-05 |
20090275150 | FILM FORMATION APPARATUS AND METHOD FOR SEMICONDUCTOR PROCESS - A film formation apparatus for a semiconductor process includes a source gas supply circuit to supply into a process container a source gas for depositing a thin film on target substrates, and a mixture gas supply circuit to supply into the process container a mixture gas containing a doping gas for doping the thin film with an impurity and a dilution gas for diluting the doping gas. The mixture gas supply circuit includes a gas mixture tank disposed outside the process container to mix the doping gas with the dilution gas to form the mixture gas, a mixture gas supply line to supply the mixture gas from the gas mixture tank into the process container, a doping gas supply circuit to supply the doping gas into the gas mixture tank, and a dilution gas supply circuit to supply the dilution gas into the gas mixture tank. | 2009-11-05 |
20090275151 | Method Of Forming Printhead By Removing Sacrificial Material Through Nozzle Apertures - A method of fabricating an inkjet printhead by forming a plurality of actuators on a monolithic substrate, covering the actuators with a sacrificial material, covering the sacrificial material with a printhead surface layer, defining a plurality of nozzle apertures in the printhead surface layer such that each of the actuators corresponds to one of the nozzle apertures and then, removing at least some of the sacrificial material on each of the actuators through the nozzle aperture corresponding to each of the actuators. | 2009-11-05 |
20090275152 | PROCESS FOR THE COLLECTIVE FABRICATION OF MICROSTRUCTURES CONSISTING OF SUPERPOSED ELEMENTS - The invention relates to the collective fabrication of superposed microstructures, such as an integrated circuit and a protective cover. Individual structures each comprising superposed first and second elements are fabricated collectively. The first elements (for example, integrated circuit chips) are prepared on a first plate and the second elements (for example, transparent covers) are prepared on a second plate. The plates are bonded to each other over the major portion of their facing surfaces, but with no bonding of the defined zones in which there is no adhesion. The individual structures are then diced via the top on the one hand and via the bottom on the other hand along different parallel dicing lines passing through the zones with no adhesion, so that, after dicing, the first elements retain surface portions (those lying between the parallel dicing lines) that are not covered by a second element. A connection pad may thus remain accessible at this point. | 2009-11-05 |
20090275153 | METHOD OF PRODUCTION OF SEMICONDUCTOR LIGHT EMISSION DEVICE AND METHOD OF PRODUCTION OF LIGHT EMISSION APPARATUS - A method of production of semiconductor light emission devices for forming stripes of two multilayers having different emission wavelengths on a substrate, including the steps of: depositing a first multilayer including an active layer on the substrate; selectively etching the first multilayer to form a plurality of adjoining pairs of stripes of the first multilayer; depositing a second multilayer including an active layer on the substrate and the stripes of the first multilayer; selectively etching the second multilayer to form a plurality of adjoining pairs of stripes of the second multilayer on the substrate between the stripes of the first multilayer; and dividing the substrate between adjoining pairs of stripes of the first multilayer and between adjoining pairs of stripes of the second multilayer to divide it into semiconductor light emission devices provided with a stripe of the first multilayer and the second multilayer having different emission wavelengths. | 2009-11-05 |
20090275154 | Method of fabricating light emitting device - A light emitting device wafer is fabricated, having a light emitting layer section, composed of AlGaInP, based on a double heterostructure and a GaP light extraction layer disposed on the light emitting layer portion, having a first main surface thereof appearing on the first main surface of the wafer, so as that a P-rich off-angled {100} surface, having a higher existence rate of P atoms than an exact {100} surface, appears on the first main surface the GaP light extraction layer. The main first surface of the GaP light extraction layer is etched with an etching solution FEA so as to form surface roughening projections. Therefore, it provides a method of fabricating a light emitting device capable of applying surface roughening easily to the GaP light extraction surface having the {100} surface, off-angled to be P-rich, as a main surface thereof. | 2009-11-05 |
20090275155 | Method of fabrication a liquid crystal display device - The present invention relates to a transflective thin film transistor substrate and method of fabricating the same that is adaptive for simplifying its process. The liquid crystal display device includes: first and second substrates; a gate line on the first substrate; a gate insulating film on the first substrate; a data line crossing the gate line to define a pixel area; a thin film transistor connected to the gate line and the data line; an organic insulating film on the gate line, the data line and the thin film transistor, and having a transmission hole in the pixel area; a pixel electrode on the organic insulating film of the pixel area via the transmission hole and connected to the thin film transistor; and a reflective electrode on the pixel electrode having a same edge part as the pixel electrode or an edge part located at inner side from an edge part of the pixel electrode and exposing the pixel electrode of the transmission hole. | 2009-11-05 |
20090275156 | Light-emitting gallium nitride-based III-V group compound semiconductor device and manufacturing method thereof - A light-emitting gallium nitride-based III-V group compound semiconductor device and a manufacturing method thereof are disclosed. The light emitting device includes a substrate, a n-type semiconductor layer over the substrate, an active layer over the n-type semiconductor layer, a p-type semiconductor layer over the active layer, a conductive layer over the p-type semiconductor layer, a first electrode disposed on the conductive layer and a second electrode arranged on exposed part of the n-type semiconductor layer. A resistant reflective layer or a contact window is disposed on the p-type semiconductor layer, corresponding to the first electrode so that current passes beside the resistant reflective layer or by the contact window to the active layer for generating light. When the light is transmitted to the conductive layer for being emitted, it is not absorbed or shielded by the first electrode. Thus the current is distributed efficiently over the conductive layer. Therefore, both LED brightness and efficiency are improved. Moreover, adhesion between the conductive layer and the p-type semiconductor layer is improved so that metal peel-off problem during manufacturing processes can be improved. | 2009-11-05 |
20090275157 | OPTICAL DEVICE SHAPING - Embodiments described herein provide methods for manufacturing an optical device having shaped sidewalls. A desired substrate shape corresponding to an LED or other optical device can be determined. The optical device can have a substrate comprising an exit face and sidewalls positioned and shaped to reflect light to the exit face to allow light to escape the exit face. A substrate material can be shaped based on the desired substrate shape for one or more LEDs. Shaping can be done using a wire saw, etching, ultrasonic shaping or other technique. | 2009-11-05 |
20090275158 | MANUFACTURING METHOD OF DISPLAY DEVICE - A liquid crystal display device having high quality and high reliability is manufactured by preventing the occurrence of damages on a terminal portion due to the radiation of laser beams in cutting a substrate of the display device which is formed using a plastic substrate by the radiation of laser beams. A first substrate has a cutting line at a position which faces a terminal portion of a second substrate. In cutting the first substrate along the cutting line, laser beams are radiated to the first substrate along the cutting line so as to form a groove having a predetermined depth in the first substrate. Then, a load is applied to the first substrate along the groove so as to cut the first substrate. | 2009-11-05 |
20090275159 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LASER ELEMENT - A method for manufacturing a nitride semiconductor laser element having a nitride semiconductor layer including at least an active layer provided on a substrate, a pair of cavity planes formed on the nitride semiconductor layer, and a protruding part where part of the substrate protrudes from said cavity plane, said method comprises: a step of forming the nitride semiconductor layer on the substrate; a first etching step of forming a first groove by etching at least the nitride semiconductor layer; and a second etching step of forming the cavity plane, in the second etching step, the inner wall of the first groove and part of the nitride semiconductor layer surface adjacent to the first groove are etched to form a second groove, and form the upper face of the protruding part. | 2009-11-05 |
20090275160 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - After a p-type cladding layer, an etching rate reducing layer and a p-type contact layer are formed in order on an n-type substrate, an etching mask is formed. Then, by using the etching mask, the p-type contact layer, the etching rate reducing layer and the p-type cladding layer are partially etched in the region outside the etching mask with an etchant. At this time, the etching rate of the layers by the etchant is slower in the etching rate reducing layer than in the p-type cladding layer and the p-type contact layer. Then, a metal thin film is formed such that the film continuously coats an upper surface and side surfaces of a ridge consisting of the above layers left after the etching step. A normal vector at a surface coated with the thin film has an upward component. | 2009-11-05 |
20090275161 | LIGHT-EMITTING ELEMENT AND LIGHT EMITTING DEVICE USING THE SAME - The present invention provides a light-emitting element having less increase in driving voltage with the accumulation of light-emission time, and provides a light-emitting element having less increase in resistance value with the increase in film thickness. A light-emitting element includes a first layer, a second layer and a third layer between a first electrode and a second electrode. The first layer is provided to be closer to the first electrode than the second layer, and the third layer is provided to be closer to the second electrode than the second layer. The first layer is a layer including an aromatic amine compound and a substance showing an electron accepting property to the aromatic amine compound. The second layer includes a substance of which an electron transporting property is stronger than a hole transporting property, and a substance showing an electron donating property to the aforementioned substance. | 2009-11-05 |
20090275162 | CMOS-COMPATIBLE BULK-MICROMACHINING PROCESS FOR SINGLE-CRYSTAL MEMS/NEMS DEVICES - A process producing a single-crystalline device fabricated on a single-sided polished wafer employing processing from only the front-side and having a significant separation between the device and substrate is provided. In one embodiment, a method comprises an upper layer and a lower substrate. A device is formed in the upper layer, defined by gaps. The gaps are filled with at least one material that has etch characteristics different from those of the device and the substrate. At least a top portion of the gap material is removed from the upper layer. The gap material is etched so that a portion of the gap-material remains on the sidewalls of the surrounding upper layer. The material beneath the device is then etched, excluding an insulating layer beneath the device, releasing the device from the substrate. The insulating material beneath the device is then etched, the etch being selective to the insulating material and the gap material. | 2009-11-05 |
20090275163 | System and Method of Encapsulation - Embodiments discussed herein generally include methods of fabricating MEMS devices within a structure. The MEMS device may be formed in a cavity above the structure, and additional metallization may occur above the MEMS device. The cavity may be formed by depositing an encapsulating layer over the sacrificial layers that enclose the MEMS device. The encapsulating layer may then be etched to expose portions of the sacrificial layers. The sacrificial layers are exposed because they extend through the sidewalls of the encapsulating layer. Therefore, no release holes are etched through the top of the encapsulating layer. An etchant then removes the sacrificial layers to free the MEMS device and form the cavity and an opening through the sidewall of the encapsulating layer. Another encapsulating layer may then be deposited to seal the cavity and the opening. | 2009-11-05 |
20090275164 | BICYCLIC GUANIDINATES AND BRIDGING DIAMIDES AS CVD/ALD PRECURSORS - Precursors for use in depositing metal-containing films on substrates such as wafers or other microelectronic device substrates, as well as associated processes of making and using such precursors, and source packages of such precursors. The precursors are useful for depositing Ge | 2009-11-05 |
20090275165 | PROCESS FOR FABRICATING A HIGH-INTEGRATION-DENSITY IMAGE SENSOR - The invention relates to the fabrication of an electronic component having a very high integration density, notably an image sensor. The component comprises two, superposed integrated circuits, one of which one (the image sensor) is formed on the front side of a thinned first silicon substrate ( | 2009-11-05 |
20090275166 | Method for manufacturing infrared detecting device - A semiconductor layer is prepared in which a silicon substrate, a BOX layer and an SOI layer are laminated in this order. A silicon diode section used as an infrared detection portion is formed in the SOI layer. Further, an isolation portion is formed so as to extend from the SOI layer to a predetermined depth of the silicon substrate via the BOX layer. The isolation portion is formed so as to surround an area in which the silicon diode section is formed, and have the form of a circle or a regular polygon more than a regular pentagon in shape. A protective film is formed on the surface of the SOI layer. Thereafter, etching holes that penetrate the protective film, the SOI layer and the BOX layer are formed. The silicon substrate corresponding to each area surrounded by the isolation portion is etched using the etching holes. | 2009-11-05 |
20090275167 | METHOD MAKING AN ELECTRICAL DEVICE - Conventionally, organic semiconductor devices are usually formed by either laser ablation, photolithography or by conductive inkjet printing. All these methods have short coming such as either being unsuitable for high volume production, slow, expensive or as is particularly the case in inject printing, the choice of metals used is restricted to those which can be formed as inks. The present invention employs flexography to print a resist pattern ( | 2009-11-05 |
20090275168 | PHASE CHANGE MATERIAL WITH FILAMENT ELECTRODE - The present invention, in one embodiment, provides a memory device that includes a phase change memory cell; a first electrode; and a layer of filamentary resistor material positioned between the phase change memory cell and the first electrode, wherein at least one bistable conductive filamentary pathway is present in at least a portion of the layer of filamentary resistor material that provides electrical communication between the phase change memory cell and the first electrode. | 2009-11-05 |
20090275169 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A semiconductor device which includes a reaction prevention layer between a resistive memory element and an insulating layer and a method of forming the same. | 2009-11-05 |
20090275170 | LOW TEMPERATURE HERMETIC BONDING AT WATER LEVEL AND METHOD OF BONDING FOR MICRO DISPLAY APPLICATION - A spatial light modulator is fabricated by bonding a capping layer over a wafer bearing active reflecting surfaces utilizing a low temperature bonding agent capable of providing a hermetic seal, such as a glass frit. The low temperature bonding agent may be B-stage cured after application to the capping layer, prior to any exposure to the substrate bearing the reflecting surfaces. In accordance with one embodiment of the present invention, the capping layer may comprise a glass wafer pre-bonded with an interposer spacer layer to provide sufficient stand-off between the capping layer and the underlying reflecting structures. In accordance with an alternative embodiment of the present invention, the capping layer may comprise a glass wafer alone, and the bonding agent may include additional materials such as beads or balls to provide the necessary stand-off between the capping layer and the underlying reflective structures. | 2009-11-05 |
20090275171 | METHODS FOR ASSEMBLING THIN SEMICONDUCTOR DIE - The invention is based on the discovery that certain self-filleting die attach adhesives are useful in semiconductor die assemblies containing thin die. As used herein, the term “self-filleting” refers to any adhesive that when dispensed and then subjected to suitable cure conditions, will flow and fill up the area between two die or between a die and a substrate while not forming a bulky fillet that can overflow onto the top of the die. In addition, the invention is useful for tight tolerance semiconductor die assemblies, since the fillet from the die-attach adhesives employed in the methods of the invention does not cover bond fingers, thereby causing wire bond yield loss. | 2009-11-05 |
20090275172 | STACKING SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - In a stacking semiconductor device in which a first-layer and a second-layer semiconductor devices are stacked and bonded with a solder, warpage occurs due to a difference in thermal expansion coefficient of constituent members or a difference in elastic modulus of individual members. Therefore, between the first-layer and the second-layer semiconductor devices are provided an external connection terminal of solder and a thermosetting resin, and the stacking semiconductor device is heated at 150 to 180° C., which are the temperatures of preheating for reflow of the solder, for 30 to 90 seconds. Thereby the warpage of the first-layer semiconductor device is reduced and the thermosetting resin is cured completely in this state. Then, the temperature is raised to a reflow temperature of the solder and solder bonding using the external connection terminal is performed. Thereby, the bonding reliability of a solder-bonded portion of the stacking semiconductor device is considerably improved. | 2009-11-05 |
20090275173 | METHODS FOR REDUCING STRESS IN MICROELECTRONIC DEVICES AND MICROELECTRONIC DEVICES FORMED USING SUCH METHODS - Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One such device can include a first support member, a second support member, and a microelectronic die positioned between the first support member and the second support member such that the second support member at least approximately completely covers a surface of the die. The die is in intimate contact with both the first support member and the second support member and electrically coupled to at least one of the first support member and the second support member. The device further includes a fill material between the first and second support members and at least partially encapsulating the die. The second support member has structural material characteristics that are closer to those of the first support member than to the structural material characteristics of the fill material. | 2009-11-05 |
20090275174 | Soldering Container and Production Method of Semiconductor Device - A soldering container configured to be conveyed by a conveyance mechanism during soldering in a state accommodating a soldering subject. The container includes a sealable container body for accommodating the soldering subject. The container body includes at least one communication passage enabling communication between the inside and outside of the container body. The container body is configured to be connectable to an atmospheric adjustment device for adjusting an internal atmosphere of the container body through the communication passage. | 2009-11-05 |
20090275175 | MODIFIED CHIP ATTACH PROCESS - A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time. | 2009-11-05 |
20090275176 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile. | 2009-11-05 |
20090275177 | SEMICONDUCTOR DEVICE WITH MULTIPLE CHANNELS AND METHOD OF FABRICATING THE SAME - A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer. | 2009-11-05 |
20090275178 | METHOD OF MANUFACTURING POLYSILICON THIN FILM AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR HAVING THE SAME - In a method of manufacturing a polysilicon thin film and a method of manufacturing a TFT having the thin film, a laser beam is irradiated on a portion of an amorphous silicon thin film to liquefy the portion of the amorphous silicon thin film. The amorphous silicon thin film is on a first end portion of a substrate. The liquefied silicon is crystallized to form silicon grains. The laser beam is shifted from the first end portion towards a second end portion of the substrate opposite the first end portion by an interval in a first direction. The laser beam is then irradiated onto a portion of the amorphous silicon thin film adjacent to the silicon grains to form a first polysilicon thin film. Therefore, electrical characteristics of the amorphous silicon thin film may be improved. | 2009-11-05 |
20090275179 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH AN ELECTROPLATED METAL REPLACEMENT GATE - Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam-free metal gate conductor layer positioned on top of a relatively thin high-k gate dielectric layer. These method embodiments incorporate a gate replacement strategy that uses an electroplating process to fill, from the bottom upward, a high-aspect ratio gate stack opening with a metal gate conductor layer. The source of electrons for the electroplating process is a current passed directly through the back side of the substrate. This eliminates the need for a seed layer and ensures that the metal gate conductor layer will be formed without voids or seams. Furthermore, depending upon the embodiment, the electroplating process is performed under illumination to enhance electron flow to a given area (i.e., to enhance plating) or in darkness to prevent electron flow to a given area (i.e., to prevent plating). | 2009-11-05 |
20090275180 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one. | 2009-11-05 |
20090275181 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an example of the present invention includes a first semiconductor region of a first conductivity type, a first MIS transistor of a second conductivity type formed in the first semiconductor region, a second semiconductor region of a second conductivity type, and a second MIS transistor of a first conductivity type formed in the second semiconductor region. A first gate insulating layer of the first MIS transistor is thicker than a second gate insulating layer of the second MIS transistor, and a profile of impurities of the first conductivity type in a channel region of the second MIS transistor has peaks. | 2009-11-05 |
20090275182 | METHOD FOR FABRICATING A METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE - A method is provided for fabricating a transistor. A silicon layer is provided, and a first layer comprising a high dielectric constant material is formed on the silicon layer. A second layer including a metal or metal alloy is formed on the first layer, and a third layer including silicon or polysilicon is formed on the second layer. The first, second, and third layers are etched so as to form a gate stack, and ions are implanted to form source and drain regions in the silicon layer. Source and drain silicide contact areas are formed in the source and drain regions, and a gate silicide contact area is formed in the third layer. After forming these silicide contact areas, the third layer is etched without etching the first and second layers, so as to substantially reduce the width of the third layer. | 2009-11-05 |
20090275183 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A thermal oxidation method capable of obtaining a high oxidation rate by generating a sufficient enhanced-rate oxidation phenomenon even in a low temperature region is provided. In addition, a thermal oxidation method capable of forming a silicon oxide film having a high reliability even when formed at a low temperature region. A basic concept herein is to form a silicon oxide film by thermal reaction by generating a large amount of oxygen radicals (O*) having a large reactivity without using plasma. More specifically, ozone (O | 2009-11-05 |
20090275184 | Fabricating Method of Semiconductor Device - Disclosed is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes removing a part of an isolation layer from a semiconductor substrate such that an active area of the semiconductor substrate protrudes from the isolation layer; rounding edge portions of the active area; forming a gate insulating layer and a gate electrode on the active area; and forming source and drain impurity areas in the active area adjacent to sides of the gate electrode. | 2009-11-05 |
20090275185 | METHODS OF FORMING CAPACITORS - A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated. | 2009-11-05 |
20090275186 | METHOD FOR FORMING CAPACITOR OF SEMICONDUCTOR DEVICE - Forming a capacitor of a semiconductor device includes forming an interlayer dielectric having holes over a semiconductor substrate. A conductive layer is then formed on surfaces of the holes and on the upper surface of the interlayer dielectric. A silicon-containing conductive layer is formed by flowing a silicon source gas for the semiconductor substrate formed with the conductive layer, so that silicon atoms can penetrate into the conductive layer. The silicon-containing conductive layer prevents etchant from infiltrating the interlayer dielectric below the silicon-containing conductive layer. | 2009-11-05 |
20090275187 | METHODS OF FORMING CAPACITORS - A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode | 2009-11-05 |
20090275188 | Slurry for polishing phase change material and method for patterning polishing phase change material using the same - Disclosed is a slurry for polishing a phase change material. The slurry includes an abrasive, an alkaline polishing promoter and deionized water. Due to the use of the abrasive and the alkaline polishing promoter, the pH of the slurry is adjusted, the polishing rate of the phase change material is improved, and the polishing selectivity of the phase change material to an underlying insulating layer is increased. Further disclosed is a method for patterning a phase change material using the slurry. | 2009-11-05 |
20090275189 | Method for manufacturing silicon on sapphire wafer - The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side. | 2009-11-05 |
20090275190 | METHOD FOR FORMING BUFFER LAYER FOR GaN SINGLE CRYSTAL - Disclosed is a method for forming a buffer layer for growing gallium nitride single crystals on a sapphire substrate using hydride vapor phase epitaxy (HVPE), wherein the buffer layer is formed in the form of a doped vertical gallium nitride (GaN) single crystal film with a nanoporosity of 0.10 to 0.15 μm on the sapphire substrate by reacting HCl and NH | 2009-11-05 |
20090275191 | METHOD AND APPARATUS FOR ELECTROSTATIC DISCHARGE PROTECTION USING A TEMPORARY CONDUCTIVE COATING - A method and apparatus for providing ESD protection of an integrated circuit using a temporary conductive coating. The method deposits a temporary conductive coating upon a chip die between contacts to be protected such that a conductive path is created between contacts, provides a carrier substrate that is then bonded to the chip die and then the conductive coating is deactivated to ready the device for use. The deactivation of the conductive coating may involve physical removal of the conductive coating (or a portion thereof), oxidation of the conductive coating to form a non-conductive coating, or some other process to interrupt the conductive path between contacts. The apparatus of the invention is a chip having a temporary conductive coating deposited thereon to protect the integrated circuit from ESD events. | 2009-11-05 |
20090275192 | MOLDED DIELECTRIC LAYER IN PRINT-PATTERNED ELECTRONIC CIRCUITS - A method forms a first active electronic layer, prints an array of pillars on the first active electronic layer, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the curable polymer with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer. Another method provides a substrate having selected areas, prints an array of pillars on the substrate, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer corresponding to the selected areas. Another method forms a first active electronic layer on a substrate, prints an array of conductive pillars on the active electronic layer on a substrate, dispenses a curable polymer on the array of conductive pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from the upper surfaces of the conductive pillars, curing the curable polymer to produce a hardened polymer, and forms a second active electronic layer on the hardened polymer such that the second active electronic layer is in electrical connection with the first active electronic layer through the conductive pillars. | 2009-11-05 |
20090275193 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light. | 2009-11-05 |
20090275194 | SEMICONDUCTOR DEVICE HAVING MULTIPLE WIRING LAYERS AND METHOD OF PRODUCING THE SAME - A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled. | 2009-11-05 |
20090275195 | Interconnect Structure Having a Silicide/Germanide Cap Layer - An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide. | 2009-11-05 |
20090275196 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 2009-11-05 |
20090275197 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A hole is formed in an insulating layer. A semiconductor substrate is heated at a temperature of equal to or more than 330° C. and equal to or less than 400° C. Tungsten-containing gas and at least one of B | 2009-11-05 |
20090275198 | Vapor Phase Methods for Forming Electrodes in Phase Change Memory Devices - A method for forming electrode materials uniformly and conformally within openings having small dimensions, including sublithographic dimensions, or high aspect ratios. The method includes the steps of providing an insulator layer having an opening formed therein, and forming a conformal conductive or semiresistive material over and within the opening. The method is a CVD or ALD process for forming metal nitride, metal aluminum nitride, and metal silicon nitride electrode compositions. The methods utilize metal precursors containing one or more ligands selected from alkyl, allyl, alkene, alkyne, acyl, amide, amine, immine, imide, azide, hydrazine, silyl, alkylsilyl, silylamine, chelating, hydride, cyclic, carbocyclic, cyclopentadienyl, phosphine, carbonyl, or halide. Suitable precursors include monometallic precursors having the general formula MR | 2009-11-05 |
20090275199 | UNSYMMETRICAL LIGAND SOURCES, REDUCED SYMMETRY METAL-CONTAINING COMPOUNDS, AND SYSTEMS AND METHODS INCLUDING SAME - The present invention provides metal-containing compounds that include at least one β-diketiminate ligand, and methods of making and using the same. In some embodiments, the metal-containing compounds are homoleptic complexes that include unsymmetrical β-diketiminate ligands. In other embodiments, the metal-containing compounds are heteroleptic complexes including at least one β-diketiminate ligand. The compounds can be used to deposit metal-containing layers using vapor deposition methods. Vapor deposition systems including the compounds are also provided. Sources for β-diketiminate ligands are also provided. | 2009-11-05 |
20090275200 | TECHNIQUE FOR REDUCING TOPOGRAPHY-RELATED IRREGULARITIES DURING THE PATTERNING OF A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS - In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond. | 2009-11-05 |
20090275201 | SUBSTRATE PROCESSING SYSTEM - A substrate processing method implemented in a substrate processing system that includes an etching apparatus that carries out plasma etching processing on a substrate and a vacuum-type substrate transferring apparatus to which the etching apparatus is connected is provided. A first step includes forming a protective film on a rear surface of the substrate before the plasma etching processing is carried out. The protective film prevents the rear surface of the substrate from being scratched by an electrostatic chuck that electrostatically attracts the substrate during the plasma etching processing. A second step includes electrostatically attracting the substrate to the electrostatic chuck such that the electrostatic chuck directly contacts the rear surface of the substrate and of carrying out the plasma etching processing on the substrate. A third step includes removing the protective film from the rear surface of the substrate after the plasma etching processing has been carried out. | 2009-11-05 |
20090275202 | SILICON STRUCTURE HAVING AN OPENING WHICH HAS A HIGH ASPECT RATIO, METHOD FOR MANUFACTURING THE SAME, SYSTEM FOR MANUFACTURING THE SAME, AND PROGRAM FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING ETCHING MASK FOR THE SILICON STRUCTURE - Provided are a silicon structure having an opening which has a high aspect ratio and an etching mask for forming the silicon structure. A step of performing hole etching or trench etching of silicon so as to substantially expose a portion of at least a bottom surface of etched silicon and a step of forming a silicon oxide film by a CVD method on the silicon structure formed by the step of performing the hole etching or the trench etching are conducted. Thereafter, a step of exposing the formed silicon oxide film to a gas containing a hydrogen fluoride vapor is conducted. Further, the above-mentioned step of performing the hole etching or the trench etching is conducted again. | 2009-11-05 |
20090275203 | METHOD FOR PROCESSING A THIN FILM MICRO DEVICE ON A SUBSTRATE - A method for processing a thin film micro device on a substrate includes: 1) depositing a carbon film on the substrate as a sacrificial layer; 2) photolithographically defining a first predetermined pattern in the carbon film; 3) etching an unwanted portion of the carbon film outside the first predetermined pattern; 4) depositing a structural film including a single or multiple layers of solid state materials; 5) photolithographically defining a second predetermined pattern in the structural film; 6) etching the discarded portion of the structural film outside the second predetermined pattern; 7) selectively removing the remaining portion of the sacrificial carbon film by using a selective etch process gas in a reactor chamber, so that the overlapped portion of the remaining structural element with the first predetermined pattern is suspended above an underneath cavity above the substrate. | 2009-11-05 |
20090275204 | METHOD FOR ABATING EFFLUENT FROM AN ETCHING PROCESS - A method for abating effluent from an etching process in one embodiment includes advancing etch gas product into a passageway of a gas connector in direct fluid communication with a first chamber of an interior void of an apparatus, advancing a gas from a gas source into said passageway of said gas connector at the same time said etch gas product is being advanced into said passageway, and advancing humidified gas from a humidified gas source into a second chamber of said interior void. | 2009-11-05 |
20090275205 | METHODS OF REMOVING SILICON OXIDE AND GASEOUS MIXTURES FOR ACHIEVING SAME - A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising a substrate and the silicon oxide to an ammonium fluoride chemical treatment and a subsequent plasma treatment, both of which may be effected in the same vacuum chamber of a processing apparatus. The ammonium fluoride chemical treatment converts the silicon oxide to a solid reaction product in a self-limiting reaction, the solid reaction product then being volatilized by the plasma treatment. The plasma treatment includes a plasma having an ion bombardment energy of less than or equal to approximately 20 eV. An ammonium fluoride chemical treatment including an alkylated ammonia derivative and hydrogen fluoride is also disclosed. | 2009-11-05 |
20090275206 | PLASMA PROCESS EMPLOYING MULTIPLE ZONE GAS DISTRIBUTION FOR IMPROVED UNIFORMITY OF CRITICAL DIMENSION BIAS - A passivation species precursor gas is furnished to an inner zone at a first flow rate, while flowing an etchant species precursor gas an annular intermediate zone at a second flow rate. Radial distribution of etch rate is controlled by the ratio of the first and second flow rates. The radial distribution of etch critical dimension bias on the wafer is controlled by flow rate of passivation gas to the wafer edge. | 2009-11-05 |