44th week of 2021 patent applcation highlights part 60 |
Patent application number | Title | Published |
20210343622 | PACKAGE STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A package structure includes a first die, an encapsulant and a securing element. The encapsulant encapsulates the first die. The securing element penetrates through the encapsulant and a corner of the first die and electrically isolated from the first die. | 2021-11-04 |
20210343623 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An object of the present invention is to provide a semiconductor device whose surfaces on both sides can be cooled and which has a function of insulating, on both the surfaces, the internal structure of a semiconductor package from the outside. The semiconductor device includes a first semiconductor package and a second semiconductor package. The second semiconductor package is joined on the first semiconductor package in such a manner that a first exposed surface of the first semiconductor package and a fourth exposed surface of the second semiconductor package are connected so as to face each other, and a second exposed surface of the first semiconductor package and a third exposed surface of the second semiconductor package are connected so as to face each other. | 2021-11-04 |
20210343624 | Memory Arrays And Methods Used In Forming A Memory Array And Conductive Through-Array-Vias (TAVs) - A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack. | 2021-11-04 |
20210343625 | METHOD FOR PACKAGING SEMICONDUCTOR, SEMICONDUCTOR PACKAGE STRUCTURE, AND PACKAGE - Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and covering a cover plate wafer on the first surface of the substrate wafer to seal up the groove so as to form a semiconductor package structure, a gap between the substrate wafer, the semiconductor die stack and the cover plate wafer being not filled with a filler. | 2021-11-04 |
20210343626 | Semiconductor Package and Method - In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy. | 2021-11-04 |
20210343627 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE - A semiconductor device including a lead frame, a die attached to the lead frame using a first solder, and a clip attached to the die using a second solder is provided. The clip includes a notch arranged for a check of the excess of the second solder. | 2021-11-04 |
20210343628 | PACKAGE STRUCTURE APPLIED TO POWER CONVERTER - A package structure applied to power converters can include: a first die having a first power transistor and a first control and drive circuit; a second die having a second power transistor; a connection device configured to couple the first and second power transistors in series between a high-level pin and a low-level pin of a lead frame of the package structure; and where a common node of the first and second power transistors can be coupled to an output pin of the lead frame through a metal connection structure with a low interconnection resistance. | 2021-11-04 |
20210343629 | SEMICONDUCTOR DEVICE - A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction. | 2021-11-04 |
20210343630 | SEMICONDUCTOR PACKAGE AND METHOD OF MAKING THE SAME - A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second low side FET, a first high side FET, a second high side FET, a first metal clip, a second metal clip, and a molding encapsulation. The semiconductor package further comprises an optional integrated circuit (IC) controller or an optional inductor. A method for fabricating a semiconductor package. The method comprises the steps of providing a lead frame; attaching a first low side FET, a second low side FET, a first high side FET, and a second high side FET to the lead frame; mounting a first metal clip and a second metal clip; forming a molding encapsulation; and applying a singulation process. | 2021-11-04 |
20210343631 | SEMICONDUCTOR PACKAGE - Provided is a semiconductor package in which a bonding structure is formed using metal grains included in metal powder layers having a coefficient of thermal expansion (CTE) similar with those of a substrate and a conductor so as to minimize generation of cracks and to improve reliability of bonded parts. | 2021-11-04 |
20210343632 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A package structure and a method for manufacturing a package structure are provided. The package structure includes a substrate, at least one redistribution structure, at least one electronic component and at least one semiconductor die. The substrate has a first surface and a second surface opposite to the first surface. The at least one redistribution structure is disposed on the first surface of the substrate. The at least one electronic component is disposed on the first surface of the substrate. The at least one semiconductor die is disposed on the at least one redistribution structure and electrically connected to the at least one electronic component through the substrate. | 2021-11-04 |
20210343633 | PACKAGE SUBSTRATE INSULATION OPENING DESIGN - A semiconductor package includes: a substrate; a first dielectric layer over the substrate; a first bond pad and a second bond pad over the first dielectric layer, the first bond pad having a first sidewall facing the second bond pad; a second dielectric layer over the first and the second bond pads; and an opening through the second dielectric layer and extending from the first bond pad to the second bond pad, the opening including a first area over and exposing the first bond pad, where in a top view, the opening exposes a first segment of the first sidewall disposed between a first edge and a second edge of the first area that intersect the first sidewall, where the first segment of the first sidewall is between a second segment and a third segment of the first sidewall, the second segment being covered by the second dielectric layer. | 2021-11-04 |
20210343634 | INTERCONNECTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - An interconnection structure includes a dielectric layer, and a wiring pattern in the dielectric layer. The wiring pattern includes a via body, a first pad body that vertically overlaps the via body, and a line body that extends from the first pad body. The via body, the first pad body, and the line body are integrally connected to each other, and a level of a bottom surface of the first pad body is lower than a level of a bottom surface of the line body. | 2021-11-04 |
20210343635 | INTERCONNECTION STRUCTURE FABRICATION USING GRAYSCALE LITHOGRAPHY - An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle. | 2021-11-04 |
20210343636 | SEMICONDUCTOR DEVICE AND LAYOUT DESIGN THEREOF - A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance. | 2021-11-04 |
20210343637 | MICROELECTRONIC DEVICES INCLUDING STADIUM STRUCTURES, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A microelectronic device comprises a stack structure, a stadium structure within the stack structure, and conductive contact structures. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each of the tiers comprises one of the conductive structures and one of the insulative structures. The stadium structure comprises a forward staircase structure having steps comprising edges of the tiers, and a reverse staircase structure opposing the forward staircase structure and having additional steps comprising additional edges of the tiers. The conductive contact structures vertically extend to upper vertical boundaries of at least some of the conductive structures of the stack structure at the steps of the forward staircase structure and the additional steps of the reverse staircase structure, and are each integral and continuous with one of the conductive structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described. | 2021-11-04 |
20210343638 | SENSOR PACKAGE AND METHOD - A device includes a sensor die having a sensing region at a top surface of the sensor die, an encapsulant at least laterally encapsulating the sensor die, a conductive via extending through the encapsulant, and a front-side redistribution structure on the encapsulant and on the top surface of the sensor die, wherein the front-side redistribution structure is connected to the conductive via and the sensor die, wherein an opening in the front-side redistribution structure exposes the sensing region of the sensor die, and wherein the front-side redistribution structure includes a first dielectric layer extending over the encapsulant and the top surface of the sensor die, a metallization pattern on the first dielectric layer, and a second dielectric layer extending over the metallization pattern and the first dielectric layer. | 2021-11-04 |
20210343639 | INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE VIA - An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer. | 2021-11-04 |
20210343640 | Memory Arrays Comprising Operative Channel-Material Strings And Dummy Pillars - A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed. | 2021-11-04 |
20210343641 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad. | 2021-11-04 |
20210343642 | THIN FILM RESISTOR WITH PUNCH-THROUGH VIAS - A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer. | 2021-11-04 |
20210343643 | TOP VIA INTERCONNECT HAVING A LINE WITH A REDUCED BOTTOM DIMENSION - A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line. | 2021-11-04 |
20210343644 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate, memory blocks, a first wiring, a second wiring, a first contact, a first transistor, and a second transistor. The memory blocks are spaced from the semiconductor substrate in a first direction and are arranged in a second direction. The first wiring is farther from the semiconductor substrate than the memory blocks. The second wiring is closer to the semiconductor substrate than the memory blocks. The first contact is electrically connected between the first wiring and the second wiring. The first and second transistors are disposed on the semiconductor substrate. The first transistor is electrically connected between the second wiring and a first memory block. The second transistor is electrically connected between the second wiring and a second memory block. The first contact is disposed between the first transistor and the second transistor in the second direction. | 2021-11-04 |
20210343645 | INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME - An integrated circuit includes a strip structure having a front side and a back side. A gate structure is on the front side of the strip structure. The integrated circuit includes a plurality of channel layers above the front side of the strip structure, wherein each of the plurality of channel layers is enclosed within the gate structure. An isolation structure surrounds the strip structure. The integrated circuit includes a backside via in the isolation structure. An epitaxy structure is on the front side of the strip structure. The integrated circuit includes a contact over the epitaxy structure. The contact has a first portion on a first side of the epitaxy structure. The first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and contacting the backside via. | 2021-11-04 |
20210343646 | INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME - A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via. | 2021-11-04 |
20210343647 | LOW RESISTANCE CONTACTS INCLUDING INTERMETALLIC ALLOY OF NICKEL, PLATINUM, TITANIUM, ALUMINUM AND TYPE IV SEMICONDUCTOR ELEMENTS - A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device. | 2021-11-04 |
20210343648 | EMBEDDED COMPONENT PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed. | 2021-11-04 |
20210343649 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a first substrate, a second substrate and an interconnection. The second substrate is arranged above the first substrate and has an opening. The interconnection passes through the opening and connects to the first substrate and the second substrate. | 2021-11-04 |
20210343650 | POWER DISTRIBUTION STRUCTURE AND METHOD - An IC package includes a first die including a front side and a back side, the front side including a first signal routing structure, the back side including a first power distribution structure, and a second die including a front side and a back side, the front side including a second signal routing structure, the back side including a second power distribution structure. The IC package includes a third power distribution structure positioned between the first and second power distribution structures and electrically connected to each of the first and second power distribution structures. | 2021-11-04 |
20210343651 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies. | 2021-11-04 |
20210343652 | METHOD FOR FORMING CHIP PACKAGE STRUCTURE - A method for forming a chip package structure is provided. The method includes forming a conductive pad over a carrier substrate. The method includes forming a substrate layer over the carrier substrate, wherein the conductive pad is embedded in the substrate layer, and the substrate layer includes fibers. The method includes forming a through hole in the substrate layer and exposing the conductive pad. The method includes forming a conductive pillar in the through hole. The method includes forming a recess in the substrate layer. The method includes disposing a chip in the recess. The method includes forming a molding layer in the recess. The method includes forming a redistribution structure over the substrate layer, the conductive pillar, the molding layer, and the chip. The method includes removing the carrier substrate. | 2021-11-04 |
20210343653 | PANEL LEVEL PACKAGING FOR MULTI-DIE PRODUCTS INTERCONNECTED WITH VERY HIGH DENSITY (VHD) INTERCONNECT LAYERS - A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed. | 2021-11-04 |
20210343654 | SEMICONDUCTOR PACKAGE WITH AIR GAP AND MANUFACTURING METHOD THEREOF - The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions to of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package. | 2021-11-04 |
20210343655 | SUPPORTS FOR THINNED SEMICONDUCTOR SUBSTRATES AND RELATED METHODS - Implementations of a semiconductor substrate may include a wafer including a first side and a second side; and a support structure coupled to the wafer at a desired location on the first side, the second side, or both the first side and the second side. The support structure may include an organic compound. | 2021-11-04 |
20210343656 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip including a chip pad, a first insulating layer provided on the semiconductor chip and including a first via hole, a first wiring pattern provided on the first insulating layer and connected to the chip pad through the first via hole of the first insulating layer, a second insulating layer provided on the first insulating layer and the first wiring pattern and including a second via hole, and a second wiring pattern provided on the second insulating layer and connected to the first wiring pattern through the second via hole of the second insulating layer, wherein the first insulating layer includes a first upper surface in contact with the second insulating layer and a first lower surface opposite to the first upper surface, and the first upper surface of the first insulating layer has surface roughness greater that the first lower surface of the first insulating layer. | 2021-11-04 |
20210343657 | MULTIDIE SUPPORTS AND RELATED METHODS - Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns. | 2021-11-04 |
20210343658 | DIE EMBEDDED IN SUBSTRATE WITH STRESS BUFFER - The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages. | 2021-11-04 |
20210343659 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip disposed in the through hole and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filing at least a portion of the through hole, and a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad. | 2021-11-04 |
20210343660 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the semiconductor chip and the dummy chip in the direction perpendicular to the first surface of the substrate, an upper end of the extension portion being disposed to be lower than the upper surface of the semiconductor chip; and a sealing material disposed on the first surface of the substrate, and sealing the semiconductor chip and the dummy chip. | 2021-11-04 |
20210343661 | VERTICALLY-ALIGNED AND CONDUCTIVE DUMMIES IN INTEGRATED CIRCUIT LAYERS FOR CAPACITANCE REDUCTION AND BIAS INDEPENDENCE AND METHODS OF MANUFACTURE - Vertically-aligned and conductive dummies in integrated circuit (IC) layers reduce capacitance and bias independence. Dummies are islands of material in areas of metal and semiconductor IC layers without circuit features to avoid non-uniform polishing (“dishing”). Conductive diffusion layer dummies in a diffusion layer and conductive polysilicon dummies in a polysilicon layer above the diffusion layer reduce bias dependence and nonlinear circuit operation in the presence of an applied varying voltage. ICs with metal dummies vertically aligned in at least one metal layer above the polysilicon dummies and diffusion dummies reduce lateral coupling capacitance compared to ICs in which dummies are dispersed in a non-overlapping layout by a foundry layout tool. Avoiding lateral resistance-capacitance (RC) ladder networks created by dispersed dummies improves signal delays and power consumption in radio-frequency ICs. | 2021-11-04 |
20210343662 | INTEGRATED CIRCUIT - An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes a substrate having an electronic component. A substrate-based coil is on the substrate and the substrate-based coil is electrically coupled to the electronic component. A magnetic mold compound encapsulates the substrate-based coil and the electronic component. | 2021-11-04 |
20210343663 | PACKAGED MODULE AND METAL PLATE - A packaged module and a metal plate. The packaged module may include a bearing structure, at least one metal strip, a circuit element, and a magnetic material. Further, a first surface of the bearing structure may bear the circuit element; two ends of each of the at least one metal strip may be coupled to the bearing structure, and a part of each metal strip other than the two ends is spaced apart from the bearing structure; and the magnetic material may cover a surface of a winding functional region of the at least one metal strip, where the winding functional region may be a part or all of the metal strip to which the winding functional region belongs. The foregoing solution helps simplify a packaging process and reduce losses and manufacturing costs of the packaged module. | 2021-11-04 |
20210343664 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor device package. The semiconductor device package includes a first electronic component having an active surface and a backside surface opposite to the active surface and a first antenna layer disposed on the backside surface of the first electronic component. The semiconductor device package further includes a first dielectric layer covering the first antenna layer and a second antenna layer disposed over the first antenna layer. The second antenna layer is spaced apart from the first antenna layer by the first dielectric layer. A method of manufacturing a semiconductor device package is also disclosed. | 2021-11-04 |
20210343665 | Semiconductor Device and Method of Manufacture - A semiconductor device and manufacturing process are provided wherein a first semiconductor device is electrically connected to redistribution structures. An antenna structure is located on an opposite side of the first semiconductor device from the redistribution structures, and electrical connections separate from the first semiconductor device connect the antenna structure to the redistribution structures. | 2021-11-04 |
20210343666 | PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant and a RDL structure, the encapsulant encapsulate sidewalls of the die. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die, the redistribution layer comprises a first seed layer and a first conductive layer disposed on the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer. | 2021-11-04 |
20210343667 | INTEGRATED FAN-OUT STRUCTURES AND METHODS FOR FORMING THE SAME - An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad. | 2021-11-04 |
20210343668 | SEMICONDUCTOR PACKAGE WITH AIR GAP AND MANUFACTURING METHOD THEREOF - The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package. | 2021-11-04 |
20210343669 | SEMICONDUCTOR DEVICES - A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads. | 2021-11-04 |
20210343670 | METHODS AND SYSTEMS FOR MANUFACTURING PILLAR STRUCTURES ON SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material. | 2021-11-04 |
20210343671 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a first semiconductor die having an active surface and a passive surface opposite to the active surface, a conductive element leveled with the first semiconductor die, a first redistribution layer (RDL) being closer to the passive surface than to the active surface, a second RDL being closer to the active surface than to the passive surface, and a second semiconductor die over the second RDL and electrically coupled to the first semiconductor die through the second RDL. A first conductive path is established among the first RDL, the conductive element, the second RDL, and the active surface of the first semiconductor die. | 2021-11-04 |
20210343672 | METHOD OF MANUFACTURING DIE PACKAGE STRUCTURE - A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies. | 2021-11-04 |
20210343673 | FIRST LAYER INTERCONNECT FIRST ON CARRIER APPROACH FOR EMIB PATCH - A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI. | 2021-11-04 |
20210343674 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package structure includes a first redistribution layer, a plurality of conductive connectors, a chip, and an encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The first redistribution layer includes at least one conductive pattern and at least one dielectric layer stacked on each other. The conductive pattern includes a plurality of landing pads, and each of the landing pads is separated from the dielectric layer. The conductive connectors are located on the first surface. Each of the conductive connectors is corresponding to and electrically connected to one of the landing pads. The chip is located on the first surface. The chip is electrically connected to the first redistribution layer. The encapsulant encapsulates the chip and the conductive connectors. A manufacturing method of a semiconductor package structure is also provided. | 2021-11-04 |
20210343675 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure includes a semiconductor die, a redistribution circuit structure, and conductive pads. The redistribution circuit structure is located on and electrically connected to the semiconductor die, the redistribution circuit structure includes a first contact pad having a first width and a second contact pad having a second width. The conductive pads are located on and electrically connected to the redistribution circuit structure through connecting to the first contact pad and the second contact pad, the redistribution circuit structure is located between the conductive pads and the semiconductor die. The first width of the first contact pad is less than a width of the conductive pads, and the second width of the second contact pad is substantially equal to or greater than the width of the conductive pads. | 2021-11-04 |
20210343676 | JOINT STRUCTURE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SAME - Provided is a joint structure interposed between a semiconductor element and a substrate, the joint structure including: a Sn phase; Cu alloy particles containing P in an amount of 1 mass % or more and less than 7 mass %; and Ag particles, wherein the Cu alloy particles are each coated with a Cu | 2021-11-04 |
20210343677 | UNDERFILL FLOW MANAGEMENT IN ELECTRONIC ASSEMBLIES - Disclosed herein are structures and techniques for underfill flow management in electronic assemblies. For example, in some embodiments, an electronic assembly may include a first component, a second component, an underfill on the first component and at least partially between the first component and the second component, and a material at a surface of the first component, wherein the material is outside a footprint of the second component, and the underfill contacts the material with a contact angle greater than 50 degrees. | 2021-11-04 |
20210343678 | BONDING APPARATUS, BONDING SYSTEM, BONDING METHOD, AND RECORDING MEDIUM - A bonding apparatus configured to bond substrates includes a first holder configured to vacuum-exhaust a first substrate to attract and hold the first substrate on a bottom surface thereof; a second holder disposed under the first holder and configured to vacuum-exhaust a second substrate to attract and hold the second substrate on a top surface thereof; a rotator configured to rotate the first holder and the second holder relatively; a moving device configured to move the first holder and the second holder relatively in a horizontal direction; three position measurement devices disposed at the first holder or the second holder rotated by the rotator and configured to measure a position of the first holder or the second holder; and a controller configured to control the rotator and the moving device based on measurement results of the three position measurement devices. | 2021-11-04 |
20210343679 | Wirebond-Constructed Inductors - Fabrication of a bondwire inductor between connection pads of a semiconductor package using a wire bonding process is disclosed herein. To that end, the bondwire inductor is fabricated by extending a bondwire connecting two connection pads of the semiconductor package around a dielectric structure, e.g., a dielectric post or posts, disposed between the connection pads a defined amount. In so doing, the bondwire inductor adds inductance between the connection pads, where the added inductance is defined by factors which at least include the amount the bondwire extends around the dielectric structure. Such additional inductance may be particularly beneficial for certain semiconductor devices and/or circuits, e.g., monolithic microwave integrated circuits (MMICs) to control or supplement impedance matching, harmonic termination, matching biasing, etc. | 2021-11-04 |
20210343680 | System on Integrated Chips and Methods of Forming Same - An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die. | 2021-11-04 |
20210343681 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die. | 2021-11-04 |
20210343682 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a display device is provided. The manufacturing method of the display device includes forming a switching structure. The switching structure includes a plurality of switching elements. The manufacturing method of the display device also includes forming a light-emitting structure. The light-emitting structure includes a plurality of light-emitting elements. The manufacturing method of the display device further includes arranging the light-emitting structure on the switching structure, so that each of the light-emitting elements is above each of the switching elements. The manufacturing method of the display device includes connecting each of the light-emitting elements to a corresponding switching element via a laser. | 2021-11-04 |
20210343683 | COMPONENT AND METHOD FOR PRODUCING A COMPONENT - A component having a carrier and at least one main body where the main body may include a semiconductor body and the carrier may have a mounting surface for arranging the mounting body thereon. A stopping structure may be arranged on the mounting surface and may project vertically beyond the mounting surface. The main body may be directly adjacent to the stopping structure such that the position of the main body is bounded along at least one lateral direction by the stopping structure. | 2021-11-04 |
20210343684 | STACKED DECOUPLING CAPACITORS WITH INTEGRATION IN A SUBSTRATE - Certain aspects of the present disclosure generally relate to an integrated circuit package having a land-side capacitor electrically coupled to an embedded capacitor. One example integrated circuit package generally includes a package substrate having a first capacitor embedded therein, a semiconductor die disposed above the package substrate, and a second capacitor disposed below the package substrate and electrically coupled to the first capacitor. | 2021-11-04 |
20210343685 | 3D PRINTABLE FEEDSTOCK INKS FOR SIGNAL CONTROL OR COMPUTATION - In one aspect the present disclosure relates to a 3D printed signal control backbone apparatus. The apparatus may have a filament including a first material section and a plurality of second material sections. The first material section is bounded on opposing ends by the second material sections. The first material section is formed by an ink having a percolating network of a plurality of chiplets infused in a non-conductive polymer. The plurality of chiplets form electrically responsive elements imparting a predetermined logic function and which are responsive to a predetermined electrical signal. The second material sections are formed by an ink which is electrically conductive. | 2021-11-04 |
20210343686 | METHOD AND APPARATUS FOR MANUFACTURING FLEXIBLE LIGHT-EMITTING DEVICE - According to a flexible light-emitting device production method of the present disclosure, after an intermediate region ( | 2021-11-04 |
20210343687 | Multichannel Monostatic Rangefinder - The present disclosure relates to optical systems and methods for their manufacture. An example optical system includes a first substrate having a mounting surface and a spacer structure having at least one cavity. The spacer structure is coupled to the mounting surface of the first substrate. The optical system also includes a light-emitter device that is coupled to the spacer structure and a detector device coupled to the first substrate such that the at least one detector device is disposed within the at least one cavity of the spacer structure. The optical system also includes a second substrate that mounts a lens and a waveguide and is coupled to the spacer structure. The optical system also includes a shim coupled between the second surface of the spacer structure and a mounting surface of the second substrate. | 2021-11-04 |
20210343688 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are disclosed. The display panel includes a first substrate and a camera assembly. The first substrate includes a display area and a non-display area. The display area includes a flexible base substrate, a pixel array layer, a light-emitting layer, and a touch layer all sequentially disposed in a stacked arrangement. The camera assembly is disposed on a side of the display area adjacent to the flexible base substrate, so that an opening of the camera assembly of the display panel can be omitted, and a screen ratio of the display panel and the display device can be increased. | 2021-11-04 |
20210343689 | SEMICONDUCTOR PACKAGES - A semiconductor package may include a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, and an adhesive layer between the first semiconductor chip and the second semiconductor chip. The first semiconductor chip may include a semiconductor substrate and a plurality of protection layers on the semiconductor substrate. The topmost layer of the protection layers may have a top surface with convex portions and concave portions, and the convex portions and the concave portions may be in contact with the adhesive layer. | 2021-11-04 |
20210343690 | DENSELY PACKED ELECTRONIC SYSTEMS - A glass circuit assembly employing densely packed components is described. Air cooled computer systems employing densely packed circuit components are described. Relating to agile reconfigurable computer systems a high-resolution substrate having an area of at least 100 cm | 2021-11-04 |
20210343691 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a mold substrate, at least one first semiconductor chip in the mold substrate and including chip pads, wiring bonding pads formed at a first surface of the mold substrate and connected to the chip pads by bonding wires, and a redistribution wiring layer covering the first surface of the mold substrate and including redistribution wirings connected to the wiring bonding wirings. | 2021-11-04 |
20210343692 | METHODS FOR REDUCING HEAT TRANSFER IN SEMICONDUCTOR ASSEMBLIES, AND ASSOCIATED SYSTEMS AND DEVICES - Methods for reducing heat transfer in semiconductor devices, and associated systems and devices, are described herein. In some embodiments, a method of manufacturing a semiconductor device includes forming a channel in a region of a substrate between a first die stack and a second die stack. The first die stack includes a plurality of first dies attached to each other by first film layers and the second die stack includes a plurality of second dies attached to each other by second film layers. The channel extends entirely through a thickness of the substrate. The method also includes applying heat to the first die stack to cure the first film layers. The channel reduces heat transfer from the first die stack to the second die stack. | 2021-11-04 |
20210343693 | Semiconductor Package and Method of Manufacturing the Same - A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages. | 2021-11-04 |
20210343694 | RESISTOR WITH EXPONENTIAL-WEIGHTED TRIM - An electronic device, e.g. a trimmable resistor, includes a plurality of fused resistors, each fused resistor including one or more doped resistive regions formed in a semiconductor substrate. The doped resistive regions may be thermistors. Each fused resistor further includes a corresponding one of a plurality of fusible links. A first terminal of each of the fused resistors is connected to a first terminal of the corresponding fusible link. First and second interconnection buses are located over the substrate, with the first interconnection bus connecting to a second terminal of each of the fused resistors, and the second interconnection bus connecting to a second terminal of each of the fusible links. The plurality of fused resistors have resistance values that form an exponential progression. | 2021-11-04 |
20210343695 | SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR LAYOUT STRUCTURE - A semiconductor layout structure includes a substrate, a plurality of gate structures, and a plurality of conductive structures. The substrate includes a plurality of active regions extending along a first direction, in which the active regions are separated from each other by an isolation structure. The transistors are respectively disposed in the active regions. The gate structures extend across the active regions along a second direction that is perpendicular to the first direction, in which each of the active regions includes a pair of source/drain portions at opposite sides of each of the gate structures. The conductive structures are embedded in a first portion of the isolation structure disposed between the adjacent active regions in the first direction, wherein the conductive structures extend along the second direction and are separated from the source/drain portions by the isolation structure. | 2021-11-04 |
20210343696 | STANDARD CELL HAVING POWER RAILS DISPOSED IN CENTRAL REGION THEREOF AND STANDARD CELL BLOCK - A standard cell comprises a first active region and a first power rail, the first active region and the first power rail disposed in a first MOS region; a second active region and a second power rail, the second active region and the second power rail disposed in a second MOS region; and a gate electrode extending to cross the first and second active regions and the first and second power rails in a first direction, wherein the first power rail is disposed closer to a boundary between the first MOS region and the second MOS region than to a first side of the first MOS region opposite the boundary, and wherein the second power rail is disposed closer to the boundary between the first MOS region and the second MOS region than to a first side of the second MOS region opposite the boundary. | 2021-11-04 |
20210343697 | SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND METHOD OF MANUFACTURING SAME - A method generating the layout diagram includes: selecting gate patterns for which a first distance from a corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value; and for each of the selected gate patterns, increasing a size of the corresponding cut-gate section from a first value to a second value; the second value resulting in a first type of overhang of a corresponding remnant portion of the corresponding gate pattern; and the first type of overhang being a minimal permissible amount of overhang of the corresponding remnant portion beyond the corresponding first or second nearest active area pattern. A result is that gaps between ends of corresponding ends of remnants of gate patters are expanded. | 2021-11-04 |
20210343698 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a cell. The cell includes an active area, gates, at least one gate via and at least one contact via. The active area includes forbidden regions. The gates are disposed across the active area. The at least one gate via is coupled with one of the gates. The at least one contact via is coupled with at least one conductive segment each corresponding to a source/drain of a transistor. In a layout view, one of the forbidden regions abuts a region of an abutted cell in which at least one of a gate via or a contact via of the abutted cell is disposed. In a layout view, the least one of the at least one gate via or the at least one contact via is arranged within the active area and outside of the forbidden regions. A method is also disclosed herein. | 2021-11-04 |
20210343699 | SEMICONDUCTOR DEVICES HAVING STANDARD CELLS THEREIN WITH IMPROVED INTEGRATION AND RELIABILITY - A semiconductor device includes first and second standard cells having respective semiconductor elements and first interconnection lines electrically connected to the semiconductor elements, on a substrate. A routing structure is provided, which is disposed on the first and second standard cells. The routing structure includes second interconnection lines electrically connected to the first interconnection lines. The first interconnection lines include a first power transmission line, which is configured to supply power to a semiconductor element, and a first signal transmission line electrically coupled to a semiconductor element. The second interconnection lines include: (i) a second power transmission line electrically connected to the first power transmission line and extending by a first length, (ii) a second signal transmission line electrically connected to the first signal transmission line, and (iii) a staple line electrically connected to the first power transmission line, extending on a boundary between the first and second standard cells, and extending by a second length, less than the first length. | 2021-11-04 |
20210343700 | Semiconductor Device Layout - Semiconductor devices and semiconductor cell arrays are provided herein. In some examples, a semiconductor device includes a multi-fin active region, a mono-fin active region, and an isolation feature between the multi-fin active region and the mono-fin active region. The multi-fin active region includes a first plurality of fins, a second plurality of fins parallel to the first plurality of fins, a first n-type field effect transistor (FET), and a first p-type FET. The mono-fin active region abuts the multi-fin active region. The mono-fin active region includes a first fin, a second fin different from the first fin, a second n-type FET, and a second p-type FET. The isolation feature is parallel to the first and second gate structures. | 2021-11-04 |
20210343701 | CIRCUIT THAT PREVENTS DEVICE BODY DIODE CONDUCTION - A circuit comprising a first device (e.g., a high voltage MOSFET) coupled in series with a second device (e.g., a low voltage MOSFET or HEMT). The first device comprises a body diode. Additionally, the circuit comprises a diode coupled across the pair of devices. The diode is arranged antiparallel to the first device. In one exemplary embodiment, the first device is a SiC MOSFET and the second device is a Si MOSFET or GaN HEMT. | 2021-11-04 |
20210343702 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge protection circuit includes: a pulse detection unit, a delay unit, a control unit, and a discharge unit. The pulse detection unit is configured to detect an electrostatic pulse signal; the delay unit is configured to delay or enhance driving capability of the pulse detection signal output by the pulse detection unit; the control unit is configured to generate a control signal based on a first delay signal and a second delay signal output by the delay unit; and the discharge unit is configured to open or close an electrostatic charge discharge passage based on the control signal output by the control unit. | 2021-11-04 |
20210343703 | SEMICONDUCTOR DEVICE WITH LINEAR PARASITIC CAPACITANCE - A semiconductor device having relatively linear and constant parasitic capacitance of an operation range includes a first component having a negatively charged carrier channel and a second component comprising a positively charged carrier channel. The first component has source terminal and a drain terminal. The second component has bias terminal. Both components share a gate terminal that is electrostatically coupled to the negatively charged carrier channel of the first component and the positively charged carrier channel of the second component to produce a capacitance profile that stays relatively linear and constant as a voltage at the gate terminal changes. | 2021-11-04 |
20210343704 | SEMICONDUCTOR DEVICE AND METHODS OF FORMING THE SAME - A semiconductor device includes a substrate having a first region and a second region, a first gate structure disposed on the substrate within the first region, a first S/D region, a first S/D contact, a second gate structure on the substrate within the second region, a second S/D region and a second S/D contact. The first S/D region is disposed in the substrate within the first region and beside the first gate structure. The first S/D contact is connected to the first S/D region. The second S/D region is disposed in the substrate within the second region and beside the second gate structure. The second S/D contact is connected to the second S/D region. The contact area between the second S/D region and the second S/D contact is larger than a contact area between the first S/D region and the first S/D contact. | 2021-11-04 |
20210343705 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section. | 2021-11-04 |
20210343706 | MONOLITHIC MULTI-I REGION DIODE LIMITERS - A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a method of manufacture of a monolithic diode limiter includes providing an N-type semiconductor substrate, providing an intrinsic layer on the N-type semiconductor substrate, implanting a first P-type region to a first depth into the intrinsic layer, implanting a second P-type region to a second depth into the intrinsic layer, and forming at least one passive circuit element over the intrinsic layer. The method can also include forming an insulating layer on the intrinsic layer, forming a first opening in the insulating layer, and forming a second opening in the insulating layer. The method can also include implanting the first P-type region through the first opening and implanting the second P-type region through the second opening. | 2021-11-04 |
20210343707 | THROUGH SILICON VIA DESIGN FOR STACKING INTEGRATED CIRCUITS - A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. A seal-ring structure is arranged in a peripheral region of the 3D IC in the first IC die and the second IC die. The seal-ring structure extends from a first semiconductor substrate of the first IC die to a second semiconductor substrate of the second IC die. A plurality of through silicon via (TSV) coupling structures is arranged at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias. | 2021-11-04 |
20210343708 | CONDUCTION ENHANCEMENT LAYERS FOR ELECTRICAL CONTACT REGIONS IN POWER DEVICES - Power switching devices include a semiconductor layer structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor including a gate finger that has a longitudinal axis that extends in a first direction on the semiconductor layer structure, the gate fingers spaced apart from each other along a second direction, and a gate connector having a longitudinal axis that extends in the second direction, the gate connector connected to the gate fingers of the plurality of unit cell transistors. | 2021-11-04 |
20210343709 | SEMICONDUCTOR DEVICE WITH ISOLATION STRUCTURE - A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride liner is thicker than the first nitride liner. | 2021-11-04 |
20210343710 | METALLIZATION STRUCTURES UNDER A SEMICONDUCTOR DEVICE LAYER - Metallization structures under a semiconductor device layer. A metallization structure in alignment with semiconductor fin may be on a side of the fin opposite a gate stack. Backside and/or frontside substrate processing techniques may be employed to form such metallization structures on a bottom of a semiconductor fin or between bottom portions of two adjacent fins. Such metallization structures may accompany interconnect metallization layers that are over a gate stack, for example to increase metallization layer density for a given number of semiconductor device layers. | 2021-11-04 |
20210343711 | METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE - A method for forming a degreFinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer. | 2021-11-04 |
20210343712 | Integrated Circuit Device Including a Power Supply Line and Method of Forming the Same - A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line. | 2021-11-04 |
20210343713 | Gate Isolation for Multigate Device - Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin. | 2021-11-04 |
20210343714 | HIGH PERFORMANCE MULTI-DIMENSIONAL DEVICE AND LOGIC INTEGRATION - A semiconductor device is provided. The semiconductor device can include a bottom substrate, a device plane over the bottom substrate, a dielectric layer over the device plane, localized substrates over the dielectric layer, and semiconductor devices over the localized substrates. The localized substrates can be separated from each other along a top surface of the bottom substrate. A method of microfabrication is provided. The method can include forming a target layer over a bottom substrate where the target layer includes one or more localized regions that include one or more semiconductor materials. The method can also include performing a thermal process to change crystal structures of the one or more localized regions of the target layer. The method can further include forming semiconductor devices over the localized regions of the target layer. | 2021-11-04 |
20210343715 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other. | 2021-11-04 |
20210343716 | Tuning Tensile Strain on FinFET - A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin. | 2021-11-04 |
20210343717 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a plurality of first wires provided above a surface of a semiconductor substrate to extend in a first direction, and a plurality of second wires provided above the first wires to extend in a second direction crossing the first direction. A plurality of capacitor elements are arranged every other intersection region among intersection regions between the first wires and the second wires as viewed from above the surface of the semiconductor substrate. A plurality of transistors are provided above the capacitor elements to correspond thereto, respectively. A first distance between two of the capacitor elements, which are adjacent to each other in the first direction, is narrower than a second distance between two of the capacitor elements, which are adjacent to each other in the second direction. | 2021-11-04 |
20210343718 | CAPACITOR AND FORMING METHOD THEREOF, AND DRAM AND FORMING METHOD THEREOF - A method for forming a capacitor includes: providing a substrate with an electric contact portion; forming a supporting layer and a sacrificial layer which are alternately laminated on a surface of the substrate, wherein the topmost layer is a supporting layer; forming a capacitor hole penetrating through the supporting layer and the sacrificial layer and exposing the electric contact portion; forming a bottom electrode layer covering an inner surface of the capacitor hole; forming a protective layer covering a surface of the bottom electrode layer; removing the sacrificial layer, during which the bottom electrode layer being protected by the protective layer; removing the protective layer; and sequentially forming a capacitor dielectric layer and a top electrode layer. | 2021-11-04 |
20210343719 | Devices Having a Transistor and a Capacitor Along a Common Horizontal Level, and Methods of Forming Devices - Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures. | 2021-11-04 |
20210343720 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME - A method of manufacturing a semiconductor structure: providing a substrate with a trench; forming a first conductive layer in the trench, wherein the top of the first conductive layer is lower than the top of the trench; forming a dielectric layer on the first conductive layer; and forming a second conductive layer on the dielectric layer. | 2021-11-04 |
20210343721 | METHOD FOR MANUFACTURING DRAM - A method for manufacturing a dynamic random access memory includes: forming a buried bit line in a substrate; forming a plurality of buried word lines in the substrate, wherein the bottom surfaces of the buried word lines are higher than the top surface of the buried bit line; forming a bit line contact structure on the buried bit line; forming a through hole passing through the bit line contact structure, wherein the bit line contact structure is not in direct contact with the buried bit line, and the material of the bit line contact structure is different from the material of the buried bit line; forming a conductive plug between the bit line contact structure and the buried bit line; and forming a capacitor structure on the substrate. | 2021-11-04 |