44th week of 2021 patent applcation highlights part 59 |
Patent application number | Title | Published |
20210343522 | COATING COMPOSITIONS AND METHODS OF FORMING ELECTRONIC DEVICES - Coating compositions comprise: a B-staged reaction product of one or more compounds comprising: a core chosen from C | 2021-11-04 |
20210343523 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure is provided, which comprises the following steps. A gate is formed by a method comprising the following steps. A gate dielectric layer is formed on a substrate. A gate electrode is formed on the gate dielectric layer. A nitride spacer is formed on a sidewall of the gate electrode. A phosphorus containing dielectric layer is formed on the gate. The phosphorus containing dielectric layer has a varied phosphorus dopant density distribution profile. The phosphorus containing dielectric layer comprises a phosphorus dopant density region on an upper surface of the gate and having a triangle-like shape. | 2021-11-04 |
20210343524 | METHOD OF FORMING OXIDE FILM INCLUDING TWO NON-OXYGEN ELEMENTS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF FORMING DIELECTRIC FILM, AND SEMICONDUCTOR DEVICE - A method of forming an oxide film including two non-oxygen elements includes providing a first source material on a substrate, the first source material including a first central element, providing an electron donor compound to be bonded to the first source material, providing a second source material on the substrate after the providing of the electron donor compound, the second source material including a second central element, and providing an oxidant on the substrate. | 2021-11-04 |
20210343525 | SEMICONDUCTOR STRUCTURE HAVING A GROUP III-V SEMICONDUCTOR LAYER COMPRISING A HEXAGONAL MESH CRYSTALLINE STRUCTURE - A semiconductor structure ( | 2021-11-04 |
20210343526 | ACTIVE DEVICE SUBSTRATE - A manufacturing method of a crystallized metal oxide layer includes: providing a substrate; forming a first insulation layer on the substrate; forming a first metal oxide layer on the first insulation layer; forming a second metal oxide layer on the first insulation layer; forming a second insulation layer on the first metal oxide layer and the second metal oxide layer; forming a silicon layer on the second insulation layer; performing a first laser process on a portion of the silicon layer covering the first metal oxide layer; and performing a second laser process on a portion of the silicon layer covering the second metal oxide layer. An active device and a manufacturing method thereof are also provided. | 2021-11-04 |
20210343527 | PATTERNING FOR SELECTIVE EJECTIONS OF PRINTABLE AMMONIUM-BASED CHALCOGENOMETALATE FLUIDS - A method that includes selectively ejecting, from a first nozzle, a patterning material on to a surface of a substrate to define an area within to eject a first printable ammonium-based chalcogenometalate fluid; ejecting, from a second nozzle, the first printable ammonium-based chalcogenometalate fluid within the area defined by the patterning material to form a first layer of the printable ammonium-based chalcogenometalate fluid; and heating the first layer of printable ammonium-based chalcogenometalate fluid to dissipate the first printable ammonium-based chalcogenometalate fluid into a transition metal dichalcogenide having the form MX | 2021-11-04 |
20210343528 | METHODS FOR FORMING A GERMANIUM ISLAND USING SELECTIVE EPITAXIAL GROWTH AND A SACRIFICIAL FILLING LAYER - A method for obtaining a semiconductor island includes epitaxially growing a semiconductor structure over a substrate with a mask layer defining a region not covered by the mask layer. The semiconductor structure includes a first portion located adjacent to the mask layer and a second portion located away from the mask layer. The first portion has a first height that is less than a second height of a portion of the mask layer located adjacent to the first portion. The second portion has a third height that is equal to, or greater than the second height. The method also includes forming a filling layer over at least the first portion; and, subsequently removing at least a portion of the semiconductor structure that is located above the second height. Devices made by this method are also disclosed. | 2021-11-04 |
20210343529 | SEMICONDUCTOR DEVICE AND METHOD - A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material. | 2021-11-04 |
20210343530 | METHOD AND DEVICE FOR BONDING OF SUBSTRATES - A method and device for bonding a first substrate with a second substrate inside a sealed bonding chamber. The method includes: a) fixing of the first and second substrates, b) arranging of the first and second substrates, c) mutual approaching of the first and second substrates, d) contacting the first and second substrates at respective bond initiation points, e) generating a bonding wave running from the bond initiation points to side edges of the substrates, and f) influencing the bonding wave during course of the bonding wave, wherein targeted influencing of the bonding wave takes place by a regulated and/or controlled change of pressure inside the bonding chamber. | 2021-11-04 |
20210343531 | LASER ANNEALING APPARATUS, INSPECTION METHOD OF SUBSTRATE WITH CRYSTALLIZED FILM, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A laser annealing apparatus ( | 2021-11-04 |
20210343532 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a semiconductor part; first and second electrodes, the semiconductor part being provided between the first and second electrodes; a control electrode selectively provided between the semiconductor part and the second electrode; and a contacting part electrically connecting the semiconductor part and the second electrode. The semiconductor part includes a first layer of a first conductivity type, a second layer of a second conductivity type provided between the first layer and the second electrode, a third layer of the first conductivity type selectively provided between the second layer and the second electrode, and a fourth layer of the second conductivity type selectively provided between the second layer and the second electrode. The contacting part includes a first semiconductor portion of the first conductivity type contacting the third layer, and a second semiconductor portion of the second conductivity type contacting the fourth layer. | 2021-11-04 |
20210343533 | Replacement Gate Methods That Include Treating Spacers to Widen Gate - A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure. | 2021-11-04 |
20210343534 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - Some examples of this disclosure relate to the field of the semiconductor technology, and disclose a method for manufacturing a semiconductor structure. The method for manufacturing of the semiconductor structure includes: providing a base, wherein the base includes a metal layer and an oxide located in the metal layer or on a surface of the metal layer; and performing heat treatment on the base, wherein a reducing gas is introduced during the heat treatment, and the metal layer is converted into a metal compound layer after the heat treatment. This disclosure can improve the performance of the semiconductor structure. | 2021-11-04 |
20210343535 | Interconnect Structure Having a Carbon-Containing Barrier Layer - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature. | 2021-11-04 |
20210343536 | TWO-COLOR SELF-ALIGNED DOUBLE PATTERNING (SADP) TO YIELD STATIC RANDOM ACCESS MEMORY (SRAM) AND DENSE LOGIC - First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern. | 2021-11-04 |
20210343537 | METHOD FOR FORMING ACTIVE REGION ARRAY AND SEMICONDUCTOR STRUCTURE - A method for forming an active region array and a semiconductor structure are provided. The method for forming the active region array includes the steps of: providing a substrate; forming a first mask layer on a surface of the substrate, a first etched pattern being provided in the first mask layer; forming a second mask layer covering a surface of the first mask layer; forming a third mask layer having a second etched pattern on a surface of the second mask layer; forming a flank covering a sidewall of the second etched pattern; removing the third mask layer to form a third etched pattern between adjacent flanks; etching the first mask layer along the third etched pattern to form a fourth etched pattern in the first mask layer; and etching the substrate along the first etched pattern and the fourth etched pattern, to form multiple active regions in the substrate. | 2021-11-04 |
20210343538 | CMP System and Method of Use - A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit. | 2021-11-04 |
20210343539 | SUBSTRATE PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A technique improves selectivity in etching of a silicon-containing film over etching of a mask in plasma etching. A substrate processing method includes providing a substrate in a chamber in a plasma processing apparatus. The substrate includes a silicon-containing film and a mask on the silicon-containing film. The substrate processing method further includes controlling a temperature of a substrate support on which the substrate is placed to 0° C. or lower. The substrate processing method further includes etching the silicon-containing film with plasma generated from a first process gas containing a hydrogen fluoride gas and at least one carbon-containing gas selected from the group consisting of a fluorocarbon gas and a hydrofluorocarbon gas. The etching includes etching the film with a chemical species contained in the plasma. The hydrogen fluoride gas has a highest flow rate among non-inert components of the first process gas. | 2021-11-04 |
20210343540 | LASER CONTACT ABLATION FOR SEMICONDUCTOR PACKAGES AND RELATED METHODS - Implementations of a semiconductor substrate may include a plurality of die including at least one contact; and a plurality of portions of an encapsulant on a surface of the semiconductor substrate, wherein each portion of the plurality of portions extends immediately above a plane of the at least one contact. | 2021-11-04 |
20210343541 | Atomic Layer Etch Process Using Plasma In Conjunction With A Rapid Thermal Activation Process - A process for etching a film layer on a semiconductor wafer is disclosed. The process is particularly well suited to etching carbon containing layers, such as hardmask layers, photoresist layers, and other low dielectric films. In accordance with the present disclosure, a reactive species generated from a plasma is contacted with a surface of the film layer. Simultaneously, the substrate or semiconductor wafer is subjected to rapid thermal heating cycles that increase the temperature past the activation temperature of the reaction in a controlled manner. | 2021-11-04 |
20210343542 | HYDROPHILIZATION TREATMENT LIQUID FOR SEMICONDUCTOR WAFER SURFACE - Provided is a hydrophilization treatment liquid for a semiconductor wafer surface, the hydrophilization treatment liquid being capable of imparting hydrophilicity to the semiconductor wafer surface. | 2021-11-04 |
20210343543 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR - A manufacturing method of a thin film transistor is provided, which has advantages that there are sufficient hydrogen ions in an interlayer dielectric layer. In an annealing treatment, an amount of the hydrogen ions diffused into an active layer is sufficient, and the hydrogen ions enter a channel of the thin film transistor to fill non-bonded or unsaturated bonds of polysilicon atoms, thereby filling defects in the channel, repairing the defects of the active layer, reducing the number of unsteady states, and improving mobility and threshold voltage uniformity. | 2021-11-04 |
20210343544 | FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a field-effect transistor and a method for manufacturing a field-effect transistor. The method comprises: forming an NMOSFET region and a PMOSFET region on a substrate; forming a hard mask on the NMOSFET region and the PMOSFET region, and patterning through the hard mask; forming a multiple of stacked nanowires in the NMOSFET region and a multiple of stacked nanowires in the PMOSFET region; forming a first array of nanowires in the NMOSFET region and a second array of nanowires in the PMOSFET region; and forming an interfacial oxide layer, a ferroelectric layer, and a stacked metal gate in sequence around each of the nanowires included in the first array and the second array. Wherein the NMOSFET region and the PMOSFET region are separated by shallow trench isolation. | 2021-11-04 |
20210343545 | CONTROLLING OF HEIGHT OF HIGH-DENSITY INTERCONNECTION STRUCTURE ON SUBSTRATE - An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part. | 2021-11-04 |
20210343546 | ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME - An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package. | 2021-11-04 |
20210343547 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages. | 2021-11-04 |
20210343548 | PACKAGE STRUCTURE AND METHOD FOR FORMING SAME - A package structure and a method for forming the same are provided. The package structure includes: a substrate, in which the substrate has a first surface and a second surface being opposite to the first surface, and has an opening penetrating through the first surface to the second surface of the substrate, the opening is in a long strip shape with a size at both two ends larger than a size at middle; a chip, in which the chip is fixed on the first surface of the substrate through solder bumps in a flipped over mode, and electrically connects with the substrate through the solder bumps, and the opening is located in a projection of the chip on the substrate; and a moulding compound wrapping the chip and filling the opening and a gap between the chip and the first surface of the substrate. | 2021-11-04 |
20210343549 | SEMICONDUCTOR DEVICE WITH BUFFER LAYER - A wafer-level buffer layer is disclosed. The wafer-level buffer layer is configured to prevent cracking and chipping the back-end-of-line (BEOL) dielectric during wafer singulation process. The wafer-level buffer layer is a composite wafer-level buffer layer with a vibration damping agent. The vibration damping agent includes a polymer-based base layer with fillers. The damping agent absorbs or dampens the vibration of the saw blade during dicing to prevent cracking and chipping of the BEOL dielectric. | 2021-11-04 |
20210343550 | Multi-Zone Platen Temperature Control - A system and method for etching workpieces in a uniform manner are disclosed. The system includes a semiconductor processing system that generates a ribbon ion beam, and a workpiece holder that scans the workpiece through the ribbon ion beam. The workpiece holder includes a plurality of independently controlled thermal zones so that the temperature of different regions of the workpiece may be separately controlled. In certain embodiments, etch rate uniformity may be a function of distance from the center of the workpiece, also referred to as radial non-uniformity. Further, when the workpiece is scanned, there may also be etch rate uniformity issues in the translated direction, referred to as linear non-uniformity. The present workpiece holder comprises a plurality of independently controlled thermal zones to compensate for both radial and linear etch rate non-uniformity. | 2021-11-04 |
20210343551 | SEMICONDUCTOR SYSTEM WITH STEAM GENERATOR AND REACTOR - A semiconductor processing system includes a semiconductor processing chamber, a pump, an exhaust line in fluid communication with the chamber through the pump, and a steam generator and reactor. The steam generator and reactor has a process conduit with an inlet in line in the exhaust line for generating superheated steam and effecting transformations of chemicals in the exhaust fluid flowing in exhaust line into the inlet. | 2021-11-04 |
20210343552 | DRY CLEANING APPARATUS AND DRY CLEANING METHOD - A dry cleaning apparatus includes a chamber, a substrate support supporting a substrate within the chamber, a shower head arranged in an upper portion of the chamber to supply a dry cleaning gas toward the substrate, the shower head including an optical window transmitting a laser light therethrough toward the substrate support, a plasma generator generating plasma from the dry cleaning gas, and a laser irradiator irradiating the laser light on the substrate through the optical window and the plasma to heat the substrate. | 2021-11-04 |
20210343553 | SEMICONDUCTOR EQUIPMENT AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - The present application relates to semiconductor equipment and a method for manufacturing a semiconductor structure. The semiconductor equipment includes: a process chamber for processing a wafer; a gas intake apparatus, configured to introduce gas into the process chamber; and a gas distribution plate, located above the wafer and on a flow path of the gas; and at least part of the gas flows to a surface of the wafer through the gas distribution plate. | 2021-11-04 |
20210343554 | FAST FOUP SWAPPING WITH A FOUP HANDLER - A vertical batch furnace assembly for processing wafers having a cassette handling space, a wafer handling space, and a first wall and separating the cassette handling space from the wafer handling space. The first wall has at least one wafer transfer opening in front of which, at a side of the first wall which is directed to the cassette handling space, a wafer transfer position for a wafer cassette is provided. The cassette handling space comprises a cassette storage having a plurality of cassette storage positions and a cassette handler configured to transfer wafer cassettes between the cassette storage positions and the wafer transfer position. The cassette handler has a first cassette handler arm and a second cassette handler arm. | 2021-11-04 |
20210343555 | NON-PLANAR SEMICONDUCTOR PACKAGING SYSTEMS AND RELATED METHODS - Implementations of a packaging system may include a wafer; and a curvature adjustment structure coupled thereto where the curvature adjustment structure may be configured to alter a curvature of a largest planar surface of the wafer. | 2021-11-04 |
20210343556 | SUBSTRATE PROCESSING SYSTEM FOR PROCESSING SUBSTRATES - The disclosure relates to a semiconductor processing system for processing semiconductor substrates and provided with a housing formed by a wall. The system may further comprise a processing module and a cassette module, the cassette module located adjacent the processing module. An electronics module may be provided with a support for mounting electronic components, whereby the electronics module is located behind a door in the wall of the system to create access for maintenance. The electronic components have a straight mounting basis for mounting of the electronics components whereby the mounting basis is mounted in the system under an angle between 10 and 80 degrees with respect to the door when the door is closed. | 2021-11-04 |
20210343557 | HEATER COVER PLATE FOR UNIFORMITY IMPROVEMENT - Embodiments of the present disclosure generally relate to an apparatus for improving the film thickness a substrate when using a heated substrate support. A cover plate to be placed over the top surface of a heated substrate support is disclosed. The cover plate includes a pocket formed in the middle thereof for the placement of a substrate. The cover plate may include a variety of features including a plurality of dimples, a plurality of radially disposed grooves, a plurality of annular grooves, lift pin holes, pin slots, and gas exhaust holes. | 2021-11-04 |
20210343558 | METHOD AND APPARATUS TO CONTROL TRANSFER PARAMETERS DURING TRANSFER OF SEMICONDUCTOR DEVICES - An apparatus includes a transfer mechanism to transfer an electrically-actuatable element directly from a wafer tape to a transfer location on a circuit trace on a product substrate. The transfer mechanism includes one or more transfer wires. Two or more stabilizers disposed on either side of the one or more transfer wires. A needle actuator is connected to the one or more transfer wires and the two or more stabilizers to move the one or more transfer wires and the two or more stabilizers to a die transfer position. | 2021-11-04 |
20210343559 | PROCESSING SYSTEM - A processing system capable of increasing an operating time of the processing system is provided. The processing system includes a vacuum transfer module, a plurality of processing modules, a plurality of load-lock modules, and a plurality of atmospheric transfer modules. The vacuum transfer module is configured to transfer a substrate in a pressure lower than an atmospheric pressure. The processing modules are connected to the vacuum transfer module and configured to process the substrate. The load-lock modules are connected to the vacuum transfer module. Each of the atmospheric transfer modules is connected to at least one of the load-lock modules and configured to transfer the substrate in an atmospheric environment. | 2021-11-04 |
20210343560 | APPARATUS AND METHOD FOR REAL-TIME SENSING OF PROPERTIES IN INDUSTRIAL MANUFACTURING EQUIPMENT - An apparatus and method for real-time sensing of properties in industrial manufacturing equipment are described. The sensing system includes first plural sensors mounted within a processing environment of a semiconductor device manufacturing system, wherein each sensor is assigned to a different region to monitor a physical or chemical property of the assigned region of the manufacturing system, and a reader system having componentry configured to simultaneously and wirelessly interrogate the plural sensors. The reader system uses a single high frequency interrogation sequence that includes (1) transmitting a first request pulse signal to the first plural sensors, the first request pulse signal being associated with a first frequency band, and (2) receiving uniquely identifiable response signals from the first plural sensors that provide real-time monitoring of variations in the physical or chemical property at each assigned region of the system. | 2021-11-04 |
20210343561 | SYSTEM AND METHOD FOR CONTROLLING SEMICONDUCTOR MANUFACTURING EQUIPMENT - The present disclosure provides systems and methods for controlling a semiconductor manufacturing equipment. The control system includes an inspection unit capturing a set of images of the semiconductor manufacturing equipment, a sensor interface receiving the set of images and generating at least one input signal for a database server, and a control unit. The control unit includes a front end subsystem, a calculation subsystem, and a message and feedback subsystem. The calculation subsystem receives the data signal from the front end subsystem, wherein the calculation subsystem performs an artificial intelligence analytical process to determine, according to the data signal, whether a malfunction has occurred in the semiconductor manufacturing equipment and to generate an output signal. The message and feedback subsystem generates an alert signal and a feedback signal according to the output signal, and the alert signal is transmitted to a user of the semiconductor manufacturing equipment. | 2021-11-04 |
20210343562 | SUBSTRATE PROCESSING APPARATUS AND FURNACE OPENING CLOSER - According to one aspect of the technique, there is provided a substrate processing apparatus including: a reaction chamber in which a substrate is processed; a lid configured to close a furnace opening of the reaction chamber; a base provided below the lid; and a connector provided to connect the lid and the base. The connector includes: a shaft provided at the lid; an elastic structure provided to surround the shaft and configured to hold the lid; a cap provided to surround the elastic structure and provided at the base; a fixing block provided below the cap; and a moving block held by a holder provided between the fixing block and the shaft. | 2021-11-04 |
20210343563 | RETICLE POD SEALING - A pod includes a cover with a cover body, a baseplate with a baseplate body, and one or more seal surfaces. The one or more seal surfaces are formed on one or more of the baseplate body and the cover body to provide sealing. A method of producing a reticle pod includes forming one or more seal surfaces on at least one of a baseplate body of a baseplate and a cover body of a cover. The one or more seal surfaces are formed to provide sealing between the baseplate and the cover. Each of the one or more seal surfaces includes a wear-resistant outermost coating with a Rockwell C hardness of about or greater than 70. | 2021-11-04 |
20210343564 | LOAD PORT OPERATION IN ELECTRONIC DEVICE MANUFACTURING APPARATUS, SYSTEMS, AND METHODS - A load port of a factory interface of an electronic device manufacturing system can include a purge apparats, a docking tray configured to receive a substrate carrier including a substrate carrier door and a substrate carrier housing, a backplane located adjacent to the docking tray, and a carrier door configured to seal an opening in the backplane when the carrier door opener is closed. The carrier door opener can include an inlet gas line therethrough that is coupled to one or more components of the purge apparatus. The load port can also include a controller that is configured to detect that the substrate carrier is placed in a docking position on the docking tray. The substrate carrier placed in the docking position on the docking tray can form a gap between the substrate carrier housing and the backplane. The controller can also purge a space between the carrier door and the carrier housing and/or an area between the carrier door and the carrier door opener via the inlet gas line and the gap between the substrate carrier housing and the backplane. The controller can cause the purge apparatus to stop the purge and close the gap between the substrate carrier housing and the backplane. | 2021-11-04 |
20210343565 | ELECTROSTATIC CLAMPING SYSTEM AND METHOD - An electrostatic clamping system including a platen, an electrostatic electrode associated with the platen, and a sealing cover having a concave lower surface defining a cavity and having a sealing ring extending about a periphery of the lower surface, the sealing cover movable relative to the platen for being moved onto, and being moved off of, a wafer disposed on the platen, the sealing cover further having an inlet valve for introducing a gas into a space between a cover body of the sealing cover and the wafer. | 2021-11-04 |
20210343566 | APPARATUS FOR MANUFACTURING DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE - An apparatus for manufacturing a display device includes: a first housing having a first chamber; a support member disposed in the first chamber and including a frame having a plurality of openings; a plurality of adhesive patterns disposed on the frame; and a plurality of electrostatic supports overlapping the plurality of openings and supported for reciprocal movement in respective ones of the openings. | 2021-11-04 |
20210343567 | MICRO LED DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a method for manufacturing a micro LED display substrate. The method may include forming an array of micro LEDs on an epitaxial wafer; transferring the array of micro LEDs on the epitaxial wafer to an adhesive layer on a surface of a transfer substrate assembly; and transferring the array of micro LEDs on the surface of the transfer substrate assembly onto corresponding pads on a driving substrate respectively. | 2021-11-04 |
20210343568 | TEMPORARY DIE SUPPORT STRUCTURES AND RELATED METHODS - Implementations of a semiconductor device may include a semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and a temporary die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The thickness may be between 0.1 microns and 125 microns. The warpage of the semiconductor die may be less than 200 microns. | 2021-11-04 |
20210343569 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - To manufacture a semiconductor package, a package intermediate structure having an element area and a dummy area is formed. A carrier substrate including an adhesion layer is formed. The adhesion layer includes a first area with a first adhesion strength and a second area with a second adhesion strength that is different from the first adhesion strength. The package intermediate structure is supported by the carrier substrate so that the element area is adjacent the first area and the dummy area is adjacent the second area. The package intermediate structure is processed while the package intermediate structure is supported by the carrier substrate. | 2021-11-04 |
20210343570 | METHOD FOR PRODUCING A 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE - A method for producing a 3D memory device, the method comprising: providing a first level comprising a first single crystal layer; forming first alignment marks and control circuits comprising first single crystal transistors, wherein said control circuits comprise at least two metal layers; forming at least one second level above said control circuits; performing a first etch step within said second level; forming at least one third level above said at least one second level; performing a second etch step within said third level; and performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, wherein said first etch step comprises performing a lithography step aligned to said first alignment marks. | 2021-11-04 |
20210343571 | METHODS FOR PRODUCING A 3D SEMICONDUCTOR MEMORY DEVICE - A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing additional processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one of the first memory cells is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with the processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly. | 2021-11-04 |
20210343572 | Method for Transferring Massive Light Emitting Diodes and Display Back Plate Assembly - The disclosure provides a method for transferring massive light emitting diodes and a display back plate assembly, the method includes: a plurality of temporary substrates are provided, light emitting diodes with one color are arranged on one of the plurality of temporary substrates, and the light emitting diodes with different colors are different in height; an adhesive layer on each of the plurality of temporary substrates is coating respectively, so that the adhesive layer covers the light emitting diodes and the adhesive layer on each of the plurality of temporary substrates is the same in height; the adhesive layer between adjacent light emitting diodes to form a flattening layer on one side, far away from the temporary substrate, of the light emitting diodes with the different colors is removed; and the light emitting diodes on each of the plurality of temporary substrates are transferred to a same display back plate. | 2021-11-04 |
20210343573 | ELECTRONIC COMPONENT, METHOD OF MANUFACTURING ELECTRONIC COMPONENT, AND ELECTRONIC COMPONENT PACKAGE - An electronic component includes a body and one or more protrusions. The body includes a first side surface, a second side surface opposite to the first side surface, and a first principal surface. The one or more protrusions are provided on at least one of the first side surface, the second side surface, or the first principal surface. | 2021-11-04 |
20210343574 | CURVED SEMICONDUCTOR DIE SYSTEMS AND RELATED METHODS - Implementations of a curved die system may include a semiconductor die; and a die curvature support structure including an organic material coupled to a surface of the semiconductor die. The die curvature support structure may induce warpage greater than 200 microns in the surface of the semiconductor die. The die curvature support structure may be configured to induce warpage prior to coupling the semiconductor die to a correspondingly curved substrate. | 2021-11-04 |
20210343575 | SUBSTRATE TABLE WITH VACUUM CHANNELS GRID - A substrate table is provided. The substrate table includes a main body having a surface and a plurality of burls extending from the surface. The burls are configured to support a substrate on the main body. The substrate table further includes a number of vacuum channels provided in the burls to apply a vacuum to the substrate. The vacuum channels are distributed throughout the main body and arranged in a grid pattern. | 2021-11-04 |
20210343576 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus according to the present disclosure includes a gripping mechanism and a base plate. The gripping mechanism grips a peripheral edge of a substrate. The base plate is located below the substrate gripped by the gripping mechanism and supports the gripping mechanism. Furthermore, the base plate includes a liquid drain hole that discharges a processing liquid flowing from the substrate to an upper surface of the base plate through the gripping mechanism. | 2021-11-04 |
20210343577 | LIFT PIN AND VACUUM PROCESSING APPARATUS - A lift pin of the invention is to be in contact with a substrate having a process-target surface and a non-processed surface, and the lift pin includes: a center member that has a first surface having first surface roughness and including an electrical insulator, and a main body serving as an electroconductive member, and that faces the non-processed surface of the substrate; and a surrounding member that has a second surface having second surface roughness lower than the first surface roughness and including an electrical insulator, that surrounds the periphery of the center member, and that faces the non-processed surface of the substrate. | 2021-11-04 |
20210343578 | INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE DIELECTRIC LAYER HAVING AIR GAP - An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure. | 2021-11-04 |
20210343579 | METHOD TO CREATE AIR GAPS - Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO | 2021-11-04 |
20210343580 | SELECTIVE DEPOSITION METHOD TO FORM AIR GAPS - A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device. | 2021-11-04 |
20210343581 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME - This disclosure relates to the technical field of semiconductor manufacturing, and discloses a semiconductor structure and a method for forming the same. The method includes: providing a semiconductor substrate having a plurality of contact structures arranged at an interval on a surface thereof, and the contact structures protruding from the substrate; forming a first dielectric layer on a side wall of the contact structure; depositing a second dielectric layer on surfaces of the semiconductor substrate, the contact structure and the first dielectric layer; enabling the first dielectric layer to react with the second dielectric layer; and removing an unreacted portion of the second dielectric layer by etching. | 2021-11-04 |
20210343582 | METHODS OF MANUFACTURING A TRANSISTOR DEVICE - A method of subdividing a semiconductor wafer is described with trenches in order to provide separate, electrically isolated regions that can be used to hold components that operate at different voltages. There is also described a masking and etching process of forming collector and emitter regions of a lateral bipolar transistor, from a layer of polysilicon deposited on a patterned later of silicon dioxide. | 2021-11-04 |
20210343583 | METHOD OF MANUFACTURING EPITAXY SUBSTRATE - A method of manufacturing an epitaxy substrate is provided. A handle substrate is provided. A beveling treatment is performed on an edge of a device substrate such that a bevel is formed at the edge of the device substrate, wherein a thickness of the device substrate is greater than 100 μm and less than 200 μm. An ion implantation process is performed on a first surface of the device substrate to form an implantation region within the first surface. A second surface of the device substrate is bonded to the handle substrate for forming the epitaxy substrate, wherein a bonding angle greater than 90° is provided between the bevel of the device substrate and the handle substrate, and a projection length of the bevel toward the handle substrate is between 600 μm and 800 μm. | 2021-11-04 |
20210343584 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; for a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit. | 2021-11-04 |
20210343585 | INTERCONNECTS HAVING SPACERS FOR IMPROVED TOP VIA CRITICAL DIMENSION AND OVERLAY TOLERANCE - A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element. | 2021-11-04 |
20210343586 | Method and Process Using Dual Memorization Layer for Multi-Color Spacer Patterning - A self-aligned multiple patterning (SAMP) multi-color spacer patterning process is disclosed for formation of structures on substrates. Trenches and vias may be formed in the process. A trench memorization layer and a via memorization layer may be formed on the substrate. In one embodiment, the trench memorization layer and the via memorization layer are formed between the multi-color spacer patterning structures and a low-k interlayer dielectric layer. The use of the trench memorization layer and the via memorization layer allows the formation of trenches and vias in the low-k interlayer dielectric layer without causing damage to the low-k properties of the low-k interlayer dielectric layer. | 2021-11-04 |
20210343587 | PASSIVATION LAYER FOR INTEGRATED CIRCUIT STRUCTURE AND FORMING THE SAME - An integrated circuit (IC) structure includes a substrate, a transistor, an interconnect structure, a plurality of metal lines, an oxide liner, a passivation layer, and a nitride layer. The transistor is on the substrate. The interconnect structure is over the transistor. The metal lines is on the interconnect structure. The oxide liner is over the plurality of metal lines. The passivation layer is over the oxide liner and is more porous than the passivation layer. The nitride layer is over the passivation layer. | 2021-11-04 |
20210343588 | INTERCONNECT STRUCTURE AND METHOD - An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via. | 2021-11-04 |
20210343589 | BARRIER-LESS PREFILLED VIA FORMATION - A method for fabricating a semiconductor device includes forming one or more layers including at least one of a liner and a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench, after forming the one or more liners, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level, and forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material. | 2021-11-04 |
20210343590 | Contact Conductive Feature Formation and Structure - Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer. | 2021-11-04 |
20210343591 | MANUFACTURING METHOD OF CHIP PACKAGE AND CHIP PACKAGE - A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle. | 2021-11-04 |
20210343592 | MULTICOLOR SELF-ALIGNED CONTACT SELECTIVE ETCH - Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. | 2021-11-04 |
20210343593 | PROCESS FOR SEPARATING A PLATE INTO INDIVIDUAL COMPONENTS - Disclosed is a method for separating a plate into multiple individual detached components or cutting the plate into chips. The back end process for a plate includes providing a substrate; attaching the plate to the substrate using a sacrificial layer that is made of materials that in a solid state at ambient temperature and ambient pressure, and having a transformation temperature into one or more gaseous compounds at ambient pressure of between 80° C. and 600° C.; and separating the plate attached on the substrate into a plurality of plate portions; increasing temperature and/or reducing surrounding pressure to transform the sacrificial layer into one or more gaseous compounds. | 2021-11-04 |
20210343594 | MOAT COVERAGE WITH DIELECTRIC FILM FOR DEVICE PASSIVATION AND SINGULATION - Techniques are described for the use of moats for isolating and singulating semiconductor devices formed on a wafer. Described techniques use dielectric films, such as an oxide-nitride film, to coat moat surfaces and provide passivation. The dielectric films may form a junction with a metal contact layer, to reduce electrical overstress that may otherwise occur in the resulting semiconductor devices. To ensure coverage of the moat surfaces, spray coating of a positive photoresist may be used. | 2021-11-04 |
20210343595 | THIN-FILM TRANSFER METHOD - A method includes transferring a layer onto a flexible substrate, the layer being located in a stack on the front face of the substrate. The substrate includes at least one supplementary stack interposed between the stack and the bulk layer of the substrate. This supplementary stack includes at least two layers with thicknesses decreasing in the direction of the front face. The method makes provision, after bonding the flexible substrate on the front face, for successively and gradually removing the various layers of the substrate. Such gradualness makes it possible to transfer a thin layer of silicon, with a thickness of less than 50 nm, onto a flexible substrate. | 2021-11-04 |
20210343596 | SOURCE/DRAIN EPITAXIAL STRUCTURES FOR HIGH VOLTAGE TRANSISTORS - The present disclosure describes a method for the formation of n-type and p-type epitaxial source/drain structures with substantially co-planar top surfaces and different depths across input/output (I/O) and non-I/O regions of a substrate. In some embodiments, the method includes forming fin structures and a planar portion on a substrate. The method also includes forming first gate structures on the fin structures and second gate structures on the planar portion. The method also includes etching the fin structures between the first gate structures to form first openings and etching the planar portion between the second gate structures to form second openings. Further, the method includes forming first epitaxial structures in the first openings and second epitaxial structures in the second openings, where top surfaces of the first and second epitaxial structures are substantially co-planar and bottom surfaces of the first and second epitaxial structures are not co-planar. | 2021-11-04 |
20210343597 | FORMATION OF HYBRID ISOLATION REGIONS THROUGH RECESS AND RE-DEPOSITION - A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap. | 2021-11-04 |
20210343598 | SEMICONDUCTOR AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device, a method of manufacturing the same, and a method of forming a uniform doping concentration of each semiconductor device when manufacturing a plurality of semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable by using ion blocking patterns to provide a semiconductor device with uniform doping concentration and a higher breakdown voltage obtainable as a result of such doping. | 2021-11-04 |
20210343599 | FINFET Device with Wrapped-Around Epitaxial Structure and Manufacturing Method Thereof - A semiconductor device includes a substrate and two fins protruding from the substrate. Each fin includes two source/drain (S/D) regions and a channel region. Each fin includes a top surface that remains flat across the S/D regions and the channel region. The semiconductor device also includes a gate stack engaging each fin at the respective channel region, a first dielectric layer on sidewalls of the gate stack, a first epitaxial layer over top and sidewall surfaces of the S/D regions of the two fins, and a second epitaxial layer over top and sidewall surfaces of the first epitaxial layer. | 2021-11-04 |
20210343600 | Self-Aligned Metal Gate for Multigate Device - Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently. | 2021-11-04 |
20210343601 | Structure and Process of Integrated Circuit Having Latch-Up Suppression - A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions. | 2021-11-04 |
20210343602 | FABRICATION OF THIN-FILM ENCAPSULATION LAYER FOR LIGHT-EMITTING DEVICE - An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink volume to be locally delivered. The grayscale values are used to generate a halftone pattern to deliver variable ink volume (and thickness) to the substrate. The halftoning provides for a relatively continuous layer (e.g., without unintended gaps or holes) while providing for variable volume and, thus, contributes to variable ink/material buildup to achieve desired thickness. The ink is jetted as liquid or aerosol that suspends material used to form the material layer, for example, an organic material used to form an encapsulation layer for a flat panel device. The deposited layer is then cured or otherwise finished to complete the process. | 2021-11-04 |
20210343603 | ATOM PROBE TOMOGRAPHY SPECIMEN PREPARATION - The disclosure is directed to techniques in preparing an atom probe tomography (“APT”) specimen. A structure in a semiconductor device is identified as including a test object for an APT procedure. A target region is identified in the structure where an APT specimen will be obtained. The target region is analyzed to determine whether a challenging component feature exists therein. A challenging component may include a hard-to-evaporate material, a hollow region, or a material unidentifiable with respect to the test object, or other structural features that pose a challenge to a successful APT analysis. If it is determined that a challenging component exists in the target region, the challenging component is replaced with a more suitable material before the APT specimen is prepared. | 2021-11-04 |
20210343604 | SEMICONDUCTOR SUBSTRATE CRACK MITIGATION SYSTEMS AND RELATED METHODS - Implementations of a method for healing a crack in a semiconductor substrate may include identifying a crack in a semiconductor substrate and heating an area of the semiconductor substrate including the crack until the crack is healed. | 2021-11-04 |
20210343605 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - The embodiments relate to a semiconductor structure and a fabrication method thereof. The fabrication method includes: providing a wafer, in the wafer there being provided with a scribe line, in the scribe line there being provided with a test pad, a first test structure, and a second test structure; the second test structure being positioned below the first test structure, and a transverse pitch between the second test structure and the first test structure being at least equal to a width of the test pad; forming a protective layer on the wafer, the protective layer at least covering the scribe line; and performing exposure and development on the protective layer, such that a thickness of the protective layer remained above the first test structure is greater than that of the protective layer remained above the second test structure. | 2021-11-04 |
20210343606 | DISPLAY DEVICE - A display device includes a display area, a peripheral area, a pad portion, a bending area, a first crack detection circuit, and a first crack detection line. The display area includes pixels and data lines. The peripheral area is disposed outside the display area. The pad portion is disposed in the peripheral area. The bending area is disposed in the peripheral area. The bending area is bendable or in a bent state. The first crack detection circuit is disposed between the display area and the pad portion. The first crack detection circuit includes switches. The first crack detection line includes a first curved portion disposed in the bending area. The first crack detection line is connected between the pad portion and the first crack detection circuit. | 2021-11-04 |
20210343607 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes: a substrate; an insulating region located in the substrate; a first conductor located above the insulating region and configured to collect charges; a second conductor at least partially located above the insulating region and configured to induce the charges of the first conductor; and a dielectric layer located between the first conductor and the second conductor to electrically insulate the first conductor from the second conductor. | 2021-11-04 |
20210343608 | SUBSTRATE PROCESSING CARRIER - Implementations of a substrate carrier may include: a top ring configured to enclose an edge of a first side of a substrate; and a bottom support configured to enclose an entire second side and an edge of the second side of the substrate. | 2021-11-04 |
20210343609 | CAP FOR PACKAGE OF INTEGRATED CIRCUIT - A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate. | 2021-11-04 |
20210343610 | GLASS SUBSTRATE AND LAMINATED SUBSTRATE - The present invention provides a glass substrate in which in a step of sticking a glass substrate and a silicon-containing substrate to each other, bubbles hardly intrude therebetween. The present invention relates to a glass substrate for forming a laminated substrate by lamination with a silicon-containing substrate, having a warpage of 2 μm to 300 μm, and an inclination angle due to the warpage of 0.0004° to 0.12°. | 2021-11-04 |
20210343611 | METHOD FOR FORMING PACKAGE STRUCTURE - A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component, and a top surface of the dam structure is higher than a top surface of the package component. The method further includes forming an underfill layer between the dam structure and the package component. In addition, the method includes removing the dam structure after the underfill layer is formed. | 2021-11-04 |
20210343612 | MULTICHIP MODULE SUPPORTS AND RELATED METHODS - Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns. | 2021-11-04 |
20210343613 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer. | 2021-11-04 |
20210343614 | DISPLAY MODULE, MANUFACTURING METHOD THEREOF AND ELECTRONIC DEVICE - A display module and a method of manufacturing the display module are provided. The display module comprises a display panel, a driving integrated circuit on the display panel, and a protective tape on the driving integrated circuit. The protective tape includes a second adhesive material on the driving integrated circuit, and an adhesive tape on the second adhesive material. The second adhesive material fills an area between the adhesive tape and the display panel. | 2021-11-04 |
20210343615 | SEMICONDUCTOR PACKAGES WITH PASSIVATING MATERIAL ON DIE SIDEWALLS AND RELATED METHODS - Implementations of a semiconductor package may include a singulated die and a passivating material of a predetermined thickness across a majority of a singulated surface of the singulated die on at least one singulated surface of the singulated die. | 2021-11-04 |
20210343616 | SEMICONDUCTOR PACKAGE - Provided is a semiconductor package including a lower semiconductor chip including a lower semiconductor substrate, a rear surface protecting layer covering a non-active surface of the lower semiconductor substrate, a plurality of lower via electrodes, and a plurality of rear surface signal pads and a plurality of rear surface thermal pads arranged on the rear surface protecting layer; an upper semiconductor chip including an upper semiconductor substrate, a wiring structure on an active surface of the upper semiconductor substrate, a front surface protecting layer that covers the wiring structure and has a plurality of front surface openings, and a plurality of signal vias and a plurality of thermal vias that fill the front surface openings; and a plurality of signal bumps connecting between the rear surface signal pads and the signal vias and a plurality of thermal bumps connecting between the rear surface thermal pads and the thermal vias. | 2021-11-04 |
20210343617 | SEMICONDUCTOR PACKAGES - A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure. | 2021-11-04 |
20210343618 | FLEXIBLE TRANSISTORS WITH NEAR-JUNCTION HEAT DISSIPATION - Flexible transistors and electronic circuits incorporating the transistors are provided. The flexible transistors promote heat dissipation from the active regions of the transistors while preserving their mechanical flexibility and high-frequency performance. The transistor designs utilize thru-substrate vias (TSVs) beneath the active regions of thin-film type transistors on thin flexible substrates. To promote rapid heat dissipation, the TSVs are coated with a material having a high thermal conductivity that transfers heat from the active region of the transistor to a large-area ground. | 2021-11-04 |
20210343619 | Package Structure and Method and Equipment for Forming the Same - A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material. | 2021-11-04 |
20210343620 | POWER MODULE PACKAGE CASING WITH PROTRUSION SUPPORTS - A method includes disposing a series of protrusions on a rectangular side panel of an open four-sided box-like structure in a frame, and attaching an electronic substrate to the frame. The electronic substrate carries one or more circuit components. The series of protrusions acts as a spring-like compensator to compensate plastic deformation, twisting or warping of the frame, and to limit propagation of stress to the electronic substrate via the frame. | 2021-11-04 |
20210343621 | Heat Sink, Heat Dissipation Apparatus, Heat Dissipation System, And Communications Device - One example heat sink includes a heat dissipation substrate, a connector, and a fastener. The heat dissipation substrate is configured to dissipate heat for a packaged chip located on a circuit board, and the heat dissipation substrate is located on a surface that is of the packaged chip and that is opposite to the circuit board. A first heat dissipation substrate and a second heat dissipation substrate of the heat dissipation substrate each have a heat conduction surface that conducts heat with a chip in the packaged chip. Different heat conduction surfaces correspond to different chips. | 2021-11-04 |