44th week of 2010 patent applcation highlights part 60 |
Patent application number | Title | Published |
20100281248 | ASSESSMENT AND ANALYSIS OF SOFTWARE SECURITY FLAWS - Security assessment and vulnerability testing of software applications is performed based at least in part on application metadata in order to determine an appropriate assurance level and associated test plan that includes multiple types of analysis. Steps from each test are combined into a “custom” or “application-specific” workflow, and the results of each test may then be correlated with other results to identify potential vulnerabilities and/or faults. | 2010-11-04 |
20100281249 | MEDIA INDEPENDENT HANDOVER PROTOCOL SECURITY - An apparatus for providing security to media independent handover service includes a point of service for providing the media independent handover services including an independent authenticator. The independent authenticator authenticates candidate access networks prior to the handover of the mobile devices from serving access networks to the candidate access networks, where each of the serving access networks and the candidate access networks belong to a plurality of heterogeneous access networks having the specific serving media. An access controller applies an access control through an access authentication with the point of service providing the media independent handover services through an authentication server, in which when the access authentication is established between the point of service and the authentication server, the mobile devices are authorized to access the media independent handover services through the point of service for the mobile devices attached between heterogeneous media. | 2010-11-04 |
20100281250 | AUTHENTICATION AND ENCRYPTION METHOD AND APPARATUS FOR A WIRELESS LOCAL ACCESS NETWORK - This invention pertains to the field of Wireless Local Area Network (WLAN). This invention allows a secure connection of a user client station to a base unit. The secure connection comprises the use of authentication and encryption means. The base unit comprises a switching unit, at least one firewall, an authentication/encryption unit and at least one port device. The invention also provides a secure roaming scheme when a roaming is performed by a wireless user. | 2010-11-04 |
20100281251 | Mobile Virtual Private Networks - An apparatus for establishing a virtual private network with an internet protocol multimedia subsystem (IMS) device that includes a key derivation module, a tunneling protocol module, a tunnel management module, and a security policies module. The apparatus includes a non-volatile memory configured to store a first routing table that maps host addresses and IMS addresses of security devices allowing access to those hosts, such that when an application running in the IMS device requests communication to a host address, the apparatus initiates a session with the IMS address to which the host address is mapped. The session is initiated by a message that includes a body that contains, for each tunneling protocol supported by the tunneling protocol module, data about the local tunnel endpoint (e.g., an address and a port), an identifier corresponding to the tunneling protocol, and identifiers corresponding to the cryptographic suite(s) supported by the cryptographic module that may be applied together with the tunneling protocol, as determined by a query from the apparatus to the security policies module. | 2010-11-04 |
20100281252 | ALTERNATE AUTHENTICATION - A user may utilize an existing digital identity to authorize the user's access to security-enabled device operations, where the security-enabled device comprises a cryptographic chip. The device can receive a user authentication token from the digital user identification service, which authenticates a user's identity. Further, the security-enabled device can validate the user authentication token, and provide the user access to device security operations on the security-enabled device if the user authentication token is successfully validated, allowing the user to reset their security access information for the device. | 2010-11-04 |
20100281253 | ISSUING A PUBLISHER USE LICENSE OFF-LINE IN A DIGITAL RIGHTS MANAGEMENT (DRM) SYSTEM - A publishing user publishes digital content and issues to itself a corresponding digital publisher license to allow itself to render the published digital content. The publishing user is supplied with a publishing certificate from a digital rights management (DRM) server, where the publishing certificate allows the publishing user to so publish the digital content and to so issue the publisher license. | 2010-11-04 |
20100281254 | SYSTEMS AND METHOD FOR SECURE DELIVERY OF FILES TO AUTHORIZED RECIPIENTS - By asking the recipient of an encrypted received file to read aloud a check text, retrieved from a network server, that address, or URL, is encoded within the file name of the encrypted received file, the system of the invention automatically verifies the identity of the recipient, confirms that the file has been received by the intended recipient, and then decrypts the file. The utterances of text spoken by the recipient are processed by means of an automatic speech recognition component. The system determines whether the spoken text corresponds to the check text presented to the reader, in which case the system applies an automatic speaker recognition algorithm to determine whether the person reciting the check text has voice characteristics matching those of the intended recipient based on a previous enrollment of the intended recipient's voice to the system. When the system confirms the identity of the recipient, the decryption key is transmitted and the encrypted received file is automatically decrypted and displayed to the recipient. In a preferred embodiment, the system records and marks with a time-stamp the recipient's reciting of the voice check text, so that it can later be compared to the intended recipient's voice if the recipient repudiates reception. | 2010-11-04 |
20100281255 | Launching A Secure Kernel In A Multiprocessor System - In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example. | 2010-11-04 |
20100281256 | HASH FUNCTION USING A PILING-UP PROCESS - In the computer data security field, a cryptographic hash function process embodied in a computer system and which is typically keyless, but is highly secure. The process is based on the type of randomness exhibited by well known tetromino stacking games. Computation of the hash value (digest) is the result of executing such a “piling on” (tetromino stacking game) algorithm using the message as an input (a seed) to a pseudo random number generator which generates the game pieces (shapes) from the resulting random numbers, then executing the game algorithm. | 2010-11-04 |
20100281257 | CONFIDENTIAL COMMUNICATION METHOD - It is an object of the present invention to solve a problem included in the onion routing which is used as a confidential communication method, that if a system down occurs in a computer within a communication route, connection is not made to further components at all, or a problem that the system and the traffic become slow by using multiplexed encryption. It is a communication method in which a client of an information providing source encrypts random numbers and calculates its hash value using respective public keys of an information server to which it connects, a function server of a destination to be sent, and an information server to which the function server connects, respective servers decrypt the encrypted random number using their own secret keys to compare the random number with the hash value, and thus, the client determines whether or not the route is related to the client. In such a way, information can be provided as an information providing source and an information provided destination are hidden, and as a response to provided contents from the function server which is the information provided source can also be kept anonymous. | 2010-11-04 |
20100281258 | SECURED PRESENTATION LAYER VIRTUALIZATION FOR WIRELESS HANDHELD COMMUNICATION DEVICE - The connectivity and security of wireless handheld devices (HDs) can be leveraged to provide a presentation appliance (PA) such as a laptop with an ability to securely communicate with an enterprise's private network. A split-proxy server, with part of it executing on the HD and a part executing on the PA, implements a full HTTP | 2010-11-04 |
20100281259 | KEY AGREEMENT AND TRANSPORT PROTOCOL WITH IMPLICIT SIGNATURES - A key establishment protocol between a pair of correspondents includes the generation by each correspondent of respective signatures. The signatures are derived from information that is private to the correspondent and information that is public. After exchange of signatures, the integrity of exchange messages can be verified by extracting the public information contained in the signature and comparing it with information used to generate the signature. A common session key may then be generated from the public and private information of respective ones of the correspondents. | 2010-11-04 |
20100281260 | HASH FUNCTION BASED ON POLYMORPHIC CODE - In the field of computer data security, a hash process which is typically keyless and embodied in a computing apparatus is highly secure in terms of being resistant to attack. The hash process uses computer code (software) polymorphism, wherein computation of the hash value for a given message is partly dependent on the content (data) of the message. Hence the computer code changes dynamically while computing each hash value. | 2010-11-04 |
20100281261 | DEVICE AND METHOD FOR NEAR FIELD COMMUNICATIONS USING AUDIO TRANSDUCERS - Secure wireless communication links are established between proximately-located devices, each of which includes respective audio transmitters and audio receivers. The audio transmitter of the first device can be used to transmit a device-dependent authentication key, which is received by the audio receiver of the second device. The audio transmitter of the second device can be used to transmit an acknowledgement, which is received at the audio receiver of the first device. The round-trip time from transmitting the authentication key from the first device to receiving the acknowledgement at the first device can be determined, and the decision of whether to establish the secure wireless communication link can be based on the determined round-trip time. In certain embodiments, these steps can be repeated starting with the second device to establish a two-way trust between the devices. | 2010-11-04 |
20100281262 | Method for Digital Rights Management in a Mobile Communications Network - The present invention relates to a method and an operator network node for enabling a user-defined DRM domain of *SIMs hosted by *SIM-enabled devices. The operator network node is connectable to a *SIM based device and to a content provider node, and comprises means for establishing a secure channel between a *SIM-based device and an operator network node, means for creating a DRM domain defined by at least one user of *SIM-based devices, means for receiving at the operator network node a registration request from the *SIM-based device to register the *SIM of the *SIM-based device into the created user-defined DRM domain, means for registering at the operator network node the *SIM of the *SIM-based device into the registered user-defined DRM domain, and means for making the registered information associated with the user-defined DRM domain available to the content provider. The invention also relates to a further method and the content provider comprising means for accessing in the operator network node registered information associated with a registered user-defined DRM domain comprising *SIMs of a user, and means for establishing a content provider defined DRM domain comprising at least one of the *SIMs of the user-defined DRM domain. | 2010-11-04 |
20100281263 | RECORDING DEVICE, SERVER DEVICE, RECORDING METHOD, RECORDING MEDIUM WITH COMPUTER PROGRAM RECORDED THEREIN AND INTEGRATED CIRCUIT - A recording device for recording one or more of a plurality of subcontents recorded on a first recording medium, onto a second recording medium, the first recording medium having further recorded thereon digest values of the subcontents, and a medium signature generated based on the digest values of the subcontents, the plurality of subcontents constituting one content, the recording device comprising: a subcontent acquisition unit operable to select and acquire one or more of subcontents permitted to be copied; an excluded digest value acquisition unit operable to acquire excluded digest values from the first recording medium, the excluded digest values being digest values of nonselected subcontents; a signature acquisition unit operable to acquire the medium signature from the first recording medium; and a write unit operable to write, onto the second recording medium, (i) the one or more selected subcontents, (ii) the excluded digest values, and (iii) the medium signature. | 2010-11-04 |
20100281264 | INFORMATION PROCESSING APPARATUS, KEY UPDATE METHOD, AND PROGRAM - An information processing apparatus includes: a signature generating section that generates an electronic signature σ by using a signature key KS associated with a verification key KV; and a substitute-key generating section that generates, with respect an electronic document m to which the electronic signature σ is attached by the signature generating section, a substitute verification key KV′ (KV′≠KV) that is capable of verifying a validity of the electronic signature σ and a substitute signature key KS′ (KS′≠KS) associated with the substitute verification key KV′. In a predetermined case, the verification key KV and the signature key KS are updated to the substitute verification key KV′ and the substitute signature key KS′. | 2010-11-04 |
20100281265 | INFORMATION DISTRIBUTION SYSTEM AND PROGRAM FOR THE SAME - The present invention is made to provide an information distribution system capable of securely storing digitized personal information in an encrypted state in a storage section and securely transferring/disclosing the stored digitized information only to a particular third person via a network. Communication of the information is securely performed in the encrypted state between information terminals connected to the communication network (between a client and a server or between peer-to-peer client terminals). An information terminal which has created information encrypts the original information by a common key generated upon communication and stores the information in a secure storage of one of the information terminals connected to the communication network while maintaining the encrypted state. Further, the system creates a mechanism for authenticating a person having a particular authority for viewing the encrypted information and index information having an encrypted common key and link information indicating the location of the information for supply to a user. | 2010-11-04 |
20100281266 | SYSTEM FOR SECURE INTERACTION WITH SECURE DOCUMENT - A system for secure interaction with a secure document is provided. The secure document has coded tags which each encode data associated with the document identity and a location of that tag on the document. The system has memory for recording a correspondence between the document identity and information relating to the document, a receiver for receiving data from a sensing device used to interact with the document, and a processor for verifying the interaction with the document using the received data and the recorded correspondence. The received data is generated by the sensing device through sensing of the data encoded by the coded tags to identify the document identity and a position of the sensing device relative to the document. | 2010-11-04 |
20100281267 | Image Processing Apparatus, Electronic Signature Generation System, Electronic Signature Key Generation Method, Image Processing Method, and Program - An image processing apparatus includes a first partial information providing unit that provides first partial information to another device holding a first signing key KS corresponding to a first verification key KV, the first partial information constituting a part of a second verification key KV′ (KV′≠KV) that is capable of verifying an electronic signature σ generated using the first signing key KS and being unable to identify the second verification key KV′; a second partial information acquisition unit that acquires second partial information which is generated by the another device using the first partial information and the first signing key KS, and which is unable to identify the first signing key KS and used for generating the remaining part of the second verification key KV′; and a second verification key generation unit that generates the second verification key KV′ based on the first and second partial information. | 2010-11-04 |
20100281268 | Personalizing an Adaptive Input Device - Methods and systems for personalizing an adaptive input device having a dynamically updateable display region are provided herein. One exemplary method includes sending an identity data query from a server to a computing device operatively coupled to an adaptive input device. The method further includes receiving identity data at the server from the computing device. The identity data includes one or more of a user identifier, a role identifier, a device identifier and a content identifier. The method further includes retrieving profile data from a profile storage module of the server, the profile data being based on the identity data, and the profile data including one or more of device-specific settings, application-specific settings, and user-specific settings for the adaptive input device. The method further includes sending the profile data to the computing device to update the visual appearance of the display region. | 2010-11-04 |
20100281269 | Identification Based on Encrypted Biometric Data - A database comprising biometric data stored in encrypted form is managed by a management unit. It comprises a set of filters respectively associated with filter identifiers. A biometric data item is received at a management unit; next, said biometric data item is stored in an encrypted form at a given address in the database. Then keywords are obtained on the basis of a first set of hash functions and of the biometric data item. A subset of indexing filters is associated with each keyword by selecting, for each keyword, filters as a function of the respectively associated filter identifiers, of said keywords, and of a second set of hash functions; and the given address is associated with each of the filters of the subset of filters. | 2010-11-04 |
20100281270 | CRYPTOGRAPHIC MODULE SELECTING DEVICE AND PROGRAM - A cryptographic module selecting device includes a cryptographic module evaluation information storage device configured to store identification information of a cryptographic module and cryptographic module evaluation information describing a function and/or performance of the cryptographic module in relation to each other, a condition information acquiring device configured to acquire condition information for specifying the condition of the cryptographic module to be selected, an extracting device configured to extract cryptographic module evaluation information conforming to the acquired condition information, from the stored cryptographic module evaluation information of the cryptographic module, and an output device configured to read out the identification information of the cryptographic module corresponding to the cryptographic module evaluation information selected by the extracting device from the cryptographic module evaluation information storage device and output the read identification information. | 2010-11-04 |
20100281271 | MUSICAL CONTENT DATA PROCESSING APPARATUS - A storage portion stores musical contents in which a plurality of musical content material data sets each of which is given a piece of identification information and is encrypted are recorded, and location information for identifying respective locations at which the respective musical content material data sets are situated in the musical contents. The respective locations of the musical content material data sets are correlated with the respective identification information pieces of the musical content material data sets. For use of a desired musical content material data set, the location at which the musical content material data set having designated identification information is stored in the musical contents is identified on the basis of the location information. On the basis of the identified location, the desired musical content material data set is extracted and decrypted. | 2010-11-04 |
20100281272 | INFORMATION UPDATING DEVICE AND INTEGRATED CIRCUIT THEREOF, INFORMATION UPDATING METHOD, AND RECORDING DEVICE AND INTEGRATED CIRCUIT THEREOF - Provided is an information updating apparatus that suppresses performance deterioration due to switching between writable recording areas in which information elements are to be written and readable recording areas from which the information elements are to be read. Also, the information updating apparatus updates a plurality of information elements recorded in a non-volatile recording medium with robustness against power discontinuity ensured. In order to achieve such effects, two groups of recording areas that are identical in number are allocated in the recording medium. The information elements are written in either group of the recording areas indicated by judgment information as the writable recording areas. Each time all the information elements have been written, the judgment information is updated. Thus, the writable recording areas are switched between the two groups of the recording areas. | 2010-11-04 |
20100281273 | System and Method for Processor-Based Security - A system and method for processor-based security is provided, for on-chip security and trusted computing services for software applications. A processor is provided having a processor core, a cache memory, a plurality of registers for storing at least one hash value and at least one encryption key, a memory interface, and at least one on-chip instruction for creating a secure memory area in a memory external to the processor, and a hypervisor program executed by the processor. The hypervisor program instructs the processor to execute the at least one on-chip instruction to create a secure memory area for a software area for a software module, and the processor encrypts data written to, and decrypts data read from, the external memory using the at least one encryption key and the verifying data read from the external memory using the at least one hash value. Secure module interactions are provided, as well as the generation of a power-on key which can be used to protect memory in the event of a re-boot event. Lightweight, run-time attestation reports are generated which include selected information about software modules executed by the processors, for use in determining whether the processor is trusted to provide secure services. | 2010-11-04 |
20100281274 | System and Method for Executing Code Securely in General Purpose Computer - The various embodiments of the invention provide a method for executing code securely in a general purpose computer. According to one embodiment, a code is downloaded into a cache memory of a computer in which the code is to be executed. The code downloaded into the cache memory is encrypted in the cache memory. Then the encrypted code in the cache memory is decrypted using a decryption algorithm to obtain the decrypted code. The decrypted code is executed in the cache to generate a result. The decrypted code is destroyed in the cache memory after the forwarding the result to a user. | 2010-11-04 |
20100281275 | METHOD OF RECORDING CONTENT ON DISC, METHOD OF PROVIDING TITLE KEY, APPARATUS FOR RECORDING CONTENT ON DISC, AND CONTENT PROVIDING SERVER - Provided are a method of recording content, a method of providing a title key, an apparatus for recording content, and a content providing server, which can prevent unauthorized users from recording the title key on a plurality of discs. The method of recording content downloaded from a network includes: receiving a title key, which is encrypted with a disc key of a disc on which content is to be recorded in a recording apparatus, from a server; and recording the received title key and the content on the disc. | 2010-11-04 |
20100281276 | COMPUTER SYSTEM WITH POWER SOURCE CONTROL AND POWER SOURCE CONTROL METHOD - A computer system with power source control and a power source control method are presented. The computer system at least includes a first storage unit and a second storage unit, and the first storage unit stores a system program required by the computer system in basic operation. A switch is disposed on a power supply path between a power supply module and the second storage unit, such that the power supply module provides an electric power for the second storage unit to operate through the switch. When the second storage unit is in an idle state, the switch is used to cut off the power supply to the second storage unit, so as to effectively reduce the power consumption of the computer system. | 2010-11-04 |
20100281277 | COMPUTER SYSTEM AND STAND-BY MODE MANAGEMENT MODULE AND STAND-BY MODE MANAGEMENT METHOD USING THE SAME - A stand-by mode management module applied in a computer system having a BIOS (basic input/output system), a graphic module and a display module is provided. The computer system is operated in a working state and at least one stand-by state. The module includes a timer and an interrupt generation unit. The timer starts a count period when detecting that the computer system is idle. The interrupt generation unit generates an interrupt request to the BIOS to request the computer system to prepare to enter to a specific state when the count period is reached. When the specific state is entered, the computer system enters the stand-by state, a PLL (phase lock loop) of the display module keeps turning on, and PLLs other than the PLL of the display module are turned off and the graphic module acquires a frame stored in a fixed area of a storing unit and displays the acquired frame on the display module. | 2010-11-04 |
20100281278 | COMPUTER SYSTEM AND OVERCLOCK CONTROLLING METHOD AND PROGRAM THEREOF - A computer system and overclock controlling method and program thereof, which includes steps of providing an overclock work voltage to a CPU when overclock is requested, then the CPU adjusts its clock domain according to the overclock work voltage. The overclock work voltage is a sum of a normal work voltage and an additional external voltage, by which the CPU may enter an overclock mode (a frequency of a clock domain signal is higher than a standard frequency value). Eventually, when the frequency of the clock domain signal of the CPU is in a stable status during the overclock mode, the work voltage for the CPU is reduced and the CPU keeps working in the overclock mode. | 2010-11-04 |
20100281279 | POWER SUPPLY SYSTEM AND ELECTRONIC DEVICE FOR CPU - A power supply system for CPU is disclosed. The CPU includes a plurality of dynamic voltage identification (VID) pins, and the power supply standard of the CPU conforms to a first standard. The power supply system includes a dynamic VID signal line set and a core voltage controller. The VID signal line set is coupled to the VID pins of the CPU. The core voltage controller conforms to a second standard and is coupled to a partial line set of the dynamic VID signal line set. The core voltage controller determines a core voltage to be output to the CPU according to the partial line set to conform to the first standard. | 2010-11-04 |
20100281280 | Interface Circuit System And Method For Performing Power Management Operations In Conjunction With Only A Portion Of A Memory Circuit - A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits | 2010-11-04 |
20100281281 | Server with Multiple Power Supplies - One exemplary embodiment is a server that includes multiple power supplies. When the server is in a standby state, one power supply is in a standby state and another power supply is in a deep sleep state. | 2010-11-04 |
20100281282 | LOOK-AHEAD PROCESSOR FOR SIGNALING SUITABLE PERFORMANCE STATE FOR MAIN PROCESSOR - A look-ahead processor identifies instructions that are at least likely to be executed by a main processor. The look-ahead processor determines a power state for the main processor that is suitable for executing the instructions. The look-ahead processor signals the main processor to enter the suitable performance state. | 2010-11-04 |
20100281283 | PRIMARY SIDE CONTROL CIRCUIT AND METHOD FOR ULTRA-LOW IDLE POWER OPERATION - A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10 | 2010-11-04 |
20100281284 | Methods and Systems for Providing Indirect Voltage Detection in a Power Supply - A method is provided for providing indirect voltage detection in a power supply of an IHS. The method may include providing output current and voltage to an IHS via a power cable and monitoring the output current within the power supply. Furthermore, the method may include adjusting the output voltage if the output current reaches a threshold value. | 2010-11-04 |
20100281285 | Managing under-utilized resources in a computer - A method, and a corresponding system, for managing under-utilized resources in a computer system includes the steps of monitoring performance of workloads executing on the computer system, where the workloads consume resources, determining resource demand and utilization by the workloads, comparing the workload performance to user-defined performance targets and resource utilization by the workloads to user-defined utilization targets, using the comparison results, determining if one or more resources may be assigned to a free resource pool, and assigning the determined resources to the free resource pool. | 2010-11-04 |
20100281286 | METHOD, COMPUTING SYSTEM, AND COMPUTER PROGRAM FOR REDUCING POWER CONSUMPTION OF A COMPUTING SYSTEM BY RELOCATING JOBS AND DEACTIVATING IDLE SERVERS - In a computing system where multiple servers are connected through a network and one or more jobs are run, a power reduction facility of a supervisory server relocates jobs according to predetermined conditions, thereby reducing the amount of power consumed by the computing system. For relocating the jobs, the power reduction facility obtains server-related information such as the power properties of the servers constituting the computing system and job-related information such as performance requirements for the jobs which are run in the computing system, and searches for one or more jobs to be relocated and destination servers, based on these server-related information and job-related information, to the extent that the performance requirements for each job are fulfilled. Based on the search results, the jobs are relocated to the destination servers, and servers on which no job is running, as a result of the relocation, are powered off. | 2010-11-04 |
20100281287 | PARTICIPANT RESPONSE SYSTEM EMPLOYING BATTERY POWERED, WIRELESS REMOTE UNITS - A participant response system ( | 2010-11-04 |
20100281288 | Layer 2 power classification support for power-over-ethernet personal computing devices - A Power-over-Ethernet (PoE) communication system dynamically provides power and data communications over a communications link. In an enterprise environment made up of one or more personal computing devices (e.g., personal or laptop computers), a switch determines a power classification for each device via a PoE control module that can be part of, for example, a Power Source Equipment/Powered Device (PSE/PD) system or a LAN-On-Motherboard/Powered Device (LOM/PD) system. A method of classifying power for each device includes detecting a device, polling it for power requirement information using a Layer 2 data link layer, receiving power requirement information from the device, and determining a power classification for the device. Power requirement information can include battery charge status, power load, power mode, etc., of the device. Various types of data packets can be used. The method can be repeated on a periodic basis, allowing power classification to be dynamic. | 2010-11-04 |
20100281289 | Bidirectional Memory Interface with Glitch Tolerant Bit Slice Circuits - A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation. | 2010-11-04 |
20100281290 | CLOCK GENERATING CIRCUIT OF COMPUTER - A clock signal generating circuit of a computer includes a first phase locked loop (PLL) circuit and a second PLL circuit. The computer includes a central processing unit (CPU) and a data bus. The first PLL provides a CPU clock signal to the CPU. A frequency of the CPU clock signal is the same as a working frequency of the CPU. The second PLL circuit provides a bus clock signal to the data bus. A frequency of bus clock signal is the same as a working frequency of the data bus. The data bus is to communicate with a graphic chip. The CPU clock signal is to control a working speed of the CPU. The bus clock signal is to control a working speed of the data bus. | 2010-11-04 |
20100281291 | METHOD FOR ADJUSTING COMPUTER SYSTEM AND MEMORY - The invention provides an adjusting method of a system for changing a working frequency in an operation system for a computer system. The adjusting method includes establishing a look-up table, and detecting a newest value of the working frequency. An adjustment value can be obtained from the look-up table according to the newest value of the working frequency. In addition, a phase difference of a control signal of a memory is adjusted in the computer system according to the adjustment value and the working frequency is executed stably in optimum status according to the present invention. | 2010-11-04 |
20100281292 | METHOD AND APPARATUS FOR RESOLVING CLOCK MANAGEMENT ISSUES IN EMULATION INVOLVING BOTH INTERPRETED AND TRANSLATED CODE - Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is emulated to generate a first set of emulated instructions that emulate a first component on the host system. A second set of code instructions is emulated to generate a second set of emulated instructions that emulate a second component of the target system on the host system. The first set is executed based on a first clock (which may be a fixed clock) and the second set is executed based on a second clock (which may be a variable clock). The host system adjusts the first or second clock, execution of the first or second sets of instructions or a memory access to maintain a desired synchronization between the first and second sets of instructions. | 2010-11-04 |
20100281293 | REPLACING RESET PIN IN BUSES WHILE GUARANTEEING SYSTEM RECOVERY - Systems and methods are disclosed that replace a separate reset pin in a bus with a reset command that guarantees a system recovery. The system comprises a host component circuitry residing on a first chip and a client component circuitry residing on a second, different chip. A bus connects the host component circuitry to the client component circuitry. The host component circuitry is configured to transfer an initial client value associated with a client component time period to the client component circuitry over the bus on a periodic time basis. The periodic time basis is dictated by a host component time period and the client component time period is greater than the host component time period. The client component circuitry is configured to initiate a reset procedure if the client component time period expires which indicates that the initial client value was not received at a next time on the periodic time basis dictated by the host component time period. | 2010-11-04 |
20100281294 | METHOD OF MANAGING OPERATIONS FOR ADMINISTRATION, MAINTENANCE AND OPERATIONAL UPKEEP, MANAGEMENT ENTITY AND CORRESPONDING COMPUTER PROGRAM PRODUCT - A method and apparatus are provided for managing administrative and maintenance operations for a computer connected to a communication network. The method includes: a phase of receiving a request in respect of at least one command to be executed, originating from the computer; a phase of programmed sequential distribution of the at least one command previously recorded within an operations database, destined for the computer; a phase of recording, within a database for collecting results associated with the computer, at least one result of implementing the at least one sequentially distributed command. | 2010-11-04 |
20100281295 | Method for Fast Connectivity Fault Management [CFM] of a Service-Network - This invention is related to a method for Fast Connectivity Fault Management (CFM) of a service-network in the realm of Carrier Ethernet, comprises steps of: learning spanning tree topology of the service-network, exchanging Fast Connectivity Check Messages (Fast-CCM)s between the adjacent service-nodes of the tree, terminating the Fast-CCMs so received, to learn the fault, in the service-network, upon failure to receive a Fast-CCM through a service-port, and pro-actively notifying the fault by service nodes on either side of the faulty service-network. | 2010-11-04 |
20100281296 | FAULT TOLERANT ROUTING IN A NON-HOT-STANDBY CONFIGURATION OF A NETWORK ROUTING SYSTEM - Methods and systems for facilitating fault tolerance in a non-hot-standby configuration of a network routing system are provided. According to one embodiment, a failover method is provided. A fault manager executing on a control blade of multiple server blades of a network routing system actively monitors an active processing engine of multiple processing engines within the network routing system. Responsive to detecting a fault associated with the active processing engine, the active processing engine is dynamically replaced with a non-hot-standby processing engine of the multiple processing engines by (i) determining one or more software contexts that were associated with the active processing engine prior to detection of the fault, and (ii) creating one or more replacement software contexts within the non-hot-standby processing engine corresponding to the one or more software contexts. | 2010-11-04 |
20100281297 | Firmware recovery in a raid controller by using a dual firmware configuration - A system comprising a first memory, a second memory, and a controller. The first memory may be configured to store a first firmware. The second memory may be configured to store a second firmware similar to the first firmware stored on the first memory. The controller may be configured to (i) operate the first firmware stored on the first memory, (ii) discontinue operating the first firmware in response to a failure of the first firmware, and (iii) begin operating the second firmware after discontinuing operation of the first firmware. | 2010-11-04 |
20100281298 | Monitoring Device - The invention relates to a monitoring device for a processor comprising a means for monitoring the power consumption of the processor and a means for analysing the power consumption to detect abnormal operation of the processor. | 2010-11-04 |
20100281299 | FILE SYSTEM RECOGNITION STRUCTURE - A set of file system data structure and file system recognition APIs are disclosed that may allow an operating system to identify a partition of a storage device as having a valid file system, even if the operating system does not know how to access the file system a priori. File systems implement these data structures in a standardized, known location within a partition on the storage device such that an operating system may use APIs or other functions to examine that known location for the presence of these data structures. Information on how to interpret the data structure may be obtained using a network or other source. | 2010-11-04 |
20100281300 | IMAGE EXCHANGE WITHOUT FULL MICR QUALIFICATION - A system and related methods of correcting errors during check or financial document processing by a bank of first deposit or other entity receiving a paper check or financial document, or by a second bank on whose accounts the checks were written. These corrections can be performed by the computer system of the bank of first deposit, the computer system of the second bank, or both. MICR or other data may be sent in electronic format from the bank of first deposit or other entity without qualification. | 2010-11-04 |
20100281301 | CIRCUIT FOR A TRANSPONDER AND METHOD FOR TESTING THE CIRCUIT - A method for testing a circuit for a transponder, and transponder circuit, is provided, in which the circuit is operated in a passive mode in that the circuit is supplied with energy from a field, in which, during the passive mode, the circuit receives a command via the field to activate a test routine, in which memory content is stored by the test routine as test data in a memory area of a memory of the circuit predetermined by the test routine, in which, during the passive mode, the test data are transmitted via the field. | 2010-11-04 |
20100281302 | Memory Having an ECC System - An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors. | 2010-11-04 |
20100281303 | Systems And Methods For Automated Determination Of Error Handling - Systems and methods for automated determination of error handling. Data is received including one or more procedural operations to be tested. A first test is run on the data to capture one or more first tracebacks, where each traceback is associated with a procedural operation. A determination is made as to whether each captured first traceback is unique, where unique tracebacks are added to a unique traceback list. An error condition is simulated on each unique traceback on the unique traceback list by running a second test. The second test is run once for each unique traceback. One or more second tracebacks are captured during each run of the second test. When a unique traceback being tested matches a captured second traceback, an error code is returned and the second test may be run to completion. Errors encountered during each iteration of the second test running to completion are identified. | 2010-11-04 |
20100281304 | DEBUG MESSAGING WITH SELECTIVE TIMESTAMP CONTROL - A data processing system having debug message generation uses processor circuitry to perform a plurality of processor operations. Global control circuitry is coupled to the processor circuitry. Debug circuitry is coupled to the global control circuitry for generating debug messages corresponding to predetermined processor operations. Message generation logic provides debug messages which selectively include a timestamp field providing information as to when a debug message is generated. Debug control circuitry is coupled to the global control circuitry and the message generation logic and has a timestamp control register. For each of a plurality of debug message types, the timestamp control register selectively enables or disables appending a timestamp to the debug message for that type of debug message. Enable logic is coupled to the timestamp control register for enabling or disabling the timestamp control register based on detecting a selected event in the data processing system. | 2010-11-04 |
20100281305 | HIERARCHICAL LOAD ESTIMATION SYSTEM, METHOD AND PROGRAM - A hierarchical load estimation system | 2010-11-04 |
20100281306 | Modular Bug Detection with Inertial Refinement - Systems and methods are disclosed to detect an error in a software with a computer readable code by applying a modular analysis based on the principle of structural abstraction and refinement of program structure; and detecting an assertion violation indicative of a software bug. | 2010-11-04 |
20100281307 | Systems and methods for identifying a relationship between multiple interrelated applications in a mainframe environment - Systems and methods are provided for identifying a relationship between multiple interrelated applications running in a mainframe environment. A repository is created to store information describing the multiple interrelated applications from the mainframe environment. A target application among the multiple interrelated applications is identified, and a frequency and a dependency relationship between the application and the multiple interrelated applications is determined. The relationship is displayed via a user interface. The relationship may be used to identify a cause of a failure in a mainframe environment. | 2010-11-04 |
20100281308 | TRACE MESSAGING DEVICE AND METHODS THEREOF - A method of generating timestamped trace messages includes generating a trace message in response to an event at an instruction pipeline of a data processing device. If timestamping is enabled, timestamps are only included in the trace message only if a programmable condition is detected. For example, a timestamp can be included in the trace message if the amount of space used to store messages at a trace message buffer exceeds a watermark value. The condition that results in a timestamped trace message is programmable, and can be selected via a debug interface. Because timestamps are only included in trace messages when the programmable condition is satisfied, some trace messages will not include a timestamp, thereby reducing the amount of buffer space needed to store the trace messages. | 2010-11-04 |
20100281309 | Power Management Events Profiling - In a method for monitoring power consumption by a system within an integrated circuit, one or more software programs are executed on the system on a chip (SOC). While the program executes, power control settings of a plurality of functional units within the SOC may be adjusted in response to executing the one or more software programs, whereby power consumption within the SOC varies over time. The power control settings may be changed in response to explicit directions from the executing software, or may occur autonomously in response to load monitoring control modules within the SOC. A sequence of power states is reported for the plurality of functional units within the SOC. Each of the sequence of power states may include clock frequencies from multiple clock domains, voltage levels for multiple voltage domains, initiator activity, target activity, memory module power enablement, or power enablement of each of the plurality of functional units. | 2010-11-04 |
20100281310 | METHOD AND SYSTEM FOR SAMPLING INPUT DATA - A method and system for sampling input data. The method includes: buffering input data; recording an execution path of the buffered input data in an online operation module; determining whether the buffered input data passes through a desired execution path, and responsive to the buffered input data passing through the desired execution path, sampling the buffered input data to a data set. The system includes: buffering means for buffering input data; recording means for recording an execution path; sampling means for determining whether the buffered input data passes through a desired execution path. | 2010-11-04 |
20100281311 | METHOD AND SYSTEM FOR RECONSTRUCTING ERROR RESPONSE MESSAGES UNDER WEB APPLICATION ENVIRONMENT - A computer-implemented method and system for reconstructing a response message to an improper accessing request in a web application environment. The method includes: obtaining the URL of a web application to be accessed by the improper accessing request and the error parameter information of the improper accessing request; obtaining a response template based on the obtained URL of the web application to be accessed; and merging the obtained error parameter information of the improper accessing request with the obtained response template to generate a reconstructed response message for the improper accessing request. The system includes: a message obtaining device; a response message template obtaining device; and a response message merging device. | 2010-11-04 |
20100281312 | SERVER-BASED NOTIFICATION OF ALARM EVENT SUBSEQUENT TO COMMUNICATION FAILURE WITH ARMED SECURITY SYSTEM - A server-based environment for reporting a status of a security, monitoring and automation controller is provided. Detecting cessation of an always-on persistent network connection between the SMA controller and the server is also provided. Reporting the cessation of the network connection to an end user and defined others is further provided. A further aspect provides for automatically reporting an alarm event to a central station, the end user, and others, in the event the cessation of the network connection occurs while the SMA controller is armed and after a zone fault event, and not receiving a disarm notification prior to expiration of a preset entry delay. | 2010-11-04 |
20100281313 | DYNAMICALLY GENERATED WEB SURVEYS FOR USE WITH CENSUS ACTIVITIES, AND ASSOCATED METHODS - Certain example embodiments disclosed herein relate to online survey systems and/or methods. In certain example embodiments, the questions to be asked are substantially insulated from an application that asks the questions. This abstraction may be accomplished in certain example embodiments by dynamically generating a computer-accessible (e.g., web-based) survey from one or more definition files. For example, a survey may be defined via a response definition file and a user interface definition file, thereby enabling the definition files to be read and the survey to be presented with the appropriate questions, validations, and transformations being specified by the response definition file, and with the look and feel being specified by the user interface definition file. Answers to questions may be persisted for a respondent in a storage location remote from the respondent. Such online surveys systems and/or methods may be suitable for census-related activities. | 2010-11-04 |
20100281314 | Smart Fields - Systems, methods, and computer programs are provided for smart interfaces that shift the burden of cognition from a user to a computer system. More particularly, a method is presented for using a computer system to interpret data. The method includes an operation for accepting data from a data entry field of the user interface, where the data is provided to the data entry field in a selected format. The selected format is different from a common data format expected by the user interface. In another operation, the accepted data is normalized to conform to the common data format expected by the user interface. This normalization is based on information about one or more of a geographic location of the user, a geographic location of a server, and a geographic location of a product being used. Further, the method includes an operation for providing the normalized data in the common data format. | 2010-11-04 |
20100281315 | MEMORY CHANNEL WITH BIT LANE FAIL-OVER - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 2010-11-04 |
20100281316 | SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING APPARATUS, OUTPUT DATA DIFFUSION METHOD, AND PROGRAM - A semiconductor integrated circuit includes a scan chain configured to serve as a connection path used for testing the semiconductor integrated circuit and connect a plurality of flip-flops and an interleave circuit provided at an output portion of the scan chain. The interleave circuit includes a plurality of branches including different numbers of stages of storage elements, a selector configured to select one of the plurality of branches serving as an input/output branch that performs input of data from the scan chain and output of data from the interleave circuit, and a selector controller configured to execute a process of switching among the plurality of branches to select the input/output branch at every predetermined timing. | 2010-11-04 |
20100281317 | CONTROLLER APPLYING STIMULUS DATA WHILE CONTINUOUSLY RECEIVING SERIAL STIMULUS DATA - An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the peripheral circuit signals which would normally be provided and received by the data processing circuitry. The serial scanning circuitry is connectable to an emulation controller for transferring serial data between the emulation controller and the emulator. The serial scanning circuitry includes a first state machine having plural states controlling the transfer of serial data. The emulator further includes control circuitry connected to the serial scanning circuitry and connectable to the emulation controller. The control circuitry, when connected to the emulation controller, effects the providing and receiving of signals and the transferring of serial data between the emulation controller and the emulator continuously without interruption while the first state machine remains in one state. | 2010-11-04 |
20100281318 | Tolerant in-system programming of field programmable gate arrays (fpgas) - Fault tolerant programming of a programmable device advantageously occurs via a host controller that first queries the programmable device through a Boundary scan interface to identify the device. Thereafter, host controller selects a program file in accordance with the device identity for subsequent downloading via the Boundary scan interface to program the device. Thereafter, the host controller verifies that successful programming has occurred. | 2010-11-04 |
20100281319 | REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY - Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains. | 2010-11-04 |
20100281320 | METHOD FOR ACCURACY IMPROVEMENT ALLOWING CHIP-BY-CHIP MEASUREMENT CORRECTION - A method for allowing measurement corrections on a chip-by-chip basis. Error correction values are generated responsive to the input value to a circuit of the calibrated integrated circuit chip and to a measured value from the circuit of the calibrated integrated circuit chip. The error correction values are stored within an error correction table within a nonvolatile memory of the integrated circuit chip. | 2010-11-04 |
20100281321 | Error Concealment - A method and apparatus for selectively replacing damaged portions of a data stream. The method comprises analyzing the data stream to identify damaged portions therein; selecting a damaged portion for replacement; and replacing the selected damaged portion. The selected damaged portion is selected for replacement in dependence on a rate of replacement, the rate of replacement being that at which previous portions of the data stream have been replaced. | 2010-11-04 |
20100281322 | SYSTEM AND METHOD FOR DYNAMIC HYBRID AUTOMATIC REPEAT REQUEST (HARQ) ENABLE/DISABLE - A system and method of increasing data throughput in a wireless communications network between a base station (BS) and one or more mobile stations (MS) includes establishing a service flow (SF) and initially enabling a hybrid automated repeat request (HARQ) protocol; determining, at a particular time, the measure of quality of the communications channel; comparing the determined measure of quality with a predetermined channel quality threshold; and selectively disabling the HARQ protocol based upon a first comparison result while continuing the SF between the BS and MS. In other aspects, after selectively disabling the HARQ protocol, the method further includes determining that the time-varying measure of quality of the communications channel has deteriorated below the predetermined channel quality threshold; and selectively re-enabling the HARQ protocol in the established SF. | 2010-11-04 |
20100281323 | CONTROL AND DATA CHANNELS FOR ADVANCED RELAY OPERATION - A relay station in a wireless communication system is configured to relay communications between the base station and a plurality of subscriber stations. The relay station includes at least one antenna configured to transmit and receive data and control information. The relay station also includes a controller coupled to the antenna. The controller is configured to transmit control information to a subscriber station during a first set of symbols in a relay station to subscriber station (RS-to-SS) subframe. The controller also switches the antenna to a receive mode; and receives control information during a second set of symbols in the RS-to-SS subframe. | 2010-11-04 |
20100281324 | METHODS AND SYSTEMS FOR ARQ RESET - Embodiments of the present propose methods and systems for managing previously initiated ARQ resets when it is determined that both the RX and TX initiated independent ARQ reset procedures. | 2010-11-04 |
20100281325 | INTERFERENCE LIMITATION FOR RETRANSMISSIONS - The present invention relates to a method for transmitting data packets from a mobile terminal to a base station using a hybrid automatic repeat request protocol and soft combining of received data. Further, the present invention provides a base station and a mobile terminal both adapted to perform the respective method steps. Moreover, a communication system is provided which comprises at least one base station and at least one mobile terminal. The present invention also provides a computer-readable medium for storing instructions that, when executed on a processor, cause the processor to transmit data packets from a mobile terminal to a base station using a hybrid automatic repeat request protocol and soft combining of received data. In order to restrict the interference caused by retransmissions, the present invention suggests controlling the amount of information in the retransmissions and thus the transmission power required for their transmission by TFCS restriction. | 2010-11-04 |
20100281326 | METHOD FOR EFFECTIVELY TRANSMITTING CONTROL SIGNAL IN WIRELESS COMMUNICATION SYSTEM - A method of performing HARQ performed by a user equipment (UE) is provided. The method includes receiving a bundling indicator which indicates the number of bundled downlink subframes, determining whether at least one bundled downlink subframe is missed by comparing the bundling indicator with the number of detected bundled downlink subframes, generating a representative ACK/NACK signal when no bundled downlink subframe is missed, and transmitting the representative ACK/NACK signal on an uplink channel. Recovery capability is maximized and the packet loss is reduced in such a situation that less number of ACK/NACK signals are fed back than that of downlink packets. | 2010-11-04 |
20100281327 | COMMUNICATION SYSTEM, TRANSMITTER, ERROR CORRECTING CODE RETRANSMITTING METHOD, AND COMMUNICATION PROGRAM - Intended is to achieve, in a wide range of an SN ratio, throughput on the same order of that attained by a method based on puncturing and improve computational complexity of decoding processing at a high coding rate. In a communication system for transmitting an error correcting code for an error on a communication path from a transmitter to a receiver, the transmitter divides information bits of a code word to be transmitted into a plurality of blocks based on a request for retransmission of an error correcting code from the receiver, generates an error correcting code by compact-coding of one block among the plurality of blocks and transmits the generated error correcting code. | 2010-11-04 |
20100281328 | HIGH SPEED LOW DENSITY PARITY CHECK CODES ENCODING AND DECODING - Certain aspects of the present disclosure relate to a method for generating a single rate or multi-rate highly structured low density parity check, encoding a data stream with the generated LDPC matrix for transmission in a wireless communication system, and for efficient LDPC decoding at a receiver. | 2010-11-04 |
20100281329 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD AND PROGRAM - The present invention relates to a data processing apparatus, a data processing method and a program which can improve the tolerance of code bits of an LDPC code to errors. | 2010-11-04 |
20100281330 | Low complexity communication device employing in-place constructed LDPC (Low Density Parity Check) code - Low complexity communication device employing in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform decoding of more than one type of LDPC coded signals. A common basis of decoder hardware (e.g., decoder circuitry) is employed when decoding all of the various types of LDPC coded signals that such a communication device can decode. However, all of the decoder hardware is only employed to decode signals corresponding to the lowest code rate LDPC code supported by the communication device. A first subset of the decoder hardware is employed to decode signals corresponding to the second to lowest code rate LDPC code, a second subset (being less than the first subset) is employed to decode signals corresponding to the third to lowest code rate LDPC code, etc. | 2010-11-04 |
20100281331 | Systems and Methods for a Rateless Round Robin Protocol for Adaptive Error Control - Systems and methods implementing a protocol that provides reliable transport over a point-to-point link characterized by deep and sustained fades. Such a communications link may be a free space optical channel or may be a radio frequency point-to-point channel. Data frames are processed through a circular data buffer that operates in a round robin fashion at a transmission node. The coding and forward error correction processes allow for continued operation in spite of possible signal fades due to atmospheric turbulence or other causes. At a receive node, incoming data is also saved in a circular buffer. A re-acknowledgment list is maintained at the receive node for tracking recently received and decoded data. This allows for a new acknowledgment to be sent in the event that a previously sent acknowledgment failed to reach the transmission node. | 2010-11-04 |
20100281332 | ENCODING METHOD AND DEVICE FOR LOW DENSITY GENERATOR MATRIX CODES - The present invention discloses an encoding method and device for Low Density Generator Matrix Codes (LDGC). Wherein, the method comprises: construct an LDGC mother code set using a plurality of LDGC with code rate R | 2010-11-04 |
20100281333 | FEEDBACK WITH UNEQUAL ERROR PROTECTION - Methods and devices provide a feedback message having unequal error protection. The feedback message may include channel quality indicators. The channel quality indicators may have different levels of error protection based on a transmission property. | 2010-11-04 |
20100281334 | SYSTEMS AND METHODS FOR COMMUNICATIONS - Systems, methods, and an article of manufacture for performing serial concatenated decoding are shown and described. The decoding includes monitoring a measure of the number of corrections made to a plurality data blocks during outer decoding and determining whether applying sub-optimal inner decoding would reduce a computational load experienced by a processor performing the serial concatenated decoding when compared to the computation load experienced by the processor when optimal inner decoding is applied. | 2010-11-04 |
20100281335 | Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code - Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform encoding of respective information bit groups using more than one type of LDPC codes. A switching module can select any one of the LDPC codes within an in-place LDPC code for use by an LDPC encoder circuitry to generate an LDPC coded signal. Depending on which sub-matrices of a superimposed LDPC matrix are enabled or disabled, one of the LDPC matrices from within an in-place LDPC code matrix set may be selected. A corresponding, respective generator matrix may be generated from each respective LDPC matrix. Selection among the various LDPC codes may be in accordance with a predetermined sequence, of based operating conditions of the communication device or communication system. | 2010-11-04 |
20100281336 | METHOD AND ENTITY FOR PROBABILISTIC SYMMETRICAL ENCRYPTION - The invention relates to a method of probabilistic symmetric encryption of a plaintext message element with the aid of a secret key that can be represented in the form of a matrix. It comprises an operation of encrypting the plaintext message element, with the aid of the matrix parametrized by a random vector, so as to obtain an encrypted message element coupled to the random vector. Furthermore, there is envisaged a step of encoding the plaintext message element as a code word with the aid of an error correcting code having a given correction capacity and a step of adding a noise vector. The error correcting code and the noise vector are adapted so that the Hamming weight of the noise vector is less than or equal to the correction capacity of the correcting code. | 2010-11-04 |
20100281337 | ANALOG ITERATIVE DECODER WITH EARLY-TERMINATION - An iterative decoder comprising a transconductance amplifier, a sampler, a Min-Sum decoder, and an early determination module is provided. The transconductance amplifier outputs a current proportional to the voltage of the coded bit stream. The sampler converts the amplified current into a plurality of currents and stores the sampled currents in a plurality of buffers. The Min-Sum decoder receives parallel currents, wherein currents represent the message of each variable node. The Min-Sum decoder exchanges the message of variable nodes and check nodes iteratively and outputs a set of decode codewords according to the possibilities. The early terminating module stops the iterative decoding when the decoded codeword converged. | 2010-11-04 |
20100281338 | Digital Broadcasting System and Error Correction Method Thereof - A digital broadcasting system comprising of a digital broadcasting station, a set of digital broadcast receivers, and a switched network, wherein the digital broadcasting station transmits a digital signal to the set of digital broadcast receivers, and the digital broadcast receivers exchange error correction information with each other using the network to compensate errors in local receptions of the digital signal at each digital broadcast receiver location. | 2010-11-04 |
20100281339 | FORWARD ERROR CORRECTION MEDIA ACCESS CONTROL SYSTEM - This disclosure relates to method, device and system for compensating for information not received in a communication system. An encoded signal is created from a source signal using a forward error correction technique. A first predetermined part of the encoded signal is transmitted. A second predetermined part of the encoded signal is transmitted. Transmission of the second predetermined part of the encoded signal is terminated after a determination of a successful decoding of the encoded signal is made. | 2010-11-04 |
20100281340 | ADAPTIVE ENDURANCE CODING OF NON-VOLATILE MEMORIES - Adaptive endurance coding including a method for storing data that includes receiving write data and a write address. A compression algorithm is applied to the write data to generate compressed data. An endurance code is applied to the compressed data to generate a codeword. The endurance code is selected and applied in response to the amount of space saved by applying the compression to the write data. The codeword is written to the write address. | 2010-11-04 |
20100281341 | NON-VOLATILE MEMORY MANAGEMENT METHOD - A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data; dividing at least one of the pages into a plurality of partitions each including the user data and parity data; determining codeword length of each of the partitions, the codeword length comprising message length with sufficient storage to store the user data and parity length storing the parity data; and storing extra parity data in the partition with the codeword length. When storing extra parity data in the codeword length, the parity length is increased and the message length is decreased. | 2010-11-04 |
20100281342 | MEMORY CONTROLLER AND MEMORY SYSTEM - A memory system is provided. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array and a read/write circuit configured to perform a read/write operation in the memory cell array during a read operation. The controller is configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data. Upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error. After correcting the detected error in the received portion of the read data, the controller is configured to resume transmission of the read data from the nonvolatile memory. | 2010-11-04 |
20100281343 | Virtual Lane Forward Error Correction in Multilane Distribution - A system and method are provided for generating virtual lane (VL) forward error correction (FEC) overhead (OH) in a communication multi-lane distribution (MLD) protocol transmitter, and for recovering data words from virtual lanes with FEC OH in an MLD protocol receiver. The transmission method accepts an Optical Transport Network (OTN) frame with n consecutively ordered payload chunks of data words, at a first data rate. Each payload chunk is assigned to a virtual lane data word (VLDW) in an MLD frame of n consecutively ordered VLDWs. The assignment order of payload chunks to VLDWs is rotated at the start of each MLD frame. VLDWs are joined into VLDW groups, where each VLDW group includes at least one VLDW. FEC blocks are calculated for VLDWs, creating ordered VL codewords (VLCWs). Then, the VLCWs are multiplexed to maintain a consistent assignment of VLCW order to physical transmission lanes and transmitted. | 2010-11-04 |
20100281344 | SOFT REED-SOLOMON DECODER BASED ON ERROR-AND-ERASURE REED-SOLOMON DECODER - An apparatus having a first circuit and a second circuit is disclosed. The first circuit may (i) generate a decoded codeword by decoding a first codeword a plurality of times based on a respective plurality of erasure location vectors and (ii) assert a fail signal upon each failure of the decoding of the first codeword, the decoding comprising an error-and-erasure Reed-Solomon decoding. The second circuit may (i) generate a count of the assertions of the fail signal and (ii) generate the erasure location vectors based on (a) the count and (b) a plurality of reliability items corresponding to the first codeword. | 2010-11-04 |
20100281345 | DTV TRANSMITTER AND METHOD OF CODING MAIN AND ENHANCED DATA IN DTV TRANSMITTER - A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data packets with main data packets. It further includes an RS encoder which RS-codes the multiplexed data packets, and a data interleaves which interleaves the RS-coded data packets. The RS encoder adds systematic RS parity data to each main data packet and adds non-systematic RS parity place holders to each enhanced data packet. The RS encoder adds the RS parity place holders such that the RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet. | 2010-11-04 |
20100281346 | DTV TRANSMITTER AND METHOD OF CODING MAIN AND ENHANCED DATA IN DTV TRANSMITTER - A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data packets with main data packets. It further includes an RS encoder which RS-codes the multiplexed data packets, and a data interleaves which interleaves the RS-coded data packets. The RS encoder adds systematic RS parity data to each main data packet and adds non-systematic RS parity place holders to each enhanced data packet. The RS encoder adds the RS parity place holders such that the RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet. | 2010-11-04 |
20100281347 | VITERBI DETECTOR THAT ASSOCIATES MULTIPLE DATA DEPENDENT NOISE PREDICTION FILTERS WITH EACH POSSIBLE BIT PATTERN - A Viterbi detector includes a plurality of possible bit patterns that correspond to branches of a detector trellis and a plurality of data dependent noise prediction filters, with multiple filters of different orders being associated with a given bit pattern. A method of decoding includes applying observables to a Viterbi detector that associates a plurality of data dependent noise filters with a given possible bit pattern that corresponds to a branch of the detector trellis, calculating the composite maximum likelihood branch metric by incorporating the results of filtering the observables through the associated plurality of filters, calculating the composite maximum likelihood branch metrics in the same manner for other possible bit patterns, and so forth, and associating soft output values with detected bits in the observables based on the calculated branch metrics. | 2010-11-04 |