44th week of 2011 patent applcation highlights part 27 |
Patent application number | Title | Published |
20110267835 | LIGHT SOURCE - The present invention relates to a light emitting diode, LED, light source that may be arranged for retrofitting into a luminaire employing an incandescent light source. The light source comprises a light guide into which light from one or more LEDs in a light unit arranged at one end of the light guide is injected, and a reflector having a reflecting surface arranged at the other end of the light guide and facing towards the light guide capable of reflecting light incident on the reflecting surface. According to the present invention, the reflector comprises at least one transmitting portion being arranged such that at least a portion of light incident on the at least one transmitting portion is transmitted through the reflector, for example a through hole extending along an axis, allowing for an almost viewing angle independent light intensity of the light source. | 2011-11-03 |
20110267836 | LIGHT SOURCE - The present invention relates to a light emitting diode, LED, light source that may be arranged for retrofitting into a luminaire employing an incandescent light source. The light source comprises a light guide into which light from one or more LEDs in a light unit arranged at one end of the light guide is injected, and a reflector having a reflecting surface arranged at the other end of the light guide and facing towards the light guide capable of reflecting light incident on the reflecting surface. According to the present invention, the reflecting surface can be arranged in a number of exemplary ways such as to enable the light emitted from the light source to have a spatial intensity distribution that is similar to the light intensity distribution of an incandescent light source. | 2011-11-03 |
20110267837 | BACKLIGHT UNIT AND DISPLAY DEVICE HAVING THE SAME - A backlight unit is disclosed. The backlight unit includes a light emitting device array including a plurality of light emitting devices, an optical sheet to transmit light emitted from the light emitting device array, a frame to support the light emitting device array and the optical sheet, and at least two heat dissipating members placed on the frame in an emission direction of light from the light emitting device array. The heat dissipating member disposed at the center has a greater area than the heat dissipating member disposed at the perimeter. | 2011-11-03 |
20110267838 | Optic System for Light Guide with Controlled Output - A light guide with optics guides light exiting the guide. The device achieves accurate control of the reflected light by extracting light from a limited area of the light guide. The configuration of the reflectors used for the selective extraction determines the nature of the output light. The reflectors may be located on a side of the light guide opposite to an output side of the light guide. | 2011-11-03 |
20110267839 | RADIATION STRUCTURE WITHOUT LIGHT GUIDING BOARD - A radiation structure without a light guiding board for a backlight module or an illuminant device includes an optical plate formed with at least one rising area having a rising surface defined at the center thereof, two light sources disposed adjacent to two sides of the optical plate, and a diffusion plate. The light sources each possess a radiant half-intensity angle below 15 degrees for respectively forming optic axial directions thereof, allowing a radiation field to be diffusively formed from the pivoting of the optic axial directions. Whereby, the optic axial directions respectively face toward the rising surface, allowing the projection of the radiation field on the rising surface, and the diffusion plate is disposed above the rising area of the optical plate. Therefore, an even radiating surface caused by a diffusion of the light sources from the diffusion plate could be preferably obtained even if no light guiding board is applied. | 2011-11-03 |
20110267840 | DISPLAY, BEZEL AND MANUFACTURING METHOD OF BEZEL - A display suitable for a portable electronic device is provided. The display includes a back cover, a bezel and a display panel. The bezel includes a frame and an electroluminescent light (EL) source layer. The frame is assembled to the back cover and has an opening. The electroluminescent light source layer is attached to the frame, wherein the electroluminescent light source layer and the frame are formed by an in-mold forming process and then integrated with the back cover. The display panel is assembled between the back cover and the frame and exposed by the opening | 2011-11-03 |
20110267841 | DISPLAY APPARATUS - Disclosed is a display apparatus. The display apparatus includes a light guide plate, a light source section, a light guide member, and a display panel. The light guide plate has a light incident surface and a light exit surface connected to the light incident surface. The light source section faces the light incident surface and has a plurality of light sources to output the light. The light guide member has a plate-like shape with first and second surfaces facing each other, in which the first surface contacts the light source section, and the second surface contacts the light incident surface, and guides light to the light guide plate. The display panel receives light output through the light exit surface to display an image. | 2011-11-03 |
20110267842 | SYNCHRONOUS DRIVE CIRCUIT FOR VARIABLE FREQUENCY RESONANT CONVERTERS - A DC to DC converter for controlling the on time and off time of a pair of synchronous switches, which reside in the position of output rectifiers in a half bridge transformer type circuit is provided. The circuit is actually two identical circuits, one for each half of the transformer output. The circuits consist of a voltage reference, a dual comparator, a bias switch, and drive buffer as well as biasing means for proper set up of the various parameters. | 2011-11-03 |
20110267843 | METHOD AND APPARATUS TO LIMIT OUTPUT POWER IN A SWITCHING POWER SUPPLY - An example integrated circuit controller for a power supply includes a modulator, a drive signal generator, a comparator, and a variable current limit generator. The modulator generates an enable signal having logic states responsive to a feedback signal. The drive signal generator either enables or skips enabling a switch of the power supply during a switching period in response to the logic state of the enable signal. The comparator asserts an over current signal to disable the switch if current flowing through the switch exceeds a variable current limit. The variable current limit generator sets the variable current limit to a first current limit in response to one logic state of the enable signal during a switching period and sets the variable current limit to a second current limit if the enable signal transitions logic states and the over current signal is asserted during the switching period. | 2011-11-03 |
20110267844 | Controller for a Resonant Switched-Mode Power Converter - An embodiment of the invention relates to an LLC power converter including a controller configured to regulate an output characteristic of the power converter by controlling a power converter switching frequency. In a first mode of operation, the controller turns off a secondary-side power switch earlier than a turn-off time of a primary-side power switch by a time difference that is controlled by a resistor coupled to an external circuit node. In a second mode of operation, the controller turns on a secondary-side power switch at substantially the same time as the primary-side power switch, and turns off the secondary-side power switch after a maximum on time that is a nonlinear function of a load current of the power converter. The nonlinear function is a substantially constant function of the load current for a value of the load current higher than a threshold value. | 2011-11-03 |
20110267845 | PARALLEL-CONNECTED RESONANT CONVERTER CIRCUIT AND CONTROLLING METHOD THEREOF - The configurations of a parallel-connected resonant converter circuit and a controlling method thereof are provided in the present invention. The proposed circuit includes a plurality of resonant converters, each of which has two input terminals and two output terminals, wherein all the two input terminals of the plurality of resonant converters are electrically series-connected, and all the two output terminals of the plurality of resonant converters are electrically parallel-connected. | 2011-11-03 |
20110267846 | APPARATUS AND METHOD FOR SENSING OF ISOLATED OUTPUT - A controller for use in a power converter providing sensing of an isolated output is disclosed. An example controller includes a current controller to be coupled to an energy transfer element and an input of the power converter. A control circuit is included that generates a mode select signal coupled to be received by the current controller. A first, second or third current is enabled in the current controller in response to a selection of a first, second or third mode of operation, respectively, of the current controller by the control circuit. The first current is substantially zero, the second current is greater than the third current and the third current is greater than the first current. A first feedback circuit is coupled to the control circuit and is coupled to generate a first feedback signal representative of an output of the power converter during the first mode of operation after a period of operation of the second mode of operation of the current controller. A second feedback circuit is coupled to the control circuit and is coupled to generate a second feedback signal representative of the output of the power converter during the first mode of operation after a period of operation of the third mode of operation of the current controller. The control circuit is coupled to control selections of the first, second or third modes of operation in response to the first and second feedback signals to control a transfer of energy from the input of the power converter to the output of the power converter. | 2011-11-03 |
20110267847 | APPARATUS AND METHOD FOR DETECTING A CHANGE IN OUTPUT VOLTAGE OF AN ISOLATED POWER CONVERTER - A controller for use in a power converter to detect changes in output voltage. An example controller includes a drive circuit to generate a switching signal. The switching signal is coupled to be received by a power switch to be coupled to an energy transfer element and an input of the power converter to control a transfer of energy from the input of the power converter to an output of the power converter. An output voltage sensor is coupled to the drive circuit and coupled to receive a feedback signal representative of the output of the power converter. The output voltage sensor includes first and second pulse sampler circuits. The first pulse sampler circuit is coupled to capture a first peak voltage representative of a second peak of a ringing voltage of the feedback signal at a first time in the feedback signal. The second pulse sampler circuit is coupled to capture a second peak voltage representative of the second peak of the ringing voltage of the feedback signal at a second time in the feedback signal. The output voltage sensor is coupled to output a change signal to the drive circuit in response to the first and second peak voltages. | 2011-11-03 |
20110267848 | POWER CONVERTER - Reduction of power loss and operation in a two-phase mode are made possible. | 2011-11-03 |
20110267849 | FLYBACK POWER SUPPLY WITH FORCED PRIMARY REGULATION - A controller that forces primary regulation is disclosed. An example controller includes a switched element to be coupled to a second winding of an energy transfer element of a power supply. A secondary control circuit is coupled to the switched element. The secondary control circuit is to be coupled across an output of the second winding to switch the switched element in response to a difference between an actual output value at the output of the second winding and a desired output value to force a current in a third winding of the energy transfer element that is representative of the difference between the actual output value at the output of the second winding and the desired output value. A primary switch is to be coupled to a first winding of the energy transfer element. A primary control circuit is coupled to the primary switch. The primary control circuit is to be coupled to receive the current forced in the third winding of the energy transfer element in response to the secondary control circuit. The primary control circuit is coupled to switch the primary switch to regulate an output of the power supply coupled to the output of the second winding in response to the forced current. | 2011-11-03 |
20110267850 | Method and Apparatus of Operating a Primary-Side-Regulation Power Converter at Both Continuous Current Mode and Discontinuous Current Mode - A method and an apparatus of operating a primary-side-regulation power converter at both continuous current mode and discontinuous current mode are provided. The apparatus includes a switching circuit, a signal generator, a correlation circuit, and a feedback modulator. The signal generator generates a half signal and a second sampling pulse in response to a switching signal. The correlation circuit receives the half signal, the second sampling pulse and a switching-current signal for generating a modulating current. The feedback modulator modulates a feedback signal in response to the modulating current, a detection signal and the switching signal. The detection signal obtained from a transformer is correlated to an output voltage of the primary-side-regulation power converter. An on-period of the half signal is half of an on-period of the switching signal. The switching-current signal is sampled at a falling-edge of the half signal. | 2011-11-03 |
20110267851 | CONVERTER CIRCUIT WITH ADJUSTABLE DC BUS VOLTAGE - A method for controlling voltage of a DC bus in a converter circuit is provided. The method includes monitoring a duty cycle of a switch that connects a resistive circuit across the DC bus, the switch being closed when the DC bus voltage reaches an upper voltage value and opened when the DC bus voltage reaches a lower voltage value and altering the lower voltage value based upon the duty cycle of the switch. | 2011-11-03 |
20110267852 | FAULT PROTECTION IN VOLTAGE SOURCE CONVERTERS WITH REDUNDANT SWITCHING CELLS VIA MECHANICAL SWITCHES BEING CLOSED PYROTECHNICALLY - A Voltage Source Converter has a series connection of switching assemblies, in which each switching assembly has an electrically conducting plate member carrying a plurality of semiconductor chips each having at least a semiconductor device of turn-off and a free-wheeling diode connected in parallel therewith. Said chips are connected in parallel with each other by each being connected by at least one individual conductor member to a said plate member of an adjacent switching assembly of said series connection. Each switching assembly has a mechanical switch configured to be open under normal operation of the switching assembly and configured to enable connection of said plate member of the switching assembly to the plate member of an adjacent switching assembly for bypassing said semiconductor chips of the switching assembly to which the mechanical switch belongs in the case of occurrence of a short circuit current through a semiconductor chip of the switching assembly. | 2011-11-03 |
20110267853 | SYSTEM AND METHOD PROVIDING PROTECTION IN THE EVENT OF CURRENT SENSING FAILURE FOR POWER CONVERTER - System and method for protecting a power converter. The system includes a first comparator configured to receive a first threshold signal and a first signal and to generate a first comparison signal. The first signal is associated with an input current for a power converter. Additionally, the system includes a second comparator configured to receive a second threshold signal and the first signal and to generate a second comparison signal. The second threshold signal is different from the first threshold signal in magnitude. Moreover, the system includes a first detection component configured to receive at least the second comparison signal, detect the second comparison signal only if one or more predetermined conditions are satisfied, and generate a first detection signal based on at least information associated with the detected second comparison signal. | 2011-11-03 |
20110267854 | POWER CONVERTER WITH DUAL RING NETWORK CONTROL - A method for providing electric power to a power system includes receiving, at a slave node of a power converter having a plurality of slave nodes, a first synchronization signal via a first communication channel, the first synchronization signal purporting to represent a master timing characteristic of a master control node of the converter; receiving, at the slave node of the converter, a second synchronization signal via a second communication channel, the second synchronization signal purporting to represent a master timing characteristic of the master control node of the converter; synchronizing an internal timing characteristic of the slave control node with the master timing characteristic of the master control node using the first synchronization signal; determining that the first synchronization signal is invalid; and synchronizing an internal timing characteristic of the slave control node with the master timing characteristic of the master control node using the second synchronization signal. | 2011-11-03 |
20110267855 | MODULAR PHOTOVOLTAIC POWER SUPPLY ASSEMBLY - An apparatus, device, and system for generating an amount of output power in response to a direct current (DC) power input includes a configurable power supply, which may be electrically coupled to the DC power input. The configurable power supply is selectively configurable between multiple circuit topologies to generate various DC power outputs and/or and AC power output. The system may also include one or more DC power electronic accessories, such as DC-to-DC power converters, and/or one or more AC power electronic accessories such as DC-to-AC power converters. The power electronic accessories are couplable to the configurable power supply to receive the corresponding DC or AC power output of the configurable power supply. | 2011-11-03 |
20110267856 | PFC WITH HIGH EFFICIENCY AT LOW LOAD - A Power Factor Corrector (PFC), typically used as the first stage of switched mode power supplies, particularly suited for Universal Mains inputs, is disclosed, along with methods for controlling a switched mode power supply having power factor correction. In order to increase efficiency, particularly under low load conditions, without undue degradation of the Power Factor, the switching of the PFC circuit is confined to one or more operating windows within each half-cycle. In embodiments, the operating window comprises a small time window centred around the peak of the mains voltage. The higher the power level, the wider the switching window. | 2011-11-03 |
20110267857 | Method and apparatus for distributed power generation - A method and apparatus for generating AC power. In one embodiment, the apparatus comprises a DC/AC inversion stage capable of generating at least one of a single-phase output power, a two-phase output power, or a three-phase output power; and a conversion control module, coupled to the DC/AC inversion stage, for driving the DC/AC inversion stage to selectively generate the single-phase output power, the two-phase output power, or the three-phase output power based on an input power to the DC/AC inversion stage. | 2011-11-03 |
20110267858 | CONFIGURABLE POWER SUPPLY ASSEMBLY - An apparatus, device, and system for generating an amount of output power in response to a direct current (DC) power input includes a configurable power supply, which may be electrically coupled to the DC power input. The configurable power supply is selectively configurable between multiple circuit topologies to generate various DC power outputs and/or and AC power output. The system may also include one or more DC power electronic accessories, such as DC-to-DC power converters, and/or one or more AC power electronic accessories such as DC-to-AC power converters. The power electronic accessories are couplable to the configurable power supply to receive the corresponding DC or AC power output of the configurable power supply. | 2011-11-03 |
20110267859 | METHOD AND DEVICE FOR CONTROLLING A CONFIGURABLE POWER SUPPLY - An apparatus, device, and system for generating an amount of output power in response to a direct current (DC) power input includes a configurable power supply, which may be electrically coupled to the DC power input. The configurable power supply is selectively configurable between multiple circuit topologies to generate various DC power outputs and/or and AC power output. The system may also include one or more DC power electronic accessories, such as DC-to-DC power converters, and/or one or more AC power electronic accessories such as DC-to-AC power converters. The power electronic accessories are couplable to the configurable power supply to receive the corresponding DC or AC power output of the configurable power supply. | 2011-11-03 |
20110267860 | POWER CONTROL SYSTEM - A power control system includes a rectifier circuit, a buck circuit, a voltage divider circuit, a control circuit, and a switch circuit. A first terminal of the rectifier circuit is connected to an alternating current (AC) power supply. A second terminal of the rectifier circuit is connected to a first terminal of the buck circuit and a first terminal of the voltage divider circuit. A first terminal of the control circuit is connected to a second terminal of the buck circuit. A second terminal of the control circuit is connected to a second terminal of the voltage divider circuit. A third terminal of the control circuit is connected to the switch circuit. The switch circuit is connected to the AC power supply and an electronic device. | 2011-11-03 |
20110267861 | Signal Transmission Arrangement with a Transformer - A signal transmission arrangement includes a transformer with a first and a second winding. A damping circuit has an input terminal for receiving an input signal. The damping circuit is coupled to the first winding and is configured to have an electrical resistance that is dependent on the input signal. An oscillator circuit includes the second winding and is configured to provide an oscillating signal. An evaluation circuit is configured to receive the oscillating signal and to provide an output signal that is dependent on an amplitude of the oscillating signal. | 2011-11-03 |
20110267862 | SYSTEM AND METHOD FOR PROTECTION OF A MULTILEVEL CONVERTER - A three level neutral point clamped (NPC) converter includes a plurality of phase legs each having at least two inner switching devices, at least two outer switching devices, at least two clamping diodes, and a protection circuit. An inner component failure sensing circuit is employed in the protection circuit to detect a failure condition in any of the inner switching devices or clamping diodes. The protection circuit further includes a gating signal generation circuit configured to generate a turn ON signal for a respective outer switching device that is adjacent to the failed inner switching device or the clamping diode. | 2011-11-03 |
20110267863 | TRANSFORMERLESS INVERTER COMPRISING A DC/DC CONVERTER - A transformerless inverter that serves to feed electricity from a DC current source into an AC power grid, has an inverter bridge and a DC/DC converter connected upstream of the inverter bridge. The DC/DC converter converts an input DC voltage that is present between two input lines of the inverter into a DC link voltage present between two input lines of the inverter bridge. The inverter bridge converts the DC link voltage present at the input lines thereof into an output AC voltage. The DC/DC converter includes at least one resonant circuit that has a resonance inductance and a resonance capacitance and is connected on its input side via at least two clocked switches to one of the two input lines of the inverter or an intermediate potential line carrying a potential in between. The input lines of the inverter and the input lines of the inverter bridge are galvanically isolated from one another by a capacitive method. The resonant circuit may be undivided and is connected alternately to the two input lines of the inverter bridge. | 2011-11-03 |
20110267864 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a first memory chip, a second memory chip, and a control chip. The first chip includes a first inductor configured to transmit/receive a signal, and a memory cell. The second chip is disposed on the first chip and includes a second inductor configured to transmit/receive a signal, and a memory cell. The control chip includes a control circuit configured to control the first and second chips, and a third inductor configured to transmit/receive a signal to/from the first and second inductors. The outer peripheries of the first and second inductors are included in a closed space produced by extending the outer periphery of the third inductor in a direction perpendicular to a plane that includes the third inductor. The inductance of the third inductor is greater than at least one of the inductances of the first and second inductors. | 2011-11-03 |
20110267865 | CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS - Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. | 2011-11-03 |
20110267866 | EXTENSIBLE THREE DIMENSIONAL CIRCUIT HAVING PARALLEL ARRAY CHANNELS - An extensible three dimensional circuit having parallel array channels includes an access layer and crossbar array layers overlying the access layer and being electrically connected to the access layer. The crossbar array layers include parallel channels, the parallel channels being formed from two classes of vias, the first class being pillar vias connected to relatively short stub lines, and the second class being traveling-line vias connected to long lines that travel away from the via; pillar vias and traveling-line vias being configured to connect to crossing lines such that each crossing point between the lines is uniquely addressed by one pillar via and one traveling-line via. Programmable crosspoint devices are disposed between the crossing lines. | 2011-11-03 |
20110267867 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings. | 2011-11-03 |
20110267868 | SHIFT REGISTER MEMORY DEVICE, SHIFT REGISTER, AND DATA STORAGE METHOD - According to one embodiment, a shift register memory device includes a shift register, a program/read element, and a rotating force application unit. The shift register includes a plurality of rotors arranged along one direction and provided with a uniaxial anisotropy. Each of the plurality of rotors has a characteristic direction rotatable around a rotational axis extending in the one direction. The program/read element is configured to program data to the shift register by causing the characteristic direction of one of the rotors to match one selected from two directions conforming to the uniaxial anisotropy and configured to read the data by detecting the characteristic direction. The rotating force application unit is configured to apply a rotating force to the shift register to urge the characteristic direction to rotate. The plurality of rotors are organized into a plurality of pairs of every two mutually adjacent rotors. A first force acts to urge the characteristic directions to be opposingly parallel for two of the rotors belonging to the same pair. A second force acts to urge the characteristic directions to be opposingly parallel for two mutually adjacent rotors belonging to mutually adjacent pairs. | 2011-11-03 |
20110267869 | CIRCUIT FOR VERIFYING THE WRITE ENABLE OF A ONE TIME PROGRAMMABLE MEMORY - A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory. | 2011-11-03 |
20110267870 | Decoders Using Memristive Switches - A decoding structure employs a main terminal ( | 2011-11-03 |
20110267871 | Contemporaneous Margin Verification And Memory Access For Memory Cells In Cross-Point Memory Arrays - Circuitry for restoring data values in re-writable non-volatile memory is disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory elements. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory elements substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory elements may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state). | 2011-11-03 |
20110267872 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path of the memory cell as to serve for stabilizing the state change of the memory cell passively. | 2011-11-03 |
20110267873 | NON-VOLATILE MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed. | 2011-11-03 |
20110267874 | Invalid Write Prevention for STT-MRAM Array - In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines. | 2011-11-03 |
20110267875 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor memory device includes a memory cell array configured to include a plurality of memory cells, a plurality of bit lines respectively coupled to the plurality of memory cells, a first power-supply voltage supplying circuit configured to provide a first power-supply voltage to the memory cell array through the plurality of bit lines, a second power-supply voltage supplying circuit configured to provide a second power-supply voltage to the memory cell array through the plurality of bit lines, a first address selection circuit configured to couple a bit line selected by a first selection address to the first power-supply voltage supplying circuit, and a second address selection circuit configured to couple a bit line selected by a second selection address to the second power-supply voltage supplying circuit. | 2011-11-03 |
20110267876 | NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT - A nonvolatile memory device that employs a variable resistive element includes: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at one side of the memory cell array and performs a first operation on the memory cells; a second circuit block that is disposed at the other side of the memory cell array and performs a second operation on the memory cells, wherein the second operation is different from the first operation; and a redundancy block that is disposed closer to the second circuit block than the first circuit block, and which compares a repair address of a repaired memory cell among the plurality of memory cells with an input address to then generate a redundancy control signal, and to supply the redundancy control signal to the first circuit block and the second circuit block. | 2011-11-03 |
20110267877 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second phase-change memory elements (GST | 2011-11-03 |
20110267878 | Josephson Magnetic Random Access Memory System and Method - One aspect of the present invention includes a Josephson magnetic random access memory (JMRAM) system. The system includes an array of memory cells arranged in rows and columns. Each of the memory cells includes an HMJJD that is configured to store a digital state corresponding to one of a binary logic-1 state and a binary logic-0 state in response to a word-write current that is provided on a word-write line and a bit-write current that is provided on a bit-write line. The HMJJD is also configured to output the respective digital state in response to a word-read current that is provided on a word-read line and a bit-read current that is provided on a bit-read line. | 2011-11-03 |
20110267879 | MAGNETIC MEMORY ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - A magnetic memory cell includes: a magnetization recording layer; and a magnetic tunneling junction section. The magnetization recording layer includes a ferromagnetic layer with perpendicular magnetic anisotropy. The magnetic tunneling junction section is used for reading information in the magnetization recording layer. The magnetization recording layer includes two domain wall moving areas. | 2011-11-03 |
20110267880 | MEMORY CIRCUITS HAVING A DIODE-CONNECTED TRANSISTOR WITH BACK-BIASED CONTROL - A memory circuit includes at least one memory array. At least one sleep transistor is electrically coupled between the at least one memory array and a first power line for providing a first power voltage. At least one diode-connected transistor is electrically coupled between the at least one memory array and the first power line. A back-bias circuit is electrically coupled with a bulk of the at least one diode-connected transistor. | 2011-11-03 |
20110267881 | MEMORY ARRAY - A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read. | 2011-11-03 |
20110267882 | MEMORY ARRAY WITH INVERTED DATA-LINES PAIRS - At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells. | 2011-11-03 |
20110267883 | DRAM-LIKE NVM MEMORY ARRAY AND SENSE AMPLIFIER DESIGN FOR HIGH TEMPERATURE AND HIGH ENDURANCE OPERATION - A DRAM-like non-volatile memory array includes a cell array of non-volatile cell units with a DRAM-like cross-coupled latch-type sense amplifier. Each non-volatile cell unit has two non-volatile cell devices with respective bit lines and source lines running in parallel and laid out perpendicular to the word line associated with the non-volatile cell unit. The two non-volatile cell devices are programmed with erased and programmed threshold voltages as a pair for storing a single bit of binary data. The two bit lines of each non-volatile cell unit are coupled through a Y-decoder and a latch device to the two respective inputs of the latch-type sense amplifier which provides a large sensing margin for the cell array to operate properly even with a narrowed threshold voltage gap. Each non-volatile cell device may be a 2 T FLOTOX-based EEPROM cell, a 2 T flash cell, 11 T flash cell or a 1.5 T split-gate flash cell. | 2011-11-03 |
20110267884 | NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM - According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors. | 2011-11-03 |
20110267885 | NON-VOLATILE MEMORY AND METHOD WITH EVEN/ODD COMBINED BLOCK DECODING - A nonvolatile memory array is organized into a plurality of interleaving even and odd blocks. When a block is selected for operation, a set of word line voltages are delivered to the block of word lines by space-efficient decoding circuits and scheme. The plurality of blocks is organized into an array of pairs of adjacent odd and even blocks. A first voltage bus allows all even blocks access to the set of word line voltages. A second voltage bus allows all odd blocks access to the set of word line voltages. A decoder for selection is provided for each pair of adjacent even and odd blocks. Selecting a block is effected by selecting the pair of adjacent even and odd blocks containing the selected block, and supplying the set of word line voltages only to the selected block, which is one of the even or odd block in the selected pair. | 2011-11-03 |
20110267886 | Nonvolatile Semiconductor Memory Device - A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed. | 2011-11-03 |
20110267887 | Reducing Energy Consumption When Applying Body Bias To Substrate Having Sets Of Nand Strings - Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage. | 2011-11-03 |
20110267888 | Controlling Select Gate Voltage During Erase To Improve Endurance In Non-Volatile Memory - A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage. | 2011-11-03 |
20110267889 | A HIGH SECOND BIT OPERATION WINDOW METHOD FOR VIRTUAL GROUND ARRAY WITH TWO-BIT MEMORY CELLS - A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable of transmitting positive voltage to reach the source/drain regions of the memory cells of the array. A method that includes the hole injection erasure of the memory cells of the array that lowers the voltage threshold of the memory cells to a value lower than the initial voltage threshold of the cells is disclosed. The hole injection induced lower voltage threshold reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. The programming and read steps reduce leakage current of the memory cells in the array. | 2011-11-03 |
20110267890 | SEMICONDUCTOR MEMORY DEVICE INCLUDING STACKED GATE HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND METHOD OF WRITING DATA TO SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold. | 2011-11-03 |
20110267891 | DRIVING CIRCUIT FOR MEMORY DEVICE - An electrically programmable non-volatile memory device is proposed. The memory device includes a plurality of memory cells and a driver circuit for driving the memory cells; the driver circuit includes programming means for providing a first programming voltage and a second programming voltage to a set of selected memory cells for programming the selected memory cells; the first programming voltage requires a first transient period for reaching a first target value thereof. In the solution according to an embodiment of the present invention, the programming means includes means for maintaining the second programming voltage substantially equal to the first programming voltage during a second transient period being required by the second programming voltage to reach a second target value thereof. | 2011-11-03 |
20110267892 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory string coupled to a bit line, a page buffer configured to sense a sensing current of the bit line in an erase verification operation or a program verification operation, and a sensing control circuit configured to differently set a level of the sensing current in the erase verification operation and the program verification operation in order to sense the threshold voltage level of a selected memory cell of the memory string. | 2011-11-03 |
20110267893 | NON-VOLATILE SEMICONDUCTOR MEMORY AND MEMORY SYSTEM - A non-volatile semiconductor memory determines that a given memory cell in an array is at a predetermined threshold voltage in a determination circuit by comparing a current of the memory cell with a reference current in a sense amplifier circuit. A reference current generation circuit includes a current variable device adjusting the reference current. A current adjustment amount calculator receives address information of the memory cell of which threshold voltage is determined and calculates a current adjustment amount corresponding to the address information. The current variable device adjusts the reference current based on the calculated current adjustment amount. Therefore, even when characteristics of interconnects coupled to the sense amplifier circuit, the target memory cell, and the sense amplifier vary, an offset amount between an actual threshold and an apparent threshold is eliminated to reduce electric stress applied to the memory cell in a rewrite operation. | 2011-11-03 |
20110267894 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a voltage transfer unit configured to transfer a first word line control voltage among a plurality of word line control voltages to an assigned word line in a first operational period, and to transfer a second word line control voltage among the plurality of word line control voltages to the assigned word line in a second operational period; and a word line discharge unit configured to discharge the word line to a voltage level that is higher than a ground voltage and lower than the first and second word line control voltages in a discharge period between the first operational period and the second operational period. | 2011-11-03 |
20110267895 | METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE - A method of operating a semiconductor memory device includes selecting one of a plurality of word lines, applying a program voltage, gradually dropping from a third level to a first level, to the selected word line, and discharging bit lines whenever a level of the program voltage is changed. | 2011-11-03 |
20110267896 | Non-Volatile Semiconductor Memory with Page Erase - In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages. | 2011-11-03 |
20110267897 | Non-Volatile Memory Cells Formed in Back-End-of-Line Processes - A method for forming and operating an integrated circuit, including providing a substrate; forming a bottom electrode over the substrate, wherein the bottom electrode is in or over a lowest metallization layer over the substrate; forming a blocking layer over the substrate; forming a charge-trapping layer over the blocking layer; forming an insulation layer over the charge-trapping layer; forming a control gate over the insulation layer; forming a tunneling layer over the control gate; and forming a top electrode over the tunneling layer. | 2011-11-03 |
20110267898 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a clock transmission unit configured to selectively output a data strobe clock signal or a phase correction clock signal based on an operation mode, and a data latch unit configured to latch a plurality of data signals under a control of a clock signal which is outputted from the clock transmission unit. | 2011-11-03 |
20110267899 | NON-VOLATILE MEMORY DEVICE AND NON-VOLATILE MEMORY SYSTEM HAVING THE SAME - A non-volatile memory device may include a memory cell array, a page buffer, a column decoder, a column selection circuit and a repair circuit. The memory cell array includes normal memory cells and redundancy memory cells. In one example, the page buffer may load normal data and redundancy data from the memory cell array. The column decoder may generate a normal column selection signal and a redundancy column selection signal in response to a column address. The column selection circuit may select the normal data and redundancy data in response to the normal column selection signal and redundancy column selection signal. The repair circuit may then output one of the normal data and redundancy data. | 2011-11-03 |
20110267900 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a pad, an impedance calibration circuit configured to provide a first code value corresponding to an impedance value coupled to the pad, a PVT sensing control circuit configured to provide a second code value corresponding to a PVT variation, and an output driver configured to receive data and to pull up or pull down the pad in response to the first code value and second code value. | 2011-11-03 |
20110267901 | SWITCHED CAPACITOR BASED NEGATIVE BITLINE VOLTAGE GENERATION SCHEME - A memory device includes an array of memory cells, the memory device including a bitline biasing circuit for biasing a bitline during a write operation. The bitline biasing circuit operating to provide a negative biasing voltage to the bitline. The magnitude of the negative biasing voltage is inversely proportional to a memory cell supply voltage level provided at a memory cell supply voltage node. | 2011-11-03 |
20110267902 | Semiconductor device - A semiconductor device includes a drive circuit that outputs a drive signal to drive an external device; a voltage output circuit that outputs a first voltage and a second voltage that is larger than the first voltage; a selector that, when supplying a power supply voltage to the drive circuit, selects the first voltage and, when supplying a power supply voltage to an internal device, selects the second voltage; and a step-up circuit that, when the first voltage selected by the selector is input, boosts the first voltage to a third voltage and outputs the third voltage as the power supply voltage to the drive circuit and, when the second voltage selected by the selector is inputted, boosts the second voltage to a fourth voltage and outputs the fourth voltage as the power supply voltage to the internal device. | 2011-11-03 |
20110267903 | SEMICONDUCTOR MEMORY DEVICE HAVING DRAM CELL MODE AND NON-VOLATILE MEMORY CELL MODE AND OPERATION METHOD THEREOF - A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected to drains of the transistors, source lines at a second side of the gate electrodes, different from the first side, and connected to sources of the transistors on the semiconductor substrate, and charge storage regions between the gate electrodes and the floating bodies. | 2011-11-03 |
20110267904 | HIGH SPEED INTERFACE FOR MULTI-LEVEL MEMORY - A memory chip including a plurality of storage elements, a receiver and a program module. Each of the storage elements has a measurable parameter. The receiver receives N target values from a memory controller, where N is an integer greater than zero. The programming module adjusts corresponding measurable parameters of N storage elements of the plurality of storage elements to the N target values. | 2011-11-03 |
20110267905 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device, including a temperature detector configured to output a temperature detection signal in response to a temperature detected in a core region which includes a plurality of memory cells, and a programming voltage generator configured to generate a programming voltage in response to the temperature detection signal and output a generated programming voltage to the core region. | 2011-11-03 |
20110267906 | Measuring SDRAM Control Signal Timing - Measuring control signal timing for synchronous dynamic random access memory (‘SDRAM’), including combining into a trigger signal for an oscilloscope display control signals of an SDRAM under test, the control signals derived only from a single type of memory operations; and driving, continually during both READ and WRITE operations to and from the SDRAM under test, the oscilloscope display with a memory bus data signal (‘DQ’) and a memory bus clock signal (‘DQS’) from the SDRAM under test. | 2011-11-03 |
20110267907 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first data input/output unit configured to receive a normal training data, whose data window is scanned based on an edge of a source clock, in response to a training input command, and output a data in a state where an edge of the data window is synchronized with the edge of the source clock in response to a training output command, and a second data input/output unit configured to receive a recovery information training data, whose data window is scanned based on the edge of the source clock, in response to the training input command, and output a data in a state where an edge of a data window is synchronized with the edge of the source clock in response to the training output command. | 2011-11-03 |
20110267908 | REPAIR CIRCUIT AND REPAIR METHOD OF SEMICONDUCTOR MEMORY APPARATUS - A repair circuit of a semiconductor memory apparatus includes a repair address detection circuit that determines the occurrence of a failure in a memory block based on a plurality of test data signals outputted from the memory block, and stores an address corresponding to the memory block determined to have failed as a repair address, and an anti-fuse circuit that receives the repair address from the repair address detection circuit and electrically programs the repair address to store a programmed address. | 2011-11-03 |
20110267909 | FUSE CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - The fuse circuit includes a first program unit, a second program unit and a sensing circuit. The first and second program units are programmed simultaneously. The first program unit is programmed in a program mode in response to a fuse program signal and outputs a first signal in a sensing mode, such that the first signal increases when the first program unit is programmed. The second program unit is programmed in the program mode in response to the program signal and outputs a second signal in the sensing mode, such that the second signal decreases when the second program unit is programmed. The sensing circuit generates a sensing output signal in response to the first and second signals, such that the sensing output signal indicates whether or not the program units are programmed. | 2011-11-03 |
20110267910 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING COLUMN REDUNDANCY FUSE BLOCK - A semiconductor integrated circuit includes a column redundancy fuse block having a fuse set array having a plurality of fuse sets including a plurality of column address fuses, and a fuse blowing information block configured to output a fuse blowing determination signal of a corresponding column based on a cutting state of the column address fuses, wherein the column redundancy fuse is disposed in the edge area, wherein the fuse blowing determination signal is inputted to a column control block through upper portion of a memory cell array of a corresponding bank. | 2011-11-03 |
20110267911 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a line calibration unit configured to selectively output one signal from the group of code signals for calibrating termination resistance values and test mode signals for testing a chip of the semiconductor memory apparatus to a common global line based on the level of a line calibration signal. | 2011-11-03 |
20110267912 | DIGIT LINE EQUILIBRATION USING ACCESS DEVICES AT THE EDGE OF SUB ARRAYS - A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second digit line to the terminated end of the first digit line. The memory array is configured with the first and second digit lines arranged directly adjacent to each other. | 2011-11-03 |
20110267913 | PROGRAM METHOD OF SEMICONDUCTOR MEMORY DEVICE - A program method of a semiconductor memory device may include precharging first bit lines, coupled to first strings, to increase a potential level of the first strings to a first potential level; programming memory cells of a selected word line, wherein the memory cells are coupled to second bit lines; pre-discharging the first bit lines to decrease a potential level of the word lines to a second potential level, wherein the second potential level is lower than the first potential level; and discharging the first bit lines and the word lines to a ground voltage after the pre-discharging. | 2011-11-03 |
20110267914 | SEMICONDUCTOR MEMORY DEVICE - Characteristics of both a memory cell and a peripheral circuit are degraded due to random variations, and a defective characteristic occurs in a combination of components having a substantially worst characteristic at a macro level. To solve this problem, a selector is provided between the memory cell and the peripheral circuit so that a positive phase and a negative phase of bit lines are switched at a portion where the defective characteristic occurs. Alternatively, the combination of a bit line and a sense amplifier is switched between adjacent data input/output sections, for example. In other words, the defective characteristic is repaired or corrected by canceling the combination of worst components. | 2011-11-03 |
20110267915 | ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE - Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer. | 2011-11-03 |
20110267916 | VDD PRE-SET OF DIRECT SENSE DRAM - A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for signal sensing during a second active period. The architecture includes a sense head having of a pair of cross coupled gated inverters. Each of the gated inverters is responsive to a first and second gate control signal which can independently gate a power supply to the inverter circuit within each gated inverter. During the second active period, a first gated inverter senses the data state on the first bit-line, and a second gated inverter performs a preset and write-back function on the first bit-line. | 2011-11-03 |
20110267917 | ROW MASK ADDRESSING - Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed. | 2011-11-03 |
20110267918 | STIR SYSTEM AND A METHOD FOR PROVIDING A CHEMICAL REACTION - A stir system for stirring a liquid in a vial includes a top for at least partially closing the vial and a stirrer rotatable mounted in the top. The stirrer extends from the top into the vial and the stirrer is being connected with a magnet, which is rotatable during use by a rotating magnet field so as to rotate the stirrer in the vial. The system further includes a holder for holding the vial and a cover for covering the vial in the holder. | 2011-11-03 |
20110267919 | INTERNAL BATCH MIXER - An internal batch mixer is provided with: a casing within which a material is mixed; a door which opens and closes a material discharge opening of the casing by being rotated about the axis thereof and closes the material discharge opening when in a closed state; and a latch mechanism which, when the material is mixed in the casing, holds the door in a latched state, the latched state being a state in which the material discharge opening is being closed by the door and cannot be opened, and which, when the material having been mixed in the casing is discharged from the inside of the casing, releases the door from the latched state. The latch mechanism is provided with a linear actuator which has a movable section capable of moving linearly and moves the movable section to the door side to supply power to the latch member, the power causing the latch member to move to the door side, and a linear sensor for measuring the distance of linear movement of the movable section caused by the linear actuator. Information relating to the displacement of the latch member is displayed on a display device on the basis of the distance of linear movement of the movable section measured by the linear sensor. | 2011-11-03 |
20110267920 | Method and Apparatus for Controlling Residence Time Distribution in Continuous Stirred-Tank Reactors - The present invention includes an apparatus and method for narrowing the residence time distribution of a continuous stirred-tank reactor, or CSTR, which includes the optional procedures of: decreasing the vertical cross-sectional area of the reactor's agitator blades; decreasing the RPM of the agitator blades; and increasing the reactor's L/D ratio. The CSTR can be used in the production of monovinylidene aromatic polymers, such as high impact polystyrene. | 2011-11-03 |
20110267921 | MULTICOMPONENT SEISMIC INVERSION OF VSP DATA - A method for seismic inversion of vertical seismic profile (VSP) data in an oilfield. The method includes obtaining an initial velocity model of a subterranean formation including acoustic velocities of wave propagation in proximity to the wellbore, determining an acquisition geometry for obtaining the VSP data including receiver locations within the wellbore and a source location, performing a seismic survey to obtain the VSP data based on the acquisition geometry, analyzing arrival signals of the VSP data to generate transit time data for wave propagation from the source location to the receiver locations, modifying the initial velocity model to generate an updated velocity model by performing a tomographic inversion of the transit time data, generating an elastic model of the subterranean formation by performing the seismic inversion of the VSP data using the updated velocity model, and adjusting the operations of the oilfield based on the elastic model. | 2011-11-03 |
20110267922 | MECHANICAL TUBE WAVE SOURCES AND METHODS OF USE FOR LIQUID FILLED BOREHOLES - The current application discloses methods and systems for generating mechanical tube waves in fluid filled boreholes penetrating subterranean formations. In one embodiment, the system of the current application comprises an energy storage chamber; a fast operating valve connected to the energy storage chamber; a pipe connected to the valve and extending to the liquid-filled borehole; where said energy storage chamber contains a first pressure that is substantially different from a second pressure in the pipe so that a fast operation of the valve generates a tube wave in the pipe. | 2011-11-03 |
20110267923 | APPARATUS AND METHOD FOR SEISMIC IMAGING USING WAVEFORM INVERSION SOLVED BY CONJUGATE GRADIENT LEAST SQUARES METHOD - Provided is an apparatus for seismic imaging by using waveform inversion in the frequency domain. The seismic imaging apparatus includes: a waveform inversion unit obtaining an equation by applying a Gauss-Newton method to an objective function consisting of residuals of logarithmic wavefields in frequency-domain waveform inversion and then obtaining a parameter vector, which minimizes the objective function, by solving the equation using a conjugate gradient method; and a subsurface structure display unit generating subsurface structure information using the parameter vector obtained by the waveform inversion unit and displaying the generated subsurface structure information. | 2011-11-03 |
20110267924 | ACOUSTIC DISTANCE MEASUREMENT SYSTEM HAVING CROSS TALK IMMUNITY - In one embodiment, an acoustic distance measurement system can use a modulation pattern to modulate a carrier wave. The modulated carrier wave may be transmitted to an acoustic transducer. An echo of the transmitted signal can be detected by correlating the received signal with the modulation pattern. Subsequent to detecting sufficient correlation between the received signal and modulation pattern, a distance determination can be made to determine the distance to the object that produced the received echo. | 2011-11-03 |
20110267925 | BOTTOM SEISMIC STATION - The proposed bottom station relates to geophysical exploration, particularly to the geo-electrical seismic survey equipment. It's intended for prediction of hydrocarbons deposits and study of the deep structure of earth's crust. The station comprises a body, a load, a registration device. The station is characterized by placement of sensors in the lower part of body, in combination with the use of the load, having a cavity on the upper surface with a diameter exceeding the corresponding body's diameter. The body is releasably fastened to the load by means of Kevlar ropes. Additional accuracy of the station is achieved by the use of orthogonal three-component sensors, rather than cardan sensors, as well as by incorporating into the station's body an additional acoustic system for control of location of the station. Substitution of a hard drive by a flush memory card in the registration device increases reliability of storing and transmitting information. | 2011-11-03 |
20110267926 | DIGITAL ALARM CLOCK WITH USER-SELECTABLE ALARM SOUND SOURCE INCLUDING FROM INTERNET - A user can select an alarm sound source from a list including, e.g., radio and Internet, and at the user-defined alarm time, audio received from the source is automatically displayed on a speaker to awaken the user. | 2011-11-03 |
20110267927 | DIGITAL ALARM CLOCK WITH USER-SELECTABLE ALARM SOUND SOURCE INCLUDING FROM INTERNET - A user can select an alarm sound source from a list including, e.g., radio and Internet, and at the user-defined alarm time, audio received from the source is automatically displayed on a speaker to awaken the user. | 2011-11-03 |
20110267928 | Chronograph timepiece - Chronograph hands are made not to start driving at an inappropriate position in a case where a sleep mode is cancelled in a chronograph timepiece in which driving of each of the hands is electrically performed by motors and reset-to-zero of the chronograph hands is performed by mechanical mechanisms. An operation mode setting portion forbids a chronograph measurement operation if only a start and stop button is operated after a sleep mode is cancelled by an amount of power generated by a solar cell exceeding a predetermined amount, and, if a reset button is operated after the sleep mode is cancelled, performs a control such that the chronograph measurement operation is started by a start operation using the start and stop button. | 2011-11-03 |
20110267929 | DUAL FACED CLOCK - A clock comprising: a housing; a first face located on the housing; a front end, adjacent to the first face; a second face located on the housing and adjacent to the front end; a first time display located on the first face; a second time display located on the second face; a single control unit located in the housing, and in signal communication with the first time display and second time display; an angle α, defining the angle between the first face and the second face, and where the angle α is greater than 0° and less than 180°. | 2011-11-03 |
20110267930 | Method and Apparatus for Aligning a Laser Diode on a Slider - An apparatus includes a structure including a waveguide and a pocket adjacent to an input facet of the waveguide. A laser has an output facet and is positioned in the pocket. A stop is included one at least one of the laser and a wall of the pocket. The stop is positioned at an interface between the laser and the wall of the pocket such that the output facet of the laser and the input facet of the waveguide are separated by a gap. | 2011-11-03 |
20110267931 | CONTROLLER FOR RECOVERING DISC MANAGEMENT INFORMATION OF A RECORDING MEDIUM - A controller for recovering disc management information is provided. The controller controls a pickup head unit to search the TDMAs for readable disc management information which is included in an in-use TDMA of the TDMAs; then determines whether a piece of information associated with an inconsistency flag of the readable disc management information is reliable. When the controller detects that the piece of information is unreliable, the controller determines at least a detection condition according to the information which is included in the readable disc management information and the in-use TDMA, and controls the pickup head unit to detect the recording medium to determine an update on the piece of information associated with the inconsistency flag under at least a detection condition. The controller generates update disc management information according to the readable disc management information and the update on the piece of information associated with the inconsistency flag. | 2011-11-03 |
20110267932 | Copy Protection System for Data Carriers - A copy-protected compact disc includes, within a single session, a table of contents (TOC) and a Video CD index (VI). Each track (T) is prefaced by unrecoverable data (UD) at a track start position (ATOC) indicated by the table of contents (TOC). However, the Video CD index (VI) indicates the actual position (AP) of the tracks. DVD players use the Video CD index (VI) to locate the tracks, while the CD-ROM drives use the table of contents (TOC) and read the unrecoverable data (UD), which prevents them from reading the subsequent track (T). The unrecoverable data (UD) may be prefaced by data pointers (DP) which cause the CD-ROM drive to load a player program in response to the error condition. The player program can be used to play the tracks (T), but restricts copying. Subchannel data (P; DX) causes audio CD players to ignore the Video CD index (VI) and the unrecoverable data (UD), and to play the tracks (T) at their actual start positions (AP). | 2011-11-03 |
20110267933 | CODING FOR OPTICAL STORAGE SYSTEMS WITH MULTIPLE READER HEADS AND MULTIPLE OPTICAL DISKS - Provided are methods and systems of encoding and decoding techniques in an optical storage system having a multi-head detector. In one embodiment, source data may be encoded using error correction coding (e.g., turbo coding) techniques, and the encoded data may be interleaved and distributed to more than one detector head of the multi-head detector. Data recorded in an optical disc may be retrieved by the multi-head detector, and a read data from more than one detector head may be concurrently decoded to retrieve estimates of the original information in the source data. Further, more than one encoder/decoder may be used, and each encoder/decoder may encode or decode data from multiple data heads. Some embodiments also include replicating multiple discs. | 2011-11-03 |
20110267934 | OPTICAL PICKUP, OPTICAL INFORMATION DEVICE, COMPUTER, OPTICAL DISK PLAYER, CAR NAVIGATION SYSTEM, OPTICAL DISK RECORDER, AND OPTICAL DISK SERVER - To provide an optical pickup and an optical information device, capable of obtaining excellent signal characteristics for an optical disk on and/or from which recording and/or reproducing are performed using a laser. The optical pickup includes an optical detector, a support holder for holding the optical detector, and an optical base for fixing the support holder. The support holder has at least two notches at its both ends, the optical base has convex portions corresponding to the notches of the support holder, the optical base and the support holder are fixed by photo-curable adhesives for bonding the convex portions and the support holder to each other, and the shortest distance between the side faces of the convex portions, which do not face each other, is equal to or less than the width of the support holder in the direction of right and left ends. | 2011-11-03 |