44th week of 2017 patent applcation highlights part 55 |
Patent application number | Title | Published |
20170316944 | SHORT-CHANNEL NFET DEVICE | 2017-11-02 |
20170316945 | BOTTOM SOURCE/DRAIN SILICIDATION FOR VERTICAL FIELD-EFFECT TRANSISTOR (FET) | 2017-11-02 |
20170316946 | METHODS FOR CHEMICAL ETCHING OF SILICON | 2017-11-02 |
20170316947 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS | 2017-11-02 |
20170316948 | TRANSFORMER, PLASMA PROCESSING APPARATUS, AND PLASMA PROCESSING METHOD | 2017-11-02 |
20170316949 | METHOD OF ETCHING ATOMIC LAYER | 2017-11-02 |
20170316950 | METHOD FOR FORMING PATTERNS OF A SEMICONDUCTOR DEVICE | 2017-11-02 |
20170316951 | FABRICATION OF FINS USING VARIABLE SPACERS | 2017-11-02 |
20170316952 | TRANSITION METAL-BEARING CAPPING FILM FOR GROUP III-NITRIDE DEVICES | 2017-11-02 |
20170316953 | METHOD FOR FABRICATING METALLIC OXIDE THIN FILM TRANSISTOR | 2017-11-02 |
20170316954 | Stack Frame for Electrical Connections and the Method to Fabricate Thereof | 2017-11-02 |
20170316955 | POWER MODULE PACKAGE HAVING PATTERNED INSULATION METAL SUBSTRATE | 2017-11-02 |
20170316956 | METHOD FOR ENCAPSULATING LARGE-AREA SEMICONDUCTOR ELEMENT-MOUNTED BASE MATERIAL | 2017-11-02 |
20170316957 | STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT STRUCTURE | 2017-11-02 |
20170316958 | CHEMICAL SUPPLY UNIT AND APPARATUS FOR TREATING A SUBSTRATE | 2017-11-02 |
20170316959 | SUBSTRATE CLEANING ROLL, SUBSTRATE CLEANING APPARATUS, AND SUBSTRATE CLEANING METHOD | 2017-11-02 |
20170316960 | SUBSTRATE CLEANING APPARATUS AND SUBSTRATE CLEANING METHOD | 2017-11-02 |
20170316961 | SUBSTRATE LIQUID PROCESSING METHOD, SUBSTRATE LIQUID PROCESSING APPARATUS, AND COMPUTER-READABLE STORAGE MEDIUM THAT STORES SUBSTRATE LIQUID PROCESSING PROGRAM | 2017-11-02 |
20170316962 | SUBSTRATE STACK HOLDER, CONTAINER AND METHOD FOR PARTING A SUBSTRATE STACK | 2017-11-02 |
20170316963 | DIRECT OPTICAL HEATING OF SUBSTRATES | 2017-11-02 |
20170316964 | DOME COOLING USING COMPLIANT MATERIAL | 2017-11-02 |
20170316965 | METHOD AND DEVICE FOR COATING A PRODUCT SUBSTRATE | 2017-11-02 |
20170316966 | METHODS AND APPARATUS FOR PROCESSING ITEMS WITH VERTICALLY ORIENTED PROCESSING TOOLS IN A CLEAN SPACE | 2017-11-02 |
20170316967 | APPARATUS AND METHODS FOR A MASK INVERTER | 2017-11-02 |
20170316968 | HIGH RESISTIVITY SEMICONDUCTOR-IN-INSULATOR WAFER AND A METHOD OF MANUFACTURING | 2017-11-02 |
20170316969 | WAFER STACK AND FABRICATION METHOD THEREOF | 2017-11-02 |
20170316970 | ENHANCEMENT OF ISO-VIA RELIABILITY | 2017-11-02 |
20170316971 | 3D IC METHOD AND DEVICE | 2017-11-02 |
20170316972 | GLOBAL DIELECTRIC AND BARRIER LAYER | 2017-11-02 |
20170316973 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE | 2017-11-02 |
20170316974 | CONDUCTIVE INTERCONNECT STRUCTURES INCORPORATING NEGATIVE THERMAL EXPANSION MATERIALS AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS | 2017-11-02 |
20170316975 | STRUCTURE AND FORMATION METHOD OF DAMASCENE STRUCTURE | 2017-11-02 |
20170316976 | METHOD OF PRODUCING AN OPENING WITH SMOOTH VERTICAL SIDEWALL IN A SEMICONDUCTOR SUBSTRATE | 2017-11-02 |
20170316977 | WAFER PROCESSING METHOD | 2017-11-02 |
20170316978 | WAFER PROCESSING METHOD | 2017-11-02 |
20170316979 | DISTINCT GATE STACKS FOR III-V-BASED CMOS CIRCUITS COMPRISING A CHANNEL CAP | 2017-11-02 |
20170316980 | FINFETS AND METHODS OF FORMING FINFETS | 2017-11-02 |
20170316981 | Semiconductor Device and Method of Manufacture | 2017-11-02 |
20170316982 | FIN FIELD EFFECT TRANSISTOR, SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | 2017-11-02 |
20170316983 | Integrated Circuit Structure And Method Forming Trenches With Different Depths | 2017-11-02 |
20170316984 | FINFET STRUCTURES AND METHODS OF FORMING THE SAME | 2017-11-02 |
20170316985 | DUAL LINER CMOS INTEGRATION METHODS FOR FINFET DEVICES | 2017-11-02 |
20170316986 | COMMONLY-BODIED FIELD-EFFECT TRANSISTORS | 2017-11-02 |
20170316987 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE | 2017-11-02 |
20170316988 | METHODS FOR DEPOSITING FILMS ON SENSITIVE SUBSTRATES | 2017-11-02 |
20170316989 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME | 2017-11-02 |
20170316990 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP, AND TEST METHOD FOR SEMICONDUCTOR CHIP | 2017-11-02 |
20170316991 | Semiconductor Devices and Methods for Testing a Gate Insulation of a Transistor Structure | 2017-11-02 |
20170316992 | Power Semiconductor Device Module Having Mechanical Corner Press-Fit Anchors | 2017-11-02 |
20170316993 | Power Semiconductor Device Module Having Mechanical Corner Press-Fit Anchors | 2017-11-02 |
20170316994 | Laminate package of chip on carrier and in cavity | 2017-11-02 |
20170316995 | SENSOR | 2017-11-02 |
20170316996 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE | 2017-11-02 |
20170316997 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | 2017-11-02 |
20170316998 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE | 2017-11-02 |
20170316999 | Electronic Sub-Module Including a Leadframe and a Semiconductor Chip Disposed on the Leadframe | 2017-11-02 |
20170317000 | ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF | 2017-11-02 |
20170317001 | Device Including a Semiconductor Chip Monolithically Integrated with a Driver Circuit in a Semiconductor Material | 2017-11-02 |
20170317002 | POWER AMPLIFIER MODULE | 2017-11-02 |
20170317003 | Thermal Management Structure with Integrated Heat Sink | 2017-11-02 |
20170317004 | Thermal Dissipation Through Seal Rings in 3DIC Structure | 2017-11-02 |
20170317005 | Electronic Component Having a Heat-Sink Thermally Coupled to a Heat-Spreader | 2017-11-02 |
20170317006 | SEMICONDUCTOR DEVICE AND POWER MODULE | 2017-11-02 |
20170317007 | HEAT DISSIPATION COMPONENT AND METHOD FOR MANUFACTURING SAME | 2017-11-02 |
20170317008 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME | 2017-11-02 |
20170317009 | HEAT DISSIPATION SUBSTRATE AND METHOD FOR PRODUCING HEAT DISSIPATION SUBSTRATE | 2017-11-02 |
20170317010 | METHOD FOR FORMING INTERCONNECT STRUCTURE OF SEMICONDUCTOR DEVICE | 2017-11-02 |
20170317011 | Through-Substrate Vias with Improved Connections | 2017-11-02 |
20170317012 | MULTI-FINGER TRANSISTOR AND SEMICONDUCTOR DEVICE | 2017-11-02 |
20170317013 | SHUNT STRIP | 2017-11-02 |
20170317014 | POWER MODULE PACKAGE HAVING PATTERNED INSULATION METAL SUBSTRATE | 2017-11-02 |
20170317015 | POWER MODULE PACKAGE HAVING PATTERNED INSULATION METAL SUBSTRATE | 2017-11-02 |
20170317016 | Package with vertical interconnect between carrier and clip | 2017-11-02 |
20170317017 | PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME | 2017-11-02 |
20170317018 | APPLICANT SCREENING | 2017-11-02 |
20170317019 | INTEGRATED INTERPOSER SOLUTIONS FOR 2D AND 3D IC PACKAGING | 2017-11-02 |
20170317020 | APPARTUS AND METHODS FOR MULTI-DIE PACKAGING | 2017-11-02 |
20170317021 | PACKAGED SEMICONDUCTOR DEVICES WITH MULTI-USE INPUT CONTACTS AND RELATED METHODS | 2017-11-02 |
20170317022 | RUTHENIUM METAL FEATURE FILL FOR INTERCONNECTS | 2017-11-02 |
20170317023 | PACKAGED SEMICONDUCTOR DEVICES WITH WIRELESS CHARGING MEANS | 2017-11-02 |
20170317024 | SEMICONDUCTOR DEVICE | 2017-11-02 |
20170317025 | STRUCTURE AND METHOD FOR MAXIMIZING AIR GAP IN BACK END OF THE LINE INTERCONNECT THROUGH VIA LANDING MODIFICATION | 2017-11-02 |
20170317026 | SELECTIVE AND NON-SELECTIVE BARRIER LAYER WET REMOVAL | 2017-11-02 |
20170317027 | POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY | 2017-11-02 |
20170317028 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES | 2017-11-02 |
20170317029 | DUMMY FEATURES IN REDISTRIBUTION LAYERS (RDLS) AND METHODS OF FORMING SAME | 2017-11-02 |
20170317030 | Structure and Formation Method for Chip Package | 2017-11-02 |
20170317031 | Fabrication Method OF A Package Substrate | 2017-11-02 |
20170317032 | COMPOSITE MANGANESE NITRIDE / LOW-K DIELECTRIC CAP | 2017-11-02 |
20170317033 | SEMICONDUCTOR MANUFACTURING PROCESS AND PACKAGE CARRIER | 2017-11-02 |
20170317034 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 2017-11-02 |
20170317035 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE | 2017-11-02 |
20170317036 | Cavity based feature on chip carrier | 2017-11-02 |
20170317037 | METHOD FOR MANUFACTURING A SEAL RING STRUCTURE TO AVOID DELAMINATION DEFECT | 2017-11-02 |
20170317038 | PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME | 2017-11-02 |
20170317039 | BONDING PAD STRUCTURE OVER ACTIVE CIRCUITRY | 2017-11-02 |
20170317040 | SUBSTRATE STRUCTURE | 2017-11-02 |
20170317041 | STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF | 2017-11-02 |
20170317042 | Multi-Layer Metal Pads | 2017-11-02 |
20170317043 | METHOD FOR WAFER DICING | 2017-11-02 |