44th week of 2013 patent applcation highlights part 33 |
Patent application number | Title | Published |
20130286691 | METHOD AND APPARATUS FOR IMPLEMENTING AN UNREGULATED DORMANT MODE IN A POWER CONVERTER - A power converter controller includes a drive signal generator coupled to generate a drive signal to control switching of a power switch to regulate a flow of energy to a power converter output in response to an energy requirement of a load. A voltage supply rail is coupled to supply a voltage to the drive signal generator. The supplied voltage is used by the drive signal generator to generate the drive signal. A control circuit is coupled to generate a power down signal that stops the supply of the voltage to the drive signal generator to stop the generation of the drive signal and the control of the switching of the power switch for a period of time. Timer circuitry determines a duration of the period of time and triggers the control circuit to restart the supply of the voltage by the supply rail to the drive signal generator. | 2013-10-31 |
20130286692 | FILTER CAPACITOR DEGRADATION DETECTION APPARATUS AND METHOD - Power conversion systems and methods are presented for detecting input filter capacitor degradation or approach of end of operational life based on filter capacitor current measurements using single and/or dual threshold comparisons for computed instantaneous sum of squares of filter currents or power values. | 2013-10-31 |
20130286693 | METHOD FOR REDUCING A VOLTAGE RIPPLE DUE TO ROTATIONAL NONUNIFORMITY OF A GENERATOR DRIVEN BY AN INTERNAL COMBUSTION ENGINE - A method for reducing a ripple, caused by rotational nonuniformity of an internal combustion engine, in the output voltage of a generator which is driven by the internal combustion engine is provided. The generator has a stator winding, a rotor winding, a field controller, associated with the rotor winding, for regulating the output voltage of the generator, and a downstream power converter having controllable switching elements. To reduce the voltage ripple, the output voltage of the generator is regulated on the stator side by appropriately controlling the switching elements of the power converter. | 2013-10-31 |
20130286694 | POWER ADAPTER AND ELECTRICAL CONNECTOR THEREFOR - A power adapter and an electrical connector for the power adapter operate to provide power to an electronic device such as a laptop computer. The power adapter includes a switch and a circuit for detecting whether or not the electrical connector is connected to the electronic device. If the adapter is not connected to an electronic device, the switch is opened so that no power is drawn from an AC supply. The electrical connector includes first and second conductors that are electrically connected to the detection circuit. The detection circuit detects a change in potential when the connector is plugged into an electronic device. | 2013-10-31 |
20130286695 | CONTROLLER FOR AN INVERTER CIRCUIT, INVERTER, AND METHOD FOR OPERATING AN INVERTER - Damage to an inverter due to an excessively high start-up current, when using space vector control without a voltage sensor in conjunction with small connection inductances, can be prevented with a method for controlling the inverter, and with a corresponding controller, wherein the controller is configured to transmit in a start-up phase of an inverter circuit a control signal to a control input of the inverter circuit, wherein the control signal simultaneously switches three first semiconductor switches, which are connected to a first DC voltage terminal of the inverter circuit, temporarily into a conducting state. | 2013-10-31 |
20130286696 | Methods, Systems, and Software For Controlling a Power Converter During Low (Zero)-Voltage Ride-through Conditions - A power converter control system having a phase tracker that is designed and configured to estimate the phase of the voltage on the power network that will be on the network when network recovers from a fault on the network. Such a power converter control system allows a power-network-connected power source to ride-through a fault event and continue supplying power thereto at the designed phase and frequency. In one embodiment, the phase tracker provides this estimate by having a response time slow enough that the voltage drop or sag caused by the fault substantially does not affect the control system. In another embodiment, the phase detector is designed and configured to freeze the frequency of its output upon detection of a fault event on the power network. | 2013-10-31 |
20130286697 | POWER QUALITY MANAGEMENT SYSTEM - A power quality management system includes a plurality of phase balancers, each phase balancer including single phase converters coupled between two phase lines and a plurality of controllers to control the plurality of phase balancers. Each controller includes a voltage unbalance detection module to detect amount of voltage unbalance in a plurality of phase lines and a voltage unbalance compensation module to generate reference current commands for each of the single phase converters to reduce the voltage unbalance. | 2013-10-31 |
20130286698 | POWER CONVERTING APPARATUS, OPERATING METHOD THEREOF, AND SOLAR POWER GENERATION SYSTEM - There are provided a power converting apparatus and an operating method thereof, and a solar power generation system. The power converting apparatus for a solar power generation system includes: a power converting unit converting an input signal generated by a solar cell module into an output signal; and a control circuit unit controlling an operation of the power converting unit, wherein the power converting unit includes at least one transformer, and a current sensor and a switching circuit connected to a primary winding of the at least one transformer, and the control circuit unit calculates a voltage and a current of the input signal using a current of the primary winding of the at least one transformer sensed by the current sensor and performs a maximum power point tracking (MPPT) control so that the power converting unit is operated at a maximum power point. | 2013-10-31 |
20130286699 | POWER SUPPLYING APPARATUS, METHOD OF OPERATING THE SAME, AND SOLAR POWER GENERATION SYSTEM INCLUDING THE SAME - There are provided a power supplying apparatus, a method of operating the same, and a solar power generation system including the same. The power supplying apparatus includes: a power supply unit generating a direct current (DC) input signal; a main circuit unit including a plurality of flyback converter circuits connected to the power supply unit to generate a DC output signal; and a control circuit unit controlling an operation of the main circuit unit, wherein the control circuit unit connects the plurality of flyback converter circuits to each other in series or in parallel according to a level of the DC input signal. Therefore, even in the case in which the level of the DC input signal is high, a circuit maybe configured using a circuit device having a low withstand voltage range and damage and deterioration of the circuit device may be prevented. | 2013-10-31 |
20130286700 | Zero-Standby Current Switch for Control of a Power Converter - A controller circuit for activating and deactivating an electrical power converter that provides power to a device includes power input terminals on a primary side, and power output terminals on a secondary side, which are configured to provide power to the device. The controller circuit includes a detection circuit configured to determine whether the device is connected and, if connected, causes power to be routed to the electrical power converter to activate the electrical power converter. When the device is not detected, the electrical power converter is deactivated until the device is reconnected. | 2013-10-31 |
20130286701 | Zero-Standby Current Switch for Control of a Power Converter - A controller circuit for activating and deactivating an electrical power converter that provides power to a device includes power input terminals on a primary side, and power output terminals on a secondary side, which are configured to provide power to the device. The controller circuit includes a detection circuit configured to determine whether the device is connected and, if connected, causes power to be routed to the electrical power converter to activate the electrical power converter. When the device is not detected, the electrical power converter is deactivated until the device is reconnected. | 2013-10-31 |
20130286702 | ADJUSTABLE SPEED DRIVE LIFETIME IMPROVEMENT SYSTEM - The present techniques include methods and systems for operating an inverter to maintain a lifespan of the inverter. In some embodiments, the switching frequency and/or the output current of the inverter may be changed such that stress may be reduced on the inverter bond wires of the inverter. More specifically, embodiments involve calculating the aging parameters for certain operating conditions of the inverter and determining whether the operating conditions result in aging the inverter to a point which reduces the inverter lifespan below a desired lifespan. If the operating conditions reduce the inverter lifespan below the desired lifespan, the switching frequency may be reduced to a lower or minimum switching frequency of the inverter and/or the output current of the inverter may be reduced to a maximum output current at the minimum switching frequency. | 2013-10-31 |
20130286703 | COMPOSITE MATERIAL, REACTOR-USE CORE, REACTOR, CONVERTER, AND POWER CONVERTER APPARATUS | 2013-10-31 |
20130286704 | CASCADED H-BRIDGE (CHB) INVERTER LEVEL SHIFT PWM WITH ROTATION - Cascade H-Bridge inverters and carrier-based level shift pulse width modulation techniques are presented for generating inverter stage switching control signals, in which carrier waveform levels are selectively shifted to control THD and to mitigate power distribution imbalances within multilevel inverter elements. | 2013-10-31 |
20130286705 | LOW POWER CONTENT ADDRESSABLE MEMORY HITLINE PRECHARGE AND SENSING CIRCUIT - An apparatus and a method of operating the apparatus. The apparatus includes a driver circuit and a memory circuit. The driver circuit may be configured to precharge a hitline in response to a predetermined voltage level and a control signal and sense a result of a compare operation based upon a hitline signal on the hitline. The driver circuit generally precharges the hitline to a voltage level lower than the predetermined voltage level and senses the result of the compare operation using the full predetermined voltage level. The memory circuit may be configured to perform the compare operation using the hitline. | 2013-10-31 |
20130286706 | Memory Modules and Devices Supporting Configurable Data Widths - Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations. | 2013-10-31 |
20130286707 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS - A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. | 2013-10-31 |
20130286708 | MEMORY EDGE CELL - A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell. | 2013-10-31 |
20130286709 | BURIED BIT LINE ANTI-FUSE ONE-TIME-PROGRAMMABLE NONVOLATILE MEMORY - An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P | 2013-10-31 |
20130286710 | ONE-TIME PROGRAMMABLE MEMORY, INTEGRATED CIRCUIT INCLUDING SAME, AND METHOD THEREFOR - A one-time programmable memory includes a first one-time programmable memory cell including a fuse core having an input terminal for receiving a trim signal, an output terminal for providing a sense signal, and a fuse. The fuse core conducts current through the fuse in response to the trim signal. The one-time programmable memory cell also includes a sense circuit having an input terminal coupled to the output terminal of the fuse core, and an output terminal for providing a termination signal, and a logic circuit having a first input terminal for receiving a program enable signal, a second input terminal for receiving a data signal, a third input terminal coupled to the output terminal of the sense circuit for receiving the termination signal, and an output terminal coupled to the input terminal of the fuse core for providing the trim signal. | 2013-10-31 |
20130286711 | BLOCKING CURRENT LEAKAGE IN A MEMORY ARRAY - A method for blocking current leakage through defective memory cells in a memory array is provided. The memory cells include access devices and programmable resistance memory elements. The method includes identifying addresses of defective memory cells in the memory array, and applying a modifying bias condition to modify the defective memory cells at the identified addresses. The modifying bias condition causes the defective memory cells to transform into a current blocking condition. The method also includes storing the identified addresses in a redundancy table of addresses. An automatic test system includes a device tester adapted to identify addresses of defective memory cells in a memory array in an integrated circuit under test, and to apply a modifying bias condition to modify the defective memory cells at the identified addresses. | 2013-10-31 |
20130286712 | BIPOLAR SWITCHING MEMORY CELL WITH BUILT-IN "ON" STATE RECTIFYING CURRENT-VOLTAGE CHARACTERISTICS - A memory array is disclosed having bipolar current-voltage (IV) resistive random access memory cells with built-in “on” state rectifying IV characteristics. In one embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/semiconductor stack that forms a Schottky diode when switched to the “on” state. In another embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/tunnel barrier/electrode stack that forms a metal-insulator-metal device when switched to the “on” state. Methods of operating the memory array are also disclosed. | 2013-10-31 |
20130286713 | PHASE CHANGE MEMORY ADAPTIVE PROGRAMMING - Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range, and to repeat at least one of the programming and the adjusting if the programmed resistance value is outside the target resistance value range, the signal including a different programming parameter value each time the programming is repeated. | 2013-10-31 |
20130286714 | DATA WRITE METHOD FOR WRITING DATA TO NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY DEVICE - Provided is a data write method for writing data to a nonvolatile memory element, the data write method including: a first application step of applying a first voltage pulse for changing a resistance state of the nonvolatile memory element from a first state to a second state; a second application step of applying a second voltage pulse which has a same polarity as the first voltage pulse and a voltage value of which has a smaller absolute value than the first voltage pulse; a determination step of determining whether the resistance state of the nonvolatile memory element is the second state; and a third application step of applying a third voltage pulse for changing the resistance state of the nonvolatile memory element from the first state to the second state when it is determined that the resistance state of the nonvolatile memory element is not the second state. | 2013-10-31 |
20130286715 | SEMICONDUCTOR DEVICE WITH MEMORY DEVICE - A memory mat ( | 2013-10-31 |
20130286716 | LOW NOISE MEMORY ARRAY - A method of operating a memory circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The method includes selecting a word line ( | 2013-10-31 |
20130286717 | IMPLEMENTING SUPPLY AND SOURCE WRITE ASSIST FOR SRAM ARRAYS - A method and circuit for implementing write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a write driver including a common bit line supply node, and a common bit line source node. The circuit includes voltage boost circuitry that temporarily boosts the common bit line supply node above supply voltage and temporarily boosts the common bit line source node below source voltage through isolation devices for applying the boosted source and supply voltages to a selected SRAM cell during a write operation. Splitting the boost differential between the common bit lines decreases an overall device voltage differential for providing substantially enhanced reliability of the SRAM array. | 2013-10-31 |
20130286718 | Methods For Reducing Power Dissipation In Drowsy Caches And For Retaining Data In Cache-Memory Sleep Mode - A method for refreshing static random access memory comprises providing at least one six-transistor static random access memory cell disposed on a substrate and providing a light source emitting light. The six-transistor static random access memory cell comprises two storage nodes, two pass transistors, two load transistors, and two driver transistors, the drain diffusion regions of the load transistors forming pn-junctions with the substrate. A portion of the light emitted by the light source is absorbed and converted to minority carriers in the substrate, The minority carriers diffuse through the substrate, and a portion of the minority carriers reach the pn-junctions and cause the pn-junctions to generate electrical current. The electrical current generated charges the storage nodes. | 2013-10-31 |
20130286719 | SEMICONDUCTOR MEMORY WITH SIMILAR RAM AND ROM CELLS - A semiconductor memory includes an array of volatile memory cells, wherein one of the volatile memory cells has transistors connected in a first memory cell circuit, and at least one non-volatile memory cell having transistors connected in a second memory cell circuit, wherein the transistors in the first memory cell circuit are at least one more than the transistors in the second memory cell circuit. | 2013-10-31 |
20130286720 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION PROCESS THEREOF - A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element. | 2013-10-31 |
20130286721 | LOW SENSING CURRENT NON-VOLATILE FLIP-FLOP - A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage. | 2013-10-31 |
20130286722 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material. The tunneling barrier material is a multiferroic material and the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are positioned between a first electrode and a second electrode. | 2013-10-31 |
20130286723 | MAGNETIC RANDOM ACCESS MEMORY WITH FIELD COMPENSATING LAYER AND MULTI-LEVEL CELL - A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, which can be a single layer structure or a synthetic multi-layer structure, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field. | 2013-10-31 |
20130286724 | METHOD, SYSTEM, AND DEVICE FOR HEATING A PHASE CHANGE MEMORY (PCM) CELL - Embodiments disclosed herein may relate to heating a phase change memory (PCM) cell. | 2013-10-31 |
20130286725 | SOLID MEMORY - Recording and erasing of data in PRAM have hitherto been performed based on a change in physical characteristics caused by primary phase-transformation of a crystalline state and an amorphous state of a chalcogen compound including Te which serves as a recording material. Since, however, a recording thin film is formed of a polycrystal but not a single crystal, a variation in resistance values occurs and a change in volume caused upon phase-transition has placed a limit on the number of times of readout of the record. In one embodiment, the above problem is solved by preparing a solid memory having a superlattice structure with a thin film containing Sb and a thin film containing Te. The solid memory can realize the number of times of repeated recording and erasing of 10 | 2013-10-31 |
20130286726 | KEYHOLE-FREE SLOPED HEATER FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a phase change memory device. | 2013-10-31 |
20130286727 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise an annular STT stack including a nonmagnetic material between a first ferromagnetic material and a second ferromagnetic material and a soft magnetic material surrounding at least a portion of the annular STT stack. | 2013-10-31 |
20130286728 | NONVOLATILE MEMORY CELL OPERATING BY INCREASING ORDER IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL - A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. Numerous other aspects are provided. | 2013-10-31 |
20130286729 | Methods and Apparatus for Non-Volatile Memory Cells - Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first storage cell having a first bit cell and a second bit cell; a second storage cell having a third bit cell and a fourth bit cell; and a column multiplexer coupled to a plurality of column lines, selected ones of the column lines coupled to a first source/drain terminal of the first and the second storage cell and coupled to a second source/drain terminal of the first and second storage cell, the column multiplexer coupling a voltage to one of the column lines connected to the first storage cell corresponding to the data, and coupling a voltage to one of the column lines connected to the second storage cell corresponding to the complementary data. Methods for operating the non-volatile memory cells are disclosed. | 2013-10-31 |
20130286730 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES MULTILEVEL DATA - According to one embodiment, a semiconductor memory device includes a memory cell, a flag memory cell for a flag, a dummy cell and a controller. The flag memory cell is selected at the same time as the memory cell. The dummy cell is selected at the same time as the memory cell and the flag memory cell. The controller controls write and read of the memory cell, the flag memory cell and the dummy cell. Data is written also in the dummy cell which neighbors the flag cell. | 2013-10-31 |
20130286731 | MEMORY DEVICE, MEMORY CONTROL DEVICE, AND MEMORY CONTROL METHOD - A memory device includes: a plurality of nonvolatile memory sections configured to allow one memory cell to record data of a plurality of bits, and to include a corresponding number of pages to the plurality of bits in accordance with a plurality of the memory cells as a write control unit; and a control section configured to control writing and reading data to and from the plurality of nonvolatile memory sections, wherein among the plurality of nonvolatile memory sections, if data is written into one of the nonvolatile memory sections, the data is written for each page in sequence from a low-order page to a high-order page, and when the data is written into the low-order page, control is performed such that the data to be written into the low-order page is written into any area of the other of the nonvolatile memory sections at same timing. | 2013-10-31 |
20130286732 | FLASH MEMORY DEVICES HAVING MULTI-BIT MEMORY CELLS THEREIN WITH IMPROVED READ RELIABILITY - Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation. | 2013-10-31 |
20130286733 | METHOD OF PROGRAMMING/READING A NON-VOLATILE MEMORY WITH A SEQUENCE - A method of programming/reading a multi-bit per cell non-volatile memory with a sequence is disclosed. A plurality of less-significant-bit pages are programmed, and a plurality of consecutive most-significant-bit pages of a plurality of consecutive word lines are programmed one after the other in a consecutive order. The most-significant-bit pages through all word lines in at least one memory block of the non-volatile memory are programmed or read after the less-significant-bit pages through all the word lines in the at least one memory block are programmed or read. | 2013-10-31 |
20130286734 | NAND FLASH MEMORY - A NAND flash memory includes a plurality of NAND flash memory structures separated by an insulating layer. In one embodiment of the present disclosure, the NAND flash memory structure includes a first bitline extending along a first direction, a first charge-trapping region positioned over the first bitline, a wordline positioned over the first charge-trapping region and extending along a second direction, a second charge-trapping region positioned over the wordline, and a second bitline positioned over the second charge-trapping region, wherein the first charge-trapping region and the second charge-trapping region are stacked along a third direction substantially perpendicular to the first direction and the second direction. | 2013-10-31 |
20130286735 | VERTICAL STRUCTURE SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes. | 2013-10-31 |
20130286736 | DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS - The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data. | 2013-10-31 |
20130286737 | NAND FLASH MEMORY HAVING C/A PIN AND FLASH MEMORY SYSTEM INCLUDING THE SAME - A NAND flash memory in which a command/address pin is separated from a data input/output pin. The NAND flash memory includes a memory cell array used for storing data, a command/address pin through which a command and an address are received for transmitting data in the memory cell array, and a data input/output pin through which data are transmitted in the memory cell array. The command/address pin is separated from the data input/output pin in the NAND flash memory. Data input/output speed is increased. Furthermore, the NAND flash memory can perform a bank interleaving operation with a minimal delay time. | 2013-10-31 |
20130286738 | SEMICONDUCTOR MEMORY APPARATUS - According to one embodiment, a semiconductor memory apparatus includes an array, a source, a bit line, a sense, and current circuit. The array includes a NAND string. The NAND string includes memory cell. The sense includes a first transistor. One end of transistor is connected to a first node, and other end of the transistor is connected to a second. The first node is used for reading the data held by the memory cell. An internal voltage is smaller than the source voltage. The current circuit outputs a first voltage to a gate of the transistor, and the first voltage is smaller than the internal voltage. The transistor limits a first current from the source to the sense based on a threshold voltage of the memory cell to be read. | 2013-10-31 |
20130286739 | METHODS OF READING MEMORY CELLS - Strings of series-coupled memory cells selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional memory array architectures. Reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device. | 2013-10-31 |
20130286740 | EEPROM CELL WITH TRANSFER GATE - An EEPROM cell including a transfer gate that can suppress a data disturbance phenomenon of the EEPROM cell is provided. The EEPROM cell includes: an inverter; a control plate; a tunneling plate; a data output metal oxide semiconductor field effect transistor (MOSFET) that is connected to the inverter; a floating plate that is connected to the inverter; a tunneling capacitor area that is formed between the floating plate and the tunneling plate; and a transfer gate that is connected to the tunneling plate. As the transfer gate is added between a bit line and the tunneling plate of the EEPROM cell, in a standby (or unselected) operation of the EEPROM cell, the tunneling plate is floated. | 2013-10-31 |
20130286741 | OVER-SAMPLING READ OPERATION FOR A FLASH MEMORY DEVICE - A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation. | 2013-10-31 |
20130286742 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD OF THE SAME - According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells and a word line coupling the memory cells. A determination circuit determines whether write to a first memory cell group of the word line succeeded, and whether write to a second memory cell group of the word line succeeded. A test circuit counts application of write voltage during write to the word line, compares with a threshold a difference between a count of write voltage application upon success of one of respective writes to the first and second memory cell groups and a count of write voltage application upon success of the other of respective the writes, and outputs a result of the comparison. | 2013-10-31 |
20130286743 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described. | 2013-10-31 |
20130286744 | Bit Line Bias Circuit With Varying Voltage Drop - A bit line bias circuit of a memory architecture includes a varying voltage drop. In some embodiments, the voltage drop can depend on the threshold voltage of the memory cell selected to be read, or on the sense current flowing through the memory cell selected to be read. | 2013-10-31 |
20130286745 | METHOD AND APPARATUS FOR READING DATA FROM NON-VOLATILE MEMORY - Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC). | 2013-10-31 |
20130286746 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device of the present invention includes a memory cell array configured to include a sensing circuit configured to perform program verifying of the page buffer group selected by the select signal, and configured to output a pass/fail signal corresponding to the page buffer group, a verifying result signal generation section configured to output one or more of a first verifying signal and a second verifying signal in accordance with pass or fail of the program for total page buffer groups by using the pass/fail signal, and a control circuit configured to output the select signals to verify the program after the program is performed, and control operation of the program in response to an output signal of the verifying result signal generation section. | 2013-10-31 |
20130286747 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A nonvolatile memory device comprises cell strings formed in a direction substantially perpendicular to a substrate and is configured to select memory cells in units corresponding to a string selection line. The device selects a page to be programmed among pages sharing a common word line, determines a level of a program voltage to be provided to the selected page according to a location of a string selection line corresponding to the selected page, and writes data in the selected page using the determined level of the program voltage. | 2013-10-31 |
20130286748 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a row direction and a column direction in a matrix shape; word lines which select the memory cell in the row direction; bit lines which select the memory cells in the column direction; a sense amplifier circuit which determines values stored in the memory cells based on states of the bit line; and a charge/discharge circuit which is formed in a well where the memory cell array is arranged and which charges or discharges the bit lines. | 2013-10-31 |
20130286749 | System and Method for Memory Array Decoding - A memory array includes a plurality of sense amplifiers and a first switch module. The plurality of sense amplifiers is connected respectively to a plurality of global bit lines. The plurality of sense amplifiers are configured to read data stored in a first block of memory cells of the memory array. The memory cells in the first block are located at intersections of a plurality of local bit lines and a first plurality of word lines. The first switch module is connected to a first group of the plurality of local bit lines and to a first group of the plurality of global bit lines. The first switch module is configured to selectively connect a subset of the first group of the plurality of local bit lines to the first group of the plurality of global bit lines. | 2013-10-31 |
20130286750 | MEMORY SYSTEM AND CONTROL METHOD THEREFOR - A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices. | 2013-10-31 |
20130286751 | BUFFER AND CONTROL CIRCUIT FOR SYNCHRONOUS MEMORY CONTROLLER - A buffer and control circuit for a synchronous memory controller includes first and second differential comparators and control logic. The first differential comparator is provided with positive and negative differential input signals and the second differential comparator is provided with offset positive and negative differential input signals. The first and second differential comparators generate output signals based on magnitudes of the positive and negative differential input signals and the offset positive and negative differential input signals. The control logic generates a reference strobe signal based on the output signals. | 2013-10-31 |
20130286752 | SEMICONDUCTOR MEMORY - A semiconductor memory according to one embodiment includes: a memory cell array including a plurality of memory cells storing data, a first buffer circuit for inputting/outputting data to and from the first memory cell array, a data transfer circuit connected with the first buffer circuit via the first data bus and configured to control data transfer, and a control circuit configured to control a first mode and a second mode. The data transfer circuit performs control such that a bus width of the first data bus differs between the first mode and the second mode. | 2013-10-31 |
20130286753 | SEMICONDUCTOR DEVICE - A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing. | 2013-10-31 |
20130286754 | Wordline Coupling Reduction Technique - A semiconductor memory includes a memory array having memory cells coupled to wordlines and bitlines. Each wordline has a left end and an opposing right end. A first wordline in every two adjacent wordlines has its left end connected to a left row driver and its right end connected to a right clamp circuit, and a second wordline in every two adjacent wordlines has its right end connected to a right row driver and its left end connected to a left clamp circuit, such that when the right clamp circuits are activated, the right clamp circuits clamp the corresponding wordline ends to a predetermined potential, and when the left clamp circuits are activated, the left clamp circuits clamp the corresponding wordline ends to the predetermined potential. | 2013-10-31 |
20130286755 | DECODER CIRCUIT OF SEMICONDUCTOR STORAGE DEVICE - The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application MOS transistors for each of plural word lines, the voltage application MOS transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation, and applying a high voltage in a predetermined high voltage operation; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation, and that outputs the normal voltage or the high voltage in the high voltage operation, to the voltage application MOS transistor. | 2013-10-31 |
20130286756 | MEMORY CIRCUIT - A memory circuit may include a shift register ring including single-bit shift registers. The circuit may include a clock connected to the shift registers to shift bits within the shift register ring, and a counter connected to the clock and indicating positions of the bits in the shift register ring. | 2013-10-31 |
20130286757 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - An error of stored data is detected with high accuracy. Data (e.g., a remainder in a CRC) used for detecting an error is stored in a memory in which an error is unlikely to occur. Specifically, the following semiconductor device is used: a memory element including a plurality of transistors, a capacitor, and a data storage portion is provided in a matrix; the data storage portion includes one of a source and a drain of one of the plurality of transistors, a gate of another one of the plurality of transistors, and one electrode of the capacitor; a semiconductor layer including a channel of the transistor, the one of the source and the drain of which is connected to the data storage portion, has a band gap of 2.8 eV or more, or 3.2 eV or more; and the data storage portion stores data for detecting an error. | 2013-10-31 |
20130286758 | REDUNDANCY CONTROL CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A redundancy control circuit includes an address fuse circuit and a first circuit. The address fuse circuit includes a plurality of first fuses. Each of the first fuses is configured to be cut based on a result of comparing a number of bits of a defective input address having a first logic level with a number of bits of the defective input address having a second logic level. The address fuse circuit is configured to generate a first address using the first fuses based on a cutting operation that depends on the result of comparing. The first circuit is configured to output either the first address or a second address that is an inverted address of the first address as a repair address, wherein a logic level of each of bits of the repair address is the same as that of the defective input address. | 2013-10-31 |
20130286759 | METHOD OF SELECTING ANTI-FUSES AND METHOD OF MONITORING ANTI-FUSES - For selecting anti-fuses in a semiconductor memory device, a decoder block may be enabled to receive selection information for selecting the anti-fuses. The selection information is decoded in the decoder block to select at least one of the anti-fuses. Target operation is performed on the selected anti-fuses. The decoder block is disabled. | 2013-10-31 |
20130286760 | SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER - In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row. | 2013-10-31 |
20130286761 | SWITCHING CIRCUIT - A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second transistor is turned on based on a second control signal delayed by a time delay from the first control signal. A second terminal of the first transistor is coupled with a second terminal of the second transistor. The second control signal is used to control a first input signal of a logic device. The logic device receives a second input signal inversed from the first control signal. An output signal of the logic device is used to control a first terminal of the second transistor. | 2013-10-31 |
20130286762 | MEMORY CONTROL APPARATUS AND METHOD - Provided are a memory control apparatus and a memory control method. In the memory control apparatus and memory control method, data are distributively stored in a plurality of banks in sequence, and the corresponding data are written to or read from the memory, based on row address information obtained by exchanging a portion of row information and bank information with each other. According to the invention, if a new row begins when the host or the processor accesses the memory, a host or a processor accesses another bank, and thus the block data can be read or written without a waiting cycle. In addition, the memory control apparatus and the memory control method can be implemented with low complexity available through simple address conversion in the memory control apparatus. | 2013-10-31 |
20130286763 | PRE-DECODER FOR DUAL POWER MEMORY - A pre-decoder for providing a pulse signal to a dual power rail word line driver is provided. The pre-decoder includes a clock generator, an address latch and decoder, a level shifter and a processing unit. The clock generator generates a first signal according to a clock, wherein the first signal is powered by a first supply voltage. The address latch and decoder decodes an address to obtain a second signal according to the first signal. The level shifter generates a third signal according to the first signal, wherein the third signal is powered by a second supply voltage higher than the first supply voltage. The processing unit generates the pulse signal according to the second signal and the third signal, wherein the pulse signal is powered by the second supply voltage. | 2013-10-31 |
20130286764 | CIRCUIT AND METHOD FOR ADDRESS TRANSITION DETECTION - A new address transition detection (ATD) circuit for use on an address bus having a plurality of address signal lines comprises a first circuit for each address signal line and a second circuit. The first circuit has a first input, a second input and an output. The first input is coupled to an address signal line. The second input is coupled to an ATD signal. The first circuit saves the current level of the first input in response to an ATD pulse on the ATD signal and generates a change signal at its output by comparing the current level and the saved level of the first input. The second circuit has an input and an output. The second circuit receives on its input the change signal from the first circuit. In response, the second circuit generates the ATD pulse on the ATD signal at its output. | 2013-10-31 |
20130286765 | CHANNEL SKEWING - Methods and systems for channel skewing are described. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding to at least one of the number of channels such that the group of data signals are skewed with respect to a group of data signals corresponding to at least one of the other respective channels. | 2013-10-31 |
20130286766 | WARM MIX ASPHALT ASSEMBLY AND METHODS THEREOF - Embodiments of the present invention generally relate to a warm mix asphalt assembly and methods of operating the same. More specifically, embodiments of the present invention relate to warm mix asphalt assembly having requisite ultra-low nitrogen oxide emissions. In one embodiment of the present invention, a warm mix asphalt assembly comprises a warm mix asphalt skid, having a water input pipe, a water output pipe and a control apparatus; a burner assembly for drying aggregate, the burner assembly comprising a water line for receiving water from the warm mix asphalt skid; and an asphalt expander and drum assembly having a water line for receiving water from the warm mix asphalt skid. | 2013-10-31 |
20130286767 | APPARATUS FOR PRODUCING A LIQUID CONCENTRATE FROM A DRY MATERIAL - An apparatus for converting a dry material into a liquid concentrate includes a mixing vessel having an outlet opening, a dispenser for dispensing a predetermined weight of a dry material at a predetermined drop rate onto a predetermined drop location within the vessel, an inlet pipe connectable to a source of liquid for introducing a liquid into the vessel; a sensor for sensing the volume of liquid within the vessel; a pump for supplying a pressurized flow of recirculating liquid to the vessel; and a first, a second and a third agitating nozzle mounted within the vessel. Each agitating nozzle is operative to produce a jet of liquid oriented in a predetermined direction within the vessel. The nozzles are cooperable to generate within the vessel a moving body of liquid into which a dry material dispensed into the vessel is able to dissolve or to disperse. | 2013-10-31 |
20130286768 | PAINT CAN-CLAMPING DEVICE APPLICABLE TO DOUBLE-GYROSCOPIC MIXER - A paint can-clamping device applicable to a double-gyroscopic mixer is disclosed, including a lower supporting plate, left and right guide rails, an upper pressing plate and a locking mechanism. The locking mechanism includes an upper pressing plate-fixing frame, a locking piece and a locking piece spring. The upper pressing plate is connected to the upper pressing plate-fixing frame via a guide pole. A cam structure having a cam handle is mounted in the upper pressing plate-fixing frame, and is cooperated, via a cam pressing mechanism for pressing the locking piece downwardly, with the locking piece such that the locking piece moves away from the V-shaped groove of the guide rail to be in unlocking state, thereby achieving a linear movement of the upper pressing plate along the guide rails. | 2013-10-31 |
20130286769 | Static Mixer Assembly - Apparatus and methods are described for use in mixing of fluids or mixing ingredients into fluids by means of a static mixer assembly (i.e. without requiring moving mechanical parts, where fluid flow is used to achieve mixing). The static mixer assembly is a cylindrical tube with three pairs of fins extending inward from the inner wall of the tube. The central fins form a prow pointing upstream, with two pairs of flanking fins arranged to prevent unhindered fluid flow parallel to the central axis of the tube a peripheral region, whilst allowing unobstructed flow in a central region and extending to a peripheral region near the inner wall opposite the prow. The fins force fluid outwards along the inner walls from the prow towards the unobstructed peripheral region opposite the prow and additionally fluid spills over the inner edges of the fins into the central region. The resulting flow pattern provides excellent mixing with a low ratio of pressure drop to volumetric flow rate across the assembly. Ingredients inserted into the unobstructed peripheral region opposite the prow are rapidly homogenised into flowing fluid. | 2013-10-31 |
20130286770 | STATIC GAS MIXER - The present invention is directed to an apparatus for mixing gaseous mixture components. The present invention likewise relates to a correspondingly applied method and to the use of an apparatus according to the invention for mixing components of the exhaust gas of internal combustion engines with a reducing agent and to a correspondingly designed reactor. | 2013-10-31 |
20130286771 | ALTERNATIVE VIBRATOR ACTUATOR SOURCE - The invention is an electric sweep type seismic vibrator source of the type used in seismic prospecting for hydrocarbons. The source uses an engine and generator combination to create electric power to drive a frame of linear electric motors that direct a rod or piston to contact the ground in a recurring fashion. Preferably, a foot is arranged on the bottom end of the rod or piston for contact with the ground and by engaging the grid of motors to push down against the ground in a rapid progression, acoustic energy is created and delivered into the ground for geophones to sense and record. | 2013-10-31 |
20130286772 | Methods and Systems for Noise-Based Streamer Depth Profile Control - Disclosed are methods and systems for depth control of a sensor streamer. An example embodiment comprises a method for depth control of a sensor streamer. The example method may comprise towing the sensor streamer in a body of water; measuring noise levels of one or more signals generated on the sensor streamer; and adjusting depth of the sensor streamer at one or more spaced apart locations in response to the measured noise levels. | 2013-10-31 |
20130286773 | SEISMIC DATA ACQUISITION - A method is proposed for acquiring seismic data relative to an area of the subsoil, wherein at least one seismic source is moved and seismic waves are emitted in successive shooting positions of the source so as to illuminate said area of the subsoil, and the signals resulting from this emissions are picked up using a set of cables having a substantially zero buoyancy and provided with receivers. The cables have a substantially zero speed or a speed substantially slower than the source in the terrestrial reference frame. And said successive shot positions are determined as a function of the position of the receivers relative to the terrestrial reference frame to optimize at least one quality criterion relating to the set of seismic signals acquired by the receivers in respect of said area. Such a method enables improved seismic data acquisition. | 2013-10-31 |
20130286774 | STREAMER CABLE WITH ENHANCED PROPERTIES - The present invention relates to streamer cables. One embodiment of the present invention relates to a method for preparing a streamer cable. The method may comprise retrofitting the streamer cable with a solid void-filler material, where the streamer cable was configured as a liquid-filled streamer cable. The retrofitting may comprise introducing a void-filler material into the streamer cable when the void-filler material is in a liquid state and curing or otherwise solidifying the void-filler material to a solid state. In another embodiment, the present invention relates to a streamer cable comprising an outer skin and-at least one sensor positioned within the outer skin. The streamer cable may also comprise a solid void-filler material positioned between the outer skin and the at least one sensor, wherein the solid void-filler material is coupled to the at least one sensor. | 2013-10-31 |
20130286775 | SEISMIC IMAGING SYSTEM FOR COUSTIC-ELASTIC COUPLED MEDIA USING ACCUMULATED LAPLACE GRADIENT DIRECTION - The description relates to a seismic imaging technology technique for modeling a subsurface structure through waveform inversion in the Laplace domain. The seismic imaging system comprises a scaled gradient calculating unit calculating a scaled gradient, a modeling parameter updating unit updating the model parameters using the scaled gradient direction, and an iteration control unit controlling the scaled gradient calculating unit and the modeling parameter updating unit to repeat processing iteratively until a stopping criteria is met. | 2013-10-31 |
20130286776 | METHOD FOR MANAGING A MULTI-VESSEL SEISMIC SYSTEM - A method for managing a multi-vessel seismic system including a first vessel, having a recording system and towing a streamer integrating seismic sensors, and a second vessel, including at least one seismic source performing shots. The second vessel sends to the first vessel a plurality of series of shot predictions. For each shot, the second vessels activates the seismic source according to the predictions and sends to the first vessel shot data relating to the shot. The first vessel activates the recording system. If the first vessel has not received the shot data relating to at least one performed shot, it sends a request to the second vessel and receives in response the missing shot data. For each performed shot and the related shot data, the system selects seismic data and combines the selected seismic data with the related shot data to obtain combined data allowing a seabed representation. | 2013-10-31 |
20130286777 | METHODS AND APPARATUS FOR GENERATING DEGHOSTED SEISMIC DATA - One embodiment relates to a method for deghosting seismic data from a marine seismic survey. The seismic data from the marine seismic survey is obtained, where the marine seismic survey was performed using multiple sub-sources towed at two or more different depths and fired at distinct time-delays. The seismic data is sorted into common receiver gathers, and the common receiver gathers are transformed from horizontal source coordinates to horizontal wavenumbers. For each selected frequency, a matrix operator is constructed, and an inversion procedure is applied to a system of equations based on the matrix operator to generate source-deghosted seismic data. Other embodiments, aspects and features are also disclosed. | 2013-10-31 |
20130286778 | REFLECTIVE ECHO TOMOGRAPHIC IMAGING USING ACOUSTIC BEAMS - An inspection system includes a plurality of acoustic beamformers, where each of the plurality of acoustic beamformers including a plurality of acoustic transmitter elements. The system also includes at least one controller configured for causing each of the plurality of acoustic beamformers to generate an acoustic beam directed to a point in a volume of interest during a first time. Based on a reflected wave intensity detected at a plurality of acoustic receiver elements, an image of the volume of interest can be generated. | 2013-10-31 |
20130286779 | QUASI-IMPULSIVE DISPLACEMENT SOURCE - The invention is an electric seismic vibrator source of the type used in seismic prospecting for hydrocarbons that creates a quasi-impulsive burst of seismic energy onto the ground and into the earth. The source uses an engine and generator combination to create electric power for all systems on the source such as driving a frame of linear electric motors that direct a rod or piston to contact the ground. All of the linear electric motors are driven against the ground in a high power pulse that delivers a band-limited spectrum of seismic energy over a very brief period of time that would like a “pop” and be measured in milliseconds. A quasi-impulsive seismic pulse would create a wave field that resembles the seismic data acquired using dynamite or other explosive seismic systems without the ultrahigh frequencies of a true explosive pulse. The quick burst or several quick bursts may further speed up the survey by minimizing the time that a vibe spends on a source point. | 2013-10-31 |
20130286780 | DISTINCTIVE LAND SEISMIC SWEEP - The invention is an electric sweep type seismic vibrator source of the type used in seismic prospecting for hydrocarbons. The source uses an engine and generator combination to create electric power for all systems on the source such as driving a frame of linear electric motors that direct a rod or piston to contact the ground in a recurring fashion along with driving the source from location to location through a survey area. Preferably a foot is arranged on the bottom end of the rod or piston for contact with the ground and by engaging the grid of motors to push down against the ground in a rapid progression, acoustic energy is created and delivered into the ground for geophones to sense and record. However, the rapid progression of pulses or sweep of seismic energy is delivered in a distinctive fashion as compared to a conventional upsweep or downsweep and the distinctiveness is also achieved by creating a designed cadence or timing such that each pulse in a series of pulses is not delivered in a regular timing. Several similar seismic sources may be employed where each is provided with its own distinctive series of pulses such that each may be identified within the data record and source separation from a number of seismic sources may be accomplished. | 2013-10-31 |
20130286781 | Method and Apparatus for Selective Seismic Detection of Elongated Targets - A seismic wave source and sensing system coupled to the surface of an elastic wave propagation medium has a seismic wave source transducer having a preferred axis of vibration oriented horizontally on the surface of the elastic wave propagation medium. A seismic wave sensing transducer has a preferred axis of vibration response oriented horizontally on the surface of said elastic wave propagation medium such that said sensing transducer is capable of detecting dynamic particle motions and displacements of SH waves. An arrangement of the source and sensing transducers is provided on the surface of the elastic wave propagation medium. A recording system capable of acquiring and storing reflected SH wave signals detected by the sensing transducer, wherein the recorded signals represent reflections from contrasting physical properties within the elastic wave propagation medium to provide preferential detection of elongate subsurface targets such as utility pipes, conduits, and other similar object. | 2013-10-31 |
20130286782 | SYSTEMS AND METHODS FOR OPTIMAL STACKING OF SEISMIC DATA - Systems and methods include seismic data stacking derived from a set of image volumes. Stacking includes finding a sub-set of seismic image volumes (and in some implementations their respective stacking weights) or multiple realizations of sub-set of seismic image volumes from a given set that are consistent and similar to each other. Some or all of the input seismic image volumes can be stacked together as they would be with a conventional stack. However, the signal-to-noise ratio can be enhanced by only stacking those volumes that contain consistent and relevant information. Optimal stacking can utilize an algorithm that can be implemented in a moving window fashion. | 2013-10-31 |
20130286783 | TARGET DETECTION AND TRACKING WITH MULTIPLE ULTRASONIC TRANSDUCERS - In an ultrasonic detection system utilizing multiple ultrasound transducers capable of both transmitting and receiving detection signals, the transducers are selectively operated to achieve immunity to ringdown delays or to optimize the detection of distant objects. For example, in one embodiment, object detection is performed within the field of a particular transducer channel by suppressing rather than activating that transducer; instead, the adjacent transducers on either side of the selected channel are driven simultaneously, and the selected channel's transducer is used only to receive. | 2013-10-31 |
20130286784 | DEVICE AND METHOD FOR TRANSCEIVING ULTRASONIC WAVE - An ultrasonic wave transceiving device is provided. The device includes a transmitter for transmitting at least one kind of first detection data ultrasonic signal and a plurality of kinds of second detection data ultrasonic signals, a receiver for receiving echo signals of the first and second detection data ultrasonic signals, and first and second information generators for generating first and second information based on the echo signal of the first and second detection data ultrasonic signals, respectively. The transmitter transmits the first and second detection data ultrasonic signals which transmission period of the first detection data ultrasonic signal intervenes between transmission periods of the second detection data ultrasonic signals in time axis. The second information generator generates the second information by using the echo signals of the second detection data ultrasonic signals. | 2013-10-31 |
20130286785 | METHOD AND APPARATUS FOR INCREASING THE DIRECTION-FINDING ACCURACY OF A RECEIVER ARRANGEMENT - A method for increasing a bearing accuracy of a receiver assembly includes providing a receiver assembly which receives sound waves to determine reception signals. The reception signals determine direction signals of a reception direction. Frequency lines of a frequency of a frequency range comprising an amplitude value are attributed to a reception direction based the direction signals. A directional function is formed for each frequency. Each directional function is transformed into a spectral range to obtain a first spectral function comprising first spectral function arguments. The first spectral function are filled with other spectral function arguments between middle spectral function arguments of the first spectral function arguments to obtain filled first spectral arguments. The other spectral function arguments have a respective value of zero or a range of zero. Each of the filled first spectral functions are transformed back from the spectral range to an interpolated first directional function. | 2013-10-31 |
20130286786 | ULTRASOUND TRANSDUCER ARRAY, METHOD OF MANUFACTURING ULTRASOUND TRANSDUCER ARRAY AND ULTRASOUND ENDOSCOPE - An ultrasound transducer array according to an embodiment includes a substrate, a plurality of groove-like recesses arranged at a predetermined interval on one surface of the substrate, a cell region arranged between the recesses on the one surface side of the substrate, a flexible film configured to cover the substrate and the cell region and having fragility lower than fragility of the substrate, and a dividing groove having a width smaller than a width of the recess and reaching from the other surface of the substrate to the flexible film in the recess. | 2013-10-31 |
20130286787 | Low-Frequency Seismic-While-Drilling Source - A bottom hole assembly is configured with a drill bit section connected to a pulse generation section. The pulse generation section includes a relatively long external housing, the particular housing length being selected for the particular drilling location. The long external housing is positioned closely adjacent to the borehole sidewalls to thereby create a high speed flow course between the external walls of the housing and the borehole sidewalls. The long external housing includes a valve cartridge assembly and optionally a shock sub decoupler. While in operation, the valve cartridge assembly continuously cycles and uses downhole pressure to thereby generate seismic signal pulses that propagate to geophones or other similar sensors on the surface. The amount of bypass allowed through the valve assembly is selectable in combination with the long external housing length and width to achieve the desired pulse characteristics. The bottom hole assembly optionally includes an acoustic baffle to attenuate wave propagation going up the drill string. | 2013-10-31 |
20130286788 | ELECTRICAL ENERGY ACCUMULATOR - The invention is an electric power accumulator used with an electric sweep type seismic vibrator source of the type used in seismic prospecting for hydrocarbons. The source uses an engine and generator combination to create electric power to drive a frame of linear electric motors that direct a rod or piston to contact the ground in a recurring fashion. The source may also be designed to use electric power to drive the source from location to location through a survey area. A large electric power accumulator is provided to store electric power when the generator is able to produce excess power and the accumulator may deliver power along with the generator to drive the rods and deliver acoustic energy. With a large electric power accumulator, such as a battery or capacitor, the engine and generator combination may be engineered to be somewhat smaller, less costly and more efficient than a system where the engine and generator were sized to provide the electric power at times of maximum electric draw. | 2013-10-31 |
20130286789 | ACTIVE ISOLATION APPARATUS - The invention is an electric sweep type seismic vibrator source of the type used in seismic prospecting for hydrocarbons. The source uses an engine and generator combination to create electric power for all systems on the source such as driving a frame of linear electric motors that direct a rod or piston to contact the ground in a recurring fashion along with driving the source from location to location through a survey area. The seismic source further includes an active isolation system that provides for significant weight on the ground through the rods of the linear electric motors, but protects the vehicle body and the remainder of the systems on the seismic source to be insulated from the harshest vibration related to the acoustic energy being applied to the ground. The active isolation system may include reactive elements such as pneumatic and hydraulic shock absorbers, but also includes active elements such as linear motors operated to counteract the impulsive forces from conveying through the frame of the seismic source. | 2013-10-31 |
20130286790 | SIMULTANEOUS COMPOSITE LAND SEISMIC SWEEP - The invention is an electric sweep type seismic vibrator source of the type used in seismic prospecting for hydrocarbons. The source uses an engine and generator combination to create electric power for all systems on the source such as driving a frame of linear electric motors that direct a rod or piston to contact the ground in a recurring fashion along with driving the source from location to location through a survey area. Preferably a foot is arranged on the bottom end of the rod or piston for contact with the ground and by engaging the grid of motors to push down against the ground to create impulses that deliver acoustic seismic energy into the earth for geophones to sense and record. However, the pulses of seismic energy are delivered in a distinctive fashion where different linear motors are deliberately and concurrently providing different signals that create a distinctive composite signature or signal that can be identified in the data record for source separation purpose. | 2013-10-31 |