44th week of 2013 patent applcation highlights part 18 |
Patent application number | Title | Published |
20130285191 | POWER CONVERSION APPARATUS - The power conversion apparatus includes semiconductor modules and a circuit board on which a control circuit is formed. Each semiconductor module includes signal terminals electrically connected to the circuit board. The signal terminals of each semiconductor module are arranged in a line so as to form a terminal row along a first direction. The semiconductor modules are grouped into upper arm semiconductor modules and lower arm semiconductor modules each connected to a corresponding one of the upper arm semiconductor module. Upper arm terminal rows as the terminal rows of the upper arm semiconductor modules and lower arm terminal rows as the terminal rows of the lower arm semiconductor modules are arranged in a staggered manner along a second direction perpendicular to the first direction and to a third direction in which the signal terminals of the semiconductor modules project, the first, second and third directions being perpendicular to one another. | 2013-10-31 |
20130285192 | LOW NOISE MEMORY ARRAY - A circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The circuit includes a substrate having a first conductivity type. A trench isolation region ( | 2013-10-31 |
20130285193 | METAL-INSULATOR-METAL (MIM) CAPACITOR WITH DEEP TRENCH (DT) STRUCTURE AND METHOD IN A SILICON-ON-INSULATOR (SOI) - A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor. | 2013-10-31 |
20130285194 | OPTICAL PROXIMITY CORRECTION FOR ACTIVE REGION DESIGN LAYOUT - The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature. | 2013-10-31 |
20130285195 | VERTICALLY INTEGRATED SEMICONDUCTOR DEVICES - A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished. | 2013-10-31 |
20130285196 | ESD PROTECTION CIRCUIT PROVIDING MULTIPLE PROTECTION LEVELS - An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface. A plurality of stacked ESD protection cells are in the semiconductor surface each having a surrounding isolation structure, wherein the ESD protection cells are connected in series by an interconnect and include a first ESD protection cell in series with at least a second ESD protection cell. A plurality of protection pins include a first protection pin across the first ESD protection cell but not across the second ESD protection cell to provide a first voltage rating and a second protection pin across both the first and second ESD protection cell to provide a second voltage rating which is higher than the first voltage rating. | 2013-10-31 |
20130285197 | Semiconductor Devices and Methods of Manufacturing and Using Thereof - A semiconductor device includes at least one first semiconductor element and two interconnectors for electrically coupling the at least one first semiconductor element to external. A spacing between the two interconnectors corresponds to a size of a second semiconductor element. The second semiconductor element can be affixed between the two interconnectors. | 2013-10-31 |
20130285198 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a spiral-shaped inductor formed to include a metal wire; and a horseshoe-shaped inductor formed to include the metal wire. The horseshoe-shaped inductor is arranged such that an opening of the horseshoe-shaped inductor is disposed opposite to the spiral-shaped inductor. Accordingly, unnecessary wave (spurious) output from a transmitting unit can be reduced as small as possible. | 2013-10-31 |
20130285199 | Semiconductor Device and Method for Making the Same - A semiconductor device includes: a substrate having a base and a pillar array including a plurality of pillars; a plurality of bit lines, each of which is disposed between two adjacent ones of the columns of the pillar array; a plurality of word lines, each of which is connected to a corresponding one of the rows of the pillar array; and a contact array including a plurality of bit line contacts arranged in rows and columns. The bit line contacts of each column of the contact array are embedded in the base and are electrically connected to a respective one of the bit lines. Each bit line contact intersects the respective one of the bit lines and extends between and is electrically connected to two adjacent ones of the pillars. | 2013-10-31 |
20130285200 | Capacitor for Interposers and Methods of Manufacture Thereof - Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate. | 2013-10-31 |
20130285201 | MIM CAPACITOR FORMATION METHOD AND STRUCTURE - Metal-insulator metal (MIM) capacitors are formed by providing a substrate having a first surface, forming thereon a first electrode having conductive and insulating regions wherein the conductive regions desirably have an area density D | 2013-10-31 |
20130285202 | SEMICONDUCTOR DEVICE - To provide a semiconductor device including a capacitor which includes a cylindrical or columnar lower electrode, a support film in contact with the upper portion of the lower electrode for supporting the lower electrode, a dielectric film covering the lower electrode and the support film, and an upper electrode facing the lower electrode with the dielectric film interposed therebetween, wherein the dielectric film has a first thickness on the upper surface of the support film and a second thickness thinner than the first thickness on the side surface of the lower electrode, and thereby the mechanical strength of the support film is increased. | 2013-10-31 |
20130285203 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention is directed to a semiconductor integrated circuit device that basically has a non-memory array area, a memory array area, and memory capacitors formed across lower embedded metal interconnection layers including a low-dielectric constant interlayer insulating film in the memory array area. In addition, a memory-periphery metal seal ring is provided in the lower embedded metal interconnection layers having at least the low-dielectric constant interlayer insulating film so as to surround the memory array area. | 2013-10-31 |
20130285204 | COMPONENT-BUILT-IN WIRING BOARD - Embodiments of the present invention provide a component-built-in wiring board capable of preventing a defect, such as a crack, resulting from stress concentration at a corner, when a component is accommodated in a housing portion of a core material with resin filler filled therebetween. The component-built-in wiring board can include a component accommodated in the housing portion of a core material, and a laminate portion in which insulating layers and conductor layers are laminated alternately on the core material. A gap between the housing portion of the core material and the component can be filled with a resin filler. In an inner circumferential portion of the housing portion of the core material a first straight chamfered portion is formed at each corner of a rectangle, and in an outer circumferential portion of the component a second straight chamfered portion is formed at each corner of a rectangle. | 2013-10-31 |
20130285205 | Method for Producing MIM Capacitors with High K Dielectric Materials and Non-Noble Electrodes - A method of producing a Metal-Insulator-Metal (MIM) capacitor stack through doping to achieve low current leakage and low equivalent oxide thickness is disclosed. A high K dielectric material is deposited on a non-noble electrode; the dielectric material is doped with oxides from group IIA. The dopant increases the barrier height of metal/insulator interface and neutralizes free electrons in dielectric material, therefore reduces the leakage current of MIM capacitor. The electrode may also be doped to increase work function while maintaining a rutile crystalline structure. The method thereby enhances the performance of DRAM MIM capacitor. | 2013-10-31 |
20130285206 | LOW LEAKAGE MIM CAPACITOR - Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits. | 2013-10-31 |
20130285207 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device. | 2013-10-31 |
20130285208 | FINFET DIODE WITH INCREASED JUNCTION AREA - A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer. | 2013-10-31 |
20130285209 | Low Leakage Diodes - A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode. | 2013-10-31 |
20130285210 | FULL BRIDGE RECTIFIER MODULE - A full bridge rectifier includes four bipolar transistors, each of which has an associated parallel diode. A first pair of inductors provides inductive current splitting and thereby provides base current to/from one pair of the bipolar transistors so that the collector-to-emitter voltages of the bipolar transistors are low. A second pair of inductors similarly provides inductive current splitting to provide base current to/from the other pair of bipolar transistors. In one embodiment, all components are provided in a four terminal full bridge rectifier module. The module can be used as a drop-in replacement for a conventional four terminal full bridge diode rectifier. When current flows through the rectifier module, however, the voltage drop across the module is less than one volt. Due to the reduced low voltage drop, power loss in the rectifier module is reduced as compared to power loss in a conventional full bridge diode rectifier. | 2013-10-31 |
20130285211 | DEVICE STRUCTURES COMPATIBLE WITH FIN-TYPE FIELD-EFFECT TRANSISTOR TECHNOLOGIES - Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material. | 2013-10-31 |
20130285212 | EPITAXIAL STRUCTURE - An epitaxial structure is provided. The epitaxial structure includes an epitaxial layer and a graphene layer. The epitaxial layer has a patterned surface. The graphene layer is located on the patterned surface of the epitaxial layer. The patterned graphene layers are a continuous structure defining the plurality of apertures. The sizes of the apertures are in a range from about 10 nanometers to about 120 micrometers. The dutyfactor of the graphene layer is in a range from about 1:4 to about 4:1. | 2013-10-31 |
20130285213 | EPITAXIAL STUCTURE - An epitaxial structure includes a patterned epitaxial growth surface defining a plurality of grooves. A graphene layer covers the patterned epitaxial growth surface. An epitaxial layer is formed on the patterned epitaxial growth surface, wherein a first part of the graphene layer is sandwiched between the substrate, and a second part of the graphene layer is embedded into the epitaxial layer. | 2013-10-31 |
20130285214 | POLYMERIC MATERIALS IN SELF-ASSEMBLED ARRAYS AND SEMICONDUCTOR STRUCTURES COMPRISING POLYMERIC MATERIALS - Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Semiconductor structures may include self-assembled block copolymer materials in the form of lines of half-cylinders of a minority block matrix of a majority block of the block copolymer. The lines of half-cylinders may be within trenches in the semiconductor structures. | 2013-10-31 |
20130285215 | STACKED WAFER STRUCTURE AND METHOD FOR STACKING A WAFER - A stacked wafer structure includes a substrate; dams provided on the substrate and having protrusions on a surface thereof; and a wafer with recesses provided on the dam. The protrusions on the surface of the dams are wedged into the recesses of the wafer, preventing air chambers from forming between the recesses of the wafer and the dams, so that the wafer is not separated from the dams due to the presence of air chambers during subsequent packaging process. A method for stacking a wafer is also provided. | 2013-10-31 |
20130285216 | SEMICONDUCTOR STRUCTURE HAVING LOW THERMAL STRESS - A semiconductor structure includes a Si substrate, a supporting layer and a blocking layer formed on the substrate and an epitaxy layer formed on the supporting layer. The supporting layer defines a plurality of grooves therein to receive the blocking layer. The epitaxy layer is grown from the supporting layer. A plurality of slots is defined in the epitaxy layer and over the blocking layer. The epitaxy layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer. | 2013-10-31 |
20130285217 | SUBSTRATE TREATING METHOD, TEMPORARY FIXING COMPOSITION AND SEMICONDUCTOR DEVICE - The invention provides a substrate treating method which can favorably prevent damages to a substrate when the substrate is separated from a support, thus achieving a high yield. The substrate treating method includes, in the sequence set forth, a step | 2013-10-31 |
20130285218 | INTEGRATED ELECTRONIC COMPONENTS AND METHODS OF FORMATION THEREOF - Provided are integrated electronic components which include a waveguide microstructure formed by a sequential build process and an electronic device, and methods of forming such integrated electronic components. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals. | 2013-10-31 |
20130285219 | INTEGRATED CIRCUIT POWER GRID WITH IMPROVED ROUTING RESOURCES AND BYPASS CAPACITANCE - An integrated circuit power grid is provided with improved routing resources and bypass capacitance. A power grid for an integrated circuit comprises a plurality of thick metal layers having a plurality of metal traces, wherein at least one of the thick metal layers has a lower pitch than a substantial maximum pitch allowed under the design rules for a given integrated circuit fabrication technology. A power grid for an integrated circuit can also comprise a plurality of thin metal layers having a plurality of metal traces, wherein a plurality of the metal traces on different thin metal layers are connected by at least one via, wherein the at least one via is substantially surrounded by a metal trace on at least one thin metal level connected to a different power supply voltage than a power supply of one or more additional thin metal levels. The via can be positioned, for example, at an intersection of a given standard cell row and a given vertical strap. | 2013-10-31 |
20130285220 | VERTICALLY PACKAGED INTEGRATED CIRCUIT - A device comprises a semiconductor package including a first integrated circuit (IC) die including a plurality of through silicon vias (TSVs). The TSVs are formed of conductive material that extend through the first IC die from an outer surface on a first side of the die to an outer surface of a second side of the die. The package further includes first electrical connections contacting the first side of the first IC die, and second electrical connections contacting the second side of the first IC die. The first electrical connections are independent of the second electrical connections. Molding compound encapsulates the first IC die and the first and second electrical connections. The semiconductor package is mounted on a substrate so that the first and second sides of the IC die are oriented perpendicular to the substrate. | 2013-10-31 |
20130285221 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device has a heat dissipating base; a patterned insulating substrate attached to the heat dissipating base with a solder therebetween; a semiconductor chip attached to a conductive pattern of the patterned insulating substrate with a solder therebetween; a first conductor attached to the semiconductor chip with a solder therebetween; a resin case attached to the heat dissipating base with an adhesive; and a second conductor attached to the first conductor by laser welding. The second conductor formed by rolling has stripe-shaped rolling traces formed on a surface thereof in a rolling direction and is disposed on the first conductor such that the rolling traces are arranged in a same direction. | 2013-10-31 |
20130285222 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package including: a lead frame including a chip attachment unit and a lead unit; a semiconductor chip that is mounted on the chip attachment unit of the lead frame; a wire that electrically connects the semiconductor chip to the lead unit; an insulation layer formed in the lead frame under the chip attachment unit; and an encapsulant that seals an upper portion of the lead frame, the semiconductor chip, and the wire, wherein the lead unit does not protrude to the outside of the encapsulant. | 2013-10-31 |
20130285223 | METHOD FOR MANUFACTURING ELECTRONIC DEVICES - A support structure includes a support cell with a support substrate, junction sacrificial portions surrounding the support substrate, and pin blocks extending from the junction sacrificial portion toward the support substrate. A semiconductor chip is mounted to the support substrate and electrically wire bonded to the pin blocks. An encapsulating body covers the chip, with the pin blocks extending from the body. A transversal groove is formed in each pin block. Surfaces of the pin block and groove are electroplated with solder material. Each pin block is sectioned at the groove to define a pin having a first end corresponding to a portion of the groove surface of the groove and a second end corresponding to the sectioned portion of the pin block that is not electroplated with solder material. Sectioning causes the separation of the chip-insulating body assembly from the junction sacrificial portions. | 2013-10-31 |
20130285224 | SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE - A semiconductor device includes a lead frame, an oscillator, an integrated circuit and first bonding wires. The oscillator includes plural terminals separated from each other by a predetermined distance, and that is mounted to an oscillator mounting region formed on a first face of the lead frame. The oscillator mounting region has a narrower width than the distance between the plural terminals. The integrated circuit is mounted to a second face of the lead frame, which is on an opposite side to the first face. The first bonding wires connect the plural terminals of the oscillator to terminals of the integrated circuit. | 2013-10-31 |
20130285225 | SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE - A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components. | 2013-10-31 |
20130285226 | SYSTEMS AND METHODS FOR LEAD FRAME LOCKING DESIGN FEATURES - Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle. | 2013-10-31 |
20130285227 | LEADFRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a die pad including a first surface and a second surface opposite to the first surface, a first chip arranged in a first area on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged in a second area on the first surface, the second chip including a third side and a fourth side crossing to the third side, a plurality of first marks formed on the first surface, the first marks including a third mark and a fourth mark, a plurality of second marks formed on the first surface, the second marks including a fifth mark and sixth mark. The semiconductor device also includes a wire and a resin encapsulating the first chip, the second chip, and the wire. | 2013-10-31 |
20130285228 | Glass Frit Wafer Bond Protective Structure - A bonded semiconductor device comprising a support substrate, a semiconductor device located with respect to one side of the support substrate, a cap substrate overlying the support substrate and the device, a glass frit bond ring between the support substrate and the cap substrate, an electrically conductive ring between the support substrate and the cap substrate. The electrically conductive ring forms an inner ring around the semiconductor device and the glass frit bond ring forms an outer bond ring around the semiconductor device. | 2013-10-31 |
20130285229 | THROUGH-HOLE ELECTRONIC DEVICE WITH DOUBLE HEAT-SINK - An electronic device includes a first chip and a second chip, where each chip has a first conduction terminal on a first surface and a second conduction terminal on a second surface. An insulating body surrounds the first and second chip, a first heat-sink coupled with the first conduction terminals of the first and second chip, and a second heat-sink coupled with the second conduction terminals of the first and second chip. A portion of the first heat-sink and/or the second heat-sink being exposed from the insulating body. The electronic device includes a first conductive lead and a second conductive lead exposed from the insulating body for through-hole mounting of the electronic device on an electronic board, the first conductive lead being coupled with the first heat-sink and the second conductive lead being coupled with the second heat-sink. | 2013-10-31 |
20130285230 | ELECTRONIC DEVICE - A power device includes a chip of semiconductor material and a further chip of semiconductor material on each of which at least one power transistor is integrated; each chip comprises a first conduction terminal on a first surface, and a second conduction terminal and a control terminal on a second surface opposite the first surface, and an insulating body embedding said chip and said further chip. In the solution according to one or more embodiments of the present disclosure, the first surface of said chip faces the second surface of said further chip, and the power device further comprises a first heat-sink arranged between said chip and said further chip and electrically coupled with the first conduction terminal of said chip and with the second conduction terminal of said further chip, the control terminal of said further chip being electrically insulated from the first heat-sink. | 2013-10-31 |
20130285231 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has an insulation substrate formed with a conductive pattern; an independent terminal, which is an externally leading terminal, soldered to the conductive pattern of the insulation substrate; a case disposed over the insulation substrate such that a top surface of the independent terminal is exposed; an opening provided on a side surface of the case; a nut glove inserted from the opening so as to be below the independent terminal, and fix the independent terminal; and a first projection part formed on a side surface of the nut glove, and having tapers in a frontward direction and a rearward direction of insertion of the nut glove, respectively. The rearward taper of the first projection part is pressure contacting with a sidewall surface of the opening. | 2013-10-31 |
20130285232 | SEMICONDUCTOR PACKAGE MODULE - Disclosed herein is a semiconductor package module, including: a circuit board having connection pads formed on one surface thereof; a semiconductor package including lead terminals protruded out of a housing; and an interposer positioned between the circuit board and the semiconductor package, the interposer including a body allowing the circuit board and the semiconductor package to be spaced apart from each other and elastic members contacted with the connection pads and the lead terminals. | 2013-10-31 |
20130285233 | THERMAL MANAGEMENT OF INTEGRATED CIRCUITS USING PHASE CHANGE MATERIAL AND HEAT SPREADERS - At least one feature pertains to an apparatus having passive thermal management that includes an integrated circuit die, a heat spreader thermally coupled to the integrated circuit die, a phase change material (PCM) thermally coupled to the heat spreader, and a molding compound that encases the heat spreader and the PCM. In one example, the heat spreader may include a plurality of fins, and at least a portion of the PCM is interposed between the plurality of fins. Another feature pertains to an apparatus that includes an integrated circuit die, and a molding compound having a phase change material intermixed therein. The resulting molding compound completely encases the die. | 2013-10-31 |
20130285234 | Power Module with Directly Attached Thermally Conductive Structures - A power module includes a substrate having an electrically insulative member with opposing first and second metallized sides and one or more semiconductor die attached to the first metallized side of the substrate. A plurality of thermally conductive structures are laterally spaced apart from one another and individually attached directly to the second metallized side of the substrate so that the plurality of thermally conductive structures extend outward from the second metallized side. | 2013-10-31 |
20130285235 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first heat spreader; a second heat spreader separated from the first heat spreader; a first semiconductor element on the first heat spreader and having a back face jointed to the first heat spreader; a second semiconductor element on the second heat spreader and having a back face jointed to the second heat spreader; a resin coating the first and second heat spreaders and the first and second semiconductor elements; and a reinforcing member provided across a region between the first and second heat spreaders in the resin, and having rigidity higher than rigidity of the resin. | 2013-10-31 |
20130285236 | Semiconductor Device and Method of Forming a Thin Wafer Without a Carrier - A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via. | 2013-10-31 |
20130285237 | Low Profile Interposer with Stud Structure - An interposer includes a substrate having a contact pad structure and a stud operably coupled to the contact pad structure. A solder ball is seated on the contact pad structure and formed around the stud. The stud is configured to regulate a collapse of the solder ball when a top package is mounted to the substrate. | 2013-10-31 |
20130285238 | STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES - A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure. | 2013-10-31 |
20130285239 | CHIP ASSEMBLY AND CHIP ASSEMBLING METHOD - A chip assembly includes a PCB and a chip positioned on the PCB. The PCB includes a number of first bonding pads. Each bonding pad includes two soldering balls formed thereon. The chip includes a number of second bonding pads, and each second bonding pad corresponds to a respective first bonding pad. The two soldering balls of each first bonding pad are electrically connected to a corresponding second bonding pad via two bonding wires, and the bonding wires are bonded to the second corresponding bonding pad by a wedge bonding manner. | 2013-10-31 |
20130285240 | SENSOR ARRAY PACKAGE - A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board. | 2013-10-31 |
20130285241 | Apparatus For Dicing Interposer Assembly - Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed. | 2013-10-31 |
20130285242 | PIN GRID INTERPOSER - An interposer to form a frame around a bottom chip bonded to a package substrate and to standoff a top chip or package for clearance of the bottom chip. The interposer has pins arrayed on a first side which are soldered to the package substrate for reduced interposer z-height and pads arrayed on a second side to which the top package (chip) is bonded. During assembly, the interposer pins may be pressed against pre-soldered pads and the solder reflowed to join the interposer to the package substrate. A top package (chip) is then joined to an opposite side of the interposer to integrate the first and second chips. | 2013-10-31 |
20130285243 | EASILY ASSEMBLED CHIP ASSEMBLY AND CHIP ASSEMBLING METHOD - A chip assembly includes a PCB, a connecting pad fixed on the PCB, and a chip. The connecting pad defines a through hole. The chip is received in the through hole and fixed on the PCB by an adhesive distributed in the through hole. A thickness of the adhesive is less than that of the connecting pad. | 2013-10-31 |
20130285244 | Through Silicon Via with Embedded Barrier Pad - A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like. | 2013-10-31 |
20130285245 | MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURES - A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub- | 2013-10-31 |
20130285246 | Semiconductor Device With Self-Aligned Interconnects and Blocking Portions - A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines. | 2013-10-31 |
20130285247 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD OF THE SAME - A semiconductor device capable of performing sufficient power supply while suppressing an increase in a manufacturing cost. The semiconductor device has a semiconductor substrate, a multilayer interconnection layer provided over the semiconductor substrate, an Al wiring layer that is provided over the multilayer interconnection layer and has pad parts, and a redistribution layer that is provided over the Al wiring layer and is coupled with the Al wiring layer, in which the redistribution layer is comprised of a metal material whose electric resistivity is lower than that of Al and is not formed over the pad parts. | 2013-10-31 |
20130285248 | Package Structure and Substrate Bonding Method - A substrate bonding method comprises the following steps. Firstly, a first substrate and a second substrate are provided, wherein a surface of the first substrate is covered by a first Ag layer and a surface of the second substrate is covered by a second Ag layer and a metallic layer from bottom to top, wherein the metallic layer comprises a first Sn layer. Secondly, a bonding process is performed by aligning the first and second substrates followed by bringing the metallic layer into contact with the first Ag layer followed by applying a load while heating to a predetermined temperature in order to form Ag | 2013-10-31 |
20130285249 | SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING A SEMICONDUCTOR DEVICE WITH A CLIP - A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip. | 2013-10-31 |
20130285250 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead arranged around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package collectively sealing the semiconductor chip, the island, the lead and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof. | 2013-10-31 |
20130285251 | ELONGATED VIA STRUCTURES - An integrated circuit structure comprises a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface. | 2013-10-31 |
20130285252 | PACKAGE CARRIER - A package carrier includes a metal substrate, a pad, a dielectric layer, and a circuit layer. The metal substrate has a first surface and a second surface opposite to the first surface. The pad is disposed on the first surface. The dielectric layer is disposed on the first surface and covers the pad. A thickness of the dielectric layer is less than 150 μm. The circuit layer is embedded in the dielectric layer and connected to the pads. | 2013-10-31 |
20130285253 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes: a step of forming an inorganic insulating film and an organic insulating film on one surface of a first substrate; a step of forming an opening portion by dry-etching a laminated film of them; a step of forming a bump electrode inside the opening portion; and a step (bonding step) of bonding the one surface of the first substrate having a bump electrode formed thereon and one surface of a second substrate having a bump electrode formed thereon to each other. A surface treatment on the inorganic insulating film is performed subsequent to the step of forming the opening portion but prior to the bonding step. By performing the surface treatment on the organic insulating film, connecting property between the substrates can be improved. | 2013-10-31 |
20130285254 | WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBTRATE - A wiring substrate includes a core substrate. The core substrate includes a first surface, a second surface, and an opening extending through the core substrate between the first and second surfaces. A first conductive film is formed on the first surface and covers the opening. A second conductive film is formed on the second surface. The second conductive film covers the opening. An electronic component is arranged in the opening and connected to the first conductive film. An insulator fills the opening. A first wiring portion includes alternately stacked insulative layers and wiring layers and covers the first surface of the core substrate and the first conductive film. A second wiring portion includes alternately stacked insulative layers and wiring layers, and covers the second surface of the core substrate and the second conductive film. | 2013-10-31 |
20130285255 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion. | 2013-10-31 |
20130285256 | METHOD AND AN APPARATUS FOR FORMING ELECTRICALLY CONDUCTIVE VIAS IN A SUBSTRATE, AN AUTOMATED ROBOT-BASED MANUFACTURING SYSTEM, A COMPONENT COMPRISING A SUBSTRATE WITH VIA HOLES, AND AN INTERPOSER DEVICE - A method is disclosed for forming conductive vias in a substrate by filling preformed via holes, preferably through via holes, with conductive material. The method includes providing a plurality of preformed objects at least partly including ferromagnetic material on a surface of the substrate; providing a magnetic source on an opposite side of the substrate with respect to the plurality of preformed objects, thereby at least partly aligning at least a portion of the preformed objects with a magnetic field associated with the magnetic source; and moving the magnetic source relative the substrate, or vice versa, thereby moving the at least portion of the preformed objects into at least a portion of the via holes. | 2013-10-31 |
20130285257 | 3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED WITH FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES FABRICATED USING A DUAL DAMASCENE TYPE APPROACH - A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow. | 2013-10-31 |
20130285258 | SEMICONDUCTOR DEVICE HAVING MESH-PATTERN WIRINGS - Disclosed herein is a device that includes: first lines formed on a first wiring layer extending in a first direction; second lines formed on a second wiring layer extending in a second direction; and conductor plugs connecting the first lines to the second lines such that the first and second lines form a mesh-structure wiring. The first lines include first enlarged portions at intersection positions where the first and second lines cross to each other, a width in the second direction of the first enlarged portions is wider than a line width of the first lines at other than the intersection position. The second lines include second enlarged portions at the intersection positions, a width in the first direction of the second enlarged portions is wider than a line width of the second lines at other than the intersection position. | 2013-10-31 |
20130285259 | METHOD AND SYSTEM FOR WAFER AND STRIP LEVEL BATCH DIE ATTACH ASSEMBLY - A method and system is provided by which multiple semiconductor die stacks can be assembled in a batch manner, and which also provides for die alignment tolerances required by microelectromechanical systems and other system-in-package applications. The batch process and accuracy is provided, in part, by an intermediate die attach carrier that has multiple die pockets fabricated to hold a set of die with an alignment required for the application. Die are placed in each pocket using a die sorting process. Then a batch process operation is performed in which wafer or strip-level alignment and bonding tools are used to join the die in the intermediate die attach carrier in stacks with a second set of die. | 2013-10-31 |
20130285260 | MULTI-CHIP MODULE INCLUDING STACKED POWER DEVICES WITH METAL CLIP - A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals. | 2013-10-31 |
20130285261 | SEMICONDUCTOR CHIP STACKING ASSEMBLIES - Embodiments of the invention provide semiconductor chip stacking assemblies that provide direct attachment of a first semiconductor device with a second semiconductor device. An assembly comprises a first semiconductor chip that has a first and a second set of electrical interconnect regions disposed on its surface and a second semiconductor chip. The first set of electrical interconnect regions are electrically connected with the electrical interconnect regions of a second semiconductor chip, and the second set of electrical interconnect regions are electrically interconnected with the substrate. Direct electrical connections are for example, silicon photonics device-to-driver or device-to-signal converters, logic-to-memory, memory-to-memory, and logic-to-logic chip interconnections. | 2013-10-31 |
20130285262 | DICING TAPE-INTEGRATED WAFER BACK SURFACE PROTECTIVE FILM - The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device. | 2013-10-31 |
20130285263 | SENSOR ARRAY PACKAGE - A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board. | 2013-10-31 |
20130285264 | WAFER ASSEMBLY WITH CARRIER WAFER - A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark. | 2013-10-31 |
20130285265 | OPEN AIR VEHICLE COOLING DEVICE AND METHOD - A vehicle misting device and method that is operable is dry and humid environments are provided. The device may also include a payment system and fan. | 2013-10-31 |
20130285266 | APPARATUS FOR RECOVERING PROCESS EXHAUST ENERGY - The present disclosure provides for an apparatus for recovering exhaust energy. The apparatus is generally provided with a waste energy stream inlet for directing an incoming waste heat energy stream from a waste energy stream generator, a heat exchanger in fluid communication with the waste energy stream inlet, a waste energy stream outlet distal from the waste energy stream inlet, a recycled energy stream outlet operatively connected and in fluid communication with said air flow that receives heat, and collecting means. | 2013-10-31 |
20130285267 | FABRICATION METHOD OF NANOPARTICLE - A fabrication method of nanoparticles is provided. A substrate having a plurality of pillar structures is provided and then a plurality of ring structures is formed to surround the plurality of the pillar structures. The inner wall of each ring structure surrounds the sidewall of each pillar structure. A portion of each pillar structure is removed to reduce the height of each pillar structure and to expose the inner wall of each ring structure. The ring structures are separated from the pillar structures to form a plurality of nanoparticles. Surface modifications are applied to the ring structures before the ring structures are separated from the pillar structures on the substrate. | 2013-10-31 |
20130285268 | SYSTEMS AND METHODS FOR MANUFACTURING ORTHODONTIC APPLIANCES - A system for debinding a green body in the form of an orthodontic appliance may include a pressure vessel configured to contain a supercritical fluid. A source of a fluid chemical may be coupled to the pressure vessel to supply the fluid chemical to the pressure vessel. A heat source may be configured to heat the fluid chemical. A pump may pressurize the fluid chemical to at least the supercritical pressure. A collection vessel is coupled to the pressure vessel to capture the binder removed from the green bodies as at least the pressure of the supercritical fluid is reduced. A method of manufacturing an orthodontic appliance includes exposing green bodies including particles and a binder to a supercritical fluid to remove at least some of the binder from the green bodies, and collecting the removed binder from the supercritical fluid as the supercritical fluid transitions to a non-supercritical fluid. | 2013-10-31 |
20130285269 | METHOD FOR MANUFACTURING BALL JOINT - Provided is an apparatus and method for manufacturing a ball joint that are capable of reducing a torque applied between a ball stud and a ball seat. | 2013-10-31 |
20130285270 | TRANSFER APPARATUS AND METHOD OF MANUFACTURING ARTICLE - A transfer apparatus transfers a pattern of an original to a resin on a shot region of a substrate. The original includes a first surface and second surface which are surfaces opposite to each other. The first surface includes a pattern region where the pattern is formed, and the second surface includes a holding surface. The apparatus includes a plurality of holding units configured to hold the holding surface of the original, a plurality of driving units configured to drive the plurality of holding units, respectively, and a control unit configured to control driving of the plurality of holding units by the plurality of driving units to align the pattern region with the shot region of the substrate. | 2013-10-31 |
20130285271 | Melt Devolatilization Extrusion Process - Thermally sensitive polymers containing polymerizable carbon-carbon unsaturation and/or aliphatically bound halogen are devolatilized in a devolatilizing extruder. The thermally sensitive polymer is blended with a second polymer, which does not contain polymerizable carbon-carbon unsaturation or more than 5% by weight aliphatically bound halogen, and which has a molecular weight of from 25,000 to 175,000. The blend is then devolatilized in the extruder to produce a devolatilized polymer blend. Thermal degradation of the thermally sensitive polymer is minimized in this process. | 2013-10-31 |
20130285272 | CONTAINER MODIFICATIONS TO MINIMIZE DEFECTS DURING REACTIVE POLYURETHANE FLOW - A method of reducing the number or size of voids in a polyurethane comprises reacting the formulation components in a container having an inner surface, or having a liner that has an inner surface, that has been modified to reduce the shear forces that normally accompany introduction of such components into a container. This is done by modifying the inner container's or container liner's surface by profiling and/or engraving it, or by including as a liner a mesh. The profiling and/or engraving or mesh serves to alter the formulation's flow dynamics such that the polyurethane has fewer and/or smaller voids, i.e., has a more uniform density, than polyurethanes formed without the modification. | 2013-10-31 |
20130285273 | KNEADING APPARATUS, METHOD FOR PRODUCING THERMOPLASTIC RESIN MOLDED PRODUCT, AND FOAM INJECTION MOLDING METHOD - A kneading apparatus for a thermoplastic resin, includes: a plasticizing cylinder which has a high pressure kneading zone and a pressure reduction zone; a screw in the plasticizing cylinder; a downstream side seal mechanism which shuts off communication between the high pressure kneading zone and the pressure reduction zone; and a pressure reduction zone pressure adjusting mechanism which is connected to the pressure reduction zone and which controls a pressure of the pressure reduction zone so that the pressure is not less than an atmospheric pressure and the pressure is not more than a maximum pressure of the high pressure kneading zone that is achieved when kneading a molten resin with a pressurized fluid, when the downstream side seal mechanism shuts off the communication between the high pressure kneading zone and the pressure reduction zone. | 2013-10-31 |
20130285274 | METHODS AND APPARATUS FOR PROCESSING POLYMERS - A method and apparatus for controlling processing temperatures and the activation of polymer by way of machine to control, and control to machine signalling, that allows heat energy compensation for polymer heat energy loss. This is useful when a lower temperature substance, like water is added to expand natural or man made polymers within short distances like that of a nozzle. | 2013-10-31 |
20130285275 | METHOD AND APPARATUS FOR MANUFACTURING MELT-BLOWN FABRIC WEB HAVING RANDOM AND BULKY CHARACTERISTICS - Disclosed is a method and apparatus for manufacturing a melt-blown fabric web, by which a melt-blown fabric web having improved filament cohesion and excellent bulky characteristics and sound-absorbing performance is manufactured. The apparatus includes a heat extruder for heating a thermoplastic resin composition and extruding the melted thermoplastic resin, a melt-blown fiber spinner for spinning the extruded thermoplastic resin as a melt-blown fiber in a filament form, a variable gas injector for injecting gas whose injection speed and injection quantity are continuously changed at random to the melt-blown fiber spun from the melt-blown fiber spinner to cause the injected gas to collide with the spun melt-blown fiber, and a collector for collecting the melt-blown fiber, which is spun from the melt-blown fiber spinner and collides with the gas, to form a melt-blown fabric web. | 2013-10-31 |
20130285276 | METHOD FOR STARTING UP A PROCESSING PLANT FOR PRODUCING PLASTICS MATERIAL GRANULATE AND PROCESSING PLANT FOR PRODUCING PLASTICS MATERIAL GRANULATE - In a processing plant for producing plastics material granulate, the start-up takes place in such a way that a screw machine is firstly driven by means of a drive device and then plastics material to be processed is fed by means of a metering device into the screw machine. At least one conveying position of the plastics material in the screw machine is determined by means of a control device by evaluating at least one measuring signal. Depending on the conveying position determined, a granulating device is activated and put into operation. The method according to the invention allows a direct start-up of the processing plant without the use of a start-up valve. This ensures an easy and safe start-up of the processing plant. | 2013-10-31 |
20130285277 | Oxygen Scavenging Compositions, Articles Containing Same, and Methods of Their Use - The disclosure relates to transition metal compositions, methods of making the compositions, articles prepared from the compositions, and methods of making the articles. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present invention. | 2013-10-31 |
20130285278 | PATCH ANTENNA AND METHOD OF MAKING THE SAME - A patch antenna includes: a dielectric layer made of an insulation material, and having upper and lower surfaces, and a through hole; a radiation metal layer disposed on the upper surface of the dielectric layer, and having a first plate body, a first aperture aligned with the through hole, and a first protruding portion extending from a peripheral edge of the first aperture into the through hole; and a grounding metal layer disposed on the lower surface of the dielectric layer, and having a second plate body, a second aperture aligned with the through hole, and a second protruding portion extending from a peripheral edge of the second aperture into the through hole. The first and second protruding portions contact each other in the through hole so that the radiation and grounding metal layers are electrically connected. A method of making a patch antenna is also disclosed. | 2013-10-31 |
20130285279 | INTEGRATED SINGLE AND TWIN SCREW EXTRUDER - An extruder is disclosed, and more particularly, to an integrated single screw extruder and a twin screw extruder for mixing, compounding, kneading and/or extruding of materials. The integrated extruder includes a first barrel assembly and a second barrel assembly. The integrated extruder further includes a first screw having a first threaded portion and a second threaded portion. The first threaded portion is housed within the first barrel assembly and is configured to provide upstream material processing. The second threaded portion is housed within the second barrel assembly and is configured to provide downstream material processing. The integrated extruder further includes a second screw having a non-threaded shaft portion and a threaded portion. The threaded portion of the second screw is housed within the second barrel assembly and is configured to provide the downstream material processing with the second threaded portion of the first screw. | 2013-10-31 |
20130285280 | OPTICAL COMPENSATION FILM, AND POLARIZING PLATE AND LIQUID CRYSTAL DISPLAY EMPLOYING THE SAME - The present invention provides an optical compensation film, which has excellent visibility such as light leakage, uneven color tone and front contrast, and can simultaneously realize retardation and wavelength dispersion. The optical compensation film is characterized by containing a cellulose ester, the following polymer (a), and the following compound (b). (a) A polymer produced by copolymerizing an ethylenically unsaturated monomer having in its molecule a partial structure represented by Formula (1) with at least one ethylenically unsaturated monomer. (b) An esterified compound produced by esterifying all or a part of OH groups in a compound (A) having one furanose structure or one pyranose structure, or an esterified compound produced by esterifying all of or a part of OH groups in a compound (B) containing nor less than 2 and not more than 12 structures of at least one of a furanose structure or a pyranose structure. | 2013-10-31 |
20130285281 | Die Assembly And Method Of Extruding Cellular Ceramic Substrates With A Skin - An extrusion apparatus including a die and a mask are provided such that no slots feed directly into the longitudinal skin forming gap between the mask and the die. In a method of forming a die adapted to improve skin uniformity of extruded cellular ceramic substrates a slotted block of die material is provided including central slots adapted to form a cellular matrix of the substrate and peripheral slots located outwardly of the central slots designed to be covered by a skin former mask and adapted to extrude peripheral batch material. An arcuate skin former is cut corresponding to a target shrinkage so as to intersect the slotted block such that skin flow from tangent slots at 90 degree positions of the die is limited to the peripheral batch material. | 2013-10-31 |
20130285282 | Moulding Method - There is disclosed a method for producing a moulded plastic product having an outer skin and in inner core. The method is particularly suitable for making structural products such as panels or the like from recycled plastic material. The method comprises the steps of: providing a mould having a mould cavity; forming an outer skin from a first plastic material on at least two opposed surfaces inside the mould cavity; forming an inner core from a second plastic material inside the mould cavity; and at least partially curing the plastic materials to form a moulding inside the mould cavity via the application of heat. The method is characterised by the subsequent steps of (optionally pre-cooling the moulding and then) simultaneously cooling the moulding and compressing the moulding so as to reduce its size in at least one dimension to a desired dimension of the finished product. | 2013-10-31 |
20130285283 | MOLD ADAPTED TO RECEIVE A PREFORM OF A COMPOSITE PART AND CORRESPONDING MOLDING METHOD - A mould including: a central core having a side wall with a plane external surface; an internal mould element having an internal surface facing the external surface of the central core, with surfaces inclined to the vertical in order to form an angle of clearance, and a substantially vertical external surface; an external mould element fitted against the internal mould element and having a substantially vertical internal surface facing the external surface of the internal mould element; at least one of the facing surfaces being designed to receive a substantially vertical lateral preform so that the internal mould element and the external mould element are suitable for clamping said lateral preform. | 2013-10-31 |
20130285284 | MODULE FOR HOLDING AT LEAST ONE BUSHING | 2013-10-31 |
20130285285 | TRANSFERRING SYSTEM AND TRANSFERRING METHOD - A transfer system ( | 2013-10-31 |
20130285286 | LIPID-BASED WAX COMPOSITIONS SUBSTANTIALLY FREE OF FAT BLOOM AND METHODS OF MAKING - Lipid-based wax compositions and their methods of making are provided for compositions substantially free of fat bloom. The compositions comprise approximately 7-80 percent by weight triacylglycerides and approximately 20-93 percent by weight monoacylglycerides and diacylglycerides combined. The methods comprise blending the monoacylglycerides, diacylglycerides, and triacylglycerides in the lipid-based wax composition by heating the lipid-based wax composition at a sufficiently high temperature to destroy substantially all crystal structure within the lipid-based wax composition. The methods further comprise pouring the lipid-based wax composition into a mold or a container having a surface and a core, wherein the pouring is conducted at a temperature at least 15° C. greater than the congeal point of the lipid-based wax composition. The methods further comprise cooling the lipid-based wax composition under conditions sufficient to cool the core to at least 5° C. below the congeal point of the lipid-based wax composition in approximately 30-90 minutes. | 2013-10-31 |
20130285287 | Mold Plate And Method Of Molding Golf Ball Core - A mold for manufacturing hemispherical sections for a golf ball includes a mold plate and a movable insert. The mold plate includes a first surface. The movable insert includes a second surface. The movable insert is connected to the mold plate. The first surface of the mold plate and the second surface of the movable insert may move relative to one another during molding of a hemispherical section for a golf ball. | 2013-10-31 |
20130285288 | COMPRESSION MOULDING THERMOPLASTIC - An apparatus includes one or more die groups which are movable independently of one another, each including a female part having a matrix cavity and a male part destined to penetrate into the cavity such as to define a forming chamber of the product, the cavity configured to contain a batch of material. The apparatus further includes a heating station having a heater to bring the plastic material to the fluid state, and a die group cooling station downstream of the heating station. The die groups are free to be cyclically inserted in the heating station and subsequently transferred to the cooling station. A thrust group is associated to a respective die group and is configured to provide a thrust for penetrating the male part into the cavity during the stage of forming the product, the thrust group being integral with the respective die-group in displacements during the operations performed. | 2013-10-31 |
20130285289 | METHOD FOR MAKING CARBON NANOTUBE FILM - A method for making a carbon nanotube film includes the following steps. An original carbon nanotube film is provided and includes a number of carbon nanotubes substantially joined end-to-end by van der Waals force and oriented along a first direction. A patterned carbon nanotube film is formed and defines a number of through holes arranged in at least one row in the first direction, the through holes of the at least one row includes at least two spaced though holes. The patterned carbon nanotube film is treated with a solvent such that the patterned carbon nanotube film is shrunk into the carbon nanotube film includes a number of spaced carbon nanotube linear units and a number of carbon nanotube groups, and the carbon nanotube groups are joined with the carbon nanotube linear units by van der Waals force. | 2013-10-31 |
20130285290 | LASER IRRADIATION DEVICE AND METHOD OF FABRICATING ORGANIC LIGHT EMITTING DISPLAY DEVICE USING THE SAME - A laser irradiation device and a method of fabricating an organic light emitting display device (OLED) using the same are disclosed. The laser irradiation device includes: a laser source generating a laser beam; a mask disposed below the laser source and patterning the beam and a projection lens disposed below the mask and determining magnification of the laser beam through the mask, wherein the laser beam penetrating the mask has different doses in at least two regions. Thus, the laser irradiation device can maximize emission efficiency and enhance the quality of a transfer layer pattern when an organic layer of the OLED is formed using the laser irradiation device. | 2013-10-31 |