44th week of 2013 patent applcation highlights part 17 |
Patent application number | Title | Published |
20130285091 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a method for manufacturing a semiconductor light emitting device includes steps for forming a fluorescent substance layer on a first face of a semiconductor layer and forming a light shielding film on the side face of the fluorescent substance layer. The fluorescent substance layer includes a resin and fluorescent substances dispersed in the resin, and have a light emitting face on a side opposite to the first face of the semiconductor layer and a side face connecting to the light emitting face with an angle of 90 degree or more between the light emitting face and the side face. The light shielding film shields a light emitted from a light emitting layer included in the semiconductor layer and a light radiated from the fluorescent substances. | 2013-10-31 |
20130285092 | LIGHT EMITTING DIODE - A light emitting diode includes a substrate, graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, a second electrode, and a reflection layer. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked on the substrate in sequence. The first electrode is electrically connected with the second semiconductor layer and the second electrode electrically is connected with the second part of the carbon nanotube layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer. The reflection layer covers the second semiconductor layer. | 2013-10-31 |
20130285093 | LIGHT EMITTING DIODE PACKAGE STRUCTURE HAVING A SUBSTRATE INCLUDING CERAMIC FIBERS - An LED package structure includes a substrate and an LED chip formed on the substrate. The substrate has a first electrode and a second electrode formed on an upper surface thereof. The LED chip is formed on the first electrode of the substrate and electrically connected with the first electrode and the second electrode respectively. The substrate is made of a composite including a base material and ceramic fibers mixed in the base material. | 2013-10-31 |
20130285094 | LIGHT EMITTING DIODE LIGHT SOURCE DEVICE - An LED light source device includes an LED light source, a first translucent structure covering the LED light source and a second translucent structure covering the first translucent structure. An interior of the first translucent structure has light scattering powder distributed therein. The LED light source is embedded in the first translucent structure. The LED light source is covered by the light scattering powder. The second translucent structure has a radius of R and an index of refraction of N | 2013-10-31 |
20130285095 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, a third semiconductor layer between the active layer and the second conductive semiconductor layer, and a light extraction structure on the second conductive semiconductor layer. A top surface of the third semiconductor layer has a Ga-face. | 2013-10-31 |
20130285096 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light emitting diode (LED) package comprises: providing a substrate having a first electrode and a second electrode electrically insulated from the first electrode, wherein an LED die is mounted on the first electrode and electrically connected to the first electrode and the second electrode; forming a first encapsulant layer on the substrate to encapsulate the LED die therein, the first encapsulant layer being colloidal; forming a nitride compound phosphor layer distributed on an outer face of the first encapsulant layer; and heating the first encapsulant layer to solidify the first encapsulant layer. A second encapsulant layer is formed on the nitride compound phosphor layer to encapsulate the first encapsulant layer. An LED package formed by the method is also provided. | 2013-10-31 |
20130285097 | SIDE-VIEW LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A side-view LED package includes a substrate, a pair of electrodes connected to the substrate, an LED die electrically connected to the electrodes, a reflective cup formed on the substrate, an opening defined at a lateral side of the reflective cup, an encapsulation formed on the substrate to cover the LED die, and a reflective layer coated on a top of the encapsulation and a top of the reflective cup, wherein part of light emitting from the LED die is reflected by the reflective cup and the reflective layer and then emits out of the side-view LED package from the opening. The present disclosure also provides a method for manufacturing the side-view LED package described above. | 2013-10-31 |
20130285098 | PATTERNED SUBSTRATE AND LIGHT EMITTING DIODE STRUCTURE - A patterned substrate includes a substrate and a plurality of protrusions. The protrusions are formed on the substrate. Each protrusion has a top face and a base. Each pair of immediately adjacent protrusions is minimally parted by 0 to 0.2 μm. When the distance between the adjacent protrusions falls as 0 μm, the bases thereof contact each other. A horizontal and a vertical light emitting diode structures using the patterned substrate are also discussed. | 2013-10-31 |
20130285099 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light-emitting element includes: a laminated semiconductor layer in which an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer are laminated; a transparent conductive layer laminated on the p-type semiconductor layer of the laminated semiconductor layer and composed of a metal oxide having optical transparency to light emitted from the light-emitting layer; an insulating reflation layer laminated on the transparent conductive layer in which plural opening portions are provided to expose part of the transparent conductive layer; a metal reflection layer formed on the insulating reflection layer and inside the opening portions and composed of a metal containing aluminum; and a metal contact layer provided between the part of the transparent conductive layer exposed at the opening portion and the part of the metal reflection layer formed inside the opening portion, which contains an element selected from Group VIA and Group VIII of a periodic table. | 2013-10-31 |
20130285100 | Method for Producing a Conversion Lamina and Conversion Lamina - A method for producing at least one conversion lamina for a radiation-emitting semiconductor component is specified. A base material including a conversion substance contained therein is applied to a substrate by means of a double-layered stencil. Furthermore, a conversion lamina for a radiation-emitting semiconductor component includes a base material and a conversion substance embedded therein. The thickness of the conversion lamina is in a range of between 60 μm and 170 μm inclusive. | 2013-10-31 |
20130285101 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, a film covering a side face of the first metal pillar and a side face of the second metal pillar, and a resin layer. The semiconductor layer includes a light emitting layer, a first major surface, and a second major surface formed on a side opposite to the first major surface. The film has a solder wettability poorer than a solder wettability of the first metal pillar and a solder wettability of the second metal pillar. The resin layer covers at least part of the film. | 2013-10-31 |
20130285102 | Light-Emitting Diode (LED) Module with Light Sensor Configurations for Optical Feedback - An embodiment of the disclosure includes a LED module. A substrate is provided. A light sensor is positioned in the substrate. A LED chip is attached to the substrate. The LED chip has a first side and a second side. The second side is covered by an opaque layer with an opening. The opening is substantially aligned with the light sensor. The light sensor receives a light output emitting from the LED chip through the opening. | 2013-10-31 |
20130285103 | LIGHT EMITTING ELEMENTS, LIGH EMITTING DEVICES INCLUDING LIGHT EMITTING ELEMENTS AND METHODS OF MANUFACTURING SUCH LIGHT EMITTING ELEMENTS AND/OR DEVICES - An emitting device including a first electrode, a second electrode spaced apart from the first electrode, an emitting pattern including a portion between the first electrode and the second electrode, and a block pattern including a portion between the emitting pattern and the first electrode and/or on a same level as the first electrode. | 2013-10-31 |
20130285104 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - Provided is a light-emitting device that has a high emission efficiency, excellent stability and temperature properties, and that generates light having a high color rendering property sufficient for practical use. This semiconductor light-emitting device ( | 2013-10-31 |
20130285105 | LIGHT EMITTING DIODE - A light emitting diode includes a substrate, graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer is on the epitaxial growth layer of the substrate. The active layer is between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected with the second semiconductor layer and the second electrode electrically is connected with the second part of the carbon nanotube layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer. | 2013-10-31 |
20130285106 | LIGHT EMITTING DIODE - A light emitting diode includes a graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked with each other in sequence. The first electrode is located on and electrically connected with the second semiconductor layer. The second electrode is located on and electrically connected with the first semiconductor layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer. | 2013-10-31 |
20130285107 | SOLID STATE LIGHTING DEVICES WITH ACCESSIBLE ELECTRODES AND METHODS OF MANUFACTURING - Various embodiments of light emitting dies and solid state lighting (“SSL”) devices with light emitting dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a light emitting die includes an SSL structure configured to emit light in response to an applied electrical voltage, a first electrode carried by the SSL structure, and a second electrode spaced apart from the first electrode of the SSL structure. The first and second electrode are configured to receive the applied electrical voltage. Both the first and second electrodes are accessible from the same side of the SSL structure via wirebonding. | 2013-10-31 |
20130285108 | Light Emitting Device, Light Emitting Device Package Comprising the Same and Lighting System - A light emitting device including a light emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a first electrode disposed on the first conductive semiconductor layer, a conductive layer disposed on the second conductive semiconductor layer, a second electrode disposed on the conductive layer, a channel layer directly contacts with the light emitting structure and disposed at an adjacent region of the second electrode, a support substrate disposed on the channel layer, and wherein the conductive layer is separated into at least two unit conductive layers. | 2013-10-31 |
20130285109 | SAPPHIRE SUBSTRATE AND SEMICONDUCTOR - A sapphire substrate having a principal surface for growing a nitride semiconductor to form a nitride semiconductor light emitting device comprises a plurality of projections on the principal surface. Each of the projections has a bottom that has a substantially polygonal shape. Each side of the bottom of the projections has a depression in its center. Vertexes of the bottoms of the respective projections extend in a direction that is within a range of ±10 degrees of a direction that is rotated counter-clockwise by 30 degrees from a crystal axis “a” of the sapphire substrate. | 2013-10-31 |
20130285110 | SELECT DEVICES INCLUDING AN OPEN VOLUME, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices. | 2013-10-31 |
20130285111 | DIODE-TRIGGERED SILICON CONTROLLED RECTIFIER WITH AN INTEGRATED DIODE - Device structures, design structures, and fabrication methods for a silicon controlled rectifier. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. A doped region of a second conductivity type is formed in the well. A cathode of a silicon controlled rectifier and a cathode of a diode are formed in the device region. The silicon controlled rectifier comprises a first portion of the well and an anode comprised of a first portion of the doped region. The diode comprises a second portion of the well and an anode comprised of a second portion of the doped region. | 2013-10-31 |
20130285112 | HIGH-TRIGGER CURRENT SCR - An SCR includes a first doped region of a first type having a first doping concentration. A first well of the first type and a first well of a second type are disposed in upper areas of the first doped region of the first type such that the first well of the second type is laterally spaced from the first well of the first type by a non-zero distance. A second doped region of the first type has a second doping concentration that is greater than the first doping concentration and is disposed in the first well of the second type to form an anode of the SCR. A first doped region of the second type is disposed in the first well of the first type and forms a cathode of the SCR. | 2013-10-31 |
20130285113 | BIDIRECTIONAL ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE - A bidirectional electrostatic discharge (ESD) protection device includes a substrate having a topside semiconductor surface that includes a first silicon controlled rectifier (SCR) and a second SCR formed therein including a patterned p-buried layer (PBL) including a plurality of PBL regions. The first SCR includes a first and second n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a first merged drain. The second SCR includes a third and a fourth n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a second merged drain. The plurality of PBL regions are directly under at least a portion of the sources while being excluded from being directly under either of the merged drains. | 2013-10-31 |
20130285114 | TWIN-WELL LATERAL SILICON CONTROLLED RECTIFIER - A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the semiconductor surface by a lateral spacing distance. A first n+ diffusion region and a first p+ diffusion region are in the first nwell. A second n+ diffusion region is in the second nwell. A second p+ diffusion is between the first nwell and second nwell which provides a contact to the semiconductor surface. Dielectric isolation is between the first n+ diffusion region and first p+ diffusion region, along a periphery between the first nwell and the semiconductor surface, and along a periphery between the second nwell and the semiconductor surface. A resistor provides coupling between the second n+ diffusion region and second p+ diffusion. | 2013-10-31 |
20130285115 | EPTAXIAL STRUCTURE - An epitaxial structure includes a substrate having an epitaxial growth surface, a first epitaxial layer, a graphene layer and a second epitaxial layer. The first epitaxial layer is stacked on the epitaxial growth surface. The graphene layer is coated on the first epitaxial layer. The second epitaxial layer is located on the first epitaxial layer and covers the graphene layer. | 2013-10-31 |
20130285116 | Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication - Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures. | 2013-10-31 |
20130285117 | CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION - A thin-body SOI CMOS structure and method for fabricating thin-body SOI CMOS structures with Si channels for NFETs and SiGe/Si or SiGe channels for PFETs. The CMOS structure imparts beneficial channel stress to PFETs while not degrading NFETs and leading to beneficial higher gate capacitance for PFETs. | 2013-10-31 |
20130285118 | CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION - A thin-body SOI CMOS structure and method for fabricating thin-body SOI CMOS structures with Si channels for NFETs and SiGe/Si or SiGe channels for PFETs. The CMOS structure imparts beneficial channel stress to PFETs while not degrading NFETs and leading to beneficial higher gate capacitance for PFETs. | 2013-10-31 |
20130285119 | PSEUDOMORPHIC HIGH ELECTRON MOBILITY TRANSISTOR (pHEMT) COMPRISING LOW TEMPERATURE BUFFER LAYER - A pseudomorphic high electron mobility transistor (pHEMT) comprises: a substrate comprising a Group III-V semiconductor material; buffer layer disposed over the substrate; and a channel layer disposed over the buffer layer. The buffer layer comprises microprecipitates of a Group V semiconductor element. A method of fabricating a pHEMT is also described. | 2013-10-31 |
20130285120 | BIPOLAR TRANSISTOR HAVING COLLECTOR WITH GRADING - This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. One aspect of this disclosure is a bipolar transistor that includes a collector having a high doping concentration at a junction with the base and at least one grading in which doping concentration increases away from the base. In some embodiments, the high doping concentration can be at least about 3×10 | 2013-10-31 |
20130285121 | BIPOLAR TRANSISTOR HAVING COLLECTOR WITH DOPING SPIKE - This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers. | 2013-10-31 |
20130285122 | ELECTRONIC DEVICE - According to one embodiment, an electronic device includes a drive circuit on a semiconductor substrate, an insulating region including a first insulating part provided on the semiconductor substrate and formed of interlayer insulating films, and a second insulating part provided on the first insulating part, an element for a high-frequency provided on the insulating region and driven by the drive circuit, an interconnect including a first conductive part in the first insulating part, and a second conductive part in the second insulating part, and transmitting a drive signal from the drive circuit to the element, a first shield provided inside the insulating region and below the element, and a second shield provided inside the insulating region and below the second conductive part. | 2013-10-31 |
20130285123 | TRANSISTOR WITH IMPROVED SIGMA-SHAPED EMBEDDED STRESSOR AND METHOD OF FORMATION - A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure. | 2013-10-31 |
20130285124 | JFET DEVICE STRUCTURES AND METHODS FOR FABRICATING THE SAME - In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source. | 2013-10-31 |
20130285125 | Through-Substrate Vias and Methods for Forming the Same - A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is disposed over and electrically connected to the source/drain region. A gate contact plug is disposed over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the top portion of the source/drain contact plug. A Through-Substrate Via (TSV) extends into the semiconductor substrate. A top surface of the TSV is substantially level with an interface between the gate contact plug and the gate electrode. | 2013-10-31 |
20130285126 | NARROW BODY FIELD-EFFECT TRANSISTOR STRUCTURES WITH FREE-STANDING EXTENSION REGIONS - Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem. | 2013-10-31 |
20130285127 | semiconductor structure and method of manufacturing the same - The present application discloses a method for manufacturing a semiconductor structure, comprises the following steps: providing a substrate and forming a gate stack on the substrate; forming an offset spacer surround the gate stack and a dummy spacer surround the offset spacer; forming the S/D region on both sides of the dummy spacer; removing the dummy spacer and portions of the offset spacer on the surface of the substrate; forming a doped spacer on the sidewall of the offset spacer; forming the S/D extension region by allowing the dopants in doped spacer into the substrate; removing the doped spacer. Accordingly, the present application also discloses a semiconductor structure. In the present disclosure the S/D extension region with high doping concentration and shallow junction depth is formed by the formation of a heavily doped doped spacer, which can be removed in the subsequent procedures, in order to efficiently improve the performance of the semiconductor structure. | 2013-10-31 |
20130285128 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are disclosed. A fin of the semiconductor device including a fin-shaped channel region is configured in the form of a non-uniform structure, and a leakage current caused by the electric field effect generated in the semiconductor device is prevented from being generated, resulting in an increased operation stability of the semiconductor device. | 2013-10-31 |
20130285129 | PULSED LASER ANNEAL PROCESS FOR TRANSISTORS WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN - A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth. | 2013-10-31 |
20130285130 | BACKSIDE ILLUMINATED IMAGE SENSOR WITH NEGATIVELY CHARGED LAYER - A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these. | 2013-10-31 |
20130285131 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS - A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of aMOS transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of aMOS transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion. | 2013-10-31 |
20130285132 | Semiconductor Module With a Semiconductor Chip and a Passive Component and Method for Producing the Same - A semiconductor module includes a semiconductor chip and a passive discrete component. The semiconductor chip includes on its top side and/or on the back side one or more contacts, which in its two-dimensional extent takes up the top side and/or the back side of the semiconductor chip virtually completely. The passive component, arranged in a package, is stacked on one of the contacts. The electrode of the passive component is electrically connected with one of the contacts. The counter electrode of the passive component is operatively connected with a control or signal electrode of the semiconductor chip or an electrode of a further semiconductor chip. | 2013-10-31 |
20130285133 | NON-VOLATILE MEMORY DEVICE FORMED BY DUAL FLOATING GATE DEPOSIT - A method includes forming a shallow trench isolation (STI) region in a substrate; depositing a first material such that the first material overlaps the STI region and a portion of a top surface of the STI region is exposed; etching a recess in the STI region by a first etch, the recess having a bottom and sides; depositing a second material over the first material and on the sides and bottom of the recess in the STI region; and etching the first and second material by a second etch to form a floating gate of the device, wherein the floating gate extends into the recess. | 2013-10-31 |
20130285134 | NON-VOLATILE MEMORY DEVICE FORMED WITH ETCH STOP LAYER IN SHALLOW TRENCH ISOLATION REGION - A method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate. | 2013-10-31 |
20130285135 | Semiconductor Device with Semiconductor Fins and Floating Gate - According to one exemplary implementation, a semiconductor device includes a channel, a source, and a drain situated in a first semiconductor fin. The channel is situated between the source and the drain. The semiconductor device also includes a control gate situated in a second semiconductor fin. A floating gate is situated between the first semiconductor fin and the second semiconductor fin. The semiconductor device can further include a first dielectric region situated between the floating gate and the first semiconductor fin and a second dielectric region situated between the floating gate and the second semiconductor fin. | 2013-10-31 |
20130285136 | Schottky diode with enhanced breakdown voltage - An apparatus of and method for making enhanced Schottky diodes having p-body regions operable to pinch a current flow path in a high-voltage n-well region and field plate structures operable to distribute an electric potential of the Schottky diode allow for a device with enhanced breakdown voltage properties. N-well regions implanted into the substrate over a p-type epitaxial layer may act as an anode of the Schottky diode and n-type well regions implanted in the high-voltage n-well regions may act as cathodes of the Schottky diode. The Schottky diode may also be used as a low-side mosfet structure device. | 2013-10-31 |
20130285137 | PROGRAMMABLE SCR FOR LDMOS ESD PROTECTION - A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type ( | 2013-10-31 |
20130285138 | Method of Fabricating Tunnel Transistors With Abrupt Junctions - A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials. | 2013-10-31 |
20130285139 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current. | 2013-10-31 |
20130285140 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device includes a gate electrode embedded into a trench penetrating a base region. The gate electrode is disposed into a lattice shape in a planar view, and a protective diffusion layer is formed in a drift layer at the portion underlying thereof. At least one of blocks divided by the gate electrode is a protective contact region on which the trench is entirely formed. A protective contact for connecting the protective diffusion layer at a bottom portion of the trench and a source electrode is disposed on the protective contact region. | 2013-10-31 |
20130285141 | Multi-Gate Devices with Replaced-Channels and Methods for Forming the Same - A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other. | 2013-10-31 |
20130285142 | NARROW BODY FIELD-EFFECT TRANSISTOR STRUCTURES WITH FREE-STANDING EXTENSION REGIONS - Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem. | 2013-10-31 |
20130285143 | Integrated Circuit Devices Including Stress Proximity Effects and Methods of Fabricating the Same - An integrated circuit can include first and second FETs of a particular conductivity type on a substrate, wherein a first source/drain region of the first FET is closer to a center of a first channel region of the first FET than a second source/drain region of the second FET is to a center of a second channel region of the second FET. | 2013-10-31 |
20130285144 | DUAL POLYSILICON GATE OF A SEMICONDUCTOR DEVICE WITH A MULTI-PLANE CHANNEL - A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, and a channel region with a protrusion structure formed in the substrate of the first region, a gate insulating layer formed over the substrate, a first polysilicon layer filling the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region. | 2013-10-31 |
20130285145 | FORMATION OF MULTI-HEIGHT MUGFET - A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure and a second rectangular fin structure, both positioned on a substrate. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. A gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The gate conductor is positioned adjacent to a relatively larger portion of the sides of the second rectangular fin structure and is positioned adjacent to a relatively smaller portion of the sides of the first rectangular fin structure. | 2013-10-31 |
20130285146 | SEMICONDUCTOR DEVICES - Semiconductor devices include a substrate, a first gate structure and a second gate structure positioned on the substrate, and a first source/drain formed in the substrate respectively at two sides of the first gate structure and a second source/drain formed in the substrate respectively at two sides of the second gate structure. The first gate structure and the second gate structure include a same conductivity type. The first source/drain and the second source/drain are different. | 2013-10-31 |
20130285147 | COMPACT TID HARDENING NMOS DEVICE AND FABRICATION PROCESS - A radiation-hardened transistor is formed in a p-type semiconductor body having an active region doped to a first level and surrounded by a dielectric filled shallow trench isolation region. N-type source/drain regions are disposed in the active region and spaced apart to define a channel. A gate is disposed above the channel, and is self-aligned with the source/drain regions. First and second p-type regions are disposed in the p-type semiconductor body on either side of one of the source/drain regions and are doped to a second level higher than the first doping level. The first and second p-type regions are self aligned with and extend outwardly from a first side edge of the gate. The ends of the gate extend past the first and second p-type regions. | 2013-10-31 |
20130285148 | SEMICONDUCTOR DEVICE MANUFACTURE METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes: forming a first active region and a second active region in a semiconductor substrate; forming a first gate insulating film on the first active region and a second gate insulating film thinner than the first gate insulating film on the second active region by using material containing silicon oxide; forming first and second gate electrodes on the first and second gate insulating films respectively; forming an insulating film on the semiconductor substrate, and anisotropically etching the insulating film to leave first side wall insulating films on side walls of the first and second gate electrodes; removing the first side wall insulating film on the first gate electrode; and after removing the first side wall insulating film on the first gate electrode, thermally treating in an oxidizing atmosphere the semiconductor substrate to form a second side wall insulating film on the first gate electrode. | 2013-10-31 |
20130285149 | ACCUMULATION FIELD EFFECT MICROELECTRONIC DEVICE AND PROCESS FOR THE FORMATION THEREOF - A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by a channel portion dopant type and concentration. An insulative dielectric is in contact with the channel portion and overlaid in turn by a gate. A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion. This channel portion has a dimension normal to the gate which is fully depleted in the off-state. The dopant type is the same across the source, drain and the channel portion of the device. The device on-state current is determined by the doping and, unlike a MOSFET, is not directly proportional to device capacitance. | 2013-10-31 |
20130285150 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. | 2013-10-31 |
20130285151 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. | 2013-10-31 |
20130285152 | FINFET WITH ENHANCED EMBEDDED STRESSOR - A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and between adjacent fins. A semiconductor stressor region extends in at least the first direction away from the fins to apply a stress to the channel region. Source and drain regions of the finFET can be separated from one another by the channel region, with the source and/or drain at least partly in the semiconductor stressor region. The stressor region includes a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region. The second semiconductor region can be more heavily doped than the first semiconductor region, and the first and second semiconductor regions can have opposite conductivity types where at least a portion of the second semiconductor region meets the first semiconductor region. | 2013-10-31 |
20130285153 | STRAINED STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE STRAINED STRUCTURE - An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material. | 2013-10-31 |
20130285154 | CMOS Transistor With Dual High-k Gate Dielectric - A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric V | 2013-10-31 |
20130285155 | III-V LAYERS FOR N-TYPE AND P-TYPE MOS SOURCE-DRAIN CONTACTS - Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures. | 2013-10-31 |
20130285156 | FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING - A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers. | 2013-10-31 |
20130285157 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure comprises: a first interlayer structure having a first dielectric layer and first contact vias; a second interlayer structure having a cap layer and second contact vias; and a third interlayer structure having a second dielectric layer and third contact vias. The first dielectric layer is flush with a gate stack or covers the gate stack, and the first contact vias penetrate through the first dielectric layer and are electrically connected with at least a portion of source/drain regions. The cap layer covers the first interlayer structure, and the second contact vias penetrate through the cap layer and are electrically connected with the first contact vias and the gate stack through a first liner. The second dielectric layer covers the second interlayer structure, and the third contact vias penetrate through the second dielectric layer and are electrically connected with the second contact vias through a second liner. | 2013-10-31 |
20130285158 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer. | 2013-10-31 |
20130285159 | METHOD FOR ETCHING GATE STACK - A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack in an aqueous solution composed of a wet etchant and an oxidizer, removing the substrate from the solution and rinsing the solution from the etched gate stack. | 2013-10-31 |
20130285160 | Microscale Metallic CNT Templated Devices and Related Methods - A microscale device comprises a patterned forest of vertically grown and aligned carbon nanotubes defining a carbon nanotube forest with the nanotubes having a height defining a thickness of the forest, the patterned forest defining a patterned frame that defines one or more components of a microscale device. A conformal coating of substantially uniform thickness at least partially coats the nanotubes, defining coated nanotubes and connecting adjacent nanotubes together, without substantially filling interstices between individual coated nanotubes. A metallic interstitial material infiltrates the carbon nanotube forest and at least partially fills interstices between individual coated nanotubes. | 2013-10-31 |
20130285161 | INTEGRATED CIRCUIT HAVING VARYING SUBSTRATE DEPTH AND METHOD OF FORMING SAME - A semiconductor device is formed such that a semiconductor substrate of the device has a non-uniform thickness. A cavity is etched at a selected side of the semiconductor substrate, and the selected side is then fusion bonded to another substrate, such as a carrier substrate. After fusion bonding, the side of the semiconductor substrate opposite the selected side is ground to a defined thickness. Accordingly, the semiconductor substrate has a uniform thickness except in the area of the cavity, where the substrate is thinner. Devices that benefit from a thinner substrate, such as an accelerometer, can be formed over the cavity. | 2013-10-31 |
20130285162 | INTEGRATED GETTER AREA FOR WAFER LEVEL ENCAPSULATED MICROELECTROMECHANICAL SYSTEMS - There are many inventions described and illustrated herein. In one aspect, present invention is directed to a thin film encapsulated MEMS, and technique of fabricating or manufacturing a thin film encapsulated MEMS including an integrated getter area and/or an increased chamber volume, which causes little to no increase in overall dimension(s) from the perspective of the mechanical structure and chamber. The integrated getter area is disposed within the chamber and is capable of (i) “capturing” impurities, atoms and/or molecules that are out-gassed from surrounding materials and/or (ii) reducing and/or minimizing the adverse impact of such impurities, atoms and/or molecules (for example, reducing the probability of adding mass to a resonator which would thereby change the resonator's frequency). In this way, the thin film wafer level packaged MEMS of the present invention includes a relatively stable, controlled pressure environment within the chamber to provide, for example, a more stable predetermined, desired and/or selected mechanical damping of the mechanical structure. | 2013-10-31 |
20130285163 | MEMS ELEMENT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a MEMS element comprises a first electrode fixed on a substrate, and a second electrode arranged above the first electrode, facing the first electrode, and vertically movable. The second electrode includes a second opening portion that penetrates from an upper surface to a lower surface of the second electrode. The first electrode includes a first opening portion at a position corresponding to at least a part of the second opening portion, the first opening portion penetrating from an upper surface to a lower surface of the first electrode. | 2013-10-31 |
20130285164 | MEMS DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a MEMS device comprises a first electrode fixed on a substrate, a second electrode formed above the first electrode to face the first electrode, and vertically movable, a second anchor portion formed on the substrate and configured to support the second electrode, and a second spring portion configured to connect the second electrode and the second anchor portion. The second spring portion is continuously formed from an upper surface of the second electrode to an upper surface of the second anchor portion, and has a flat lower surface. | 2013-10-31 |
20130285165 | METHOD FOR MANUFACTURING A HYBRID INTEGRATED COMPONENT - A manufacturing method for hybrid integrated components having a very high degree of miniaturization is provided, which hybrid integrated components each have at least two MEMS elements each having at least one assigned ASIC element. Two MEMS/ASIC wafer stacks are initially created independently of one another in that two ASIC substrates are processed independently of one another; a semiconductor substrate is mounted on the processed surface of each of the two ASIC substrates, and a micromechanical structure is subsequently created in each of the two semiconductor substrates. The two MEMS/ASIC wafer stacks are mounted on top of each other, MEMS on MEMS. Only subsequently are the components separated. | 2013-10-31 |
20130285166 | HYBRID INTEGRATED COMPONENT AND METHOD FOR THE MANUFACTURE THEREOF - Hybrid integrated components including an MEMS element and an ASIC element are described, whose capacitor system allows both signal detection with comparatively high sensitivity and sensitive activation of the micromechanical structure of the MEMS element. The hybrid integrated component includes an MEMS element having a micromechanical structure which extends over the entire thickness of the MEMS substrate. At least one structural element of this micromechanical structure is deflectable and is operationally linked to at least one capacitor system, which includes at least one movable electrode and at least one stationary electrode. Furthermore, the component includes an ASIC element having at least one electrode of the capacitor system. The MEMS element is mounted on the ASIC element, so that there is a gap between the micromechanical structure and the surface of the ASIC element. According to the invention, at least one electrode of the capacitor system is separated from the layered structure of the ASIC element and instead mechanically and electrically connected to the deflectable structural element of the MEMS element, so that this electrode functions as a movable electrode of the capacitor system. | 2013-10-31 |
20130285167 | TMAP SENSOR SYSTEMS AND METHODS FOR MANUFACTURING THOSE - A pressure sensor system comprising a pressure sensor chip is disclosed. The pressure sensor chip comprises a sensing side where pressure sensing is performed and one or more interconnections where electrical connections are made at the other side of the chip. The pressure sensor comprising an integrated circuit ( | 2013-10-31 |
20130285168 | MEMS INERTIAL SENSOR AND METHOD FOR MANUFACTURING THE SAME - A MEMS inertial sensor and a method for manufacturing the same are provided. The method includes: depositing a first carbon layer on a semiconductor substrate; patterning the first carbon layer to form a fixed anchor bolt, an inertial anchor bolt and a bottom sealing ring; forming a contact plug in the fixed anchor bolt and a contact plug in the inertial anchor bolt; forming a first fixed electrode, an inertial electrode and a connection electrode on the first carbon layer, where the first fixed electrode and the inertial electrode constitute a capacitor; forming a second carbon layer on the first fixed electrode and the inertial electrode; and forming a sealing cap layer on the second carbon layer and the top sealing ring. Under an inertial force, only the inertial electrode may move, the fixed electrode will almost not move or vibrate, which improves the accuracy of the MEMS inertial sensor. | 2013-10-31 |
20130285169 | METHOD FOR PRODUCING AN OPTICAL WINDOW DEVICE FOR A MEMS DEVICE - A method for producing an optical window device for a MEMS device, including applying a layer made of a transparent material onto a substrate having a recess, and deforming the layer so that it is folded and the deformed area of the layer forms an optical window. | 2013-10-31 |
20130285170 | MULTIPLE BONDING IN WAFER LEVEL PACKAGING - A MEMS device is described. The device includes a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, a semiconductor substrate including a second bonding layer, and a cap including a third bonding layer, the cap coupled to the semiconductor substrate by bonding the second bonding layer to the third bonding layer. The first bonding layer includes silicon, the semiconductor substrate is electrically coupled to the MEMS substrate by bonding the first bonding layer to the second bonding layer, and the MEMS substrate is hermetically sealed between the cap and the semiconductor substrate. | 2013-10-31 |
20130285171 | ENVIRONMENT-RESISTANT MODULE, MICROPACKAGE AND METHODS OF MANUFACTURING SAME - An environment-resistant module which provides both thermal and vibration isolation for a packaged micromachined or MEMS device is disclosed. A microplatform and a support structure for the microplatform provide the thermal and vibration isolation. The package is both hermetic and vacuum compatible and provides vertical feedthroughs for signal transfer. A micromachined or MEMS device transfer method is also disclosed that can handle a wide variety of individual micromachined or MEMS dies or wafers, in either a hybrid or integrated fashion. The module simultaneously provides both thermal and vibration isolation for the MEMS device using the microplatform and the support structure which may be fabricated from a thin glass wafer that is patterned to create crab-leg shaped suspension tethers or beams. | 2013-10-31 |
20130285172 | Combined Sensor - To provide a combined sensor that can detect a plurality of physical quantities. With the combined sensor, it is possible to realize, while maintaining performance, a reduction in size and a reduction in costs by increasing elements that can be shared among respective sensors. A weight M | 2013-10-31 |
20130285173 | ACOUSTIC TRANSDUCERS WITH PERFORATED MEMBRANES - A MEMS device, such as a microphone, uses a perforated plate. The plate comprises an array of holes across the plate area. The plate has an area formed as a grid of polygonal cells, wherein each cell comprises a line of material following a path around the polygon thereby defining an opening in the centre. In one aspect, the line of material forms a path along each side of the polygon which forms a track which extends at least once inwardly from the polygon perimeter towards the centre of the polygon and back outwardly to the polygon perimeter. This defines a meandering hexagon side wall, which functions as a local spring suspension. | 2013-10-31 |
20130285174 | ULTRASOUND PROBE - Disclosed is an ultrasonic probe comprising: CMUT cells ( | 2013-10-31 |
20130285175 | MICROMECHANICAL COMPONENT AND METHOD FOR MANUFACTURING A MICROMECHANICAL COMPONENT - A micromechanical component, in particular a micromechanical sensor having a carrier substrate and having a cap substrate, and a manufacturing method are provided. The carrier substrate and the cap substrate are joined together with the aid of a eutectic bond connection or by a metallic solder connection or a glass solder connection (e.g., glass frit), in an edge area of the carrier substrate and the cap substrate. The connection of the carrier substrate and the cap substrate is established with the aid of connecting areas, and a stop trench or a stop protrusion or both a stop trench and a stop protrusion are situated within the edge areas in the bordering areas. | 2013-10-31 |
20130285176 | MAGNETIC BODY DEVICE AND MANUFACTURING METHOD THEREOF - A magnetic body device has a stacked structure comprising an underlying layer, a magnetic body layer, and a cap layer. The material for the underlying layer is different from that for the cap layer. The magnetic body layer has a free magnetization region having perpendicular magnetic anisotropy and a first characteristic change region and a second characteristic change region situated on both sides of the free magnetization region in a first in-plane direction. The perpendicular magnetic anisotropy of the first characteristic change region and the second characteristic change region is at a level lower than that of the free magnetization region. An external magnetic field containing a component in the first in-plane direction is applied to the free magnetization region. Further, a current in the first in-plane direction is supplied to the free magnetization region. | 2013-10-31 |
20130285177 | MAGNETIC MEMORY AND METHOD OF FABRICATION - In one embodiment a magnetic memory includes a memory device base and a plurality of memory cells disposed on the memory cell base, where each memory cell includes a layer stack comprising a plurality of magnetic and electrically conductive layers arranged in a stack of layers common to each other memory cell. The magnetic memory further includes an implanted matrix disposed between the memory cells and surrounding each memory cell, where the implanted matrix includes component material of the layer stack of each memory cell inter mixed with implanted species, where the implanted matrix comprises a non-conducting material and a non-magnetic material, wherein each memory cell is electrically and magnetically isolated from each other memory cell. | 2013-10-31 |
20130285178 | Magnetic Memory Device - A magnetic memory device is provided. The magnetic memory device includes a first vertical magnetic layer and a second vertical magnetic layer on a substrate, a tunnel barrier layer between the fist vertical magnetic layer and the second vertical magnetic layer, and an exchange-coupling layer between a first sub-layer of the first vertical magnetic layer and a second sub-layer of the first vertical magnetic layer. | 2013-10-31 |
20130285179 | Image Sensor Device and Method - A system and method for reducing cross-talk between photosensitive diodes is provided. In an embodiment a first color filter is formed over a first photosensitive diode and a second color filter is formed over a second photosensitive diode, and a gap is formed between the first color filter and the second color filter. The gap will serve to reflect light that otherwise would have crossed from the first color filter to the second color filter, thereby reducing cross-talk between the first photosensitive diode and the second photosensitive diode. A reflective grid may also be formed between the first photosensitive diode and the second photosensitive diode in order to assist in the reflection and further reduce the amount of cross-talk. | 2013-10-31 |
20130285180 | Apparatus for Vertically Integrated Backside Illuminated Image Sensors - A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias. | 2013-10-31 |
20130285181 | Apparatus and Method for Reducing Cross Talk in Image Sensors - A method for reducing cross talk in image sensors comprises providing a backside illuminated image sensor wafer, forming an isolation region in the backside illuminated image sensor wafer, wherein the isolation region encloses a photo active region, forming an opening in the isolation region from a backside of the backside illuminated image sensor wafer and covering an upper terminal of the opening with a dielectric material to form an air gap embedded in the isolation region of the backside illuminated image sensor wafer. | 2013-10-31 |
20130285182 | PHOTOSENSITIVE TRANSPARENT COMPOSITION FOR COLOR FILTER OF SOLID-STATE IMAGING DEVICE, AND PRODUCTION METHOD OF COLOR FILTER OF SOLID-STATE IMAGING DEVICE, COLOR FILTER OF SOLID-STATE IMAGING DEVICE, AND SOLID-STATE IMAGING DEVICE, EACH USING THE SAME - There is provided a photosensitive transparent composition for a color filter of a solid-state imaging device, containing (A) a photopolymerization initiator, (B) a polymerizable compound, and (C) an alkali-soluble resin, wherein the cured film obtained from the photosensitive transparent composition has a refractive index of 1.60 to 1.90 for light at a wavelength of 633 nm. | 2013-10-31 |
20130285183 | DUAL-FACING CAMERA ASSEMBLY - Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). | 2013-10-31 |
20130285184 | WAVEGUIDE PHOTODETECTOR AND FORMING METHOD THEREOF - Techniques are described for forming a waveguide photodetector. In one example, a method of forming a waveguide photodetector includes forming a waveguide on a substrate, e.g., silicon on insulator, depositing a first oxide coating over the waveguide and on the SOI substrate, creating a seed window through the first oxide coating to a bulk silicon layer of the SOI substrate, depositing a photodetector material into the seed window and on top of the first oxide coating over the waveguide, depositing a second oxide coating over the photodetector material and over the first oxide coating deposited over the waveguide and on the SOI substrate, and applying thermal energy to liquefy the photodetector material. | 2013-10-31 |
20130285185 | IMAGE SENSOR PACKAGE - An image sensor package and image sensor chip capable of being slenderized while enhancing the reliability with respect to physical impact are provided. The image sensor package includes an image sensor chip provided with a pixel domain at a central portion of an upper surface thereof, a substrate disposed at an upper side of the image sensor chip so as to be flip-chip bonded with respect to the image sensor chip, provided with a hole formed at a position corresponding to the pixel domain, and formed of organic material, a printed circuit board at which the substrate provided with the image sensor chip bonded thereto is mounted, and a solder ball configured to electrically connect the substrate to the printed circuit board. | 2013-10-31 |
20130285186 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A semiconductor device comprising a first semiconductor section including a first wiring layer at one side thereof, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other, a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication. | 2013-10-31 |
20130285187 | PHOTO CELL DEVICES AND METHODS FOR SPECTROMETRIC APPLICATIONS - Embodiments relate to photo cell devices. In an embodiment, a photo cell device includes an array of transmission layers having different optical thicknesses and with photo diodes underneath. The transmission layers can include two different materials, such as a nitride and an oxide, that cover each diode with a different proportional area density in a damascene-like manner. Embodiments provide advantages over conventional devices, including that they can be integrated into a standard CMOS process and therefore simpler and less expensive to produce. | 2013-10-31 |
20130285188 | SOLID STATE IMAGING DEVICE - A solid state imaging device | 2013-10-31 |
20130285189 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In a semiconductor device including unit cells which are aligned in one direction, wirings disposed along end portions in the one direction have high Young's moduli. | 2013-10-31 |
20130285190 | Layout of a MOS Array Edge with Density Gradient Smoothing - A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry. | 2013-10-31 |