44th week of 2014 patent applcation highlights part 51 |
Patent application number | Title | Published |
20140322823 | Metallic Nanoparticle Synthesis with Carbohydrate Capping Agent - The disclosure relates to metal nanoparticle compositions and their methods of formation and use, in particular gold nanoparticles (AuNP) and gold-coated magnetic nanoparticles. Compositions according to the disclosure include aqueous suspensions of metal nanoparticles that are stabilized with one or more carbohydrate capping agents and/or that are functionalized with one or more binding pair members for capture/detection of a target analyte. The nanoparticle suspensions are stable for extended periods and can be functionalized as desired at a later point in time, typically prior to use in an assay for the detection of a target biological analyte. The stable nanoparticle suspension can be formed by the aqueous reduction of oxidized metal precursors at non-acidic pH values in the presence of a carbohydrate-based capping agent such as dextrin or other oligosaccharides. | 2014-10-30 |
20140322824 | ADRENOMEDULLIN ASSAYS AND METHODS FOR DETERMINING MATURE ADRENOMEDULLIN - Subject of the present invention is an in vitro method for therapy follow-up in septic patients wherein the concentration of mature ADM 1-52 and/or mature ADM 1-52-Gly in a sample of bodily fluid of said septic patient is determined using an assay comprising two binders that bind to two different regions within the region of mature adrenomedullin and/or adrenomedullin-Gly that is aminoacid 21-52-amid SEQ ID No. 1 or aminoacid 21-52-Gly SEQ ID No. 2 wherein each of said regions comprises at least 4 or 5 amino acids. | 2014-10-30 |
20140322825 | LAMBODIES WITH HIGH AFFINITY AND SELECTIVITY FOR GLYCANS AND USES THEREFOR - The invention relates to dimeric proteins comprised of subunits having (i) recombinant lamprey variable lymphocyte receptor (VLR) diversity regions linked to (ii) multimerization domains. The dimeric proteins exhibit binding specificity for glycosylated antigens, and they may be used in methods of detecting or isolating glycans from a sample, and in methods of disease diagnosis, prognosis, progression monitoring, treatment, and imaging. | 2014-10-30 |
20140322826 | METHOD FOR DETECTION OF BINDING - The present invention relates to a method for detection of binding or interaction events between a binding agent and its corresponding analyte (such as an antibody and an antigen) in which a signal is detected which is substantially more amplified and thus easier to detect than in prior art systems. The method comprises simultaneous but separate addition of a first enhancement reagent having affinity for said analyte and a second enhancement reagent having affinity for the first enhancement reagent wherein the first enhancement reagent binds to the analyte and the second enhancement reagent binds to the first enhancement reagent, and, wherein the first and second enhancement reagents have more than one binding site so that they are able to bind to each other to thereby amplify a detectable signal from the binding event. | 2014-10-30 |
20140322827 | METHOD FOR PACKAGING DISPLAY DEVICE AND APPARATUS THEREFOR - The present application provides a method for packaging a display device and an apparatus therefor. The method includes: providing a display device, a platform, a laser beam and a magnetic mechanism; wherein the display device includes a light emitting element, the light emitting element includes at least one effective light emitting region thereon and is prepared on an upper surface of a glass substrate, the glass substrate is bonded to a glass cover plate via a sealing adhesive layer; the display device is placed on the platform; the laser beam penetrates the glass cover plate and focuses on the sealing adhesive layer to sinter the sealing adhesive layer; and the magnetic mechanism clamps the glass cover plate and the glass substrate from top to bottom and applies a uniform pressing force on the effective light emitting region of the display device. | 2014-10-30 |
20140322828 | Method for Manufacturing Magnetoresistance Component - A method for manufacturing a magnetoresistance component is provided. A substrate is provided. A circuit structure layer including an interconnect structure is formed on the substrate, wherein the interconnect structure comprises a metal pad. A dielectric layer is formed on the circuit structure. A metal damascene structure is formed in the dielectric layer. A patterned magnetoresistance component is formed above the metal damascene structure to electrically connect to the metal damascene structure. | 2014-10-30 |
20140322829 | SEMICONDCUTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a pinned layer having a magnetic direction permanently set to a first direction, a tunnel insulating layer arranged on the pinned layer, a free layer arranged on the tunnel insulating layer and having a changeable magnetic direction, and a magnetic induction layer formed to surround the pinned layer and have a magnetic direction permanently set to a second direction different from the first direction. | 2014-10-30 |
20140322830 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Such a device is disclosed that includes: redundancy circuits for replacing defective memory cells included in a memory cell array; an electrical fuse circuit that stores addresses of the defective memory cells; a data determination circuit that generates a determination signal by determining whether test data read from the memory cell array is correct or incorrect; and an analysis circuit that supplies, in a first operation mode, the electrical fuse circuit with an address signal supplied when the determination signal is activated, and supplies, in a second operation mode, the electrical fuse circuit with an address signal supplied when a data mask signal supplied from outside is activated irrespective of the determination signal. | 2014-10-30 |
20140322831 | LITHOGRAPHY APPARATUS, LITHOGRAPHY METHOD, AND METHOD OF MANUFACTURING ARTICLE - A lithography apparatus for performing pattern formation on a substrate includes a stage configured to hold the substrate and be movable, an optical system configured to irradiate the substrate with an energy beam for the pattern formation, and a controller configured to set an arrangement of first and second marks for overlay inspection, which is variable with respect to a first substrate for condition setting, and control the stage and the optical system so that first processing for forming the first mark on the first substrate without the pattern formation and second processing for forming the second mark on the first substrate with the pattern formation are performed based on the set arrangement. | 2014-10-30 |
20140322832 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster. | 2014-10-30 |
20140322833 | IRRADIATION APPARATUS FOR IRRADIATING CHARGED PARTICLE BEAM, METHOD FOR IRRADIATION OF CHARGED PARTICLE BEAM, AND METHOD FOR MANUFACTURING ARTICLE - An apparatus includes an optical system configured to irradiate a substrate with a charged particle beam, a control unit configured to control an irradiation position of the charged particle beam, and a first measurement unit and a second measurement unit each configured to measure a surface position of the substrate. The first measurement unit and the second measurement unit have different characteristics in terms of charging. The control unit controls the irradiation position of the charged particle beam based on values measured by the first measurement unit and the second measurement unit. | 2014-10-30 |
20140322834 | APPARATUS AND METHOD FOR BONDING SUBSTRATES - An apparatus for bonding substrates and a method of bonding substrates are provided. In accordance with one exemplary embodiment of the present invention, a first plate to mount a first substrate is provided. A chamber body movably connected to the first plate is provided. A second plate that is placed opposite to the first plate and a second substrate is mounted on the second plate is provided. A chamber lead having the second plate mounted inside is provided which is movably connected to the chamber body to move rotationally or linearly to open or close the chamber space with the chamber body. A pair of first alignment cameras is placed outside of the chamber space to scan the first substrate or the second substrate. A stage control unit is provided to move the first plate or the second plate to align the first substrate and the second substrate. | 2014-10-30 |
20140322835 | METHOD OF MANUFACTURING LIQUID DISCHARGE HEAD - A method of manufacturing a liquid discharge head is provided. The method includes forming a heating element on a substrate in which a semiconductor element is arranged. The method further includes forming a protection layer to contact an upper surface of the heating element. Annealing is performed in a hydrogen-containing atmosphere before the step of forming the protection layer. | 2014-10-30 |
20140322836 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE, ORGANIC LIGHT-EMITTING DISPLAY HAVING THE SAME, AND METHOD OF MANUFACTURING THE ORGANIC LIGHT-EMITTING DISPLAY - A thin-film transistor array substrate, an organic light-emitting display having the same, and a method of manufacturing the organic light-emitting display are disclosed. In one embodiment, the thin-film transistor array substrate includes a buffer layer formed on a substrate, a first insulating layer formed on the buffer layer, a pixel electrode formed on the first insulating layer using a transparent conductive material, an intermediate layer that covers an upper side and outer side-surfaces of the pixel electrode and includes a organic light-emitting layer, a gap formed by etching the first insulating layer and the buffer layer at a peripheral of the pixel electrode, and a facing electrode that is formed on an upper side and outer side-surfaces of the pixel electrode to cover the intermediate layer and the gap. | 2014-10-30 |
20140322837 | Method of Forming Nanocrystals and Method of Manufacturing an Organic Light-Emitting Display Apparatus Including a Thin Film Having Nanocrystals - A method of forming nanocrystals includes loading a substrate into a chamber, applying a first voltage to a first target to form a thin film including a first metal compound on the substrate by sputtering, and applying a second voltage to a second target and forming nanocrystals in the thin film by sputtering. | 2014-10-30 |
20140322838 | Semiconductor Optoelectronic Device And The Method Of Manufacturing The Same - A semiconductor optoelectronic device comprises an operating substrate; a semiconductor epitaxial stack unit disposed on the operating substrate comprising a first semiconductor material layer having a first electrical conductivity disposed on the operating substrate and a second semiconductor material layer having a second electrical conductivity disposed on the first semiconductor material layer; a transparent conductive layer disposed on the second semiconductor material layer, wherein the transparent conductive layer comprises a first surface, a directly contacting part disposed on the first surface and directly contacting with the second semiconductor material layer, a second surface substantially parallel with the first surface, and a directly contacting corresponding part disposed on the second surface corresponding to the directly contacting part; and a first electrode disposed on the operating substrate and electrically connected with the semiconductor epitaxial stack by the transparent conductive layer, wherein the first electrode is connected with the transparent conductive layer by an area excluding the directly contacting part and the directly contacting corresponding part. | 2014-10-30 |
20140322839 | METHOD OF MANUFACTURING LED COMPONENT BY INTEGRATING EPITAXIAL STRUCTURE AND PACKAGE SUBSTRATE TOGETHER - An integral LED component is mounted into a hollow carrier. The carrier has two conductive electrodes with opposite polarities. The LED component comprises a substrate, N number of LED epitaxial structures where N is a number greater than one, a third electrode and a fourth electrode. The N number of LED epitaxial structures are formed on the upper surface of the substrate, the at least one of the N number of LED epitaxial structures comprises a first and a second electrode. The third and fourth electrodes are formed on the upper surface and located outside the N number of LED epitaxial structures, the respective electrodes are electrically connected to form a circuit. The two conductive electrodes of the hollow carrier are used for electrically connecting the third and fourth electrodes of the substrate, and the lower surface of the substrate is exposed to the hollow carrier. | 2014-10-30 |
20140322840 | SEMICONDUCTOR LASER ASSEMBLY AND PACKAGING SYSTEM - A system for self-aligning assembly and packaging of semiconductor lasers allows reduction of time, cost and testing expenses for high power density systems. A laser package mounting system, such as a modified TO-can (transistor outline can), has modifications that increase heat transfer from the active laser to a heat exchanger or other heat sink. A prefabricated heat exchanger assembly mounts both a laser package and one or more lenses. Direct mounting of a fan assembly to the package further minimizes assembly steps. Components may be physically and optically aligned during assembly by clocking and other indexing means, so that the entire system is self-aligned and focused by the assembly process without requiring post-assembly adjustment. This system can lower costs and thereby enable the use of high powered semiconductor lasers in low cost, high volume production, such as consumer items. | 2014-10-30 |
20140322841 | LIGHT EMITTING ELEMENT MODULE SUBSTRATE, LIGHT EMITTING ELEMENT MODULE, AND ILLUMINATING DEVICE - According to an aspect of the invention, there is provided a light emitting element module substrate including: a laminated plate; and a metal layer. The laminated plate includes a base metal plate and an insulating layer provided on the base metal plate. The metal layer is provided on the insulating layer. The metal layer includes a mounting section on which a light emitting element is to be mounted, and a bonding section to which a wiring electrically connected to the light emitting element is to be bonded. The metal layer includes a silver layer which is an uppermost layer of at least one of the mounting section and the bonding section and is formed by electrolytic plating. The mounting section and the bonding section are electrically isolated from a periphery of the laminated plate. | 2014-10-30 |
20140322842 | DONOR SUBSTRATE, METHOD OF MANUFACTURING DONOR SUBSTRATE, AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY DEVICE - Aspects of the present invention are directed toward donor substrate, method of manufacturing donor substrate, and method of manufacturing organic light-emitting display device. According to an embodiment of the present invention, a donor substrate includes a base layer which includes an element region and an encapsulation region surrounding the element region; a transfer assist layer which is disposed on the base layer and includes a first uneven portion disposed on the encapsulation region; and a transfer layer which is disposed on the transfer assist layer. The first uneven portion is formed on a surface of the transfer assist layer which contacts the transfer layer. | 2014-10-30 |
20140322843 | ANNEALING APPARATUS AND ANNEALING METHOD - The present disclosure relates to an annealing apparatus and an annealing method, which are applied to the packaging art of the AMOLED panel, wherein the annealing apparatus comprises an electromagnetic wave generator coupled with a plurality of irradiators and comprises a plate whose surface is provided with the irradiators and which is placed above or below the AMOLED panel for annealing it. The method comprises the following steps: annealing the AMOLED panel by an annealing apparatus which comprises an electromagnetic wave generator and a plate having lots of irradiators; when the irradiators aim at the annealing area, the annealing areas are annealed by the high frequency electromagnetic wave generated by the electromagnetic wave generator and irradiated from the irradiators. The present disclosure can save the time of the annealing process and can improve the process situation. Meanwhile, the present disclosure increases production yield and improves product quality. | 2014-10-30 |
20140322844 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - Provided is a method for manufacturing a light emitting device comprising a light emitting element and an optical part, the method comprising the steps of (i) forming a hydroxyl film on a bonding surface of each of the light emitting element and the optical part by an atomic layer deposition, and (ii) bonding the bonding surfaces of the light emitting element and the optical part with each other, each of the bonding surfaces having the hydroxyl film formed thereon, wherein a substep is repeated at least one time in the step (i), in which substep a first raw material gas and a second raw material gas are sequentially supplied onto the bonding surfaces of the light emitting element and the optical part, and wherein the bonding of the bonding surfaces in the step (ii) is performed without a heating treatment. | 2014-10-30 |
20140322845 | DEVICE FOR MONITORING LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY - A device for monitoring a liquid crystal display includes: a substrate including a display region and a non-display region disposed at an edge of the display region. The display region includes: a thin film transistor disposed on the substrate, a pixel electrode disposed on the substrate and connected to the thin film transistor, a first sacrificial layer disposed on the pixel electrode, and a roof layer disposed on the sacrificial layer. The non-display region includes: a second sacrificial layer disposed on the substrate, and the roof layer disposed on the second sacrificial layer. The first sacrificial layer has a first longitudinal dimension and a first cross-sectional area, and the second sacrificial layer has a second longitudinal dimension and a second cross-sectional area. The first cross-sectional area is the same as the second cross-sectional area. The second longitudinal dimension is greater than the first longitudinal dimension. | 2014-10-30 |
20140322846 | LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME - Provided is a liquid crystal display including: a first substrate; a thin film transistor disposed on the first substrate; a passivation layer disposed on the thin film transistor and comprising a contact hole exposing an electrode of the thin film transistor; a pixel electrode disposed on the passivation layer and connected to the electrode of the thin film transistor through the contact hole; a lower buffer layer disposed on the pixel electrode; a lower alignment layer disposed on the lower buffer layer; a second substrate facing the first substrate; a common electrode disposed on the second substrate; an upper buffer layer disposed on the common electrode; and an upper alignment layer disposed on the upper buffer layer, in which the lower buffer layer comprises parylene, the upper buffer layer comprises parylene, or both the lower and the upper buffer layers comprise parylene. | 2014-10-30 |
20140322847 | WAFER PROCESSING METHOD - A wafer processing method including a modified layer forming step of applying a laser beam having a transmission wavelength to a substrate from the back side of the substrate along division lines. The modified layer forming step includes the steps of making the polarization plane of linearly polarized light of the laser beam parallel to the direction perpendicular to each division line, shifting the beam center of the laser beam from the optical axis of a focusing lens of a focusing unit for focusing the laser beam, in the direction perpendicular to each division line, and shifting the focal point of the laser beam by the focusing lens in the same direction as the direction where the beam center of the laser beam has been shifted. | 2014-10-30 |
20140322848 | THERMAL TRANSFER METHOD AND METHOD OF MANUFACTURING AN ORGANIC LIGHT EMITTING DISPLAY DEVICE USING THE SAME - A thermal transfer method includes a step of forming a donor member having a base layer, a light-to-heat conversion layer disposed on the base layer, an intermediate layer disposed on the light-to-heat conversion layer, an organic transfer layer disposed on the intermediate layer, and a first protecting film disposed over the base layer and contacting at least one edge of the base layer, irradiating a first laser onto the donor member to form a preliminary organic layer on the display substrate, forming a pressing member having a second protecting film and a third protecting film disposed over the second protecting film and contacting at least one edge of the second protecting film, disposing the display substrate within a space formed by the second protecting film and the third protecting film, and irradiating a second laser onto the pressing member to change the preliminary organic layer to an organic layer. | 2014-10-30 |
20140322849 | VAPOR DEPOSITION APPARATUS, DEPOSITION METHOD USING THE SAME, AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - A vapor deposition apparatus for forming a deposition layer on a substrate includes a supply unit that is supplied with a first raw gas to form the deposition layer and an auxiliary gas, wherein the auxiliary gas does not constitute a raw material to form the deposition layer, a reaction space that is connected to the supply unit to be supplied with the first raw gas and the auxiliary gas, a plasma generator in the reaction space to convert at least a portion of the first raw gas into a radical form, and a first injection portion that is connected to the reaction space and that supplies at least a radical material of the first raw gas toward the substrate. | 2014-10-30 |
20140322850 | METHOD FOR FORMING AN ORGANIC DEVICE - The present invention provides a method for forming an organic device having a patterned conductive layer that includes providing a substrate, depositing organic materials over the substrate to form one or more organic layers, coating a photoresist solution over the one or more organic layers to form a photo-patternable layer, wherein the solution includes a fluorinated photoresist material and a first fluorinated solvent, selectively exposing portions of the photo-patternable layer to radiation to form a first pattern of exposed fluorinated photoresist material and a second pattern of unexposed fluorinated photoresist material, exposing the substrate to a second fluorinated solvent to develop the photo-patternable layer, removing the second pattern of unexposed fluorinated photoresist material without removing the first pattern of exposed fluorinated photoresist material, coating one or more conductive layers over the one or more organic layers and removing a portion of the one or more of the conductive layers to form a pattern. Particular embodiments of the present invention for forming arrays of top contact TFTs and a pixilated organic device are also provided. | 2014-10-30 |
20140322851 | TABLET FOR PLASMA COATING SYSTEM, METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING A THIN FILM USING THE METHOD OF MANUFACTURING THE TABLET - A tablet for a plasma coating system having a first part that includes a first material having a first sublimation point at a first pressure and a second part that is disposed on the first part and comprises a second material having a second melting point at the first pressure, wherein the second melting point is lower than the first sublimation point. | 2014-10-30 |
20140322852 | DEPOSITION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY - A deposition apparatus includes a deposition chamber, a plurality of substrate holders comprising a first holder configured to maintain a substrate at a first substrate position in the deposition chamber and a second holder configured to maintain another substrate at a second substrate position in the deposition chamber, a deposition source disposed in the deposition chamber and configured to supply a deposition material to apply onto substrates placed at the first and second substrate positions, and a deposition source transfer mechanism configured to move the deposition source to be opposite to one of the first and second substrates in a first direction, a substrate transfer mechanism configured to transfer a substrate in a second direction to or from the first substrate position and further configured to transfer another substrate in the second direction to or from the second substrate position. | 2014-10-30 |
20140322853 | Novel Zwitterionic Polyelectrolytes as Efficient Interface Materials for Application in Optoelectronic Devices - Facile ways towards the development of linear and brush-type zwitterionic conjugated polyelectrolytes possessing hole or electron blocking abilities are presented using combination of polymerization techniques, such as Suzuki or Stille cross coupling, Grignard Metathesis Polymerization and Atom transfer radical polymerization. These zwitterionic conjugated polyelectrolytes will serve as excellent interface materials in various optoelectronic devices. | 2014-10-30 |
20140322854 | METHOD FOR MANUFACTURING A MEMS SENSOR - A capacitance type gyro sensor includes a semiconductor substrate, a first electrode integrally including a first base portion and first comb tooth portions and a second electrode integrally including a second base portion and second comb tooth portions, formed by processing the surface portion of the semiconductor substrate. The first electrode has first drive portions that extend from opposed portions opposed to the respective second comb tooth portions on the first base portion toward the respective second comb tooth portions. The second electrode has second drive portions formed on the tip end portions of the respective second comb tooth portions opposed to the respective first drive portions. The first drive portions and the second drive portions engage with each other at an interval like comb teeth. | 2014-10-30 |
20140322855 | MODULE ASSEMBLY FOR THIN SOLAR CELLS - Solar cells are packaged by placing the solar cells between sheets of encapsulants. The encapsulants are exposed to ultraviolet (UV) light to cure the encapsulants and bond the encapsulants together to encapsulate the solar cells. The UV curing steps may be performed to bond one of the encapsulants to a transparent top cover and the solar cells, and to bond the other encapsulant to the solar cells and a backsheet. A protective package that includes the transparent top cover, encapsulated solar cells, and the backsheet is then optionally mounted on a frame. | 2014-10-30 |
20140322856 | METHOD OF MAKING INTERPOSER PACKAGE FOR CMOS IMAGE SENSOR - An image sensor package and method of manufacture that includes a crystalline handler with conductive elements extending therethrough, an image sensor chip disposed in a cavity of the handler, and a transparent substrate disposed over the cavity and bonded to both the handler and image sensor chip. The transparent substrate includes conductive traces that electrically connect the sensor chip's contact pads to the handler's conductive elements, so that off-chip signaling is provided by the substrate's conductive traces and the handler's conductive elements. | 2014-10-30 |
20140322857 | Dark Current Reduction for Back Side Illuminated Image Sensor - A method of fabricating a semiconductor image sensor device is disclosed. A plurality of radiation-sensing regions is formed in a substrate. The radiation-sensing regions are formed in a non-scribe-line region of the image sensor device. An opening is formed in a scribe-line region of the image sensor device by etching the substrate in the scribe-line region. A portion of the substrate remains in the scribe-line region after the etching. The opening is then filled with an organic material. | 2014-10-30 |
20140322858 | Solar Cells with Patterned Antireflective Surfaces - Systems and methods for producing nanoscale textured low reflectivity surfaces may be utilized to fabricate solar cells. A substrate may be patterned with a resist prior to an etching process that produces a nanoscale texture on the surface of the substrate. Additionally, the substrate may be subjected to a dopant diffusion process. Prior to dopant diffusion, the substrate may be optionally subjected to liquid phase deposition to deposit a material that allows for patterned doping. The order of the nanoscale texture etching and dopant diffusion may be modified as desired to produce post-nano emitters or pre-nano emitters. | 2014-10-30 |
20140322859 | FABRICATION OF IONIC LIQUID ELECTRODEPOSITED CU-SN-ZN-S-SE THIN FILMS AND METHOD OF MAKING - A semiconductor thin-film and method for producing a semiconductor thin-films comprising a metallic salt, an ionic compound in a non-aqueous solution mixed with a solvent and processing the stacked layer in chalcogen that results in a CZTS/CZTSS thin films that may be deposited on a substrate is disclosed. | 2014-10-30 |
20140322860 | METAL CONTACT SCHEME FOR SOLAR CELLS - A method of depositing metal on an exposed surface of a p-type semiconductor region of a semiconductor device comprising a p-n junction is disclosed, the method comprising: immersing the exposed surface of the p-type semiconductor region on which the metal is to be deposited in a solution of metal ions; producing an electric field in the semiconductor device such that the p-n junction is forward biased; electrochemically depositing the metal on the exposed surface of the p-type semiconductor region of the semiconductor device by reduction of metal ions in the solution. | 2014-10-30 |
20140322861 | SOLAR BATTERY, MANUFACTURING METHOD THEREOF, AND SOLAR BATTERY MODULE - A solar battery includes a transparent electrode and a collector electrode in this order on the surface of a light incident surface side of a photoelectric conversion layer. The collector electrode is formed in a predetermined region on the photoelectric conversion layer and a first transparent electrode of the transparent electrode is formed only in a region right under the collector electrode in contact with the photoelectric conversion layer and the collector electrode. A second transparent electrode of the transparent electrode is formed in a region on the photoelectric conversion layer where the collector electrode is not formed and on the collector electrode in contact with the photoelectric conversion layer or the collector electrode. The carrier concentration of the first transparent electrode is higher than the carrier concentration of the second transparent electrode. | 2014-10-30 |
20140322862 | METHOD OF MAKING A RESISTIVE RANDOM ACCESS MEMORY DEVICE WITH METAL-DOPED RESISTIVE SWITCHING LAYER - A method for forming a resistive random access memory (RRAM) device is disclosed. The method comprises forming a first electrode, forming a resistive switching oxide layer comprising a metal oxide by thermal atomic layer deposition (ALD), doping the resistive switching oxide layer with a metal dopant different from metal forming the metal oxide, and forming a second electrode by thermal atomic layer deposition (ALD), where the resistive switching layer is interposed between the first electrode and the second electrode. In some embodiments, forming the resistive switching oxide may be performed without exposing a surface of the switching oxide layer to a surface-modifying plasma treatment after depositing the metal oxide. | 2014-10-30 |
20140322863 | Metal Bump Joint Structure and Methods of Forming - A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension. | 2014-10-30 |
20140322864 | LOW CTE INTERPOSER - An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”). | 2014-10-30 |
20140322865 | Semiconductor Device and Method of Forming Stacked Semiconductor Die and Conductive Interconnect Structure Through an Encapsulant - A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first semiconductor die is mounted to the first substrate and electrically connected to the first conductive layer. A second semiconductor die is mounted to the second substrate and electrically connected to the second conductive layer. The first semiconductor die is mounted over the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and the first and second substrates. A conductive interconnect structure is formed through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device. Forming the conductive interconnect structure includes forming a plurality of conductive vias through the encapsulant and the first substrate outside a footprint of the first and second semiconductor die. | 2014-10-30 |
20140322866 | Package for Three Dimensional Integrated Circuit - A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package. | 2014-10-30 |
20140322867 | CONDUCTIVE VIA STRUCTURES FOR ROUTING POROSITY AND LOW VIA RESISTANCE, AND PROCESSES OF MAKING - An integrated circuit structure includes a first conductive layer (MET4) including a first forked conductive structure ( | 2014-10-30 |
20140322868 | BARRIER LAYER ON BUMP AND NON-WETTABLE COATING ON TRACE - Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized. | 2014-10-30 |
20140322869 | METHOD FOR MANUFACTURING CHIP PACKAGE STRUCTURE - A method for manufacturing a chip package structure includes following steps. A carrier having a metal layer is provided. A patterned photoresist layer is formed on the metal layer. The patterned photoresist layer has a plurality of first openings exposing a portion of the metal layer. Connection terminals are formed in the first openings, respectively, and the connection terminals are connected to the metal layer. A chip is placed on the carrier, and first pads of the chip are respectively connected to the connection terminals through a plurality of connection conductors. After the chip is placed on the carrier, the patterned photoresist layer is removed. A encapsulant is formed on the carrier. The encapsulant encapsulates the chip, the connection conductors, and the metal layer. The carrier and the metal layer are removed to expose the connection terminals. | 2014-10-30 |
20140322870 | SRAM CELL WITH DIFFERENT CRYSTAL ORIENTATION THAN ASSOCIATED LOGIC - An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the SRAM cells are formed in an epitaxial semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the SRAM cells are formed in a top semiconductor layer with one crystal orientation and the logic transistors are formed in an epitaxial semiconductor layer with another crystal orientation. | 2014-10-30 |
20140322871 | PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT - Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device. | 2014-10-30 |
20140322872 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH GATE PROFILE CONTROL - A method for forming a semiconductor device includes forming a gate structure over a semiconductor substrate. The gate structure includes a gate electrode, at least two hard mask (HM) layers over the gate electrode, and a spacer abutting a side wall of the gate electrode and the at least two hard mask layers. The method further comprises forming a contact etch stop layer (CESL) over the gate structure, exposing at least one of the HM layers after forming the CESL, and removing the exposed at least one of the HM layers. | 2014-10-30 |
20140322873 | HIGH PERFORMANCE STRESS-ENHANCED MOSFETS USING SI:C AND SIGE EPITAXIAL SOURCE/DRAIN AND METHOD OF MANUFACTURE - Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a stressing layer on a substrate. The method may include doping the stressing layer with dopants. The method may include forming a silicide layer on the stressing layer. Moreover, the stressing layer may include a first lattice constant different from a second lattice constant of the substrate. | 2014-10-30 |
20140322874 | NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced. | 2014-10-30 |
20140322875 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer. | 2014-10-30 |
20140322876 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer. | 2014-10-30 |
20140322877 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n | 2014-10-30 |
20140322878 | SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME - A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced. | 2014-10-30 |
20140322879 | METHOD OF FORMING SIGMA-SHAPED TRENCH - A method of forming a Σ-shaped trench is disclosed. The method includes: providing a silicon substrate; and sequentially performing a plasma etching process and a wet etching process on the silicon substrate to form a Σ-shaped trench therein. The plasma etching process includes: horizontally etching the silicon substrate using a first plasma etching gas including a nitrogen-containing fluoride; and vertically etching the silicon substrate using a second plasma etching gas including a polymer gas. A method of forming a semiconductor device is also disclosed. | 2014-10-30 |
20140322880 | METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND A METHOD OF MANUFACTURING SAME USING DUMMY GATE PROCESS - A method of manufacturing a transistor by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a mixed crystal layer. | 2014-10-30 |
20140322881 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer. | 2014-10-30 |
20140322882 | METHODS OF FORMING FIELD EFFECT TRANSISTORS, INCLUDING FORMING SOURCE AND DRAIN REGIONS IN RECESSES OF SEMICONDUCTOR FINS - Methods of forming a fin-shaped Field Effect Transistor (FinFET) are provided. The methods may include selectively incorporating source/drain extension-region dopants into source and drain regions of a semiconductor fin, using a mask to block incorporation of the source/drain extension-region dopants into at least portions of the semiconductor fin. The methods may include removing portions of the source and drain regions of the semiconductor fin to define recesses therein. The methods may include epitaxially growing source and drain regions from the recesses in the semiconductor fin. | 2014-10-30 |
20140322883 | METHOD FOR FABRICATING METAL-OXIDE SEMICONDUCTOR TRANSISTOR - A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates. | 2014-10-30 |
20140322884 | Nonvolatile resistive memory element with a silicon-based switching layer - A nonvolatile resistive memory element includes a novel switching layer and methods of forming the same. The switching layer includes a material having bistable resistance properties and formed by bonding silicon to oxygen or nitrogen. The switching layer may include at least one of SiO | 2014-10-30 |
20140322885 | METHOD OF MAKING A RESISTIVE RANDOM ACCESS MEMORY DEVICE - A method for forming a resistive random access memory (RRAM) device is disclosed. The method comprises forming a first electrode, forming a resistive switching oxide layer comprising a metal oxide by thermal atomic layer deposition (ALD) and forming a second electrode by thermal atomic layer deposition (ALD), where the resistive switching layer is interposed between the first electrode and the second electrode. Forming the resistive switching oxide may be performed without exposing a surface of the switching oxide layer to a surface-modifying plasma treatment after depositing the metal oxide. | 2014-10-30 |
20140322886 | RESISTIVE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit. | 2014-10-30 |
20140322887 | Surface Treatment to Improve Resistive-Switching Characteristics - This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution. | 2014-10-30 |
20140322888 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - According to an example embodiment, a variable resistance memory device includes a lower electrode that includes a spacer-shaped first sub lower electrode and a second sub lower electrode covering a curved sidewall of the first sub lower electrode. The second sub lower electrode extends upward to protrude above the top of the first sub lower electrode. The lower electrode includes an upward-tapered shape. | 2014-10-30 |
20140322889 | HIGH VOLTAGE RESISTOR WITH BIASED-WELL - Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L. | 2014-10-30 |
20140322890 | POLISHING SYSTEMS AND METHODS FOR REMOVING CONDUCTIVE MATERIAL FROM MICROELECTRONIC SUBSTRATES - Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material. | 2014-10-30 |
20140322891 | METHOD OF FORMING SHALLOW TRENCH ISOLATIONS - A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer. | 2014-10-30 |
20140322892 | MULTI-WAFER PAIR ANODIC BONDING APPARATUS AND METHOD - An electric field concurrently anodically bonds together wafers of each of a plurality of independent wafer pairs. | 2014-10-30 |
20140322893 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device with a treated member, includes: subjecting an adhesive support having a substrate and an adhesive layer capable of increasing or decreasing in adhesiveness upon irradiation with an actinic ray, radiation or heat to irradiation of the adhesive layer with an actinic ray, radiation or heat, adhering a first surface of a to-be-treated member to the adhesive layer of the adhesive support, applying a mechanical or chemical treatment to a second surface different from the first surface of the to-be-treated member to obtain a treated member, and detaching a first surface of the treated member from the adhesive layer of the adhesive support, wherein the irradiation of the adhesive layer with an actinic ray, radiation or heat is conducted so that adhesiveness decreases toward an outer surface from an inner surface on the substrate side of the adhesive layer. | 2014-10-30 |
20140322894 | Method for Handling a Thin Substrate and for Substrate Capping - An embodiment is a method for bonding. The method comprises bonding a handle substrate to a capping substrate; thinning the capping substrate; etching the capping substrate; and after the thinning and the etching the capping substrate, bonding the capping substrate to an active substrate. The handle substrate has an opening therethrough. The method also comprises removing the handle substrate from the capping substrate. The removing comprises providing an etchant through the opening to separate the handle substrate from the capping substrate. Other embodiments further include forming a bonding material on a surface of at least one of the handle substrate and the capping substrate such that the capping substrate is bonded to the handle substrate by the bonding material. The bonding material may be removed by using a dry etching to remove the handle substrate from the capping substrate. | 2014-10-30 |
20140322895 | METHOD FOR MANUFACTURING A BONDED SOI WAFER - According to the present invention, there is provided a method for manufacturing an SOI wafer having the step of performing a first sacrificial oxidation treatment on the aforementioned bonded SOI wafer in which the delamination has been performed after a first RTA treatment has been performed thereon and then performing a second sacrificial oxidation treatment thereon after a second RTA treatment has been performed thereon, wherein the first and second RTA treatments are performed under a hydrogen gas containing atmosphere and at a temperature of 1100° C. or more, wherein after a thermal oxide film has been formed on the aforementioned SOI layer front surface by performing only thermal oxidation by a batch type heat treating furnace at a temperature of 900° C. or more and 1000° C. or less in the first and second sacrificial oxidation treatments, a treatment for removing the thermal oxide film is performed. | 2014-10-30 |
20140322897 | FLOW CONTROLLED LINER HAVING SPATIALLY DISTRIBUTED GAS PASSAGES - Embodiments of the present disclosure provide a liner assembly including a plurality of individually separated gas passages. The liner assembly enables tenability of flow parameters, such as velocity, density, direction and spatial location, across a substrate being processed. The processing gas across the substrate being processed may be specially tailored for individual processes with a liner assembly according to embodiment of the present disclosure. | 2014-10-30 |
20140322898 | NANOCOMPOSITE AND METHOD OF MAKING THEREOF - An embodiment of an inorganic nanocomposite includes a nanoparticle phase and a matrix phase. The nanoparticle phase includes nanoparticles that are arranged in a repeating structure. In an embodiment, the nanoparticles have a spherical or pseudo-spherical shape and are incompatible with hydrazine. In another embodiment, the nanoparticles have neither a spherical nor pseudo-spherical shape. The matrix phase lies between the nanoparticles of the nanoparticle phase. An embodiment of a method of making an inorganic nanocomposite of the present invention includes forming a nanoparticle superlattice on a substrate. The nanoparticle superlattice includes nanoparticles. Each nanoparticle has organic ligands attached to a surface of the nanoparticle. The organic ligands separate adjacent nanoparticles within the nanoparticle superlattice. The method also includes forming a solution that includes an inorganic precursor. The nanoparticle superlattice is placed in the solution for a sufficient time for the inorganic precursor to replace the organic ligands. | 2014-10-30 |
20140322899 | SUBSTRATE RECYCLING METHOD - Exemplary embodiments of the present disclosure relate to a substrate recycling method and a recycled substrate. The method includes separating a first surface of a substrate from an epitaxial layer; forming a protective layer on an opposing second surface of the substrate; electrochemically etching the first surface of the substrate; and chemically etching the electrochemically etched first surface of the substrate. | 2014-10-30 |
20140322900 | LOW-PRESSURE CHEMICAL VAPOR DEPOSITION APPARATUS AND THIN-FILM DEPOSITION METHOD THEREOF - A low-pressure chemical vapor deposition (LPCVD) apparatus and a thin-film deposition method thereof The apparatus comprises a reaction furnace, having reaction gas input pipelines respectively arranged at a furnace opening part and a furnace tail part. During thin film deposition, each reaction gas is synchronously introduced into the reaction furnace through the input pipeline at the furnace opening part and the input pipeline at the furnace tail part. | 2014-10-30 |
20140322901 | SEMICONDUCTOR NANOCRYSTALS, METHOD FOR PREPARING, AND PRODUCTS - A method for preparing semiconductor nanocrystals includes adding a non-protonated surface modification agent to semiconductor nanocrystal cores in a liquid medium to form a mixture; adding one or more precursors for forming a shell including a semiconductor material to the mixture under conditions for forming the shell over at least a portion of an outer surface of the cores, and adding an acid ligand to the mixture after addition of at least a portion of the one or more precursors. Semiconductor nanocrystals, other methods of making semiconductor nanocrystals, compositions and products including semiconductor nanocrystals are also disclosed. | 2014-10-30 |
20140322902 | METHODS FOR USING ISOTOPICALLY ENRICHED LEVELS OF DOPANT GAS COMPOSITIONS IN AN ION IMPLANTATION PROCESS - A novel process for using enriched and highly enriched dopant gases is provided herein that eliminates the problems currently encountered by end-users from being able to realize the process benefits associated with ion implanting such dopant gases. For a given flow rate within a prescribed range, operating at a reduced total power level of the ion source is designed to reduce the ionization efficiency of the enriched dopant gas compared to that of its corresponding non-enriched or lesser enriched dopant gas. The temperature of the source filament is also reduced, thereby mitigating the adverse effects of fluorine etching and ion source shorting when a fluorine-containing enriched dopant gas is utilized. The reduced levels of total power in combination with a lower ionization efficiency and lower ion source temperature can interact synergistically to improve and extend ion source life, while beneficially maintaining a beam current that does not unacceptably deviate from previously qualified levels. | 2014-10-30 |
20140322903 | ENRICHED SILICON PRECURSOR COMPOSITIONS AND APPARATUS AND PROCESSES FOR UTILIZING SAME - Isotopically enriched silicon precursor compositions are disclosed, as useful in ion implantation to enhance performance of the ion implantation system, in relation to corresponding ion implantation lacking such isotopic enrichment of the silicon precursor composition. The silicon dopant composition includes at least one silicon compound that is isotopically enriched above natural abundance in at least one of | 2014-10-30 |
20140322904 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - An exemplary semiconductor device comprises a through silicon via penetrating a semiconductor substrate including a circuit pattern on one side of the substrate, a first doped layer formed in the other side , and a bump connected with the through silicon via. | 2014-10-30 |
20140322905 | METHOD OF FORMING THE BUFFER LAYER IN THE LTPS PRODUCTS - The present disclosure disclosed a method of forming the buffer layer in the LTPS products. The method comprises the following steps: heating the substrate to make the alkali metal ions diffuse to the surface of the glass; washing the substrate by acid to remove the alkali metal ions on the surface of the glass; forming the buffer layer on the glass which has been heated and washed by acid, wherein the material of the buffer layer is SiOx. The method of the present disclosure based on the design of the single buffer layer, it can greatly promote the capacity and can economize the gas. Furthermore, it can avoid the cross contamination of the different layers so as to promote characteristic of the element. | 2014-10-30 |
20140322906 | Method for Patterned Doping of a Semiconductor - A method for an improved doping process allows for improved control of doping concentrations on a substrate. The method may comprise printing a polymeric material on a substrate in a desired pattern; and depositing a barrier layer on the substrate with a liquid phase deposition process, wherein a pattern of the barrier layer is defined by the polymeric material. The method further comprises removing the polymeric material, and doping the substrate. The barrier layer substantially prevents or reduces doping of the substrate to allow patterned doping regions to be formed on the substrate. The method can be repeated to allow additional doping regions to be formed on the substrate. | 2014-10-30 |
20140322907 | SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR - A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact. | 2014-10-30 |
20140322908 | METHOD OF MAKING BOND PAD - A method of making a bonding pad for a semiconductor device which includes forming a first region over a buffer layer, where the first region includes aluminum and having a first average grain size. The method further includes forming a second region over the first region, where the second region includes aluminum, and where the second region has a second average grain size different from the first average grain size. Additionally, the method includes forming a first passivation layer surrounding the first region and the second region. Furthermore, the method includes forming a second passivation layer partially covering the second region, where the first region and the second region extend along a top surface of the first passivation layer. | 2014-10-30 |
20140322909 | Wafer Backside Interconnect Structure Connected to TSVs - An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line. | 2014-10-30 |
20140322910 | VIA-FREE INTERCONNECT STRUCTURE WITH SELF-ALIGNED METAL LINE INTERCONNECTIONS - The present disclosure provides a method for forming a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer. | 2014-10-30 |
20140322911 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A method of forming a semiconductor device may include forming a contact mold layer on a substrate; forming an interconnection mold layer on the contact mold layer that includes a material having an etching selectivity with respect to the contact mold layer; forming grooves in the interconnection mold layer that extend in a first direction and expose the contact mold layer; forming holes in the contact mold layer connected to the grooves by etching a part of the contact mold layer exposed by the groove; and forming contact portions in the holes and interconnections in the groove. A diffusion coefficient of mobile atoms in the contact mold layer is greater than a diffusion coefficient of mobile atoms in a nitride. | 2014-10-30 |
20140322912 | METHOD AND COMPOSITION FOR ELECTRODEPOSITION OF COPPER IN MICROELECTRONICS WITH DIPYRIDYL-BASED LEVELERS - A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound. | 2014-10-30 |
20140322913 | POLISHING COMPOSITION - A polishing composition of the present invention is to be used for polishing an object including a portion containing a high-mobility material and a portion containing a silicon material. The polishing composition comprises an oxidizing agent and abrasive grains having an average primary particle diameter of 40 nm or less. The polishing composition preferably further contains a hydrolysis-suppressing compound that bonds to a surface OH group of the portion containing a silicon material of the object to function to suppress hydrolysis of the portion containing a silicon material. Alternatively, a polishing composition of the present invention contains abrasive grains, an oxidizing agent, and a hydrolysis-suppressing compound. The polishing composition preferably has a neutral pH. | 2014-10-30 |
20140322914 | GAP EMBEDDING COMPOSITION, METHOD OF EMBEDDING GAP AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE BY USING THE COMPOSITION - A gap embedding composition used for embedding a patterned gap formed between photosensitive resin film portions on a semiconductor substrate surface, the gap embedding composition, having a hydrolysis condensate having an average molecular weight of 3,000 to 50,000 derived from an alkoxysilane raw material including at least alkyltrialkoxysilane and an ether compound having a total carbon atom of from 7 to 9 and/or an alkyl alcohol compound having a total carbon atom of from 6 to 9, as a solvent. | 2014-10-30 |
20140322915 | SEMICONDUCTOR DEVICE HAVING HARD MASK STRUCTURE AND FINE PATTERN AND FORMING METHOD THEREOF - A method for fabricating a semiconductor device includes forming a plurality of first hard mask patterns separated by a plurality of trenches on a target layer, forming a plurality of second hard mask patterns filling the plurality of trenches, forming a plurality of first opening units in the plurality of second hard mask patterns, forming a plurality of second opening units in the plurality of first hard mask patterns and forming a plurality of patterns using the plurality of first opening units and the plurality of second opening units, which are transferred by etching the target layer. | 2014-10-30 |
20140322916 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE USING VOIDS IN A SACRIFICIAL LAYER - A semiconductor device is fabricated by forming first holes arranged along a first direction on an etch-target layer, forming dielectric patterns in the first holes, conformally forming a barrier layer on the dielectric patterns, forming a sacrificial layer on the barrier layer to define a first void, partially removing the sacrificial layer to expose the first void, anisotropically etching the barrier layer to form second holes below the first void, and etching portions of the etch-target layer located below the first and second holes to form contact holes. The first void may be formed on a first gap region confined by at least three of the dielectric patterns disposed adjacent to each other, and the sacrificial layer may include a material having a low conformality. | 2014-10-30 |
20140322917 | GRAPHO-EPITAXY DSA PROCESS WITH DIMENSION CONTROL OF TEMPLATE PATTERN - A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern. | 2014-10-30 |
20140322918 | MICRO-POSTS HAVING IMPROVED UNIFORMITY AND A METHOD OF MANUFACTURE THEREOF - As discussed herein, there is presented an apparatus comprising micro-posts. The apparatus includes a substrate having a planar surface, a plurality of micro-posts located on the planar surface, wherein each micro-post has a base portion on the planar surface and a post portion located on a top surface of the corresponding base portion, and wherein side surfaces of the base portions intersect the planar surface at oblique angles. | 2014-10-30 |
20140322919 | SEMICONDUCTOR WAFER CHUCK AND METHOD - A semiconductor wafer spinning chuck includes a rotatable base, a plurality of arms, upstanding from the base, a selectively releasable clamping mechanism, associated with the arms, and a spray nozzle, extending through the base. The clamping mechanism has a first portion configured to mechanically clamp an edge of a first semiconductor wafer and hold the first wafer in a substantially horizontal orientation upon all of the arms, with a backside of the first wafer facing down. The spray nozzle is oriented to direct a spray of fluid at the backside of the first wafer. | 2014-10-30 |
20140322920 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - Provided are a deposition apparatus and a method of manufacturing a semiconductor device. In the method, a reaction chamber provided with a gaseous source supply unit and a liquid source supply unit is prepared, and an etch stop layer is formed on a substrate by using a gaseous source. Then, an interlayer insulation layer is formed on the etch stop layer by using a vaporized liquid source and a vaporized dopant source. In this way, the etch stop layer and the interlayer insulation layer are formed in-situ in the same reaction chamber. | 2014-10-30 |
20140322921 | Method and apparatus for microwave treatment of dielectric films - A method for processing a dielectric film on a substrate comprises: depositing a porous dielectric film on a substrate; removing the porogen; stuffing the film with a protective polymeric material; performing at least one intermediate processing step on the stuffed dielectric film; placing the film in a microwave applicator cavity and heating to a first temperature to partially burn out the polymeric material; introducing a controlled amount of a polar solvent into the porosity created by the partial burn out; applying microwave energy to heat the film to a second selected temperature below the boiling point of the solvent to clean away remaining polymeric material; and applying microwave energy to heat the film to a third temperature above the boiling point of the solvent to completely burnout the residues of polymeric material. The interaction of the polar solvent with the microwaves enhances the efficiency of the cleaning process. | 2014-10-30 |
20140322922 | Method and apparatus for microwave treatment of dielectric films - An apparatus for thermal treatment of dielectric films on substrates comprises: a microwave applicator cavity and microwave power source; a workpiece to be heated in the cavity, comprising a porous coating on a selected substrate; and, a means of introducing a controlled amount of a polar solvent into said porous coating immediately before heating by said microwave power. The interaction of the polar solvent with the microwaves enhances the efficiency of the process, to shorten process time and reduce thermal budget. A related method comprises the steps of: depositing a porous film on a substrate; soft baking the film to a selected state of dryness; introducing a controlled amount of a polar solvent into the soft baked film; and, applying microwave energy to heat the film via interaction with the polar solvent. | 2014-10-30 |
20140322923 | DIELECTRICS CONTAINING AT LEAST ONE OF A REFRACTORY METAL OR A NON-REFRACTORY METAL - Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film. | 2014-10-30 |