44th week of 2014 patent applcation highlights part 24 |
Patent application number | Title | Published |
20140320122 | CURRENT SENSOR - A first magnetoelectric conversion element group including magnetoelectric conversion elements, and a second magnetoelectric conversion element group including magnetoelectric conversion elements are arranged across a cutout of a wiring board. The first and second groups are arranged line-symmetrically with respect to a first imaginary line. The elements in the first and second groups are arranged line-symmetrically with respect to a second imaginary line. The first imaginary line and the second imaginary line orthogonally intersect each other at a placement position at which a current path to be measured is placed. The orientation of the sensitivity axis of each of a plurality of magnetoelectric-conversion-element sets having point symmetry about the placement position is parallel or antiparallel. An element spacing, which is spacing between neighboring elements in the first and second groups, is narrower than a group spacing, which is the narrowest spacing between the first and second groups. | 2014-10-30 |
20140320123 | OPTICAL PUMPING MAGNETOMETER AND MAGNETIC SENSING METHOD - An optical pumping magnetometer is provided that is capable of improving the response of the magnetometer with respect to a magnetic field that varies with a period shorter than the transverse relaxation time of electron spin of an alkali metal atom. | 2014-10-30 |
20140320124 | INTEGRATED CIRCUIT PACKAGE HAVING A SPLIT LEAD FRAME AND A MAGNET - A magnetic field sensor includes a lead frame having a plurality of leads, at least two of which have a connection portion and a die attach portion. A semiconductor die is attached to the die attach portion of the at least two leads and a separately formed ferromagnetic element, such as a magnet, is disposed adjacent to the lead frame. | 2014-10-30 |
20140320125 | NON-INTRUSIVE MONITORING - Methods and apparatus for non-intrusive monitoring by sensing physical parameters such as electric and/or magnetic fields. Such apparatus and techniques may find application in a variety of fields, such as monitoring consumption of electricity, water, etc., in homes or businesses, for example, or industrial process monitoring. | 2014-10-30 |
20140320126 | Statistical Analysis of Combined Log Data - A method for determining at least one characteristic of a geological formation having a borehole therein may include collecting nuclear magnetic resonance (NMR) data of the geological formation adjacent the borehole, and collecting non-NMR data for the geological formation adjacent the wellbore. The method may further include performing a Monte Carlo analysis based upon a combination of the collected NMR and non-NMR data to determine the at least one characteristic of the geological formation having a bounded uncertainty therewith. | 2014-10-30 |
20140320127 | METHOD AND DEVICE FOR DETERMINATION OF A MAGNETIC RESONANCE CONTROL SEQUENCE - In a method and device for the determination of a magnetic resonance control sequence that includes at least one first pulse arrangement that acts in a spatially selective manner in a first selection direction and a subsequent second pulse arrangement that acts in a spatially selective manner in a second selection direction, viewing volume dimension parameter values are registered that define the spatial extent of a viewing volume to be excited. The first selection direction and the second selection direction are established automatically depending on a length ratio of the spatial extent of the viewing volume to be excited in the different selection directions. | 2014-10-30 |
20140320128 | METHOD AND MAGNETIC RESONANCE APPARATUS TO ACQUIRE IMAGE DATA SETS OF AN EXAMINATION SUBJECT - In a magnetic resonance method and apparatus to image data sets of an examination subject by operation of the magnetic resonance apparatus, after detecting a region of the examination subject that is relevant to the examination, a coil element from each of two coil units is selected depending on the detected region, and acquisition of the image data sets of the examination subject takes place with the use of the selected coil elements. The selection of the coil elements of the coil units can be based on information about a position of a slice of a volume of the examination subject, and the position of the slice can be determined automatically using reference measurements. | 2014-10-30 |
20140320129 | MAGNETIC RESONANCE SPECTROSCOPIC IMAGING VOLUME OF INTEREST POSITIONING - A MRSI system ( | 2014-10-30 |
20140320130 | Antenna Array for a Magnetic Resonance Tomography System - An antenna array for a magnetic resonance tomography system includes a first ring with a plurality of first capacitors, a second ring with a plurality of second capacitors, and a plurality of antenna rods each extending from a region between two adjacent first capacitors to a region between two adjacent second capacitors. The antenna array enables, as a body coil, a multi-channel reception for use of modern imaging methods with a low level of technical complexity. An antenna rod of the plurality of antenna rods comprises a decoupling module configured to decouple, as required, the respective antenna rod from the remaining antenna rods of the plurality of antenna rods. | 2014-10-30 |
20140320131 | NMR RF PROBE COIL EXHIBITING DOUBLE RESONANCE - NMR probe coils designed to operate at two different frequencies, producing a strong and homogenous magnetic field at both the frequencies. This single coil, placed close to the sample, provides a method to optimize the NMR detection sensitivity of two different channels. In addition, the present invention describes a coil that generates a magnetic field that is parallel to the substrate of the coil as opposed to perpendicular as seen in the prior art. The present invention isolates coils from each other even when placed in close proximity to each other. A method to reduce the presence of electric field within the sample region is also considered. Further, the invention describes a method to adjust the radio-frequency tuning and coupling of the NMR probe coils. | 2014-10-30 |
20140320132 | COIL ARRANGEMENT FOR MPI - The present invention relates to a coil arrangement, in particular for use in a magnetic particle imaging apparatus ( | 2014-10-30 |
20140320133 | SONDE DEVICES INCLUDING A SECTIONAL FERRITE CORE - Sonde devices for providing magnetic field signals for use with utility locators or other devices are disclosed. In one embodiment a sonde device includes a housing, a core comprising a plurality of core sections, and one or more support structures, which may include windings. Circuit and/or power supply elements may be disposed fully or partially within the core to control generation of predefined magnetic field frequencies and waveforms. | 2014-10-30 |
20140320134 | Electroacoustic Method of Conductivity Measurement Through Casing - The present disclosure relates to methods and apparatuses for evaluating a porous earth formation. The method may include estimating a value of at least one parameter of interest of the earth formation using a signal indicative of acoustic waves generated at a metallic surface ( | 2014-10-30 |
20140320135 | SENSOR MODULE AND ELECTRODE FOR A SENSOR MODULE - The invention relates to a sensor module ( | 2014-10-30 |
20140320136 | METHOD OF TESTING ORGANIC LIGHT-EMITTING DISPLAY PANEL, MOTHER SUBSTRATE TESTING APPARATUS, AND METHOD OF TESTING MOTHER SUBSTRATE - A method of testing an organic light-emitting display panel, a mother substrate testing apparatus, and a method of testing a mother substrate are provided. The method of testing an organic light-emitting display panel includes operations of applying an electric field to an encapsulation layer of the organic light-emitting display panel and determining a defect of the organic light-emitting display panel. | 2014-10-30 |
20140320137 | INSPECTION METHOD AND INSPECTION APPARATUS - An inspection method including following steps is provided. A pixel array substrate including a plurality of pixel units is in contact with a photoelectric inspection device. A plurality of electrical signals is inputted to the pixel units of the pixel array substrate and the photoelectric inspection device. Based on an optical property of the photoelectric inspection device, the pixel units of the pixel array substrate are being examined on whether they are normal or not. Moreover, an inspection apparatus realizing the inspection method is also provided. | 2014-10-30 |
20140320138 | LOOP POWERED ISOLATED CONTACT INPUT CIRCUIT AND METHOD FOR OPERATING THE SAME - A voltage is sensed at a switching device and the voltage is associated with a status of a switching device. The sensed voltage is converted to a useable voltage regardless of the value and type of the sensed voltage. At a single self-contained integrated circuit that is powered by the sensed voltage, the usable voltage is converted into a digital representation. The digital representation is configured to be usable by a processing device to determine the value of the voltage at the switching device. | 2014-10-30 |
20140320139 | APPARATUS AND METHOD FOR REMOTE MONITORING OF PARTIAL DISCHARGE IN ELECTRICAL APPARATUS - Apparatus for remote monitoring of partial discharge events in electrical apparatus | 2014-10-30 |
20140320140 | METHOD FOR DETERMINING COMPLETION OF DISCHARGE OF A WASTE BATTERY AND DETERMINATION DEVICE - Provided is an efficient method for determining the completion of discharging waste batteries, the method being capable of accurately identifying the discharging states of the charge remaining in the waste batteries and appropriately determining the completion of discharging without measuring the residual voltage of each of the waste batteries. The method for determining the completion of discharging waste batteries according to the present invention is characterized in that after immersing the waste batteries in a conductive liquid, the concentration of hydrogen gas produced from the liquid is measured, thereby determining the completion of discharging the charge remaining in the waste batteries. | 2014-10-30 |
20140320141 | SECONDARY BATTERY CONTROL DEVICE AND SOC DETECTION METHOD - A control device of a secondary battery uses, as material of a positive electrode, positive electrode active material that shows a difference of an open circuit voltage curve between charging and discharging. A storing unit stores, as discharge open circuit voltage information, a relationship between an SOC in a discharge process and an open circuit voltage for each changeover SOC that is an SOC when changing a state of the secondary battery from the charge to the discharge. An SOC calculating unit calculates the SOC of the secondary battery in the discharge process on the basis of a changeover SOC when actually performing the change from the charge to the discharge and the discharge open circuit voltage information stored in the storing unit. It is therefore possible to properly detect the SOC during the discharge | 2014-10-30 |
20140320142 | METHOD AND SYSTEM FOR MEASURING ELECTRIC CURRENT - A system for measuring electric current supplied by an electric battery, for example a battery in a motor vehicle, including: a Hall effect current sensor; a device for compensating for measurement errors made by the sensor, including a mechanism applying an operation close to the inverse of an operator characterizing magnetic hysteresis of the sensor to the measured current. | 2014-10-30 |
20140320143 | BATTERY MANAGEMENT SYSTEM AND METHOD FOR DETERMINING THE CHARGE STATE BATTERY CELLS, BATTERY AND MOTOR VEHICLE COMPRISING A BATTERY MANAGEMENT SYSTEM - A method for determining the charge state of battery cells or battery modules of a battery includes monitoring several battery cells or at least one battery module using a plurality of cell monitoring units. The respective electric current of the battery cells or battery modules is measured by the cell monitoring units, the battery current is measured, and the measured current value is transmitted to the plurality of cell monitoring units. A charge state is calculated in each of the cell monitoring units for the respective monitored battery cells, or respectively, the at least one battery module. A battery management system is configured to carry out the method for determining the charge state of the battery cells or battery modules of the battery. A battery and a motor vehicle include the battery management. | 2014-10-30 |
20140320144 | STORAGE BATTERY TRANSFER SUPPORT DEVICE AND STORAGE BATTERY TRANSFER SUPPORT METHOD - The present invention serves to reduce the costs associated with the overall life cycle of storage batteries by performing support so that a plurality of batteries are transferred between and used at a plurality of facilities. This storage battery transfer support device comprises: a collection unit that collects battery information representing the status of each battery used at a plurality of facilities; a battery information storage unit that stores the battery information collected by the collection unit; and a deterioration prediction unit that, on the basis of the battery information stored in the battery information storage unit, predicts deterioration of storage batteries that have been transferred between and used at a plurality of facilities. | 2014-10-30 |
20140320145 | OSCILLOSCOPE SYSTEM AND METHOD FOR SIMULTANEOUSLY DISPLAYING ZOOMED-IN AND ZOOMED-OUT WAVEFORMS - An oscilloscope system includes a current probe, a processing unit and a display unit. The current probe includes a high and low gain signal paths for receiving simultaneously a signal of interest from a device under test (DUT), and to output amplified small and large current portions of the signal of interest, respectively. The processing unit receives first and second digitized data corresponding to the amplified small and large current portions output by the high and low gain signal paths, respectively, and processes the first and second digitized data for display as zoomed-in and zoomed-out waveform data, respectively. The display unit displays simultaneously a zoomed-in waveform in a first display window, based on the zoomed-in waveform data, and a zoomed-out waveform in a second display window, based on the zoomed-out waveform data, using the same time scale. The small current portion is less than a predetermined threshold. | 2014-10-30 |
20140320146 | ION CHROMATOGRAPH - A suppressor is structured by an ion exchange section being structured by an eluate path forming member forming an eluate path and a regenerant path forming member forming a regenerant path being stacked across an ion exchange film, and a heat-conductive heat block covering the outside of the ion exchange section. A separation column, the suppressor, and an electrical conductivity meter are accommodated in a common constant temperature bath. The inside of the constant temperature bath is feedback-controlled by a temperature control section so as to be maintained at constant temperature. | 2014-10-30 |
20140320147 | ELECTRICAL CIRCUIT - An electrical circuit includes a first circuit part and a second circuit part. A first electrical potential is applicable to the first circuit part, wherein a second electrical potential is applicable to the second circuit part. The two circuit parts are galvanically isolated from each other by an insulator, wherein the insulator includes a conducting portion. This conducting portion can be safely sensed by an additional circuitry, to detect if a full or partial contact to the first electrical potential or the second electrical potential has occurred due to a voltage shift or a current flow on the conducting portion, which is itself insulated. This sensing circuitry can incorporate protection elements to clamp voltages and limit currents to prevent destruction of connected circuitries in case of a fail of the insulation. | 2014-10-30 |
20140320148 | SYSTEM AND METHOD FOR DETECTING EXCESS VOLTAGE DROP IN THREE-PHASE AC CIRCUITS - A system and method for detecting excess voltage drop (EVD) in a three-phase electrical distribution circuit includes a diagnostic system comprising a processor that is programmed to receive three-phase voltages and currents provided to terminals of the electrical machine, determine fundamental components of the three-phase voltages and currents provided to the terminals, and compute positive, negative, and zero sequence currents from the fundamental components. The processor is also programmed to extract a compensated negative sequence current from the negative sequence current component, add the compensated negative sequence current to the positive sequence current to determine fault reference current phasors, determine a negative current reference phase angle for each phase based in part on a phase angle of the positive sequence current, and identify an EVD fault in the electrical distribution circuit based on the compensated negative sequence current, the fault reference current phasors, and the negative current reference phase angles. | 2014-10-30 |
20140320149 | DEVICE FOR DETECTING FAULT IN AN ELECTRIC LINE - A device for detecting faults in an electric line between a voltage source and a load is disclosed, The device includes a signal-generation unit a signal-receiving unit and an evaluation mechanism. The signal-generation unit is configured to produce a power-line signal and transmit the power-line signal via the electric line to an external mechanism. The signal-receiving unit is configured to receive a response signal from the external mechanism, The evaluation mechanism is configured to detect an occurrence of a fault, when the signal-receiving unit fails to receive a response signal. | 2014-10-30 |
20140320150 | SHUNT RESISTOR BASED CURRENT SENSOR - A temperature sensor ( | 2014-10-30 |
20140320151 | Tamper Detection Arrangement - A tamper detection arrangement for use within an integrated circuit ( | 2014-10-30 |
20140320152 | Dosimetry via platinum-ruthenium nanoparticle-decorated nanostructure - A dosimeter includes a platinum-ruthenium (PtRu) nanoparticle-decorated, -coated, or -deposited carbon nanostructure element. The PtRu nanoparticle-decorated carbon nanostructure element is foulably sensitive to a gas. | 2014-10-30 |
20140320153 | Oscilloscope Current Probe with Interchangeable Range and Sensitivity Setting Modules - An oscilloscope current probe system includes a probe amplifier unit, a probe head identifier, and first and second probe heads interchangeably connectable to the probe amplifier unit. Each probe head has a respective electrically-readable type identifier, a respective current input to receive a current to be measured, a respective internal sensing resistor in connected series with the current input, and a respective output at which a measurement voltage across the sensing resistor is output. The first and second probe heads differ in the resistance of their sensing resistors and the way their type identifiers read. The probe amplifier unit includes a differential amplifier to amplify the measurement voltage output by the probe head connected thereto. The probe head identifier is to read the type identifier of the probe head connected to the probe amplifier unit. | 2014-10-30 |
20140320154 | FIELD DEVICE WITH SELF-TESTING OF A PIEZOELECTRIC TRANSDUCER - An industrial process field device having a piezoelectric transducer performs self-testing of the condition of the piezoelectric transducer during a self-test mode. A charging current is supplied to the piezoelectric transducer, and voltage on the piezoelectric transducer as a result of the charging current is monitored. A diagnostic test result indicating condition of the piezoelectric transducer is produced based on the magnitude of the voltage. | 2014-10-30 |
20140320155 | CRITICAL CAPACITOR BUILT IN TEST - An electronic circuit and method for carrying out built in test of a capacitor connected to, and arranged to suppress noise at, an input of an electrical circuit is disclosed. The electronic circuit causes current pulses at the input, and monitors the voltage at the input by comparing the voltage at the input with high and/or low reference voltages, outputting a fault signal if the voltage at the input is greater than a high reference voltage or lower than a low reference voltage. | 2014-10-30 |
20140320156 | APPARATUS FOR DETECTING MISALIGNMENT OF TEST PAD - An apparatus for detecting misalignment of a test pad and a probe card includes: a test pad unit; a guard unit configured to surround the test pad unit, and formed to maintain a predetermined interval with the test pad unit; and a power supply unit configured to supply a predetermined voltage to the guard unit. | 2014-10-30 |
20140320157 | OSCILLOSCOPE PROBE HAVING OUTPUT CLAMPING CIRCUIT - A probe for a measurement instrument comprises an input terminal configured to receive an input signal from a device under test (DUT), an output terminal configured to transmit an output signal to a measurement instrument, and a clamping circuit disposed in a signal path between the input terminal and the output terminal and configured to clamp an internal probe signal between an upper clamping threshold and a lower clamping threshold to produce the output signal, wherein the clamping circuit operates with substantial gain and amplitude linearity throughout a range between the upper clamping threshold and the lower clamping threshold. | 2014-10-30 |
20140320158 | Electrical Probe for Testing Electronic Device - An electrical probe comprises a cylindrical body which has a first end including a plurality of claws and a second end opposite to the first end for cooperating with an electrical test machine, wherein a concave contact surface conforming with the curvature of a solder ball of an electronic device under test is formed between the claws, whereby the first end of the cylindrical body can be brought into line contact with the solder ball at a predetermined length to ensure a proper electrical connection, so that the accuracy of an electrical test can be increased. | 2014-10-30 |
20140320159 | PROBE MEMBER FOR POGO PIN - Provided is a probe member for a pogo pin, which is used for testing a semiconductor device, and at least a portion of which is inserted into a cylindrical body to be supported by an elastic member and an upper end of which contacts a terminal of the semiconductor device. | 2014-10-30 |
20140320160 | INTEGRATED CIRCUIT FOR SWITCHING LOADS, CIRCUIT ARRANGEMENT COMPRISING AN INTEGRATED CIRCUIT AND A CONNECTED LOAD, AND METHOD FOR OPERATING SUCH A CIRCUIT ARRANGEMENT - An integrated circuit has a controllable switching element, the load path of which is arranged between an output of the integrated circuit and a supply potential. A test unit is connected to the connections of the switching element in order to carry out tests. A control unit is connected to the test unit via at least one control line. The sequence of tests is carried out dependent on signals on the control line(s). A memory is connected to the control unit the content and the type of which determines the time of the tests. The memory is connected to an input of the integrated circuit in order to enter the content. | 2014-10-30 |
20140320161 | TESTING SYSTEM AND METHOD FOR DC-TO-DC BUCK CONVERTER CIRCUIT - A testing system for a DC-to-DC buck converter circuit includes a multi-meter connected to the DC-to-DC buck converter circuit, an oscilloscope, and a control device. The control device is connected to the multi-meter and the oscilloscope and is configured to adjust the multi-meter and the oscilloscope, and gather data and waves measured by the multi-meter and the oscilloscope. The control device generates a test report according to the data and waves measured by the multi-meter and the oscilloscope. The present disclosure further discloses a testing method based upon the above testing system. | 2014-10-30 |
20140320162 | WIRING STATE DETECTION DEVICE AND INTELLIGENT POWER MODULE - A wiring state detection device is configured to detect a state of a wiring that detachably and electrically connects a drive unit and a control unit via a connector. The drive unit has a switching element. The control unit is configured to perform drive control of the switching element. The wiring state detection device includes a phase delay detection unit and a connection state determination unit. The phase delay detection unit is configured to detect a phase delay of the drive of the switching element with respect to a command signal that the control unit supplies toward the switching element of the drive unit. The connection state determination unit is configured to determine whether or not a connection state of the connector or the wiring is normal based on whether or not the phase delay detected by the phase delay detection unit is less than a predetermined threshold. | 2014-10-30 |
20140320163 | METHOD FOR MONITORING A PUMP - A method for monitoring the functioning of an electric motor-driven pump ( | 2014-10-30 |
20140320164 | FAST DYNAMIC REGISTER WITH TRANSPARENT LATCH - A fast dynamic register including a data block, a precharge circuit, a transparent latch, and an output logic gate. The precharge circuit precharges first and second precharge nodes and then releases the first precharge node in response to a clock. The data block evaluates data by either pulling the first precharge node low in response to the clock or does not pull it low, in which case the second precharge node is discharged. The transparent latch passes a state of the second precharge node to a store node when transparent, and otherwise latches the store node. The output logic gate drives an output node to a state based on states of the second precharge node and the store node. The transparent latch may be implemented with relatively small devices to reduce size and power consumption to improve efficiency. | 2014-10-30 |
20140320165 | Runtime Loading of Configuration Data In A Configurable IC - Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network. | 2014-10-30 |
20140320166 | FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY - Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a V | 2014-10-30 |
20140320167 | LEVEL CONVERSION CIRCUIT AND LEVEL-CONVERSION-FUNCTION-EQUIPPED LOGIC CIRCUIT - A level conversion circuit ( | 2014-10-30 |
20140320168 | LEVEL SHIFTER CIRCUIT AND OPERATION METHOD THEREOF - A level shifter transfers a first voltage signal to a second voltage signal. The level shifter comprises a comparison circuit, a delay circuit, and a selection circuit. The comparison circuit generates a first signal according to the comparison result between the first voltage signal and the reverse-phase signal of the first voltage signal. The delay circuit generates a second signal according to the first voltage signal. The selection circuit receives the first and the second signals and chooses the higher voltage one from the first signal and the second signal to be the second voltage signal. | 2014-10-30 |
20140320169 | CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY - A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output node. The control circuit is configured to turn off the transistor during the standby mode. | 2014-10-30 |
20140320170 | GLITCH FREE CLOCK MULTIPLEXER - Apparatus for glitch-free switching between two clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch between different (unrelated) clocks without causing erratic behavior. | 2014-10-30 |
20140320171 | ELECTRONIC CIRCUIT - An electronic circuit includes: a weighting circuit configured to generate a first current by weighting and combining a first input signal and a second input signal in accordance with a modifiable coefficient and to generate a second current by weighting and combining a first inverted signal and a second inverted signal in accordance with the coefficient, the first inverted signal being an inverted signal of the first input signal, the second inverted signal being an inverted signal of the second input signal; and a decision circuit configured to decide on an output signal by comparing the first current with the second current. | 2014-10-30 |
20140320172 | CURRENT-TO-VOLTAGE CONVERTER AND ELECTRONIC APPARATUS THEREOF - A current-to-voltage converter comprises a gain circuit, a flip circuit, and a chopper circuit. The gain circuit receives an input current, and amplifies the input current to generate an amplified current. The flip circuit receives the amplified current, and uses the amplified current to charge or discharge a capacitor thereof according to a charge signal and a discharge signal, so as to generate an output voltage, wherein before using the amplified current to charge or discharge the capacitor, the flip circuit resets the output voltage respectively to a charge reset voltage and a discharge reset voltage according to a charge reset signal and a discharge reset signal. When the capacitor is charged, the chopper circuit samples and holds the output voltage to generate a recovered voltage. When the capacitor is discharged, the chopper circuit samples, holds, and flips the output voltage to generate the recovered voltage. | 2014-10-30 |
20140320173 | FRACTIONAL PHASE LOCKED LOOP HAVING AN EXACT OUTPUT FREQUENCY AND PHASE AND METHOD OF USING THE SAME - A fractional-N frequency synthesizer having an exact output frequency and phase includes a phase locked loop including a phase detector responsive to a reference signal and a fractional divider. The phase locked loop has an output signal whose frequency is a fractional multiple of the input reference signal. The synthesizer also includes a modulator having a modulus for providing an output to the fractional divider, in which the modulus multiplied by the ratio of the frequency of the output signal to the frequency of the reference signal is a non-integer number. | 2014-10-30 |
20140320174 | INTEGRATED CIRCUITS WITH LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR STRUCTURES - Integrated circuits with improved LDMOS structures are provided. An integrated circuit includes a semiconductor substrate, a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions electrically isolate devices fabricated in the semiconductor substrate. The integrated circuit further includes a transistor structure. The transistor structure includes a gate dielectric positioned over a portion of a first one of the plurality of STI regions, a drain region adjacent to the first one of the plurality of STI regions and spaced apart from the gate dielectric, a first gate electrode that extends over a first portion of the gate dielectric, a second gate electrode that extends over a second portion of the gate dielectric and positioned adjacent to the first gate electrode, and a source region positioned adjacent to the first portion of the gate dielectric. | 2014-10-30 |
20140320175 | GATE DRIVING CIRCUIT - A gate driving circuit includes a first input terminal, a second input terminal, a third input terminal, an output terminal, a first transistor, a second transistor, a third transistor, and a capacitor. The first terminal of the first transistor is coupled to the first input terminal. The control terminal of the first transistor is coupled to the second input terminal. The first terminal of the second transistor is coupled to the third input terminal. The control terminal of the second transistor is coupled to the second terminal of the first transistor. The second terminal of the second transistor is coupled to the output terminal. The first terminal of the third transistor is coupled to the output terminal. The second terminal of the third transistor is coupled to ground terminal. The capacitor is coupled between the control terminal of the second transistor and the output terminal. | 2014-10-30 |
20140320176 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a transistor circuit including a power supply terminal and a back gate terminal; a variable resistance connected between a first voltage terminal and the power supply terminal; and a control circuit controlling the variable resistance based on a digital signal in which a difference voltage is converted when an absolute value of the difference voltage between a voltage of the first voltage terminal and a voltage of the back gate terminal is lower than a threshold value. | 2014-10-30 |
20140320177 | CIRCUIT FOR DRIVING HIGH-SIDE TRANSISTOR - A circuit for driving a transistor includes a drive circuit, a first voltage boost circuit and a second voltage boost circuit. The drive circuit has a first specific node, a second specific node, and a third specific node coupled to a control node of the transistor. The drive circuit is arranged for coupling the first specific node to the third specific node according to at least a voltage of the first specific node and a voltage of the second specific node in order to charge the control node. The first voltage boost circuit is coupled between the first specific node and a connection node of the transistor, and is arranged for boosting the voltage of the first specific node. The second voltage boost circuit is coupled between the first specific node and the second specific node, and is arranged for boosting the voltage of the second specific node. | 2014-10-30 |
20140320178 | INTELLIGENT GATE DRIVER FOR IGBT - A reverse-conducting insulated gate bipolar transistor, particularly a bi-mode insulated gate transistor, is controlled by responding to an ON command by applying high-level gate voltage for a first period, during which a current is fed into a connection point, from which it flows either through the RC-IGBT or along a different path. Based hereon, it is determined whether the RC-IGBT conducts in its forward/IGBT or reverse/diode mode, and the RC-IGBT is either driven at high or low gate voltage. Subsequent conduction mode changes may be monitored in the same way, and the gate voltage may be adjusted accordingly. A special turn-off procedure may be applied in response to an OFF command in cases where the RC-IGBT conducts in the reverse mode, wherein a high-level pulse is applied for a second period before the gate voltage goes down to turn-off level. | 2014-10-30 |
20140320179 | SIGNAL GENERATING APPARATUS FOR GENERATING POWER-ON-RESET SIGNAL - A signal generating apparatus, for generating a power-on-reset signal, including a bias circuit and a power-on-reset signal generating circuit is disclosed. The bias circuit is for generating an output bias voltage, and includes at least one bipolar junction transistor (BJT), wherein a base terminal of the BJT is coupled to a collector terminal of the BJT, and the output bias voltage is related to an emitter-to-base voltage of the BJT. The power-on-reset signal generating circuit is coupled to the bias circuit, and is for generating a duplicated voltage by duplicating the output bias voltage, wherein the power-on-reset signal is generated according to the duplicated voltage. | 2014-10-30 |
20140320180 | SEMICONDUCTOR DEVICE - In aspects of the invention, a semiconductor device can include one level shift circuit that outputs a low-side input signal as a high-side signal upon raising a signal level, a pulse modulation circuit that operates in a low-side region, generates a data symbol constituted by or more bits and representing a set signal or a reset signal, where bit is defined as a combination of codes forming a pair. The pulse generation circuit can output the generated data symbol as an input signal of the level shift circuit. Also included can be a pulse demodulation circuit that operates in a high-side region, demodulates the data symbol outputted from the level shift circuit and generates a level-shifted set signal or reset signal; and a control circuit that controls conduction/non-conduction of the high-potential-side switching element on the basis of the level-shifted set signal or reset signal outputted from the pulse demodulation circuit. | 2014-10-30 |
20140320181 | PHASE LOCKED LOOP WITH SIMULTANEOUS LOCKING TO LOW AND HIGH FREQUENCY CLOCKS - A phase-locked loop to is simultaneously synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to a high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference. | 2014-10-30 |
20140320182 | GEOGRAPHIC LOCATING REMOTE ENDPOINT MONITOR DEVICE, SYSTEM, AND METHODOLOGY THEREOF - A phase-locked loop frequency synthesizer includes an L-state pulse width modulator configured to receive a reference frequency signal and at least one entry from a frequency table, and to output at least one N/N+1 modulus signals corresponding to the at least one entry from the frequency table. The synthesizer includes a divide by N/N+1 controllable modulus divider configured to receive the at least one N/N+1 modulus signals and to divide the output frequency signal by the at least one N/N+1 modulus signals to generate a second reference frequency signal. The synthesizer includes a phase frequency detector configured to receive the reference frequency signal and the second reference frequency signal and to generate an error signal. The synthesizer also includes a filter network configured to receive the error signal and to output a voltage; and a voltage controlled oscillator configured to receive the voltage and to generate the output frequency signal. | 2014-10-30 |
20140320183 | PLL FREQUENCY SYNTHESIZER WITH MULTI-CURVE VCO IMPLEMENTING CLOSED LOOP CURVE SEARCHING USING CHARGE PUMP CURRENT MODULATION - A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit increases the charge pump current above a nominal current value during the closed loop curve search operation and set the charge pump current to the nominal current value after an operating curve is selected. | 2014-10-30 |
20140320184 | PLL FREQUENCY SYNTHESIZER WITH MULTI-CURVE VCO IMPLEMENTING CLOSED LOOP CURVE SEARCHING - A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit implements a binary jump method and an operating curve is selected when the operating curve has an output frequency meeting the target frequency with the control voltage being within a first voltage range being a narrowed and centered voltage range within the control voltage range. | 2014-10-30 |
20140320185 | PLL CIRCUIT - A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator. | 2014-10-30 |
20140320186 | PHASE LOCKED LOOP WITH PRECISE PHASE AND FREQUENCY SLOPE LIMITER - Phase slope is controlled in a phase locked loop wherein a phase error signal controlling a controlled oscillator has a proportional component and an integral component, by determining whether the proportional component falls within a range bounded by upper and lower limit values. The proportional component is combined with the integral component if the proportional component falls within the range to provide the phase error signal. Otherwise, the proportional component is modified to meet a phase slope requirement while leaving the integral component unmodified. The modified proportional component is combined with the unmodified integral component to provide the phase error signal. | 2014-10-30 |
20140320187 | BUFFER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A buffer circuit section receives an input clock, and outputs an output clock by wave-shaping the input clock, a measurement circuit section measures a first pulse width at a first potential level of the output clock and a second pulse width at a second potential level of the output clock, and an adjustment circuit section adjusts a ratio between the first pulse width and the second pulse width by varying a drive capability of the buffer circuit section on the basis of the measurement result of the measurement circuit section. | 2014-10-30 |
20140320188 | SCANNABLE FAST DYNAMIC REGISTER - A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration. | 2014-10-30 |
20140320189 | PROGRAMMABLE BUS SIGNAL HOLD TIME WITHOUT SYSTEM CLOCK - A circuit is disclosed that provides a programmable hold time for a bus signal without running a system clock and without a frequency requirement between the system clock and a bus clock. | 2014-10-30 |
20140320190 | POWER SUPPLY INDUCED SIGNAL JITTER COMPENSATION - Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response. | 2014-10-30 |
20140320191 | DIFFERENTIAL ANALOG SIGNAL PROCESSING STAGE WITH REDUCED EVEN ORDER HARMONIC DISTORTION - The even order harmonic distortion in a differential circuit is reduced or eliminated by treating the amplitude and phase mismatch sources that cause the distortion as impedance mismatches, and utilizing switched resistor circuitry that adjusts the load resistance to reduce the effects of the amplitude mismatch sources, and switched capacitor circuitry that adds shunt capacitance to reduce the effects of the phase mismatch sources. | 2014-10-30 |
20140320192 | INTERPOLATION CIRCUIT AND RECEIVING CIRCUIT - An interpolation circuit includes: a plurality of holding circuits configured to each hold a corresponding input data input chronologically; and a generating circuit configured to generate interpolation data by giving weights, based on an interpolation code, to input data that are chronologically adjacent to each other and are held by the plurality of holding circuits and combining the weighted data together. | 2014-10-30 |
20140320193 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first layer of a first-type, a second layer of a second-type formed on the first layer, a third layer of the first type formed on the second layer, a first electrode connected to the second and third layers, a second electrode connected to the first layer, a third electrode embedded in a trench formed through the third and second layers and into the first layer, a fourth electrode embedded in the trench below the third electrode, and an insulating layer formed in the trench around the fourth electrode. The first layer includes a first region that is in contact with the insulating layer and at which a concentration of the first-type dopant is lower than the concentration at a second region that is formed around the first region. | 2014-10-30 |
20140320194 | SOLID STATE POWER CONTROLLER GATE CONTROL - A system for controlling gate power includes a metal oxide semiconductor field effect transistor (MOSFET) configured to supply power to a load according to a gate control voltage applied to a gate of the MOSFET. The system includes a gate control circuit configured to turn on and off the gate control voltage supplied to the gate of the MOSFET. The system also includes a ramping circuit configured to perform at least one of ramping up a voltage applied to the gate of the MOSFET based on the gate control circuit turning on power to the gate of the MOSFET and ramping down the voltage applied to the gate of the MOSFET based on the gate control circuit turning off power to the gate of the MOSFET. | 2014-10-30 |
20140320195 | UNIVERSAL CONTACT INPUT APPARATUS AND METHOD FOR OPERATING THE SAME - At a contact input circuit, a voltage at a switching device is sensed and the voltage is associated with a status of a switching device. The contact input circuit is operated according to the sensed voltage regardless of the value of the sensed voltage. The power usage of the contact input circuit is maintained to be within a predetermined range of power consumption values regardless of the value of the sensed voltage. Wetting voltages can be continuously monitored and the approaches described herein can monitor open contact, closed contact, and open field wire conditions. | 2014-10-30 |
20140320196 | Control Device and Method for Actuating a Semiconductor Switch - A control device for influencing a flow of energy in a load circuit between an electrical voltage source and an electrical load, having a semiconductor switch including a conductive section which is formed between an input connection and an output connection, can be looped into the load circuit, and has an electrical resistance adjustable by means of an electrical potential which can be applied to a control connection associated with the semiconductor switch, and having a control circuit which is coupled to the control connection and includes a freewheeling means connected in parallel to the load. The control circuit is designed to supply a control current at the control connection which is proportional to a voltage via the freewheeling means. | 2014-10-30 |
20140320197 | GATE DRIVER CIRCUIT - In High Voltage CMOS technologies the supply voltage is typically higher than the maximum allowed gate voltage. In a switching output stage of amplifiers such class-D amplifiers and DC-DC converters the gates of the power field effect transistors need to be charged quickly. This requires a gate driver that is capable of delivering large currents without exceeding the maximum allowed voltage on the gate of the power field effect transistors. | 2014-10-30 |
20140320198 | PROTECTIVE DEVICE FOR A VOLTAGE-CONTROLLED SEMICONDUCTOR SWITCH - A protective device for a voltage-controlled semiconductor switch has a gate connection, a power emitter connection, an auxiliary emitter connection and a collector connection. The semiconductor switch can switch a current between the collector connection and the power emitter connection. A voltage-limiting device limits the voltage between the gate connection and the power emitter connection. A deactivation device is connected to the voltage-limiting device and deactivates the voltage-limiting device during a switch-on of the semiconductor switch. | 2014-10-30 |
20140320199 | Touchscreen Routing Flow for Single Layer Pattern - A touch sensor comprising a plurality of first electrode lines along a first direction, each of the first electrode lines comprising a plurality of first electrodes; a plurality of second electrode lines along a second direction that is substantially perpendicular to the first direction, each of the second electrode lines comprising one second electrode, the one second electrode of each of the second electrode lines being interdigitated with one of the first electrodes of each of the first electrode lines, the first and second electrodes being disposed on a first side of a substrate; and a plurality of bond pads disposed on the first side of the substrate, wherein at least one bond pad of the plurality of bond pads is coupled to at least two of the first electrodes of the plurality of first electrodes. | 2014-10-30 |
20140320200 | TOUCH SWITCH AND CONTROL PANEL - A technique reduces erroneous judgment due to effects of noise accompanying PWM control while using PWM control for brightness adjustment of light-emitting diodes disposed proximate of an electrode. An electrode is disposed proximate of operating portions that are subject to touch operations by unit of a conductive body. An operating portion of a light-emitting diode is lightened. A CPU performs brightness adjustment of the light-emitting diode through PWM control. A detecting circuit outputs detected values in accordance with electrostatic capacitances of the electrode. The CPU judges that a touch operation has been made when a difference between a detected value of the detecting circuit and a reference value stored in a RAM is not less than a prescribed value. The CPU stores a detected value that is first detected by the detecting circuit after transition of an executing state of PWM control in the RAM as a reference value. | 2014-10-30 |
20140320201 | APPARATUSES AND METHODS FOR PROVIDING CAPACITANCE IN A MULTI-CHIP MODULE - Apparatuses, multi-chip modules, capacitive chips, and methods of providing capacitance to a power supply voltage in a multi-chip module are disclosed. In an example multi-chip module, a signal distribution component may be configured to provide a power supply voltage. A capacitive chip may be coupled to the signal distribution component and include a plurality of capacitive units. The capacitive chip may be configured to provide a capacitance to the power supply voltage. The plurality of capacitive units may be formed from memory cell capacitors. | 2014-10-30 |
20140320202 | APPARATUS AND METHOD FOR EXTENDING BANDWIDTH AND SUPRESSING PHASE ERRORS IN MULTI-PHASE SIGNALS - Described herein is an integrated circuit which comprises: a first buffer, with positive trans-conductance, to drive a first signal with first phase; and a second buffer, with negative trans-conductance, to drive a second signal with second phase, wherein the first buffer and the second buffer are cross-coupled to one another. | 2014-10-30 |
20140320203 | SEMICONDUCTOR DEVICE - A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias | 2014-10-30 |
20140320204 | ADJUSTABLE MOS RESISTOR - A variety of circuits, methods and devices are implemented for providing an adjustable resistance. According to one such implementation an adjustable resistive device includes a metal-oxide semiconductor (MOS) transistor having a gate, a drain, a source, and a body. First circuitry controls a resistance from drain to source by applying a gate voltage that is a function of a variable control input. Second circuitry adjusts a voltage at the body according to a drain voltage and a source voltage, whereby the resistance from drain to source is substantially linear for a given value of the variable control input and over a voltage range. | 2014-10-30 |
20140320205 | AUTOTRANSFORMER-BASED IMPEDANCE MATCHING CIRCUITS AND METHODS FOR RADIO-FREQUENCY APPLICATIONS - Disclosed are devices and methods related to autotransformer-based impedance matching for radio-frequency (RF) applications. In some embodiments, an impedance matching device can include a primary metal trace and a secondary metal trace, each having a respective number of turns. Such metal traces can be interconnected to form an autotransformer with the primary metal trace and the secondary metal trace being in respective planes separated by a selected distance. Such an autotransformer can be utilized to, for example, facilitate impedance matching of an amplified RF signal from a power amplifier (PA). In some embodiments, the impedance matching device can be implemented as an integrated passive device (IPD) mountable on a packaging substrate. Such an IPD can be configured to allow stacking of another component on the IPD to yield a number of desirable features in products such as RF modules. | 2014-10-30 |
20140320206 | METHOD AND SYSTEM FOR A PSEUDO-DIFFERENTIAL LOW-NOISE AMPLIFIER AT KU-BAND - Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor may be coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor may be capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground. The second inductor may be embedded within the first inductor. | 2014-10-30 |
20140320207 | LOW NOISE VARIABLE GAIN AMPLIFIER UTILIZING VARIABLE FEEDBACK TECHNIQUES WITH CONSTANT INPUT/OUTPUT IMPEDANCE - Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs. | 2014-10-30 |
20140320208 | ADAPTIVE OPERATIONAL AMPLIFIER BIAS CURRENT - An operation amplifier (op amp) having a bias current detection circuit that monitors the bias current flowing in an output stage of the op amp. When the bias current detection circuit detects that too much current is being wasted, e.g., sunk to ground, then the amount of bias current is reduced. Similarly, when the bias current detection circuit detects that insufficient bias current is being supplied to the output stage of the op amp, the amount of bias current is increased. In one implementation, the output of the bias current detection circuit may be signals indicative of, respectively, too much bias current and too little bias current, wherein those outputs are supplied to a state machine which is configured to control the amount of bias current being supplied in a stepwise fashion. | 2014-10-30 |
20140320209 | TIME AMPLIFIER AND METHOD FOR CONTROLLING THE SAME - Provided is a time amplifier. The time amplifier includes: an SR latch providing an output at a timing determined according to a time difference between two inputs; and an operation determination unit connected to a power terminal of the SR latch and configured to determine an operation of the SR latch. | 2014-10-30 |
20140320210 | POWER AMPLIFIER TRANSISTOR CHARACTERISTIC STABILIZATION DURING BIAS SWITCHING - Communications equipment including communications equipment for wireless communications may benefit from power amplifier transistors having stabilized characteristics. For example, certain power amplifier transistors may benefit from having their characteristics stabilized during bias switching. An apparatus can include a power amplifier device. The apparatus can also include a voltage or current input to the power amplifier device. An input voltage or current to the voltage or current input can be configured to be controlled according to scheduled transmission in a slot. The apparatus can also include a gate bias insertion circuit provided at the bias input. The gate bias insertion circuit can be configured to provide a reduced input voltage or current as a power amplifier bias. The reduced input voltage or current can be configured to correspond to a threshold of a transistor of the power amplifier when transmission is not scheduled in a slot. | 2014-10-30 |
20140320211 | DISTRIBUTED AMPLIFIER WITH IMPROVED STABILIZATION - A distributed amplifier with improved stabilization includes an input transmission circuit, an output transmission circuit, at least one cascade amplifier coupled between said input and output transmission circuits. Each cascade amplifier includes a common-gate configured transistor coupled to the output transmission circuit, and a common-source configured transistor coupled between the input transmission circuit and the common-gate configured transistor. The distributed amplifier also includes a non-parasitic resistance and capacitance coupled in series between a drain and a gate of at least one of the common-gate configured transistors for increasing the amplifier stability. | 2014-10-30 |
20140320212 | RADIO FREQUENCY POWER AMPLIFIERS - A radio frequency power amplifier amplifies an input signal at an input port, and produces an output signal at an output port. The power amplifier may include one or more amplifier stages. An amplifier stage may include an active device, and a feedback network. The feedback network may include one or more reactive elements configured to resonate at a predetermined frequency, to provide an impedance match at the input to the amplifier stage, and to provide an impedance match at the output of the amplifier stage. In some example implementations, the input and output impedance matching is caused by biasing the active device to produce a transconductance at least one of equal to or greater than a critical transconductance. | 2014-10-30 |
20140320213 | RADIO FREQUENCY POWER AMPLIFIER CIRCUIT AND METHOD - An amplifier circuit is disclosed for providing a radio frequency output signal having a variable signal envelope, comprising a main amplifier device and an auxiliary amplifier and a combiner network for combining an output signal from said first amplifier device and a second output signal from said second amplifier device to provide a combined output signal of variable signal envelope to a load, and a signal processing circuit comprising an input and a non-linear processing section to provide at least said second radio frequency output signal with a signal envelope that has a non-linear dependency from an amplitude characteristic of the input signal such that the degree of non-linearity of the non-linear dependency varies dependent on the amount of change per time unit of the amplitude characteristic of the input signal. Further, a method of power amplifying a radio frequency signal having a variable signal envelope is disclosed. | 2014-10-30 |
20140320214 | DOHERTY POWER AMPLIFICATION APPARATUS AND METHOD - A multi-way Doherty power amplifier, DPA, is disclosed, comprising a first path comprising a carrier amplifier or at least one carrier amplifier segment partitioned from the carrier amplifier; a second to N-th paths each comprising at least one carrier amplifier segment and/or at least one peaking amplifier segment partitioned from a peaking amplifier; and a power splitter for splitting an input power signal to each of the at least one carrier amplifier segment and/or at least one peaking amplifier segment in a same path, wherein N is an integer not less than 2; a signal preparation unit configured for generating separately input power signal for the first path and each of the second path to N-th paths; and an impedance inverting network configured for combining output signal power from each path. The performance of each amplifier cell can be maximized independently without any compromises made for each other. | 2014-10-30 |
20140320215 | Oscillator - An oscillator, comprising: a pair of transistors to which source terminals are interconnected and to which drain and gate terminals are coupled by a positive feedback loop comprising an oscillator tank, wherein the source terminals of the transistors are connected to a current source configured to control physical parameters of the oscillator. | 2014-10-30 |
20140320216 | OSCILLATOR CIRCUIT - An oscillator circuit includes: a switched-capacitor filter filtering a voltage at a common node between a current generating unit and a frequency-controlled resistor so as to generate a filtered voltage; an amplifier generating a control voltage based on the filtered voltage and a voltage at a common node between the current generating unit and a reference resistor; a voltage-controlled oscillator generating an oscillation signal based on the control voltage; and a control signal generating unit generating, based on the oscillation signal, a control input having a frequency proportional to that of the oscillation signal. The frequency-controlled resistor has a resistance variable according to the control input. | 2014-10-30 |
20140320217 | PROGRESSIVELY SIZED DIGITALLY-CONTROLLED OSCILLATOR - A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string. | 2014-10-30 |
20140320218 | DIGITALLY CONTROLLED OSCILLATOR CALIBRATION CIRCUIT AND METHOD - A calibration circuit for a DCO includes a signal-conditioning module configured for (i) receiving at input an oscillating signal generated by the DCO and a reference signal, both designed to oscillate between a high logic value (“1”) and a low logic value (“0”), and (ii) detecting a respective first and second stable logic value of the reference signal and of the oscillating signal; and a period-to-voltage converter module coupled to the signal-conditioning module and configured for (iii) generating a difference signal identifying a difference between the period of the reference signal and the period of the oscillating signal, and (iv) controlling, on the basis of the difference signal, the DCO so as to conform the duration of the period of the oscillating signal to the duration of the period of the reference signal. Likewise described is a calibration method implemented by the calibration circuit. | 2014-10-30 |
20140320219 | PASSIVE PHASE NOISE CANCELLATION ELEMENT - A passive electro-mechanical device that reduces phase noise in oscillators, thereby improving their frequency precision. The noise reduction device can consist of a pair of coupled nonlinear resonators that are driven parametrically—by modulating their natural frequency in time, through the output signal of a conventional oscillator at a frequency close to the sum of the linear mode frequencies. Above the threshold for parametric response, the coupled resonators can exhibit oscillation at an inherent frequency. The novel possibility for noise elimination is realized by tuning the system to operating points for which this periodic signal is immune to frequency noise in the drive signal, providing a way to clean the phase noise of the driving oscillator. | 2014-10-30 |
20140320220 | OVEN CONTROLLED CRYSTAL OSCILLATOR AND MANUFACTURING METHOD THEREOF - The present invention discloses an Oven Controlled Crystal Oscillator and a manufacturing method thereof. The Oven Controlled Crystal Oscillator comprises a thermostatic bath, a heating device, a PCB and a signal generating element, where the signal generating element is used for generating a signal of a certain frequency, the heating device, the PCB and the signal generating element are mounted in the thermostatic bath, the signal generating element is mounted in a groove formed on one side of the PCB, while the heating device is mounted against the other side of the PCB that is opposite to the groove. The signal generating element may be a passive crystal resonator or an active crystal oscillator. The Oven Controlled Crystal Oscillator according to the invention is advantageous for a small volume and a high temperature control precision. | 2014-10-30 |
20140320221 | ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND MOVING OBJECT - An electronic device includes: a substrate; a resonation device; a heating element; a first support which is mounted on the substrate and supports the resonation device; and a second support which supports the substrate, in which the relationship between thermal conductivity λ1 of the first support and thermal conductivity λ2 of the second support satisfies an expression, λ1>λ2. | 2014-10-30 |