44th week of 2008 patent applcation highlights part 33 |
Patent application number | Title | Published |
20080266941 | 8/9 AND 8/10-BIT ENCODING TO REDUCE PEAK SURGE CURRENTS WHEN WRITING PHASE-CHANGE MEMORY - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The memory cell's reset current can be double a set current, causing peak currents to depend on write data. When all data bits are reset to the amorphous state, a very high peak current is required. To reduce this worst-case peak current, the data is encoded before storage in the PCM cells. An 8/10 encoder adds 2 bits but ensures that no more than half of the data bits are reset. An 8/9 encoder adds an indicator bit, and inverts the 8 bits to ensure that no more than half of the bits are reset. The indicator bit indicates when the 8 bit are inverted, and when the 8 bits are uninverted. Peak currents are thus reduced by encoding to reduce reset data bits. | 2008-10-30 |
20080266942 | Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices - A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell. | 2008-10-30 |
20080266943 | Spin-torque MRAM: spin-RAM, array - A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines are connected to the gate of the gating MOS transistor of each MRAM cell of the rows. The MRAM cells are written in a two step process with selected MRAM cells written to a first logic level (0) in a first step and selected MRAM cells written to a second logic level (1) in a second step. A second embodiment of the spin-torque MRAM array has the bit lines commonly connected together to receive the data and the source select lines commonly connected together to receive an inverse of the data for writing. | 2008-10-30 |
20080266944 | NON-VOLATILE MEMORY CELL WITH A HYBRID ACCESS TRANSISTOR - A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well. | 2008-10-30 |
20080266945 | ADAPTIVE DETECTION OF THRESHOLD LEVELS IN MEMORY - Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location. | 2008-10-30 |
20080266946 | METHOD OF MANAGING A MULTILEVEL MEMORY DEVICE AND RELATED DEVICE - A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels. | 2008-10-30 |
20080266947 | Bit-Symbol Recognition Method and Structure for Multiple-Bit Storage in Non-Volatile Memories - Storage of information represented by a multi-bit word in a single non-volatile memory cell is made possible by programming the threshold voltage of the non-volatile memory to a specific threshold level corresponding to the multi-bit word. Stored or generated multi-bit words are scanned and converted into a gate voltage to be applied to the non-volatile memory cell until the electrical response from the non-volatile memory cell indicates that the voltage generated from the specific multi-bit word which has been applied to the gate matches the information stored in the non-volatile memory cell. The matched multi-bit word is read out of storage and represents the stored bits in the single non-volatile memory cell. | 2008-10-30 |
20080266948 | Memory system, program method thereof, and computing system including the same - Disclosed is a memory system and a method of programming a multi-bit flash memory device which includes memory cells configured to store multi-bit data, where the method includes and the system is configured for determining whether data to be stored in a selected memory cell is an LSB data; and if data to be stored in a selected memory cell is not an LSB data, backing up lower data stored in the selected memory cell to a backup memory block of the multi-bit flash memory device. | 2008-10-30 |
20080266949 | INTEGRATED CIRCUITS WITH SUBSTRATE PROTRUSIONS, INCLUDING (BUT NOT LIMITED TO) FLOATING GATE MEMORIES - A floating gate memory cell's channel region ( | 2008-10-30 |
20080266950 | DATA PATH CIRCUIT IN A FLASH MEMORY DEVICE - A data output circuit in an NAND flash memory device is disclosed. The data path circuit in a flash memory includes at least one switching means configured to output one or more internal address signals in accordance with a data output control signal, and one or more data output circuit configured to output data when a specific internal address signal is outputted through the switching means. | 2008-10-30 |
20080266951 | NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD - A non-volatile memory device, related memory system, and program method for the non-volatile memory device are disclosed. In the method, memory cells in a memory cell array are accessed through a plurality of word lines by applying a program voltage to a selected word line, wherein the selected word line is not adjacent to an outmost word line, applying a first reduced pass voltage to word lines adjacent to the selected word line, and applying a second reduced pass voltage to the outermost word lines. | 2008-10-30 |
20080266952 | MEMORY ARRAY ARCHITECTURE FOR A MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY ARRAY ARCHITECTURE - A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the memory cell array. By applying a proper bias voltage to the selection transistors, specific memory strings can be selected, so that operations for the memory array can be performed without intervening with adjacent memory cells. | 2008-10-30 |
20080266953 | SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE - A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on. | 2008-10-30 |
20080266954 | Transition areas for dense memory arrays - A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F. | 2008-10-30 |
20080266955 | SRAM CELL CONTROLLED BY FLASH MEMORY CELL - First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node. | 2008-10-30 |
20080266956 | FLASH MEMORY DEVICE AND METHOD OF CONTROLLING FLASH MEMORY DEVICE - A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, and a controller configured to generate the block select signals in response to a block address. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address. | 2008-10-30 |
20080266957 | Method for Column Redundancy Using Data Latches in Solid-State Memories - A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved. | 2008-10-30 |
20080266958 | FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS - A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells. | 2008-10-30 |
20080266959 | MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS - A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells. | 2008-10-30 |
20080266960 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF AND CIRCUIT SYSTEM INCLUDING THE NON-VOLATILE MEMORY - A non-volatile memory including a memory cell is described. The memory cell includes a first unit, a semiconductor layer, a second unit, and a doped region. The first unit includes a first gate, a first charge trapping layer, and a second charge trapping layer. The first and the second charge trapping layer are respectively disposed on both sides of the first gate. The semiconductor layer is disposed on the first unit. The second unit is disposed on the semiconductor layer and is in mirror symmetry to the first unit. The second unit includes a second gate and a third and a fourth charge trapping layer respectively disposed on both sides of the second gate. The doped region is disposed at both sides of the semiconductor layer and serves as a common source/drain region of both the first and the second unit. | 2008-10-30 |
20080266961 | NON-VOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING IN THE SAME - A non-volatile memory device according to one example embodiment of the present invention includes a page buffer configured to have a first register for receiving data and storing temporarily the received data to be inputted to a pair of first bit lines, a second register coupled selectively to the first register and for storing temporarily data to be inputted to a pair of second bit lines, and a third register for storing temporarily specific data in accordance with a level of the data stored in the first register; a first bit line selecting circuit configured to couple selectively a given bit line of the first bit lines to the first register; and a second bit line selecting circuit configured to couple selectively a certain bit line of the second bit lines to the second register. | 2008-10-30 |
20080266962 | FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM - A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied. | 2008-10-30 |
20080266963 | COMPENSATING SOURCE VOLTAGE DROP IN NON-VOLATILE STORAGE - A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated. | 2008-10-30 |
20080266964 | NON-VOLATILE STORAGE WITH COMPENSATION FOR SOURCE VOLTAGE DROP - A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated. | 2008-10-30 |
20080266965 | NONVOLATILE SEMICONDUCTOR MEMORY HAVING PLURAL DATA STORAGE PORTIONS FOR A BIT LINE CONNECTED TO MEMORY CELLS - Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used. | 2008-10-30 |
20080266966 | OPERATION METHOD OF NON-VOLATILE MEMORY AND METHOD OF IMPROVING COUPLING INTERFERENCE FROM NITRIDE-BASED MEMORY - An operation method of a non-volatile memory is provided. The operation method is that a reading operation is performed to a selected nitride-based memory cell, a first positive voltage is applied to a word line adjacent to one side of the selected memory cell and a second positive voltage is applied to another word line adjacent to the other side of the selected memory cell. The operation method of this present invention not only can reduce a coupling interference issue but also can obtain a wider operation window. | 2008-10-30 |
20080266967 | NONVOLATILE SEMICONDUCTOR MEMORY - A semiconductor memory device comprising: a memory cell array having memory cell units each formed by connecting a plurality of memory cells; a first and a second select gate transistors, the first select gate transistor being connected between one end of the memory cell array and a common source line, the second select gate transistor being connected between the other end of the memory cell array and bit lines; word lines acting also as control gates of the memory cells; a first select gate voltage-generating circuit for generating a first select gate voltage; a second select gate-setting circuit for setting an instructed value of a second select gate voltage; a second select gate voltage-generating circuit for generating the second select gate voltage based on the set, instructed value; a first transfer circuit for transferring the first select gate voltage generated by the first select gate voltage-generating circuit to a second select gate; a discharging circuit for discharging the first select gate voltage transferred to the second select gate; and a discharging characteristics selection circuit for selecting discharging characteristics of the discharging circuit. | 2008-10-30 |
20080266968 | CHARGE PUMP CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes: a memory cell array including a plurality of memory cells arranged in rows and columns for holding information, each of the memory cells having a control gate; a plurality of word lines extending in a row direction, each of the word lines being connected to the control gates of the memory cells of a corresponding row of the memory cell array; a plurality of bit lines extending in a column direction and connected to sources or drains of the memory cells; a row decoder for selecting any of the plurality of word lines; a column decoder for selecting any of the plurality of bit lines; a charge pump circuit for generating a voltage higher than a supply voltage; and a first switch located in a connection path between the row decoder and the charge pump circuit. | 2008-10-30 |
20080266969 | METHOD OF OPERATING NON-VOLATILE MEMORY - A method of operating a non-volatile memory having a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is greater than the fourth voltage, the third voltage is greater than the second voltage, and the second voltage is greater than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region. | 2008-10-30 |
20080266970 | PROGRAMMING AND/OR ERASING A MEMORY DEVICE IN RESPONSE TO ITS PROGRAM AND/OR ERASE HISTORY - For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of one or more erase pulses applied to one or more memory cells is based on a number of erase pulses previously required to erase the one or more memory cells. For another embodiment, a program starting voltage level and/or an erase starting voltage level of one or more program and/or erase pulses applied to one or more memory cells is in response, at least in part, to a number of program/erase cycles previously applied to the one or more memory cells. | 2008-10-30 |
20080266971 | PROGRAMMING A FLASH MEMORY DEVICE - An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is verified up to a maximum verify voltage. A second verify read operation is then performed after the program/verify operation. The second verify read operation uses a verify voltage that is substantially close to the maximum verify voltage used during the program/verify step. | 2008-10-30 |
20080266972 | PROGRAMMING A NON-VOLATILE MEMORY DEVICE - A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial programming pulse, a verify operation determines if the cell has been programmed. If the cell is still erased, the initial programming voltage is increased by the step voltage. The step voltage for the lowest word line near the source line is lower than the step voltage for the word line closest to the drain line. | 2008-10-30 |
20080266973 | REDUCING POWER CONSUMPTION DURING READ OPERATIONS IN NON-VOLATILE STORAGE - Power consumption in a non-volatile storage device is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line. | 2008-10-30 |
20080266974 | NON-VOLATILE MEMORY HAVING A STATIC VERIFY-READ OUTPUT DATA PATH - A memory has first and second memory arrays and first and second sense amplifiers coupled to the first and second memory arrays, respectively. A verify data line is coupled to first outputs of the first sense amplifier and the second sense amplifier as well as to a program/erase controller. The verify data line has a first logic circuit having a first input coupled to the first output of the first sense amplifier and an output. A second logic circuit has a first input coupled to the output of the first logic circuit, a second input coupled to the first output of the second sense amplifier, and an output. A global data line is coupled to a second output of the first sense amplifier and a second output of the second sense amplifier. A global sense amplifier is coupled to the global data line. | 2008-10-30 |
20080266975 | NON-VOLATILE STORAGE WITH REDUCED POWER CONSUMPTION DURING READ OPERATIONS - A non-volatile storage device in which power consumption is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line. | 2008-10-30 |
20080266976 | NAND MEMORY DEVICE AND PROGRAMMING METHODS - A NAND Flash memory device is described that can reduce circuitry noise during program operations. The memory includes bit lines that can be electrically coupled together to charge share their respective voltage potentials prior to performing a discharge operation on the bit lines. | 2008-10-30 |
20080266977 | METHOD FOR HIGH SPEED PROGRAMMING OF A CHARGE TRAPPING MEMORY WITH AN ENHANCED CHARGE TRAPPING SITE - A method of high speed programming and erasing of a charge trapping memory using turn-on-mode assist-charge (TOM-AC) operations. The charge trapping memory includes a charge trapping structure overlying a substrate body with source and drain regions. The charge trapping structure includes a charge trapping layer overlying a dielectric layer. The charge trapping layer has an assist charge site (also referred to as AC-site, AC-side, or a first charge trapping site) and a data site (also referred to as data-side or a second charge trapping site). Initially, to place the charge trapping memory cell in a TOM operation, both the AC-site and the data site of the charge trapping memory cell are erased to a negative threshold voltage level, −Vt, by FN injection, thereby inducing a hole charge induced channel between the source and drain regions. | 2008-10-30 |
20080266978 | Arrangements for operating a memory circuit - In one embodiment a method for programming memory cells is disclosed. The method can include applying a programming voltage to a selected memory cell during a lower page programming procedure, the selected memory cell can be part of a string of memory cells containing unselected memory cells, where the string of cells have a source side between the selected memory cell and a source line and have a drain side between the selected memory cell and bit line. The method can also include applying pass voltages to the unselected memory cells during the lower page programming procedure and applying pass voltages to the unselected memory cells during the upper cell programming procedure. The pass voltages can be higher during the upper page programming than during the lower page programming procedure. | 2008-10-30 |
20080266979 | METHODS OF BIASING A MULTI-LEVEL-CELL MEMORY - Methods are described for double-side-bias of multi-level-cell memory devices comprising a NAND array that comprises a plurality of charge trapping memory cells. A memory device is programmed by a double-side-bias electron injection technique and is erased by a double-side-bias hole injection technique. Each charge trapping memory cell includes 2 | 2008-10-30 |
20080266980 | METHODS FOR CONDUCTING DOUBLE-SIDE-BIASING OPERATIONS OF NAND MEMORY ARRAYS - Methods are described for double-side-biasing of a NAND memory array device comprising a plurality of charge trapping memory cells for programming and erasing the NAND memory array device. A double-side-biasing method applies a bias voltage simultaneously on a first junction (a source region) and a second junction (a drain region) so that a left bit and a right bit in a charge trapping memory cell can be programmed in parallel or erased in parallel. Random (or selective) bit program and random (or selective) bit erase can be achieved by using a double-side-biasing method on a NAND memory array device for both data and code application. A first type of double-side-biasing method is to program the NAND array with a double-side-bias electron injection. A second type of double-side-biasing method is to erase the NAND array with a double-side-bias hole injection. | 2008-10-30 |
20080266981 | NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - A nonvolatile memory device includes first and second impurity diffusion regions formed in a semiconductor substrate, and a memory cell formed on a channel region of a semiconductor substrate between the first and second impurity diffusion regions. The memory cell includes a stacked gate structure formed on the channel region, and first and second select gates formed on the channel regions and opposite sidewalls of the stacked gate structure. Since the first and second select gates are spacer-shaped to be self-aligned on opposite sidewalls of the stacked gate structure, a size of a memory cell is reduced to enhance an integration density of a semiconductor device. | 2008-10-30 |
20080266982 | CHANNEL DISCHARGING AFTER ERASING FLASH MEMORY DEVICES - A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate but not allowed into a deeper well of opposite conductivity type relative to the upper well. After a brief time, T, the charged particles are pushed by a bias voltage into the deeper well from the upper well. This two step clearing procedure avoids device latchup that might occur otherwise. | 2008-10-30 |
20080266983 | FLASH MEMORY DEVICE AND METHOD OF ERASING FLASH MEMORY DEVICE - A flash memory device includes a memory cell array, a bulk voltage generator and a controller. The memory cell array is formed in a bulk area and including memory cells arranged in rows and columns. The bulk voltage generator is configured to supply a bulk voltage to the bulk area. The controller is configured to control the bulk voltage generator to vary an erase time based on a time when the bulk voltage reaches a target voltage. | 2008-10-30 |
20080266984 | Programmable Heavy-Ion Sensing Device for Accelerated DRAM Soft Error Detection - Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode. | 2008-10-30 |
20080266985 | METHODS AND APPARATUS FOR TESTING INTEGRATED CIRCUITS - In some aspects, a method is provided for testing an integrated circuit (IC). The method includes the steps of selecting a bit from each of a plurality of memory arrays formed on an IC chip, selecting one of the plurality of memory arrays, and storing the selected bit from the selected memory array. Numerous other aspects are provided. | 2008-10-30 |
20080266986 | TIMING IMPROVEMENTS BY DUAL OUTPUT SYNCHRONIZING BUFFER - Provided are a system and method for timing improvements by dual output synchronizing buffer. The method comprises providing at least two outputs on a synchronizing first-in-first-out buffer (“FIFO”) in a combinational logic circuit. The method further includes latching data into the FIFO. The method also includes alternating which of the two outputs by which the data is latched out of the FIFO, thereby extending timing in the combinational logic circuit. | 2008-10-30 |
20080266987 | DRAM WITH WORD LINE COMPENSATION - In one embodiment, a DRAM is provided that includes: a word line intersecting with a pair of bit lines, the DRAM including a memory cell at each intersection, each memory cell including an access transistor adapted to couple a storage cell to the corresponding bit line if its gate voltage is raised; and a word line compensation circuit adapted to compensate for a capacitively-coupled voltage increase on the corresponding bit line if the access transistor's gate voltage is raised. | 2008-10-30 |
20080266988 | MULTI- PORT MEMORY DEVICE FOR BUFFERING BETWEEN HOSTS AND NON-VOLATILE MEMORY DEVICES - A multi-port volatile memory device can include a first port that is configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core can be configured to store data received thereat and read requested stored data therefrom. A main interface circuit can be coupled to the first port and can be configured to provide data to/from the volatile main memory core and the first port in a master mode and can be configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port can be configured for data transfer to/from an external non-volatile memory device and the device and a sub interface circuit can be coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode. | 2008-10-30 |
20080266989 | SRAM CIRCUITRY - A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell has three main operating modes, reading, writing, and data retention. Reading is performed by sensing current flowing from a powered-up wordline through a conductive one of the cross-coupled transistors. Writing is performed by pulsing the source of the conductive one of the cross-coupled transistors with a positive voltage to flip the conductive states of the cross-coupled transistors. Data retention is performed by using leakage currents to retain the conductive states of the cross-coupled transistors. A decoder for an array of static ram cells may be operated synchronously and in a pipelined fashion using a rotary traveling wave oscillator that provides the clocks for the pipeline. The cell is capable of detecting an alpha particle strike with suitable circuitry. | 2008-10-30 |
20080266990 | Flexible redundancy replacement scheme for semiconductor device - A redundancy replacement scheme for repairing a faulty memory cell including memory cells arranged in memory blocks containing word lines and column select lines. The redundancy replacement scheme including replacing the faulty memory cell in a second memory block with a spare memory cell in the second memory block based on a decoded address of a first memory block. | 2008-10-30 |
20080266991 | Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks. | 2008-10-30 |
20080266992 | DRAM WITH HYBRID SENSE AMPLIFIER - In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein the memory cells are constructed using I/O transistors. | 2008-10-30 |
20080266993 | Serial connection external interface from printed circuit board translation to parallel memory protocol - A translator of an apparatus in an example through a serial connection external interface of a printed circuit board (PCB) communicates between a serial memory protocol within the PCB and a parallel memory protocol outside the PCB. | 2008-10-30 |
20080266994 | LEVEL DETECT CIRCUIT - A detect circuit may be used to detect one or more characteristics corresponding to the fuse being programmed. When the one or more characteristics of the fuse being programmed reach the desired states or values, the programming of the fuse is discontinued. Thus, the programming duration for each fuse is customized for each fuse. As a result, for some embodiments, there may be fewer fuses that have been over-programmed. In addition, for some embodiments, the range of impedances of the programmed fuses have a narrower distribution of impedances due to the use of the detect circuit. | 2008-10-30 |
20080266995 | METHOD OF SELECTIVELY POWERING MEMORY DEVICE - An approach to selectively powering a memory device is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various methods are provided to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state. | 2008-10-30 |
20080266996 | MEMORY POWER SUPPLY CIRCUIT - A memory power supply circuit configured for supplying power to two types of memories slots of a motherboard includes a slot detecting terminal configured to connect with a detecting pin of the motherboard which is used to detect the memory slots, an electrical switch element, a first resistor, a second resistor, a third resistor, and a voltage output terminal connected to power input pins of the two types of memories slots. The second resistor and third resistor are connected in series between a first power supply and ground. The slot detecting terminal is connected to a first terminal of the electrical switch element. A second terminal of the electrical switch element is grounded. A third terminal of the electrical switch element is connected to the voltage output terminal via the first resistor and connected to a node between the second and third resistors. | 2008-10-30 |
20080266997 | VOLATILE MEMORY ELEMENTS WITH ELEVATED POWER SUPPLY LEVELS FOR PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS - Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level. | 2008-10-30 |
20080266998 | VOLTAGE BOOSTER AND MEMORY STRUCTURE USING THE SAME - A voltage booster and a memory structure using the same are provided. When a data storage unit in the memory structure is in normal operation, all voltage pumps in the voltage booster are turned on for boosting a supply voltage. However, when the data storage unit is in standby state, in the voltage booster, some voltage pumps are turned on while other voltage pumps are turned off, for boosting the supply voltage. Accordingly, the standby current and power consumption are reduced and the pump efficiency is improved. | 2008-10-30 |
20080266999 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM PROVIDING SPARE MEMORY LOCATIONS - A semiconductor memory device having a plurality of memory locations is presented. The plurality of memory locations includes a plurality of primary memory locations and a plurality of spare memory locations. The device includes an address decoder configured to receive a memory location address and process the address to select one of the memory locations. The device further includes control logic configured to receive control signals and process the control signals to determine whether the selected one of the memory locations is one of the primary memory locations or one of the spare memory locations, and to provide access to the selected one of the memory locations via data lines. | 2008-10-30 |
20080267000 | SINGLE-CLOCK, STROBELESS SIGNALING SYSTEM - A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path. | 2008-10-30 |
20080267001 | Protocol Enhancement for PCI Express - In a method for enabling a root device to access a plurality of memory locations in an address space in an endpoint device, a first access is sent to the endpoint device by transmitting a first header and a first address. The header includes a continue bit that is set at a first state that indicates that the first access is accessing a selected first memory location that the address is being sent. A first memory location is accessed when the continue bit is in the first state. A second access, which accesses accessing a second memory location that is contiguous to an immediately previously accessed memory location, is sent to the endpoint device by transmitting a header that includes a continue bit set to a second state and not sending an address. The second memory location corresponds to the first address plus a predetermined address offset. | 2008-10-30 |
20080267002 | Method for Dosing Additive in Injection-Moulding Unit, and Injection-Moulding Unit - A method for dosing an additive in an injection-moulding unit, and an injection-moulding unit. The injection-moulding unit ( | 2008-10-30 |
20080267003 | EXTRUSION METHOD AND APPARATUS - An extrusion apparatus including a mixing chamber comprising two intersecting housing bores and an inlet positioned to receive material into the mixing chamber. Two screw shafts are supported for rotation about respective generally parallel axes and include respective screw sections positioned for co-wiping intermeshing rotation within the respective housing bores of the mixing chamber. The apparatus supports screw shaft rotational speeds greater than approximately 800 rpm and includes screw shaft conveying portions that are rotatably cantilevered for self-journaled support within respective separate conveying chambers arranged generally parallel to one another downstream of the mixing chamber. | 2008-10-30 |
20080267004 | Apparatus for Producing a Mixture Composed of Various Bulk Material Components - The present invention relates to an apparatus for producing a mixture of various bulk material components, with supply containers for the individual bulk material components and with a weighing container with an integrated mixing device which is suspended or supported on a weighing device, and to which the desired mixture of the bulk material components is supplied from the supply containers by means of feed devices via an upper inlet. The object of the invention is to provide an apparatus such as this in which the ratio of the empty weight of the weighing container to the items being weighed is considerably improved, in order to increase the measurement accuracy. This object is achieved in that the mixing device ( | 2008-10-30 |
20080267005 | Applicator system and method of use - Disclosed is an applicator system for mixing, homogenizing and/or emulsifying two or more solutions and/or substances prior to application. The system includes a first and a second container of solution, a hand-held homogenizer having a homogenizing assembly and an applicator assembly configured to fluidly communicate the first and second containers with the homogenizing assembly. The solution from each container is mixed by the homogenizing assembly when the solution is dispensed from the containers. The applicator assembly may be integrally formed with the homogenizer and may be configured to include an outlet for dispensing the homogenized solution. The outlet may form an applicator tip or a connection for releasably securing a hose or tube. The homogenizing assembly may be integrally formed with the applicator and may include rotors and stators. | 2008-10-30 |
20080267006 | Device for Mixing Fluids - The present invention relates to a device for mixing fluids. It is a hydraulic or pneumatic apparatus, depending on the fluid used for transportation. It is static and has the characteristics of both an extractor and a fluid mixer. Extraction is effected by dragging the suction elements, by means of the circulation of a transporting fluid injected at low pressure. The injection inlets ( | 2008-10-30 |
20080267007 | Device for Mixing or Amalgamating Products in Liquid, Granular or Powder Form - The device ( | 2008-10-30 |
20080267008 | METHOD FOR DISPERSION OF A SECOND PHASE INTO A NON-NEWTONIAN FLUID BASE PRODUCT - A method and apparatus for producing a non-Newtonian fluid product including a non-Newtonian fluid base product including at least one second phase is disclosed. A second phase dispersion apparatus is disclosed which receives the at least one second phase and the non-Newtonian fluid base product and disperses the at least one second phase within the non-Newtonian fluid base product to produce the non-Newtonian fluid product. | 2008-10-30 |
20080267009 | Containerized Geophysical Equipment Handling and Storage Systems, and Methods of Use - Systems and methods for marine seismic cable deployment and retrieval are described. One system comprises a plurality of portable containers, each container temporarily storing a marine seismic component, at least some of the containers able to be removably fastened to a deck of a vessel of opportunity, and at least one of the portable containers storing a main cable winch on which is wound a marine seismic cable. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2008-10-30 |
20080267010 | Methods and Systems for Efficiently Acquiring Towed Streamer Seismic Surveys - Methods and systems for efficiently acquiring towed streamer marine seismic data are described. One method and system comprises positioning a plurality of source-only tow vessels and one or more source-streamer tow vessels to acquire a wide- and/or full-azimuth seismic survey without need for the spread to repeat a path once traversed. Another method and system allows surveying a sub-sea geologic feature using a marine seismic spread, the spread smartly negotiating at least one turn during the surveying, and shooting and recording during the turn. This abstract is provided to comply with the rules requiring an abstract, allowing a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2008-10-30 |
20080267011 | INTELLIGENT EFFICIENT SERVO-ACTUATOR FOR A DOWNHOLE PULSER - An improved energy efficient intelligent pulser driver used for generating a mud pulse in a MWD (measurement while drilling) application. In the pulser driver, a direct current (DC) powered control circuit activates a three-phase DC brushless motor that operates a servo-valve. Opening of the servo-valve equalizes pressure in a plenum causing the operation of a main valve reducing flow area and causing a pressure spike in the mud column. Closing of the servo-valve creates a reduction in mud pressure that operates the main valve and increases the flow area causing an end to the pressure spike. The servo-valve is powered both in opening and closing operations by the motor. | 2008-10-30 |
20080267012 | Systems and methods of communications for weapon detection systems - A system and method for detecting, identifying, and fixing the location of the source of an acoustic event. The inventive system includes: a plurality of sensors dispersed at somewhat regular intervals throughout a monitored area; a communication network adapted to deliver information from the sensors to a host processor; and a process within the host processor for determining, from the absolute times of arrival of an event at two or more sensors, a position of the source of the event. Acoustic events are detected and analyzed at each sensor so that the sensor transmits over the network: an identifier for the sensor; an identifier for the type of event; and a precise absolute time of arrival of the event at the sensor. In a preferred embodiment, the system also identifies the type of weapon firing a gunshot. | 2008-10-30 |
20080267013 | Systems and methods of identifying/locating weapon fire including aerial deployment - A system and method for detecting, identifying, and fixing the location of the source of an acoustic event. The inventive system includes: a plurality of sensors dispersed at somewhat regular intervals throughout a monitored area; a communication network adapted to deliver information from the sensors to a host processor; and a process within the host processor for determining, from the absolute times of arrival of an event at two or more sensors, a position of the source of the event. Acoustic events are detected and analyzed at each sensor so that the sensor transmits over the network; an identifier for the sensor; an identifier for the type of event; and a precise absolute time of arrival of the event at the sensor. In a preferred embodiment, the system also identifies the type of weapon firing a gunshot. | 2008-10-30 |
20080267014 | Tracking and monitoring system - A tracking device is incorporated into a watch. The tracking device appears as an ordinary watch, but cannot be removed by the individual wearing it. If necessary, the location of the tracking device can be determined by a central server and reported to the authorities or to the individual's family. | 2008-10-30 |
20080267015 | ELECTRONIC DEVICE AND AUTOMATIC TURNOFF METHOD FOR THE SAME - An electronic device includes an input unit for generating control signals according to operations of a user, a power supply unit for supplying power to the electronic device, a first timer for measuring and signaling the end of a first time interval by outputting a first end signal, a second timer for measuring and signaling the end of a second time interval by outputting a second end signal, a notifier for generating a notice signal based on a notice file, and a controller. The controller is for restarting the first timer and disabling the second timer whenever receiving one of the control signals, restarting the second timer and enabling the notifier when receiving the first end signal, and disabling the power supply unit when receiving the second end signal. A related automatic turnoff method for automatically turning off an electronic device is also disclosed. | 2008-10-30 |
20080267016 | Electric Counter Circuit - An electric counter circuit ( | 2008-10-30 |
20080267017 | NOVEL WATCHCASE ASSEMBLY - A watchcase is provided including a watchcase and an exoskeleton. The exoskeleton is aesthetically pleasing and engineeringly sound, encompassing the watchcase and protecting it from everyday wear and tear, of which it could be totally independent from the watchcase or could be attached to the watchcase in a supportive manner with connectors attaching it to the watchcase and connected with screws and separate supportive parts, reinforced from the exoskeleton mainframe to the top of the watchcase. The supports or connections could be engineered to evenly distribute any stress points, creating a ridged protective barrier for the watchcase. | 2008-10-30 |
20080267018 | DISC TRANSPORT AUTO-CALIBRATION - The present invention provides a media device apparatus having an improved design for auto-calibration providing efficient operation and improved engagement to one or more storage discs. In one aspect, the present invention provides a disc transport movable along at least one axis, one or more media device components including an engagement area, and a calibrating device for aligning the disc transport with the engagement area, the calibrating device including a first member associated with the disc transport and a second member associated with the media device component, wherein either the first member or the second member moves along a first axis until a calibration position is sensed, which is at a known distance from the engagement area. In another aspect, the present invention provides a method for calibrating at least one of the disc transport and the one or more media device components along an engagement axis. | 2008-10-30 |
20080267019 | Optical Pickup Apparatus and Optical Disk Drive - When tracking a dual-layer optical disc by a differential push-pull method, the adverse effect of the reflected light from an adjacent layer, which produces stray light, on a tracking control signal is prevented. A split wavelength plate | 2008-10-30 |
20080267020 | OPTICAL DISC APPARATUS AND FOCUS CONTROL METHOD - An optical disk apparatus that performs focus control and tracking control, the focus control focusing an objective lens on an optical disk, and the tracking control making the objective lens track a partial area on the optical disk. The optical disk apparatus has a light-blocking element and a light detector. The light-blocking element is disposed on a first light path on which light reflected by the optical disk travels, and blocks a part of the reflected light. The light detector detects, for the focus control, the reflected light which passes the light-blocking element. The light-blocking element has a predetermined area for blocking the reflected light, the predetermined area extending along a direction optically corresponding to the tracking direction in which the objective lens tracks, for the tracking control, the partial area on the optical disk. | 2008-10-30 |
20080267021 | Recording method, optical disk, reproduction method, and recording/reproduction device - A wide test region is ensured in an optical disk and the number of repeated recording instances is suppressed so that the optical disk is made insusceptible to damage and the test region can effectively be utilized. In an optical disk which includes a plurality of recording layers each having a power adjustment region for performing adjustment of power of a beam emitted while the data is recorded and in which the data can be rewritten in each recording layer, when, in performing the adjustment of power while the data is recorded, a region between a first power adjustment region that is a power adjustment region in a first recording layer and a second power adjustment region that is a power adjustment region in a second recording layer provided at a position that is more apart than that of the first recording layer from a plane from which the light beam enters becomes smaller, along a radial direction of the optical disk, than a predetermined size, a utilized region, in one of the first power adjustment region and the second power adjustment region, which is larger than that in the other is erased. | 2008-10-30 |
20080267022 | Method and System With Focus Control for Scanning an Information Carrier - The invention relates to a method and system for reading data on a data layer ( | 2008-10-30 |
20080267023 | Information recording medium - An optically detectable information recording medium is at least comprised of a substrate and a recording layer, wherein a surface of the recording layer opposite to another surface of the recording layer in contact with the substrate has a Root Mean Square roughness Rσ of less than 5 nm, and wherein the recording layer has dye recording material selected from cyanine dye, phthalocyanine dye, naphtalocyanine dye, azo dye, naphtoquinone dye, fulgide dye, polymethyne dye, and acridine dye. | 2008-10-30 |
20080267024 | Optical Storage System Method for Improving Reliability Thereof - A method and system for improving reliability in an optical storage system ( | 2008-10-30 |
20080267025 | Method of Lens Positioning For Tilt Compensation, Method and Apparatus For Reading And Recording Data Onto An Optical Disc - A method of controlling the positioning of an objective lens of a lens system for controlling an optical beam used in reading and/or recording information from/onto a track of an optical disc, the method comprising steps of detecting modulated optical signals corresponding to the intensity of a reflected optical beam, the reflected optical beam being modulated by the periodic structures of the track of the optical disc, deriving a radial tilt error signal from the modulated optical signals indicative of a radial tilt, wherein the radial tilt refers to the tilt of the objective lens with respect to the optical disc in a radial direction; using the radial tilt error signal for adjusting the position of the objective lens with respect to the optical disc in a radial direction, the method characterized by using the radial tilt error signal for adjusting the position of the objective lens by means of a feedback loop. The radial tilt error signal may be proportional to a cross correlation signal between a Radial Push Pull (RPP) signal and a Central Aperture (CA) signal or a cross correlation signal between a Radial Push Pull (RPP) and a Diagonal Push Pull (DPP) signal. | 2008-10-30 |
20080267026 | OPTICAL DISK DEVICE - This optical disk device includes a read means which reads data from an optical disk upon which data is recorded at a variable bit rate for each sector. Moreover, this optical disk device includes a buffer memory which sequentially stores data which has been read by the read means, and a replay means which sequentially reads out and decodes data stored in the buffer memory, and replays that data. Furthermore, this optical disk device includes a control means which, when a command for special replay is issued, calculates the address of the sector currently being decoded by the replay means based upon the address of the sector currently being read by the read means, and upon the amount of data stored in the buffer memory. And the control means commands the read means to read out, from the optical disk, a sector to be jumped to. | 2008-10-30 |
20080267027 | Method and Apparatus for Optimizing Optical Disc Writing Strategy - The present invention provides a method and apparatus for optimizing optical disc writing strategy. The method for optimizing optical disc writing strategy comprises the steps of obtaining the information concerning whether said area to be written has experienced any writing before; searching for an area that has the corresponding information in the writing optimization area on said optical disc; and performing writing test on said area that has the corresponding information to optimize and determine an optical disc writing strategy for writing said optical disc. The method and apparatus could not only reduce the difference between the optical disc writing strategy and the real optical disc writing condition as much as possible, but also lower the requirement on the optical disc writing equipment and the cost, and could be easily realized. | 2008-10-30 |
20080267028 | INFORMATION RECORDING APPARATUS, INFORMATION RECORDING METHOD, INFORMATION PLAYBACK APPARATUS, AND INFORMATION PLAYBACK METHOD - According to one embodiment, an information recording apparatus which records content compliant with a second DVD standard on an information storage medium, the second DVD standard being a DVD standard later than a first DVD standard defined for a first image quality and being defined for a second image quality higher than the first image quality, includes a determination unit configured to determine whether narrow burst cutting area (NBCA) of the information storage medium is valid or not, and whether supported maximum recording speed of the information storage medium is triple speed or more of a predetermined recording speed, and a recording unit configured to perform real-time recording of the content compliant with the second standard on the information storage medium on the basis of the determination. | 2008-10-30 |
20080267029 | Method of Generating a Position Error Signal, Method of Writing a Data Track, and Method and Apparatus for Testing a Head - A method of generating a position error signal for a desired radial position of a read/write head relative to a data track of a disk is disclosed. The track has a plurality of servo bursts defining a plurality of servo nulls for the track, and are positioned such that they are at more than four different radial positions relative to the track, and define a predetermined locus having a known position relationship with the track. The method comprises determining a target null position on the null locus corresponding to the radial position of the head relative to the track; detecting the position of the servo null with the head; determining from the detected servo null position the position error of the head relative to the target null position; and, generating a position error signal. | 2008-10-30 |
20080267030 | DISK RECORDING DEVICE - The disk recording device of the present invention includes a recording means and a file system recording means. The recording means performs recording of an image signal upon a recordable type optical disk. The file system recording means includes an address information search means and an address information recording means. If the recording of the file system has failed, the address information recording means records the address information in the lead-in region, but does not thus record the address information if it is already recorded in the lead-in region, or the like. | 2008-10-30 |
20080267031 | Optical Disc Drive - In a recordable data storage medium on which property data was recorded after having been modulated and on which data that is decodable by a cryptographic key to be generated from the property data was recorded, the property data was preferably modulated by a different method from that applied to a read-only data storage medium. Then, an optical disc drive, having no ability to distinguish the recordable data storage medium from the read-only data storage medium, cannot read the recordable data storage medium. Consequently, a greater number of drives should be equipped with the function of recognizing the type of a given data storage medium and the copyright protection function should be consolidated. | 2008-10-30 |
20080267032 | REPRODUCTION-ONLY RECORDING MEDIUM, REPRODUCING APPARATUS, REPRODUCING METHOD, AND DISK MANUFACTURING METHOD - A ROM disk having a block data format provided with linking areas as with a rewritable disk. Main data recorded in a main data area and linking data recorded in a linking area in each block are scrambled by identical scrambling data. The scrambling data is generated by a random sequence using address information of the block as an initial value. | 2008-10-30 |
20080267033 | RECORDING APPARATUS, RECORDING METHOD, AND PROGRAM - A recording apparatus that can record a content on a first recording medium, and on a second recording medium taking longer time to record a content than the first recording medium does, the recording apparatus includes: a recording control means for controlling recording of a transferred content such a way that when the transferred content that is a content sent from another device is recorded on the second recording medium, the transferred content is recorded on the first recording medium prior to the second recording medium and the transferred content recorded on the first recording medium is recorded on the second recording medium; and a notifying means for notifying the another device that reception of the transferred content is completed at a time when the recording of the transferred content on the first recording medium is completed before the recording of the transferred content on the second recording medium is completed. | 2008-10-30 |
20080267034 | (Re) Writable Disk with Electrophoetic Ink Label - A storage medium for storing digital information is disclosed. The storage medium comprises a label comprising a light addressable electrophoretic ink layer. Further, a method for labeling a storage medium provided with an electrophoretic ink label is disclosed. The method comprises the steps of applying a voltage between a first and a second electrode being arranged on mutual sides of a electrophoretic ink layer; irradiating selected pixel areas of the electrophoretic ink for addressing a change of visual state. Further, a recorder for an optical storage medium and a label writer for labeling an optical storage medium are disclosed. The recorder and the label writer comprise a light source and a charging device. The charging device is arranged to apply an electric field across an electrophoretic ink layer of the storage medium, and the light source is arranged to write a label on said storage medium by addressing pixel areas of said electrophoretic ink layer. | 2008-10-30 |
20080267035 | Information Recording Medium - An information recording medium ( | 2008-10-30 |
20080267036 | Air Gap Servo for Optical Recording - A device reads and/or records marks in a track on a record carrier via near field optical recording. The device has a head including a lens to be positioned at a near field distance from a surface of the record carrier. An air gap controller is for controlling an air gap between the lens and the surface, and has an approach mode for bringing the lens from a remote distance in the far field ( | 2008-10-30 |
20080267037 | METHOD OF READING OPTICAL INFORMATION IN SUPER-RESOLUTION - The invention relates to the reading of digital optical recordings at very high density (CD, DVD, etc.). Reading is done by a PRML (“Partial Response Maximum Likelihood”) technique which uses a model of analog response to the recording of an isolated information bit. Customarily, the response model is represented by four or five signal samples having standardized levels 1 or 2. To take account of particular phenomena of super-resolution reading, the invention proposes the use of a model having 6 to 10 samples that can take 4 or 5 standardized levels. This model can result from the superposition of two simpler models having only two possible levels of samples taken from 1, 2 and 3. | 2008-10-30 |
20080267038 | OPTICAL DEVICE FOR HOLOGRAPHIC RECORDING OR READING AND METHOD FOR CONTROLLING THE SAME - An optical device for holographic recording or reading is provided and includes: a light emission unit that emits light to be irradiated on an optical recording medium, the light being recording or reading light; a first prism unit that moves in accordance with a moving speed of the optical recording medium and refracts the light to move the light irradiated on the optical recording medium over a distance in a moving direction of the optical recording medium so that the light is irradiated on substantially the same position on the optical recording medium for a period of time; and a second prism unit that moves in accordance with the moving speed of the first prism unit to compensate for an optical path length of the light. | 2008-10-30 |
20080267039 | HOLOGRAPHIC RECORDING APPARATUS, HOLOGRAPHIC REPRODUCING APPARATUS AND HOLOGRAPHIC RECORDING AND REPRODUCING APPARATUS - A holographic recording apparatus causes reference light and information light to interfere with each other, and records the interference pattern in a recording medium. The holographic recording apparatus has an objective lens and a focus position controller. The objective lens focuses both the reference light and the information light at a focus position of the recording medium. The focus position controller changes the focus position into a predetermined position on the light path of the reference light. | 2008-10-30 |
20080267040 | TWO-DIMENSIONAL DIGITAL DATA ACQUISITION ELEMENT AND HOLOGRAPHIC STORAGE APPARATUS - A two-dimensional digital data acquisition element includes: a pixel area having a plurality of pixels arranged in a matrix form, each of the pixels having a photoelectric conversion element to convert the reproduced light from the optical information recording medium to an electric signal; selection circuits which select the pixel; a readout circuit which reads out an electric signal of a pixel selected by the selection circuits; and a 1-bit AD converter which converts an output of the readout circuit to 1-bit digital data. A pitch ratio N between a pitch P1 of the unit data areas in the two-dimensional digital image information and a pitch P | 2008-10-30 |