44th week of 2015 patent applcation highlights part 67 |
Patent application number | Title | Published |
20150311831 | POWER SUPPLY DEVICE - A power supply device for supplying power to a load by combining a secondary battery and a capacitor includes a bypass switch which enables power to be directly supplied to the load from the capacitor by being switched to a connected state when a voltage of the capacitor is a voltage capable of driving the load, and a first DC-DC converter which enables the voltage of the capacitor to be stepped up and supplied to the load when the voltage of the capacitor drops below a minimum voltage capable of driving the load. | 2015-10-29 |
20150311832 | SYSTEMS AND METHODS FOR THE CONTROL AND OPERATION OF A PARALLEL MOTOR CONTROLLER ARCHITECTURE - A method for real time power control over a plurality of motor controllers by at least one processor on a computer system may include determining a power load demand from a first set of motors, selecting a combination of motor controllers to match the power load demand, assigning a first set of system-wide priorities, configuring a power switching network to connect the first set of motors to the motor controllers, receiving from a control unit a power request for a motor, determining a priority designation for that motor, assigning a second set of system-wide priorities, determining a second power load demand from a second set of motors, wherein the second plurality of active motors comprises the first plurality of active motors and the first motor, selecting a second combination of motor controllers necessary to match the second power load demand, and configuring the power switching network in accordance with the second set of system-wide priorities. | 2015-10-29 |
20150311833 | GENERAL-PURPOSE DESIGN OF DC-AC INVERTERS IN ELECTRIFIED AUTOMOBILE SYSTEMS - A general purpose DC-AC inverter in an electrified automobile system provides DC-AC inverter control based on different types of the motors. The DC-AC converter is configured to convert a voltage from a primary battery system of the EV to different voltage/current waveforms. One controller controls different types of motors without changing the firmware. Sensorless control is also achieved based on the same firmware. | 2015-10-29 |
20150311834 | CONTROL CIRCUIT AND METHOD FOR CONTROLLING A MULTIPHASE MOTOR - A circuit for controlling a multiphase SRM motor, comprising for each winding a low-side and a high-side transistor, and a low-side and a high-side diode for, and at least one current sensor, e.g. a single current sensor, arranged in low-side or high-side implementation for measuring a current through a first and second winding, and a controller adapted for configuring the transistors such that: during a first time slot only the first winding is energized while the second winding is freewheeling via a selected freewheeling path, during a second time slot only the second winding is energized while the first winding is freewheeling via a selected freewheeling path, and measuring the first and second current in said time slots. A method of driving said transistors. | 2015-10-29 |
20150311835 | MOTOR DRIVING SYSTEM - The disclosed invention provides a synchronous motor driving system that reduces vibration attributed to a temporal second-order component of radial electromagnetic force in a three-phase synchronous motor and controls a d-axis current and a q-axis current to reduce noise that is produced as a result of vibration resonating with a structure. A motor driving system of the present invention causes a predefined negative d-axis current to flow into a motor in which a q-axis current is less than or equal to a predefined current value and d-axis inductance and q-axis inductance match substantially. The motor driving system causes a predefined negative d-axis current to flow into a motor in which d-axis inductance and q-axis inductance differ and causes the negative d-axis current to increase with an increase in the q-axis current. | 2015-10-29 |
20150311836 | INTEGRATED POWER CONVERTING APPARATUS FOR VEHICLE - An integrated power converting apparatus for a vehicle is provided. The apparatus includes an inverter configured to drive a motor and a converter configured to output a low voltage. The inverter and the converter are disposed on an inner bottom surface of a housing. A shield plate is mounted at a predetermined height from the inner bottom surface of the housing. In addition, an integrated control board configured to operate the inverter and the converter is disposed on a top surface of the shield plate. | 2015-10-29 |
20150311837 | ANGLE DETECTOR, MOTOR DRIVE CONTROLLER, AND MOTOR DEVICE - An angle detector includes an intersection phase detector to compare each pair of multiple sensor signals or multiple sensor processed signals generate and output each intersection phase detection signal indicating a phase at which the signal level difference of the each pair is a first maximum hysteresis error after signal levels of signals of the each pair match, an intersection level detector to detect each intersection level and generate and output multiple intersection level signals indicating the detected intersection level, a signal selector to single out a selection signal of the either of the multiple sensor signals or the multiple sensor processed signals; a phase detector to detect that a signal level of the selection signal selected by the signal selector has reached a threshold level and a threshold level adjuster to adjust the threshold level based on the intersection level signal and the first maximum hysteresis error. | 2015-10-29 |
20150311838 | Improvements Relating to Electrical Power Assisted Steering Systems - An electric power assisted steering system comprises a motor adapted to apply an assistance torque to a portion of a steering shaft in response to a motor drive signal from a drive circuit, in which the motor comprises a synchronous wound field motor of the kind comprising a stator and a rotor, in which the rotor includes at least one pole and at least one coil winding associated with the pole and the stator comprises a number of phase windings, and in which the drive circuit which is configured to provide current in the coils of the stator and rotor during operation of the motor. | 2015-10-29 |
20150311839 | CIRCUIT FOR DETERMINING POSITION OF A MOVABLE MEMBER - A circuit for determining a position of a movable member driven by at least one electric motor includes a sampling circuit for generating a ripple signal indicative of a rotational number of the motor and a converter for converting the ripple signal to a pulse signal which has a frequency the same as the frequency of the ripple signal. | 2015-10-29 |
20150311840 | POWER CONTROLLER FOR SUPERCAPACITOR - A power controller, including a supercapacitor, a motor, a switching tube, an annunciator, an output resistor, a sampling resistor, a filter capacitor, a voltage-stabilizing circuit, a fly-wheel diode, and a switch. The supercapacitor, the motor, the switching tube and the sampling resistor are connected in series to form a main working circuit. The signal output end of the annunciator is connected to a trigger electrode of the switching tube via the output resistor. The sampling end of the annunciator is connected to the sampling resistor. The motor is connected in parallel to the fly-wheel diode. The sampling resistor is connected in parallel to the filter capacitor. The Vcc end of the annunciator is connected to the supercapacitor via the voltage-stabilizing circuit. The state control ends of the annunciator are connected to the GND or Vcc of the annunciator via the switch. | 2015-10-29 |
20150311841 | APPARATUS AND SYSTEMS FOR ENGINE AND GENERATOR CONTROL WITHIN AN AIRCRAFT - A system is provided for engine and generator control. The system includes a compound AC generator, a generator control unit (GCU) module and an engine electronic controller (EEC) module. The compound AC generator includes a shaft, and a permanent magnet generator (PMG) configured to be driven by the shaft to generate an AC power signal. The GCU module is configured to control the compound AC generator. The PMG is coupled to the GCU module and the EEC module such that it is configured to simultaneously supply the AC power signal to the GCU module and to the EEC module. | 2015-10-29 |
20150311842 | METHOD AND APPARATUS FOR DETECTING A STATE OF AN ALTERNATOR REGULATOR - A detection circuit for an alternator regulator, and method therefor. The detection circuit comprises an input circuit arranged to receive a phase signal from an alternator regulator and to output an attenuated sense signal representative of the received phase signal, a detection component operably coupled to the input circuit and arranged to receive the attenuated sense signal output by the input circuit, and a blocking capacitance operably coupled between the input circuit and the detection component and arranged to block a DC component of the attenuated sense signal. The detection component is arranged to compare the received attenuated sense signal to at least one reference voltage signal, and to output a signal representative of a frequency of the phase signal from the alternator regulator based at least partly on the comparison of the received attenuated sense signal to the at least one reference voltage signal. | 2015-10-29 |
20150311843 | METHOD OF LOADSHEDDING FOR A VARIABLE SPEED, CONSTANT FREQUENCY GENERATOR - A method of controlling operation of a variable speed, constant frequency generator system is disclosed. During operation, loads may be added to or removed from the output of the generator system. A controller monitors the power output by the generator system and detects a change in the output power exceeding a predefined threshold. The change indicates the addition of a large electrical load. The controller quickly detects the change in power output and activates a relay to disconnect the load from the generator system. The controller then accelerates the engine of the generator system to maximum speed and reconnects the load to the output of the generator system. | 2015-10-29 |
20150311844 | MOTOR CONTROLLER FOR POSITION SENSORLESS DRIVES - A system includes a permanent magnet motor having a rotor and a stator. The rotor and the stator have a configuration that causes the motor to generate a back-electromagnetic force (EMF) waveform that is substantially sinusoidal. The system also includes a motor controller having a sliding-mode observer configured to identify the back-EMF waveform and a position observer configured to estimate at least one characteristic of the motor using the identified back-EMF waveform. The stator may include multiple teeth projecting towards the rotor and multiple conductive windings, where each conductive winding is wound around a single tooth. The rotor may include multiple magnetic poles, where each magnetic pole has a span of about 60° or less. The sliding-mode observer may be configured to receive current measurements associated with three-phase signals and voltage commands generated by the motor controller. The position observer may include a proportional-integral (PI) regulator. | 2015-10-29 |
20150311845 | MOTOR DRIVE DEVICE AND ELECTRIC COMPRESSOR - A motor drive device drives a multi-phase synchronous motor in an electric compressor. The multi-phase synchronous motor includes a rotor that is provided with a permanent magnet and a stator having coils of different phases. The motor drive device includes an inverter that supplies current to the coils and a control unit that controls the inverter. The control unit executes an initial angular position calculation processing of detecting a d-axis and a q-axis as an initial angular position of the rotor, a rotating processing of rotating the d-axis and the q-axis in a direction opposite to rotation of the rotor, an acceleration processing of accelerating the rotation of the rotor, and a sensorless control processing of controlling the rotation of the rotor. | 2015-10-29 |
20150311846 | PRIMARY MAGNETIC FLUX CONTROL METHOD - A primary magnetic flux command value is changed in accordance with a torque of a rotary electric motor to control a current phase of an armature current with respect to a q axis that advances by π/2 with respect to a d axis in phase with a field flux to be a desired phase in accordance with the torque. | 2015-10-29 |
20150311847 | ROTATION ANGLE ESTIMATION MODULE FOR SENSORLESS VECTOR CONTROL OF PMSM - A rotation angle estimation module is provided. The rotation angle estimation module includes: a fixed flux instruction estimation unit calculating a rotating flux (λ | 2015-10-29 |
20150311848 | ROTARY ELECTRIC MACHINE CAPABLE OF DETECTING MALFUNCTION IN SWITCH - In a rotary electric machine, a modulation signal generator generates a modulation signal including information indicative of rotation of a rotor based on change of a voltage at an output end of a stator winding, and outputs the modulation signal. A rectifying unit alternately turns on and off the switch to rectify the voltage at an output end of the stator winding, thus generating a rectified voltage. An excitation current supplying circuit is communicably connected to the modulation signal generator via a communication line, and starts a supply of an excitation current to the excitation winding of the rotor to induce a rotating magnetic field in the stator winding when the modulation signal output from the modulation signal generator is input thereto via the communication line. | 2015-10-29 |
20150311849 | INDUCTION MOTOR SPEED ESTIMATION - A method for estimating a speed of an induction motor includes applying a voltage to the induction motor and measuring a current of the induction motor. A current fast fourier transform (FFT) of the current is then determined and a slip of the induction motor is calculated based on the current FFT. A speed of the induction motor is then estimated based on the slip of the induction motor. | 2015-10-29 |
20150311850 | ELECTRIC MOTOR DRIVE SYSTEM AND WINDING SWITCHING METHOD - An electric motor drive system includes an electric motor including windings for separate phases including a center tap, a winding for a low-speed rotation located between the center tap and a winding start terminal, and a winding for a high-speed rotation located between the center tap and a winding end terminal; an inverter configured to supply an inverter electric current to the winding of each phase; a first winding switch portion configured to open and close connection between the inverter and the winding start terminal, and a second winding switch portion configured to open and close connection between the inverter and the center tap of the winding of each phase; and a controller configured or programmed to control opening and closing of each of the first and second winding switch portions. | 2015-10-29 |
20150311851 | SWITCHING CONTROL DEVICE - A switching control device is applied to a motor generator drive system equipped with a boost converter and an inverter. In order to avoid generation of a superimposed surge voltage, the switching control device corrects a switching timing tsw of the booster converter so that a switching timing of the booster converter is not overlapped with a switching timing of the inverter. A booster converter switching correction means corrects the switching timing tsw of the correction target to bring forward and before a start timing tpa of the switching inhibition period Pp. This makes it possible to suppress fluctuation in output of a load due to deterioration in controllability of the electric power converter, for example, suppress fluctuation in output torque of a motor generator. | 2015-10-29 |
20150311852 | Motor Drive Voltage Control Device and Method for Controlling Motor Drive Voltage - To suppress a decline in the control accuracy of an applied voltage associated with an increase in quantum noise, and to increase the control accuracy of a motor speed. When generating a driving voltage signal supplied to a motor from a driving command signal, a motor-driving voltage control device reduces the gradation level and performs noise-shaping modulation before performing PWM modulation. Reducing the gradation level allows the degree of gradation of the driving voltage signal to be within the resolution range of the PWM modulation, and thus PWM modulation can be performed even when the driving voltage signal has a high frequency. Noise-shaping modulation reduces the level of quantum noise near the low frequency range by causing the quantum noise due to digitization, included in the driving voltage signal, to be biased toward the high frequency range side. Of modulation signals with the reduced-gradation level, the components near the high frequency band are cut, while the components near the low frequency range are used to suppress quantum noise and control the driving voltage applied to the motor with a high accuracy. | 2015-10-29 |
20150311853 | SYSTEM FOR OPERATING A THREE-PHASE VARIABLE FREQUENCY DRIVE FROM AN UNBALANCED THREE-PHASE OR SINGLE-PHASE AC SOURCE - A variable frequency motor drive comprises a converter including a rectifier having an input for connection to an AC power source and converting the AC power to DC power. A DC bus is connected to the rectifier circuit. At least one bus capacitor is across the DC bus. An inverter receives DC power from the DC bus and converts the DC power to AC power to drive a motor. A controller is operatively connected to the converter. The controller comprises a speed control controlling the inverter responsive to a speed command to maintain a desired motor speed. A speed foldback control measures DC bus ripple voltage and regulates the speed command responsive to the measured DC bus ripple voltage. | 2015-10-29 |
20150311854 | System For Mounting And Supporting Photovoltaic Modules - A system for mounting and supporting photovoltaic (PV) modules includes a frame rail that is formed with a longitudinally extending channel for retaining a plurality of mounting clips, and mounting clamps for anchoring the frame rail to a support base or support structure. Each mounting clamp includes a pair of jaws for engaging along a base portion of the fame rail. The mounting clips are arranged along the length of the frame rail, and are used to support the PV modules adjacent to the frame rails. Module clamps are used to hold the PV modules in place, the module clamps being secured to the mounting clips using elongated fasteners having an engaging end for engaging the mounting clip. The mounting clamps allow the frame rail position to be adjusted in two directions, and the mounting clips facilitate rapid mounting of the PV modules to the frame rail structure. | 2015-10-29 |
20150311855 | PHOTOVOLTAIC CELL MOUNTING SUBSTRATE AND PHOTOVOLTAIC CELL MODULE - A photovoltaic cell mounting substrate includes a substrate; and a plurality of grooves provided at one surface of the photovoltaic cell mounting substrate, the plurality of grooves including a first groove and a second groove that is placed at a circumferential side of the first groove, at the one surface of the substrate, the second groove being formed deeper than the first groove, with respect to the one surface of the substrate. | 2015-10-29 |
20150311856 | BUILDING BODY WITH SOLAR TRACKING DEVICE - A building body with solar tracking device includes a top tent supported on the building body. The top tent includes at least one set of intersection section where multiple beams in different directions intersect each other. A support assembly of the solar tracking device is mounted on an upper side of the intersection section or in a position corresponding to the upper side of the intersection section. A solar generation module is mounted on the support assembly, whereby the top tent provides a sufficient strength for supporting the solar tracking device. | 2015-10-29 |
20150311857 | CONCENTRATING SOLAR PANEL WITH INTEGRATED TRACKER - The present invention is an integrated sun tracking and concentrating solar panel that uses compact optical elements to track the sun and concentrate its sunlight to one or more energy conversion devices that are collocated on the solar panel. The invention eliminates the need for large mechanical solar trackers while also substantially increasing the efficiency of land use for arrays of solar panels. | 2015-10-29 |
20150311858 | Solar Collector and Conversion Array - A solar array for collecting sunlight that is converted into electricity. The array includes an arrangement of solar collectors strategically positioned on a frame to maximize the amount of sunlight collected in relation to the size of the array. The collectors are plate like members with a reflective side and shaped so that sunlight collected by the reflective side is concentrated at a location away from the reflective side. The collectors are recumbently positioned in rows with their respective reflective sides directed away from the array frame. The collectors are spaced apart so that no collector casts shade on any part of another collector and substantially no sunlight between adjacent collectors. | 2015-10-29 |
20150311859 | SMART DUST-CLEANER AND COOLER FOR SOLAR PV PANELS - The smart dust-cleaner and cooler for solar PV panels is a smooth transparent shield with low absorption coefficient (such as a plastic sheet) placed on the top of the panel to facilitate the removal of dust. Two Membrane Vibrators (MVs) are placed on opposite sides of the panel. The vibrators have the ability to shake and resonate the sheet, dislodging the dust particulates from their positions. A compressor powered by the PV panel compresses air before the cleaning process, which operates in short duration. Release of the compressed air creates an air stream over the panel that removes the loose dust and cools the panel to enhance performance. Using a microcontroller-based timer, the dust cleaning/cooling process is timed for daily operation before noon, when the panel temperature is at its peak to maximize panel efficiency at maximum irradiance time. | 2015-10-29 |
20150311860 | MULTI-ORTHOGONAL PHOTONIC ENERGY COLLECTION SYSTEM - A method of energy collection using a set of collecting manifolds or surfaces such as solar cells immersed into a refracting matrix. The combination of the surfaces and matrix into a module forms the system. | 2015-10-29 |
20150311861 | SOLAR CELL MODULE - A solar cell module is discussed. The solar cell module includes a solar cell panel and an integrated type inverter positioned at a back surface of the solar cell panel. The integrated type inverter includes a circuit unit having a terminal connected to the solar cell panel and an inverter member having a DC-AC inverter electrically connected to the terminal, and a receiving unit receiving the terminal and the DC-AC inverter, the receiving unit having at least one open surface. One of the open surfaces of the receiving unit is covered by the solar cell panel. | 2015-10-29 |
20150311862 | APPARATUS FOR MONITORING LEAKAGE CURRENT OF TRANSFORMER-LESS PHOTOVOLTAIC INVERTER - Disclosed is an apparatus for monitoring a leakage current of a transformer-less photovoltaic inverter, which can reduce the risk of a fault in a grid due to a leakage current in a photovoltaic inverter. The apparatus comprises a low pass filter configured to remove a high-frequency noise of a sensed leakage current signal; an average value calculator configured to calculate an average value of an output of the low pass filter; a direct current component remover configured to subtract the average value from the output of the low pass filter; a phase locked loop circuit section configured to calculate a peak value and a phase of a signal from which the direct current component has been removed; and a resistive component leakage current calculator configured to calculate a resistive component value of a leakage current, based on the peak value and the phase calculated. | 2015-10-29 |
20150311863 | COMPUTATION OF GLINT, GLARE, AND SOLAR IRRADIANCE DISTRIBUTION - Described herein are technologies pertaining to computing the solar irradiance distribution on a surface of a receiver in a concentrating solar power system or glint/glare emitted from a reflective entity. At least one camera captures images of the Sun and the entity of interest, wherein the images have pluralities of pixels having respective pluralities of intensity values. Based upon the intensity values of the pixels in the respective images, the solar irradiance distribution on the surface of the entity or glint/glare corresponding to the entity is computed. | 2015-10-29 |
20150311864 | SWITCHING SYSTEM WITH LINEARIZING CIRCUIT - A transistor-based switch is coupled to a replica circuit that includes transistor circuitry similar to that of the switch. The replica circuit biases a switched transistor to promote linear operation of the switch. | 2015-10-29 |
20150311865 | Flyback Amplifier with Direct Feedback - In at least one embodiment, the invention provides a bidirectional amplifier and method of control that enables immediate feedback directly from the output for fast response and low distortion. Mechanisms responsive to instantaneous feedback eliminate undershoot, overshoot, and sub-harmonic behavior. One embodiment comprises two switches and a single two-terminal inductor. Another embodiment produces a bipolar output from a single unregulated supply rail. The use of Predictive Energy Balancing controls yield high efficiency and low total harmonic distortion. These amplifiers are suited for audio application, and can drive piezo or dynamic speakers. | 2015-10-29 |
20150311866 | DEVICE AND METHOD FOR CONTROLLING POWER AMPLIFIER - A control device provides a supply voltage to an output transistor of a power amplifier. The control device includes a detector encoder, a switch sequencer and a power switch. The detector encoder receives a detection signal indicating a negative peak voltage level of an output signal of the power amplifier, receives a reference signal indicating a critical voltage of the detection signal at which the negative peak voltage level of the output transistor is deemed to be out of voltage with reference to saturation voltage of the output transistor, compares the detection and reference signals, and outputs Boost Request and Recovery Request signals in response. The switch sequencer translates the Boost Request and Recovery Request signals into multiple control bits. The power switch coordinates switching among a no boost voltage and multiple boost voltages based on the control bits, and outputs one of these voltages as the supply voltage. | 2015-10-29 |
20150311867 | HIGH-FREQUENCY AMPLIFIER CIRCUIT - A high-frequency amplifier circuit ( | 2015-10-29 |
20150311868 | Digitally-Programmable Gain Amplifier with Direct-Charge Transfer and Offset Cancellation - A Programmable-Gain Amplifier (PGA) has a digital value that programmably adjusts the gain of the analog amplifier. A variable capacitor has several switched sub-capacitors that are enabled by the digital value. Enabled sub-capacitors are switched between a sampled input and a virtual ground on one terminal, and connect to a summing node on the other terminal. The summing node connects to the inverting input of an op amp either through a switch or through a double-sampling capacitor that stores an offset. A feedback capacitor is in parallel with a sampling capacitor during a second clock phase when direct-charge transfer occurs, reducing power consumption of the amplifier. The feedback capacitor samples the sampled input during the first clock phase. The PGA gain is proportional to the sum of capacitances of enabled sub-capacitors. The gain can be adjusted for sensor inputs to an Analog Front-End (AFE), such as for an electro-cardiogram (ECG). | 2015-10-29 |
20150311869 | AMPLIFIER CIRCUIT AND OPERATION METHOD THEREOF - Disclosed is an amplifier circuit capable of achieving high efficiency at back off power while maintaining high output power when an amplifier of a driving stage is saturated in a multistage amplifier in which a plurality of amplifiers are connected in series to each other. In the amplifier circuit, at least two amplifiers including a first amplifier and a second amplifier, the first amplifier preceding the second the first amplifier, are connected in series to each other, the second amplifier changes input impedance according to output power from the first amplifier, and an impedance adjusting unit for adjusting output load impedance of the first amplifier is disposed between the first amplifier and the second amplifier, wherein the impedance adjusting unit optimizes the output load impedance of the first amplifier according to a change of input impedance of the second amplifier. | 2015-10-29 |
20150311870 | System and Method for Capacitive Signal Source Amplifier - In accordance with an embodiment, a system for amplifying a signal provided by a capacitive signal source includes a first voltage follower device, a second voltage follower device, and a first capacitor. The first voltage follower device includes an input terminal configured to be coupled to a first terminal of the capacitive signal source, and the second voltage follower device includes an input terminal coupled to the first output terminal of the first voltage follower device, and an output terminal coupled to a second output terminal of the first voltage follower device. Furthermore, first capacitor has a first end coupled to a first output terminal of the first voltage follower device, and a second end configured to be coupled to a second terminal of the capacitive signal source. | 2015-10-29 |
20150311871 | RECEIVER CIRCUIT - A receiver circuit includes a first amplifier circuit to differentially amplify differential input signals by a linear operation, a second amplifier circuit configured to differentially amplify output differential signals of the first amplifier circuit by a limiting operation, a feedback circuit, first and second resistors coupled between the feedback circuit and outputs of the first amplifier circuit, and third and fourth resistors coupled between the feedback circuit and outputs of the second amplifier circuit. The feedback circuit amplifies a positive-phase signal that is output from a positive-phase output node thereof coupled to the first and third resistors, and a negative-phase signal that is output from a negative-phase output node thereof coupled to the second and fourth resistors, and feeds back a feedback signal after amplification to the first amplifier circuit. | 2015-10-29 |
20150311872 | APPARATUS AND METHODS FOR AMPLIFIER INPUT PROTECTION - Apparatus and methods for amplifier input protection are provided. In certain implementations, an amplifier input protection circuit includes a first JFET electrically connected between a first input and a first output, and a second JFET electrically connected between a second input and a second output. Additionally, a first clamp is electrically connected to the first output, and a second clamp is electrically connected to the second output. A first current mirror mirrors a current through the first clamp, and provides the mirrored current to a third JFET electrically connected between the first JFET's source and gate. Additionally, a second current mirror that mirrors a current through the second clamp, and provides the mirrored current to a fourth JFET that is electrically connected between a source and gate of the second JFET. Configuring the protection circuit in this manner can provide the benefits of both low noise and low fault current. | 2015-10-29 |
20150311873 | RADIO FREQUENCY POWER AMPLIFIER AND METHOD FOR INCREASING POWER ADDED EFFICIENCY AND LINEARITY - A radio frequency (RF) power amplifier is disclosed. The RF power amplifier includes an impedance transformation circuit, a current unit gain amplifier, and an output match circuit. The impedance transformation circuit receives a first input power signal and outputs a second input power signal correspondingly, wherein the impedance transformation circuit transforms an input impedance to an output impedance according to an impedance matching parameter for increasing power added efficiency of a pre-stage circuit. The current unit gain amplifier provides a linear transimpedance so as to transmit an input current to an output impedance, and then generate a linear output power for increasing power added efficiency of the current unit gain amplifier, wherein the impedance matching parameter is determined by a first system voltage, a second system voltage, and a predetermined power gain value. | 2015-10-29 |
20150311874 | BROADBAND POWER AMPLIFIER SYSTEMS AND METHODS - Disclosed are systems, devices, and methodologies to reduce harmonics in a radio frequency output signal. A power amplifier system comprises a power amplifier and a tunable output matching network electrically connected between the output of the power amplifier and an output of the tunable output matching network. The tunable output matching network reduces second-order harmonics in an amplified radio frequency signal when the power amplifier operates in a low frequency mode. The tunable output matching network includes traps such as a series inductor and a first capacitor in series with a first switch, a second capacitor in series with a second switch, and a third capacitor in series with a third switch, where the traps are tuned to selected harmonic frequencies when the power amplifier operates in the low frequency band of the operating band of frequencies. | 2015-10-29 |
20150311875 | SENSE AMPLIFIER WITH IMPROVED RESOLVING TIME - Sense amplifiers that can provide improved resolving times can be used, for example, in clock and data recovery circuits. The sense amplifiers sense the value of a differential input signal using a latch circuit and then, after an initial sensing time, force the latch circuit to resolve a digital value that corresponds to the value of the input signal. An implementation of the sense amplifies uses a first latch with cross-coupled inverters that produce set and reset signals. A transistor pair couples the differential input signal to the cross-coupled inverters via a switch to ground. A discharge path circuit arranged to accelerate the resolving of the latch circuit is also coupled to the cross-coupled inverters. The discharge path can be enabled after an initial sensing time. | 2015-10-29 |
20150311876 | Amplifiers and Related Biasing Methods and Devices - Biasing methods and devices for amplifiers are described. The described methods generate bias voltages proportional to the amplifier output voltage to control stress voltages across transistors used within the amplifier. | 2015-10-29 |
20150311877 | Automatic Gain Control in a Heterogeneous Mobile Communication Network - The invention refers to performing an automatic gain control—AGC—with respect to a received signal comprising a plurality of consecutive subframes (S | 2015-10-29 |
20150311878 | RECEIVING APPARATUS THAT RECEIVES PACKET SIGNAL - An RF unit receives predetermined signals. The RF unit amplifies the received signals. A gain control unit controls the gain at the RF unit based on the amplified signal and has the RF unit use the controlled gain. The gain control unit performs different controls on the received signals, depending on the case when the received signal is a known signal placed in the beginning of packet signal and the case when the received signal is a signal other than the packet signal. | 2015-10-29 |
20150311879 | MICROPHONE BIAS CIRCUIT - A bias circuit supplies a bias voltage V | 2015-10-29 |
20150311880 | Electric Power Transmission Device and Electric Power Transmission Method - An electric power transmission device characterized in that the electric power transmission device includes a power transmitting unit which wirelessly transmits an electric power and a power receiving unit which receives the electric power, the power transmitting unit and the power receiving unit include a coil for electric power transmission and an inclusion unit made of a dielectric material covering the coil for electric power transmission, at least one of the power transmitting unit and the power receiving unit includes an impedance adjustment unit which varies the impedance thereof, and the electric power is transmitted at a resonance frequency determined by an impedance of the power transmitting unit, an impedance of the power receiving unit, and an impedance of the conducting medium. | 2015-10-29 |
20150311881 | ANTENNA DEVICE - A stray capacitance is generated between an antenna element and a ground electrode. A capacitance detection circuit detects the stray capacitance. An antenna matching circuit, is provided along a wireless communication signal path, which is a transmission path between the antenna element and a feeder circuit. A feedback control circuit transmits a control signal to the variable matching circuit on the basis of a detection result of the capacitance detection circuit in accordance with the stray capacitance. The capacitance detection circuit includes a constant current source and a timing circuit to measure the time taken to charge the antenna from the constant current source and for the voltage to reach a predetermined voltage. | 2015-10-29 |
20150311882 | A FILTER ASSEMBLY AND A METHOD OF FILTERING - A filter assembly is provided comprising a first filter ( | 2015-10-29 |
20150311883 | System and Method for a Switchable Capacitance - In accordance with an embodiment, a switchable capacitance circuit includes a plurality of capacitance-switch cells that each have a capacitance circuit having a capacitance between a first terminal and a second terminal of the capacitance circuit, and a semiconductor switching circuit including a first terminal coupled to the first terminal of the capacitance circuit, a plurality of series connected radio-frequency (RF) switch cells having a load path and a common node. Each of the plurality of series connected RF switch cells has a switch transistor and a gate resistor having a first end coupled to a gate of the switch transistor and a second end coupled to the common node. The switchable capacitance circuit also includes a resistance circuit having a first end coupled to the common node and a second end coupled to a control node. | 2015-10-29 |
20150311884 | CHARGE-RECYCLING CIRCUITS INCLUDING SWITCHING POWER STAGES WITH FLOATING RAILS - In one embodiment, a circuit comprises a first switching transistor and a second switching transistor. The first switching transistor and the second switching transistor are coupled in series between an input voltage and ground and having a common node therebetween to provide a switching output. A first switching circuit selective couples a gate of the first switching transistor to the input voltage and a first mid-level voltage supply. A second switching circuit selectively couples a gate of the second switching transistor to a second mid-level voltage supply and ground. A charge-recycling circuit is coupled to the gate of the first switching transistor, the gate of the second switching transistor, the first mid-level voltage supply, and the second mid-level voltage supply to selectively recycle charge between the first mid-level voltage supply and the second mid-level voltage supply. | 2015-10-29 |
20150311885 | POWER-UP SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A power-up signal generation circuit including a pre-power-up signal generation block operates by using a first power supply voltage, and generates a pre-power-up signal when the first power supply voltage becomes higher than a first level, and a second power supply voltage becomes higher than a second level; a level shifting block suitable for pull-down driving a first node when the pre-power-up signal is not in an activated state, and pull-up driving the first node with the second power supply voltage when the pre-power-up signal is in the activated state; a driving block suitable for pull-down driving the first node when the second power supply voltage is lower than the second level; and a power-up signal driving block operates by using the second power supply voltage, and generates a power-up signal through a second node by driving the second node based on a voltage level of the first node. | 2015-10-29 |
20150311886 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - The circuit includes a first wiring for supplying a power supply potential to a signal processing circuit, a transistor for controlling electrical connection between the first wiring and a second wiring for supplying the a power supply potential, and a transistor for determining whether or not the first wiring is grounded. At least one of the two transistors is a transistor whose channel is formed in the oxide semiconductor layer. This makes it possible to reduce power consumption due to cutoff current of at least one of the two transistors. | 2015-10-29 |
20150311887 | ANALOG SIGNAL GENERATION CIRCUIT - An analog signal generation circuit is provided. The analog signal generation circuit includes a first control section that generates a first control signal; a second control section that generates a second control signal; current cells, each of the plurality of current cells controlled to generate current or to not generate current based on the first and second control signals; and an analog signal output section that outputs an analog signal generated based on current generated by the current cells. The first control signal includes first and second cell state setting signals. A logical value corresponding to the first cell state setting signal is complementary to a logical value corresponding to the second cell state setting signal. Each current cell has an initialized state based on the first cell state setting signal. | 2015-10-29 |
20150311888 | CLOCK FREQUENCY MODULATION METHOD AND CLOCK FREQUENCY MODULATION APPARATUS - Embodiments of the present invention provide a clock frequency modulation method and a clock frequency modulation apparatus. The method includes: determining N digital clocks according to a first digital clock of a system, where the N digital clocks includes a second digital clock and N-1 digital clocks except the second digital clock, and a sum of frequency ratios of the first digital clock to each of the N-1 digital clocks is equal to N-1 times a frequency ratio of the first digital clock to the second digital clock, where N is an integer greater than 2; and fitting, during a modulation period by using the N digital clocks, the first digital clock into the periodic second digital clock. The embodiments of the present invention use a clock frequency modulation technology to make energy concentrated in a frequency spread to a wider frequency range. | 2015-10-29 |
20150311889 | CIRCUITRY FOR PHASE DETECTOR - A circuit for a phase detector is provided. A first buffer of the circuit receives a data signal and generates a first modified data signal using the data signal. A notifier receives the data signal and determines whether a violation exists. A first multiplexer receives the first modified data signal and transmits a first multiplexer signal to a second multiplexer. The second multiplexer receives the first multiplexer data signal and the first modified data signal, and transmits a second multiplexer data signal to a flip-flop of the phase detector. | 2015-10-29 |
20150311890 | SIGNAL GENERATOR, SIGNAL GENERATION METHOD, AND NUMERICALLY CONTROLLED OSCILLATOR - A waveform conversion unit ( | 2015-10-29 |
20150311891 | HIGH VOLTAGE BOOTSTRAP GATE DRIVING APPARATUS - A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage. | 2015-10-29 |
20150311892 | ELECTRONIC CONTROL DEVICE - Provided is an electronic control device capable of preventing all of semiconductor relays from being forcibly controlled to be opened by a self-protection shutoff function. An electronic control device controls semiconductor relays provided in a load control unit, which correspond to loads mounted in an automobile. The electronic control device includes a temperature measuring means which measures the ambient temperature of the semiconductor relays. The electronic control device also includes an operation restricting means which, when the temperature measured by the temperature measuring means is higher than or equal to an operation restriction temperature threshold set within an ambient temperature range in which the self-protection shutoff function is not performed in the semiconductor relays, performs control for opening semiconductor relays that correspond to some loads among the loads. | 2015-10-29 |
20150311893 | METHOD, APPARATUS AND SYSTEM FOR AN EDGE RATE CONTROLLED OUTPUT BUFFER - A circuit for minimizing variation over process, voltage and temperature for edge rate over and propagation delay. The circuit includes at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers, at least two second buffers for level shifting to the at least two first buffers, at least two voltage sources for initializing the stage of at least one of the first or the second buffer, and a current source generator coupled to the voltage source of the second buffers. | 2015-10-29 |
20150311894 | Systems and Methods for Sensing Current Through a Low-Side Field Effect Transistor - Systems and techniques detecting a reverse current are disclosed. An apparatus comprises a switching circuit coupled to a load and a reference node. The switching circuit may be capable of conducting a reverse current from the reference node to the load when a voltage at the load is lower than a voltage at the reference node. A voltage source has a first terminal coupled to the load, a second terminal configured to follow a voltage at the load, and produces a voltage proportional to a voltage drop across the switching circuit. A comparator circuit is coupled to compare a voltage at the second terminal of the voltage source to the voltage at the reference node and configured to indicate when the reverse current has a magnitude greater than a predetermined threshold. | 2015-10-29 |
20150311895 | HIGH PERFORMANCE RECONFIGURABLE VOLTAGE BUFFERS - In this disclosure, new structures for high-performance voltage buffers (source followers and emitter followers) are described. The structures achieve high performance (linearity) and reduce power consumption. In addition, they are reconfigurable to optimize the performance and power consumption depending on the input frequency range. | 2015-10-29 |
20150311896 | SOURCE DRIVING CIRCUIT AND RESISTOR RENORMALIZATION METHOD - A resistor renormalization method for a source driving circuit is provided, wherein the source driving circuit includes a plurality of resistors coupled in series, and the resistors respectively have a resistance and correspond to a number section value. The resistor renormalization method includes the steps of: (A) adding the resistances of the resistors to generate a total resistance; (B) providing a radix, wherein the radix is a natural number; (C) dividing the total resistance by the radix to generate a calculated section value; (D) dividing the resistances of the resistors by the radix to generate a plurality of remainders, respectively, and adding the remainders to generate an accumulated remainder; and (E) setting the number section value and the resistance of each resistor according to a relation between the calculated section value and the number section value and a relation between the remainder of each resistor and the radix. | 2015-10-29 |
20150311897 | SEMICONDUCTOR DEVICE - A dynamic reconfigurable semiconductor device is provided. The semiconductor device includes two logic blocks, a pass transistor, two selection transistors and a precharge transistor. The two selection transistors are arranged to sandwich the pass transistor so that a source and a drain of the pass transistor are located between the sources of the two selection transistors. The sources and the drains of the two selection transistors are located between the two logic blocks. When the two selection transistors are in off-state, a potential can be supplied to the source or the drain of the pass transistor via the precharge transistor, and by electrical conduction, another potential for a context is applied to the gate of the pass transistor. When the context is executed, the gate of the pass transistor is in a floating state, the two selection transistors are in on-state, and the precharge transistor is in off-state. | 2015-10-29 |
20150311898 | SPARE GATE CELL FOR INTEGRATED CIRCUIT - Spare gate cells for inclusion in an integrated circuit have multiple inputs and outputs and are capable of selectively performing, concurrently, multiple logic functions on signals appearing at the inputs. Selection of required logic functions depends on the connections of at least one of the inputs of the spare cell. One of the outputs is fed back to an input of the spare gate cell to provide certain functionality while other outputs are set to a fixed logical value. The spare gate cell may be configured to perform NOR, OR and inverter operations on inputs simultaneously. | 2015-10-29 |
20150311899 | VIRTUALIZATION OF PROGRAMMABLE INTEGRATED CIRCUITS - A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC. | 2015-10-29 |
20150311900 | PROGRAMMABLE LOGIC CIRCUIT AND NONVOLATILE FPGA - A programmable logic circuit according to an embodiment includes: a first programmable device with a first and second terminals, a resistance of the first programmable device being changeable from a high resistance to a low resistance; a second programmable device with a third and fourth terminals, a resistance of the second programmable device being changeable from a high resistance to a low resistance; a first wiring line to which the first terminal is connected; a second wiring line to which the third terminal is connected; a third wiring line to which the second terminal and the fourth terminal are connected; and a fuse element of which one terminal is connected to the third wiring line. | 2015-10-29 |
20150311901 | A NONVOLATILE MAGNETIC LOGIC DEVICE - In one aspect, a nonvolatile magnetic logic device comprises an electrically insulating layer, a write path, and a read path. The write path comprises a plurality of write path terminals and a magnetic layer having a uniform magnetization direction that is indicative of a direction of magnetization of the magnetic layer in a steady state. A logic state is written to the nonvolatile magnetic logic device by passing a current through the plurality of write path terminals. The read path comprises a plurality of read path terminals for evaluation of the logic state. The electrically insulating layer promotes electrical isolation between the read path and the write path and magnetic coupling of the read path to the write path. | 2015-10-29 |
20150311902 | PLL WITH ACROSS-STAGE CONTROLLED DCO - In some embodiments, a PLL comprises an across-stage DCO controller and a DCO. The across-stage DCO controller comprises a first detector and a second tuning code adjustor. The first detector receives a first tuning code in a current stage in which an output frequency of the DCO is tuned by a first step size and generates a first detect signal which indicates whether the first tuning code exceeds a first range that the DCO can be correspondingly tuned in the current stage. The second tuning code adjustor adjusts a second tuning code from a previous stage in which the output frequency of the DCO is tuned by a second step size in response to the first detect signal. The second step size is larger than the first step size. The DCO generates the output frequency in response to codes comprising the adjusted second tuning code. | 2015-10-29 |
20150311903 | Communication Over Generator Bus - A generator system includes at least one generator, at least one generator controller, and a power bus. The power bus transmits power to a load circuit. Data communications are also transmitted by the power bus. In one example, multiple generator controllers exchange messages over the power bus. In another example, one or more generator controllers exchange messages with a central controller over the power bus. The messages may include a status for the generators, output values for the generators, or commands for the generators. | 2015-10-29 |
20150311904 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal. | 2015-10-29 |
20150311905 | ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL) - An all-digital phase-locked loop (ADPLL) is provided. The ADPLL comprises a first circuit and a second circuit. The first circuit is configured to monitor a first signal and set a voltage of a second signal to a voltage within a first voltage range when a code of fine-tuning is equal to a first specified value. The first circuit is configured to set a voltage of a third signal to a voltage within a second voltage range when the code of fine-tuning is equal to a second specified value. The second circuit is configured to increase a code of coarse-tuning when the voltage of the second signal is within the first voltage range, and decrease the code of coarse-tuning when the voltage of the third signal is within the second voltage range. The ADPLL provides a target frequency despite changes in at least one of process, voltage or temperature. | 2015-10-29 |
20150311906 | OSCILLATOR CROSSTALK COMPENSATION - Systems and methods for mitigating crosstalk between controlled oscillators of Phase-Locked Loops (PLLs) are disclosed. In one embodiment, a system includes a first PLL including a first controlled oscillator and a second PLL. The system further includes a compensation signal generator adapted to generate a compensation signal at an offset frequency that is approximately equal to an offset between output frequencies of the first and second PLLs and apply the compensation signal to the first controlled oscillator such that the output signal of the first controlled oscillator is modulated by the compensation signal. An amplitude and a phase of the compensation signal are such that, when the compensation signal is applied to the first controlled oscillator, a crosstalk signal output by the first controlled oscillator resulting from crosstalk from the second controlled oscillator of the second PLL to the first controlled oscillator of the first PLL is mitigated. | 2015-10-29 |
20150311907 | SAMPLING CIRCUIT MODULE, MEMORY CONTROL CIRCUIT UNIT, AND METHOD FOR SAMPLING DATA - A sampling circuit module, a memory control circuit unit, and a method for sampling data are provided. The sampling circuit module includes a state machine circuit, a first delay line circuit, a second delay line circuit and a delay signal output circuit. In response to a first control signal, the state machine circuit outputs a second control signal and/or a third control signal. The first delay line circuit is configured to receive a reference clock signal and the second control signal to output a first delay clock signal. The second delay line circuit is configured to receive the reference clock signal and the third control signal to output a second delay clock signal. The delay signal output circuit is configured to receive the first delay clock signal and the second delay clock signal to output a third delay clock signal. | 2015-10-29 |
20150311908 | LOCAL OSCILLATOR INTERFERENCE CANCELLATION - Systems and methods for mitigating interference in a Local Oscillator (LO) signal generated by a Phase-Locked Loop (PLL) are disclosed. In one embodiment, a system includes a PLL and an error compensation subsystem. The PLL includes a Controlled Oscillator (CO) that provides a LO output signal based on a control signal, a phase detector that generates a phase detector output signal that is indicative of a phase error between a feedback signal that is a function of the LO output signal and a reference signal, and a loop filter that filters the phase detector output signal to provide the control signal for the CO. The error compensation subsystem applies, based on the phase detector output signal, a phase rotation to a signal derived from the LO output signal to thereby compensate for a phase error in the signal resulting from a phase error in the local oscillator output signal. | 2015-10-29 |
20150311909 | CONVERTER FOR ANALOG INPUTS - A device having a first oscillator circuit configured to generate a first signal with a first frequency based on an analog input and external characteristics, and a second oscillator circuit configured to generate a second signal with a second frequency based on a constant voltage and the external characteristics. The device also having one or more discrete logic gates configured to generate a digital composite signal based on the first signal and the second signal, such that a number of transitions in the digital composite signal over a period of time, based on the first frequency of the first signal, are indicative of the analog input. | 2015-10-29 |
20150311910 | CURRENT COMPARATOR OFFSET CALIBRATION IN DIGITAL-TO-ANALOG CONVERTER CALIBRATIONS - In an aspect of the disclosure, a method and an apparatus are provided for calibrating a current comparator circuit associated with a DAC element. The apparatus receives an output of a current comparator module, determines calibration data using a finite state machine (FSM) based on the output of the current comparator module, and reduces an offset current at an input of the current comparator module based on the calibration data from the FSM. | 2015-10-29 |
20150311911 | Quantum Tunneling Devices and Circuits with Lattice-Mismatched Semiconductor Structures - Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials. | 2015-10-29 |
20150311912 | ANALOG-TO-DIGITAL CONVERTER AND AN IMAGE SENSOR INCLUDING THE SAME - An analog-to-digital converter includes a modulator, a controller, and a digital filter. The modulator generates a modulated signal based on an analog signal. The controller generates a weight control signal. The digital filter includes a weight signal generator and a first integrator. The weight signal generator generates a weight signal based on the weight control signal. The first integrator generates a digital signal corresponding to the analog signal by integrating the weight signal in response to the modulated signal. The weight control signal corresponds to a type and an order of the digital filter. | 2015-10-29 |
20150311913 | DISTRIBUTED VIRTUAL-GROUND SWITCHING FOR SAR AND PIPELINED ADC - Systems, apparatuses, and methods are provided for analog-to-digital converters (ADCs), such as successive-approximation-register (SAR) ADCs and pipelined ADCs that utilize distributed virtual-ground switching (DVS). DVS circuits and systems receive reference signal inputs that are provided to input signal buffers at the input side of the buffers via reference switches. The input signal buffers and corresponding switches are distributed into scaled replicas that each receive an analog input signal via input signal switches during a first operational phase and are connected to top plates of corresponding distributed capacitors. The bottom plates of the capacitors are sampled to provide analog input signal representations. Based on the value of the signal representations, a state machine controls each of the switches to apply reference signals to the input buffers, during a second operation phase, and to iteratively generate additional signal representations and provide a digital signal that corresponds to the analog input signal. | 2015-10-29 |
20150311914 | RECONFIGURABLE ANALOG-TO-DIGITAL CONVERTER, IMAGE SENSOR AND MOBILE DEVICE INCLUDING THE SAME - An image sensor includes a pixel array, a controller, and a plurality of analog-to-digital converters. The pixel array includes a plurality of pixels coupled to column lines, respectively, and the plurality of pixels are configured to sense incident lights to generate analog signals through the column lines. The controller generate a conversion control signal that is configurable based on changes of at least one operational condition. The plurality of analog-to-digital converters are coupled to the column lines, respectively. The plurality of analog-to-digital converters perform a delta-sigma modulation and a digital filtering to convert the analog signals to digital signals. The plurality of analog-to-digital converters adjust a conversion gain internally in response to the conversion control signal. | 2015-10-29 |
20150311915 | FIELD LEVEL COMPRESSION IN PARALLEL DATA FLOWS - According to one embodiment of the present invention, a system selectively compresses data fields in a parallel data flow. The system identifies within an execution plan for the parallel data flow a first instance of a data field within a stage of the parallel data flow. The system traces the identified data field through stages of the parallel data flow and determines a score value for the identified data field based on operations performed on the identified data field during traversal of the stages. The system compresses the identified data field based on the score value indicating a performance gain with respect to the compressed data field. Embodiments of the present invention further include a method and computer program product for selectively compressing data fields in a parallel data flow in substantially the same manners described above. | 2015-10-29 |
20150311916 | ENCODING AND DECODING OF DATA - An apparatus run-length encodes data to obtain a sequence of records. The data are associate to grid points of a grid and the records are defined such that they allow embedding data associated to a same grid point and representing pieces of information of at least two different types in a same record. The encoded data may be stored or transmitted. When receiving or retrieving such run-length encoded data in a sequence of records, the data may be run-length decoded to obtain decoded data and an association of the decoded data to the grid points of the grid. | 2015-10-29 |
20150311917 | LOW DENSITY PARITY CHECK DECODER - A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order | 2015-10-29 |
20150311918 | EFFICIENT STORAGE ARCHITECTURE FOR LOW-DENSITY PARITY-CHECK DECODING - A low-density parity-check (LDPC) decoder may comprise a shift register configured to receive LDPC coded data, perform an iteration associated with decoding the LDPC coded data, and provide a result of performing the iteration. The shift register may include a quantity of lanes corresponding to a quantity of data words received by the shift register at a particular clock cycle, a quantity of stages corresponding to a quantity of clock cycles needed to perform the iteration, a quantity of storage elements, associated with storing the data words during the iteration, and a set of check node elements associated with updating the data words during the iteration. The quantity of stages times the quantity of lanes may be greater than the quantity of storage elements by a particular number of storage elements. The particular number of storage elements may be displaced by the set of check node elements. | 2015-10-29 |
20150311919 | CODE DESIGN AND HIGH-THROUGHPUT DECODER ARCHITECTURE FOR LAYERED DECODING OF A LOW-DENSITY PARITY-CHECK CODE - A low-density parity-check (LDPC) decoder may receive LDPC coded data. The LDPC decoder may perform a decoding iteration associated with decoding the LDPC coded data. The decoding iteration may be performed by processing a group of layers. Each layer may include a corresponding set of check node elements, and may be processed by causing each check node element, of the set of check node elements corresponding to the layer, to update a set of variable node elements, connected to the check node element and associated with the LDPC coded data, based on a check node function associated with the check node element. The decoding iteration may be performed such that each layer is processed in parallel, and such that each check node element updates the corresponding set of variable node elements in parallel. The LDPC decoder may provide a result of performing the decoding iteration. | 2015-10-29 |
20150311920 | DECODER FOR A MEMORY DEVICE, MEMORY DEVICE AND METHOD OF DECODING A MEMORY DEVICE - According to embodiments of the present invention, a decoder for a memory device is provided. The decoder includes an error detection circuitry configured to multiply a vector of one or more data words with a parity matrix to determine a plurality of syndrome values and generate a plurality of coefficients from multiplying a syndrome vector with an inverse of a syndrome matrix; and an error correction circuitry configured to perform a Chien search on a first part of the plurality of coefficients to determine error indicators indicating error locations in a first part of the one or more data words, and subsequently on a second part of the plurality of coefficients to determine error indicators indicating error locations in a second part of the one or more data words. According to further embodiments of the present invention, a memory device and method of decoding a memory device are also provided. | 2015-10-29 |
20150311921 | MEMORY CONTROLLER, STORAGE DEVICE AND DECODING METHOD - According to one embodiment, a memory controller includes a first decoder that decodes a block product code read out from a non-volatile memory and calculates reliability information of each sub-block, and an error cancellation unit that detects a sub-block having many errors based on the reliability information, and performs EXOR operation of a codeword in a column direction including the detected sub-block and a codeword in a row direction including the detected sub-block, and performs decoding using a result of the EXOR operation. | 2015-10-29 |
20150311922 | System and Method for a Radio Frequency Integrated Circuit - In accordance with an embodiment, a radio frequency integrated circuit (RFIC) includes an adjustable capacitance coupled to an input terminal of the RFIC, and a first single-pole multiple-throw (SPMT) radio frequency (RF) switch having an input coupled to the adjustable capacitance and a plurality of output nodes coupled to a corresponding plurality of second output terminals of the RFIC. | 2015-10-29 |
20150311923 | TECHNIQUES FOR DIFFERENTIATING BETWEEN SIGNALS OF DIFFERENT RADIO ACCESS TECHNOLOGIES - Systems and methods for differentiating between LTE and Wi-Fi signals based on distinguishing characteristics thereof are disclosed. A radio or receiver configured for processing signals associated with a first RAT can detect a signal associated with a second RAT, wherein the signals associated with the first RAT and the signal associated with the second RAT are received over a communications medium using an unlicensed frequency spectrum. One or more characteristics of the decoded signal can be detected or identified, such as a pilot or reference signal pattern, an interframe spacing, a cyclic prefix or guard interval structure, a bandwidth utilization, etc. The decoded signal can be determined as relating to the second RAT based at least in part on determining that the one or more characteristics correspond to the second RAT. | 2015-10-29 |
20150311924 | TELECONTROL FOR AUTOMOBILE COMPRISING A DEVICE FOR SUPPRESSING MAGNETIC COUPLING - The invention relates to a telecontrol (TEL) tier the locking/unlocking and the starting of a motor vehicle comprising:—an electronic circuit (ELEC) comprising at least one pathway comprising an input pin (BE) and an output pin (BS),—a first radiofrequency antenna (ANT | 2015-10-29 |
20150311925 | Wireless Communication Device and Sensing Method - A wireless communication device which includes: a sensing antenna for sensing communication by a primary user; a first transmission antenna; a second transmission antenna; first transmitting unit that generates a transmission signal to be transmitted from the first transmission antenna; second transmitting unit that generates a transmission signal to be transmitted from the second transmission antenna and that cancels, in the sensing antenna, a transmission signal from the first transmission antenna; digital signal processing unit that suppresses the transmission signal from the first transmission antenna, from a received signal of the sensing antenna; and sensing unit that detects communication by a primary user on the basis of the received signal of the sensing antenna that has been processed by the digital signal processing unit. While performing communication as a secondary user, the device detects communication by a primary user. Hence, constant sensing is enabled in a cognitive radio communication device. | 2015-10-29 |
20150311926 | Acquisition of Nonlinearity in Electronic Communication Devices - Circuitry of an electronic transmitter may determine characteristics of nonlinear distortion introduced by the electronic transmitter during transmission of electronic signals onto a communication medium, and transmit a training signal, from which the characteristics of the nonlinear distortion can be recovered, prior to transmitting data onto the communication medium. The circuitry may transmit the training signal as part of a preamble of each burst of data transmitted by the circuitry of the electronic transmitter. The circuitry may transmit the training signal as part of a handshaking protocol used for admission of the electronic transmitter to a network. The circuitry may transmit the training signal in response to a request from receiver. The characteristics of the nonlinear distortion comprise an indication of a type of nonlinear distortion model suited for replicating the nonlinear distortion introduced by the electronic transmitter. | 2015-10-29 |
20150311927 | MULTICARRIER SUCCESSIVE PREDISTORTION FOR DIGITAL TRANSMISSION - An approach for improved compensation for nonlinear distortion in multicarrier satellite systems is provided. Source reflecting encoded and modulated sequences of source data symbols are received. Each source signal is predistorted, and a transmit filter is applied to each predistorted source signal. Each filtered signal is translated to a carrier frequency, and the translated signals are combined into a composite signal for transmission via a multicarrier transponder. The final predistorted version of each source signal is generated via an iterative process of a number of stages, wherein, for a given stage and for each source signal, the process comprises: receiving a prior predistorted version of each source signal from a preceding stage; processing each prior predistorted source signal based on all of the received prior predistorted source signals, wherein the processing is performed based on a characterization of one or more characteristics of the multicarrier satellite transponder. | 2015-10-29 |
20150311928 | ADAPTIVE RADIO-FREQUENCY INTERFERENCE CANCELLING DEVICE, METHOD, AND RECEIVER - The present invention provides an adaptive radio-interference cancelling device and method, a receiver, and a wireless full duplex communication system. The device includes an amplitude phase adjusting module, configured to adjust an amplitude and a phase of a radio-frequency reference signal and output a radio-frequency adjustment signal to enable the radio-frequency adjustment signal to converge to a self-interference signal in a radio-frequency received signal; a subtractor, configured to output a radio-frequency residual signal, where the radio-frequency residual signal is a difference signal between the radio-frequency received signal and the radio-frequency adjustment signal; and a baseband extracting and filtering module, configured to receive the radio-frequency reference signal and the radio-frequency residual signal output by the subtractor, extract baseband signals and perform least mean squares adaptive filtering processing on the baseband signals to obtain an amplitude phase control signal and output to the amplitude phase adjusting module. | 2015-10-29 |
20150311929 | INTERFERENCE CANCELLATION USING INTERFERENCE MAGNITUDE AND PHASE COMPONENTS - A communication device can independently determine an interference magnitude component and an interference phase component for interference cancellation. The interference magnitude component may be estimated based, at least in part, on a magnitude polynomial expansion and a transmit signal of the communication device. The interference phase component may be estimated based, at least in part, on a phase polynomial expansion and the transmit signal. The magnitude polynomial expansion and the phase polynomial expansion may have different polynomial terms. The interference signal may be determined based, at least in part, on the interference magnitude component and the interference phase component. At least a portion of the interference signal may be cancelled from a receive signal received by the communication device. | 2015-10-29 |
20150311930 | ANTENNA SYSTEM CALIBRATION - A method for calibrating an antenna system ( | 2015-10-29 |