44th week of 2015 patent applcation highlights part 61 |
Patent application number | Title | Published |
20150311231 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY APPARATUS - An array substrate, a method for manufacturing the same and a display apparatus are provided. The array substrate comprises: a substrate ( | 2015-10-29 |
20150311232 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - The invention discloses an array substrate and a manufacturing method thereof and a display device, which can solve the problems such as complicated, high cost, time-consuming process in the prior art, and increase the storage capacitance. In the array substrate, data lines and a common electrode line are provided in the same layer on the base substrate and below an active layer, the data lines and the common electrode line are provided separately, the common electrode is provided with a connection part which partly overlaps with the common electrode line in an orthographic projection direction, and the common electrode is electrically connected to the common electrode line through a first via between the connection part and the common electrode line. | 2015-10-29 |
20150311233 | TFT ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - The embodiments of the present disclosure relate to a TFT array substrate and method for manufacturing the same, including: forming a gate electrode on a transparent substrate, and forming a first insulating layer on the gate electrode covering the gate electrode and transparent substrate; forming a patterned IGZO layer on the first insulating layer; processing the IGZO layer to form source region and drain region; forming a second insulating layer on the IGZO layer; and forming contacting holes communicating with the source region and the drain region in the second insulating layer, and depositing electrodes in the contacting holes. The present disclosure need not form the second metal layer so as to omit photolithography and etching processes for forming the second metal layer, which may shorten the manufacturing process, improve the efficiency, and reduce dimension of the TFT. | 2015-10-29 |
20150311234 | THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc. | 2015-10-29 |
20150311235 | DISPLAY DEVICE - A display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area is necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and whose end portions are over the first oxide semiconductor layer and overlap with the gate electrode. The gate electrode of the non-linear element is connected to a scan line or a signal line, the first wiring layer or the second wiring layer of the non-linear element is directly connected to the gate electrode layer so as to apply potential of the gate electrode. | 2015-10-29 |
20150311236 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF - A thin film transistor array substrate is discussed. The thin film transistor array substrate includes, according to one embodiment, gate and data lines crossing each other, a gate insulation film, a gate electrode, an active layer, an etch stop layer formed on the active layer to define a channel region of the active layer, and a source electrode and a drain electrode formed on the active layer. The etch stop layer is between the source and drain electrodes spaced apart from the etch stop layer. The source electrode and the drain electrode include a first electrode layer and a second electrode layer disposed on the first electrode. The first electrode layer is formed from a dry-etchable material and the second electrode layer is formed from a wet-etchable material. | 2015-10-29 |
20150311237 | REWORK METHOD OF ARRAY SUBSTRATE FOR DISPLAY DEVICE AND ARRAY SUBSTRATE FORMED BY THE METHOD - The present invention provides a method of reworking an array substrate including a gate metal layer, a gate insulation layer (G | 2015-10-29 |
20150311238 | IMAGE SENSORS INCLUDING DEPOSITED NEGATIVE FIXED CHARGE LAYERS ON PHOTOELECTRIC CONVERSION REGIONS AND METHODS OF FORMING THE SAME - A method of forming an image sensor can be provided by forming a respective photoelectric conversion region in each of a plurality of unit pixel regions of a substrate and depositing a material configured to provide a negative fixed charge layer on the photoelectric conversion region. | 2015-10-29 |
20150311239 | CMOS IMAGE SENSOR INCLUDING INFRARED PIXELS HAVING IMPROVED SPECTRAL PROPERTIES, AND METHOD OF MANUFACTURING SAME - The present invention relates to a CMOS image sensor including an infrared pixel with enhanced spectral characteristics in which a stepped portion is formed between color filters of RGB pixels and a filter of an infrared pixel, and a manufacturing method thereof. A stepped portion is formed between color filters and an infrared filter according to respective pixels and the thicknesses of the filters are arbitrarily adjusted regardless of the characteristics of material in the formation of the color filters and the infrared filter, so that crosstalk characteristics are improved. | 2015-10-29 |
20150311240 | DEEP WELL PHOTODIODE FOR NIR IMAGE SENSOR - An active pixel image sensor includes a photodiode structure which enables high near-infrared modulation transfer function and high quantum efficiency, with low pinning voltage for a medium- to large-size pixel. The photodiode includes a shallow photodiode region and a deep photodiode region both of a first dopant type, where the length of the shallow photodiode region is larger than the length of the deep photodiode region; and a shallow depleting region and a deep depleting region both of a second dopant type. The deep depleting region surrounds the deep photodiode region on at least two opposite sides. | 2015-10-29 |
20150311241 | STACK TYPE IMAGE SENSOR - A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench. | 2015-10-29 |
20150311242 | IMAGE SENSOR WITH DUAL LAYER PHOTODIODE STRUCTURE - An image system with a dual layer photodiode structure is provided for processing color images. In particular, the image system can include an image sensor that can include photodiodes with a dual layer photodiode structure. In some embodiments, the dual layer photodiode can include a first layer of photodiodes (e.g., a bottom layer), an insulation layer disposed on the first layer of photodiodes, and a second layer of photodiodes (e.g., a top layer) disposed on the insulation layer. The first layer of photodiodes can include one or more suitable pixels (e.g., green, blue, clear, luminance, and/or infrared pixels). Likewise, the second layer of photodiodes can include one or more suitable pixels (e.g., green, red, clear, luminance, and/or infrared pixels). An image sensor incorporating dual layer photodiodes can gain light sensitivity with additional clear pixels and maintain luminance information with green pixels. | 2015-10-29 |
20150311243 | PIXEL ARRAY OF AN IMAGE SENSOR AND IMAGE SENSOR - A pixel array of an image sensor includes a substrate, a chromatic pixel including a first photodiode formed in the substrate and a color filter formed over the first photodiode, and an achromatic pixel including a second photodiode formed in the substrate, the second photodiode having a nano pillar pattern at a surface region of the substrate. | 2015-10-29 |
20150311244 | NEAR-INFRARED-ABSORBING COMPOSITION, NEAR-INFRARED CUT-OFF FILTER USING SAME, CAMERA MODULE, AND MANUFACTURING METHOD THEREFOR - A near-infrared-absorbing composition includes a copper compound and a compound having a partial structure represented by Formula (1) described below and the content of the copper compound is in a range of 3×10 | 2015-10-29 |
20150311245 | IMAGING DEVICE - An image-capturing device which is capable of capturing high quality images and can be formed at a low cost is provided. The image-capturing device includes a first circuit including a first transistor and a second transistor, and a second circuit including a third transistor and a photodiode. The first transistor is provided on a first surface of a silicon substrate. The second transistor is provided over the first transistor. The photodiode is provided to the silicon substrate. The silicon substrate includes a second insulating layer surrounding a side surface of the photodiode. The first transistor is a p-channel transistor including an active region in the silicon substrate. The third transistor is an n-channel transistor including an oxide semiconductor layer as an active layer. A light-receiving surface of the photodiode is a surface of the silicon substrate opposite to the first surface. | 2015-10-29 |
20150311246 | MICROBOLOMETER CONTACT SYSTEMS AND METHODS - Systems and methods are directed to contacts for an infrared detector. For example, an infrared imaging device includes a substrate having a first metal layer and an infrared detector array coupled to the substrate via a plurality of contacts. Each contact includes for an embodiment a second metal layer formed on the first metal layer; a third metal layer formed on the second metal layer, wherein the third metal layer at least partially fills an inner portion of the contact; and a first passivation layer formed on the third metal layer. | 2015-10-29 |
20150311247 | METHOD AND APPARATUS FOR FORMING BACK SIDE ILLUMINATED IMAGE SENSORS WITH EMBEDDED COLOR FILTERS - A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. The radiation-sensing regions are separated by a plurality of gaps. A plurality of radiation-blocking structures is disposed over the second side of the substrate. Each of the radiation-blocking structures is aligned with a respective one of the gaps. A plurality of color filters are disposed in between the radiation-blocking structures. | 2015-10-29 |
20150311248 | BACK SIDE ILLUMINATED IMAGE SENSOR WITH DEEP TRENCH ISOLATION STRUCTURES AND SELF-ALIGNED COLOR FILTERS - A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. A plurality of isolation structures are each disposed between two respective radiation-sensing regions. The isolation structures protrude out of the second side of the substrate. | 2015-10-29 |
20150311249 | CHIP-SCALE PACKAGED LED DEVICE - An LED device includes a substrate, a number (N) of flip-chip LED die(s), an electrical conductive structure and a lens structure. The substrate has upper and lower surfaces and is formed with multiple through holes. A ratio of LED die(s) surface area to an area of the upper surface of the substrate ranges from 22.7% to 76.2%. The electrical conductive structure includes a number (N) of upper bonding pad assembly (assemblies), a number (N+1) of lower bonding pads and a number (2N) of interconnectors. Each upper bonding pad assembly includes two upper bonding pads electrically connected to the LED die(s). The interconnectors are disposed in the through holes and interconnect the upper and lower bonding pads. The lens structure covers the LED die(s). | 2015-10-29 |
20150311250 | Light-Emitting Device, Electronic Device, and Lighting Device - A novel light-emitting device with small power consumption, which can be formed with high productivity, is provided. The light-emitting device includes a first pixel, a second pixel, and a third pixel. The first pixel includes a first light-emitting element and a first optical element, the second pixel includes a second light-emitting element and a second optical element, and the third pixel includes a third light-emitting element. A first light-emitting layer or a second light-emitting layer is shared among the first to third light-emitting elements. Furthermore, the first light-emitting layer includes a first light-emitting material having a spectrum peak in the range of higher than or equal to 540 nm and lower than or equal to 580 nm, and the second light-emitting layer includes a second light-emitting material having a spectrum peak in the range of higher than or equal to 420 nm and lower than or equal to 480 nm. | 2015-10-29 |
20150311251 | INTEGRATED CIRCUITS WITH SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY AND METHODS FOR FABRICATING THE SAME - A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack. | 2015-10-29 |
20150311252 | MAGNETIC RANDOM ACCESS MEMORY WITH ULTRATHIN REFERENCE LAYER - The present invention is directed to an MRAM device comprising a plurality of MTJ memory elements. Each of the memory elements includes a magnetic free layer and a first magnetic reference layer with an insulating tunnel junction layer interposed therebetween; a second magnetic reference layer formed adjacent to the first magnetic reference layer opposite the insulating tunnel junction layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the first magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The magnetic free layer has a variable magnetization direction substantially perpendicular to the layer plane thereof. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof. The magnetic fixed layer has a second fixed magnetization direction that is substantially perpendicular to the layer plane thereof and is substantially opposite to the first fixed magnetization direction. | 2015-10-29 |
20150311253 | MEMORY DEVICE - Provided is a memory device, including a memory element on a substrate; a protection insulating pattern covering a side surface of the memory element and exposing a top surface of the memory element; an upper mold layer on the protection insulating pattern; and a bit line on and connected to the memory element, the bit line extending in a first direction, the protection insulating pattern including a first protection insulating pattern covering a lower side surface of the memory element; and a second protection insulating pattern covering an upper side surface of the memory element and including a different material from the first protection insulating pattern. | 2015-10-29 |
20150311254 | MEMORY CELLS HAVING A COMMON GATE TERMINAL - Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group. | 2015-10-29 |
20150311255 | VARIABLE RESISTIVE MEMORY DEVICE INCLUDING VERTICAL CHANNEL PMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a vertical channel, a variable resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device having a vertical channel includes a vertical pillar formed on a semiconductor substrate and including an inner portion and an outer portion surrounding the inner portion, junction regions formed in the outer portion of the vertical pillar, and a gate formed to surround the vertical pillar. The inner portion of the vertical pillar has a lattice constant smaller than that of the outer portion of the vertical pillar. | 2015-10-29 |
20150311256 | Vertical Bit Line Wide Band Gap TFT Decoder - A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a body formed from a wide energy band gap semiconductor is disclosed. The wide energy band gap semiconductor may be an oxide semiconductor, such as a metal oxide semiconductor. As examples, this could be an InGaZnO, InZnO, HfInZnO, or ZnInSnO body. The source and drains can also be formed from the wide energy band gap semiconductor, although these may be doped for better conduction. The vertically oriented TFT selection device serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device has a high drive current, a high breakdown voltage and low leakage current. | 2015-10-29 |
20150311257 | Resistive Random Access Memory Cells Having Shared Electrodes with Transistor Devices - Provided are resistive random access memory (ReRAM) cells having extended conductive layers operable as electrodes of other devices, and methods of fabricating such cells and other devices. A conductive layer of a ReRAM cell extends beyond the cell boundary defined by the variable resistance layer. The extended portion may be used a source or drain region of a FET that may control an electrical current through the cell or other devices. The extended conductive layer may be also operable as electrode of another resistive-switching cell or a different device. The extended conductive layer may be formed from doped silicon. The variable resistance layer of the ReRAM cell may be positioned on the same level as a gate dielectric layer of the FET. The variable resistance layer and the gate dielectric layer may have the same thickness and share common materials, though they may be differently doped. | 2015-10-29 |
20150311258 | IMAGE SENSORS AND ELECTRONIC DEVICES INCLUDING THE SAME - Image sensors, and electronic devices including the same, include a first photo-sensing device sensing light in a full visible to near infrared ray region, a second photo-sensing device sensing light in a blue wavelength region, a third photo-sensing device sensing light in a red wavelength region, and a fourth photo-sensing device sensing light in a green wavelength region. At least one of the first photo-sensing device, the second photo-sensing device, the third photo-sensing device, and the fourth photo-sensing device includes a pair of light-transmitting electrodes facing each other, and a photoactive layer between the light-transmitting electrodes. The photoactive layer includes an organic light-absorbing material. | 2015-10-29 |
20150311259 | SOLID-STATE IMAGE SENSING DEVICE AND SOLID-STATE IMAGE PICKUP UNIT INCLUDING SAME - Image sensors, image pickup devices, and electronic apparatuses are provided. These can include an image sensor or image pickup device that includes a first insulating layer over a semiconductor substrate. A depression section is formed in the first insulating layer. An organic photoelectric conversion section fills the depression section. One or more inorganic photoelectric conversion sections can also be provided, with the organic photoelectric conversion section overlapping the inorganic photoelectric conversion sections. Alternatively or in addition, the depression section can taper from a side adjacent a light receiving side of the image sensor to a side adjacent the at least a first inorganic photoelectric conversion section. | 2015-10-29 |
20150311260 | INPUT AND OUTPUT DEVICE - A flexible input and output device in which defects due to a crack is reduced. The input and output device includes a first flexible substrate, a second flexible substrate, a first buffer layer, a first crack inhibiting layer, an input device, and a light-emitting element. A first surface of the first flexible substrate faces a second surface of the second flexible substrate. The first buffer layer, the first crack inhibiting layer, and the input device are provided on the first surface side of the first flexible substrate. The first buffer layer includes a region overlapping with the first crack inhibiting layer. The first buffer layer is between the first crack inhibiting layer and the first surface. The input device includes a transistor and a sensor element. The light-emitting element is provided on the second surface side of the second flexible substrate. | 2015-10-29 |
20150311261 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a plurality of pixels defined on a substrate. Each of the plurality of pixels has a plurality of sub-pixels, and each of the plurality of sub-pixels has a light emitting area and a driving area. Widths in a first direction of the driving areas of the plurality of sub-pixels are identical to each other. A size of a light emitting area of a first sub-pixel of the plurality of sub-pixels is greater than a size of a light emitting area of a second sub-pixel of the plurality of sub-pixels. | 2015-10-29 |
20150311262 | ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL - An organic light-emitting diode (OLED) display panel is provided. The OLED display panel includes a pixel. The pixel includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first light emitting unit and a second light emitting unit. The first light emitting unit is used for emitting a first color light. The second light emitting unit is used for emitting a second color light. The second sub-pixel includes a third light emitting unit and a fourth light emitting unit. The third light emitting unit is used for emitting a third color light. The fourth light emitting unit is used for emitting a fourth color light. The combination of the first color light and the second color light is different from the combination of the third color light and the fourth color light. | 2015-10-29 |
20150311263 | PIXEL STRUCTURE AND ELECTROLUMINESCENT DISPLAY HAVING THE SAME - A pixel structure and an electroluminescent display having the same are disclosed. The pixel structure comprises a first pixel and a second pixel. The first pixel and the second pixel each comprise a first sub-pixel, a second sub-pixel and a third sub-pixel. The first sub-pixel of the first pixel is adjacent to the first sub-pixel of the second pixel, the second sub-pixel of the first pixel is adjacent to the second sub-pixel of the second pixel, and the third sub-pixel of the first pixel is adjacent to the third sub-pixel of the second pixel. The first sub-pixel of the first pixel is adjacent to the first sub-pixel of the second pixel in a first direction, and the second sub-pixel of the first pixel is adjacent to the second sub-pixel of the second pixel in a second direction that is not parallel to the first direction. | 2015-10-29 |
20150311264 | DISPLAY PANEL AND PIXEL ARRAY THEREOF - A pixel array includes a plurality of pixel groups, each of which includes a plurality of brightness sub-pixel regions, a plurality of first sub-pixel regions, and a plurality of second sub-pixel regions. Each brightness sub-pixel regions has a first side, a second side, a third side, and a fourth side. The first sub-pixel regions include a first group and a second group, and the second sub-pixel regions include a third group and a fourth group. The first, the second, the third, and the fourth groups are respectively disposed at the first, the third, the second, and the fourth sides of the first brightness sub-pixel region. Extension lines of long directions of the first, the second, the third, and the fourth groups respectively interlace a vertical baseline at a first angle θ1, a second angle θ2, a third angle θ3, and a fourth angle θ4. 0°<θ1<90°, 0°<θ2<90°, 0°<θ3<90°, and 0°<θ4<90°. | 2015-10-29 |
20150311265 | PIXEL ARRAY, ELECTRO-OPTIC DEVICE, AND ELECTRIC APPARATUS - There are provided a pixel array, an electro-optic device, and an electric apparatus. A pixel array includes plural pixels each having a rectangular shape and including a first-colored sub-pixel of a first color being the maximum in relative luminosity, a second-colored sub-pixel, and a third-colored sub-pixel of a third color being the minimum in relative luminosity. The third-colored sub-pixel is greater in size than each of the first-colored sub-pixel and the second-colored sub-pixel, and is arranged next to the first-colored sub-pixel and the second-colored sub-pixel. The center of gravity of the first-colored sub-pixel is located nearer to the center of gravity of the pixel than that of the second-colored sub-pixels, and/or the center of gravity of a part of the third-colored sub-pixel at the second-colored-sub-pixel side is located at a shorter distance to the center of gravity of the pixel than that of the other part of the third-colored sub-pixel. | 2015-10-29 |
20150311266 | Display Device and Method for Manufacturing Display Device - The thickness of a display device including a touch sensor is reduced. Alternatively, the thickness of a display device having high display quality is reduced. Alternatively, a method for manufacturing a display device with high mass productivity is provided. Alternatively, a display device having high reliability is provided. Stacked substrates in each of which a sufficiently thin substrate and a relatively thick support substrate are stacked are used as substrates. One surface of the thin substrate of one of the stacked substrates is provided with a layer including a touch sensor, and one surface of the thin substrate of the other stacked substrate is provided with a layer including a display element. After the two stacked substrates are attached to each other so that the touch sensor and the display element face each other, the support substrate and the thin substrate of each stacked substrate are separated from each other. | 2015-10-29 |
20150311267 | PIXEL STRUCTURE FOR ACTIVE MATRIX DISPLAY, AND METHOD FOR MANUFACTURING SAME - The present invention relates to a pixel structure for an active matrix display and to a method for manufacturing same, and the objective thereof is to simplify processes for manufacturing pixel electrodes and pixel defining layers and address a problem caused by a terminal which is formed at an edge part of the pixel electrode through the patterning of the pixel electrode. The pixel structure according to the present invention includes: a base substrate; a plurality of pixel circuit electrodes; an insulating layer; and a composite layer. The plurality of pixel circuit electrodes is arranged in a matrix form on the base substrate. The insulating layer is formed on the base substrate to cover the outer peripheries of the plurality of pixel circuit electrodes. The composite layer is integrally formed to cover the plurality of pixel circuit electrodes and the top of the insulating layer. In this case, the composite layer has: the conductive pixel electrodes that are formed to be respectively connected to the plurality of pixel circuit electrodes which are exposed from the insulating layer; and the non-conductive pixel defining layers on the outer peripheries of the pixel electrodes. | 2015-10-29 |
20150311268 | OLED PANEL - The present invention provides an OLED panel. The OLED panel includes a substrate and a plurality of walls formed on the substrate. The substrate and the walls define a plurality of containing areas. Each of the containing areas is corresponding to each of a plurality of sub-pixels. The sub-pixels are separated from each other by the walls. Each of the sub-pixels includes one of emitting materials formed in one of the containing areas. At least one of the containing areas corresponding to the sub-pixel includes a first partition. The height of the first partition is lower than the walls. | 2015-10-29 |
20150311269 | DISPLAY SUBSTRATE AND DISPLAY DEVICE APPLYING THE SAME - A display substrate and a display device applying the same are provided. The display substrate includes a base plate and a display structure. The display structure is disposed on the base plate and includes a plurality of display units arranged in an array. The display units have a core region and a peripheral region. The core region includes at least one first sub-pixel and at least one second sub-pixel. The peripheral region includes at least one third sub-pixel and is located outside the core region. | 2015-10-29 |
20150311270 | DISPLAY DEVICE, METHOD FOR DRIVING THE SAME, AND ELECTRONIC APPARATUS - A display device including a pixel array unit having a matrix of pixels each configured such that an anode electrode of an organic electroluminescent element is connected to a source electrode of a drive transistor, a gate electrode of the drive transistor is connected to a source or drain electrode of a writing transistor, and a storage capacitor is connected between the gate and source electrodes of the drive transistor, scanning lines and power supply lines for individual pixel rows, and signal lines for individual pixel columns. A video signal reference potential is supplied to the signal lines for a period during which a scanning signal is supplied to the scanning lines during driving of pixels in a preceding row. During threshold correction for the drive transistor in a current pixel, the video signal reference potential and a potential of the cathode electrode of the organic electroluminescent element are equal. | 2015-10-29 |
20150311271 | LANDSIDE EMBEDDED INDUCTOR FOR FANOUT PACKAGING - One or more high-inductance, high-quality factor (Q) three-dimensional inductors, for example, solenoid or toroid inductors with small form factors, are provided in an integrated circuit package, such as an integrated fanout package. | 2015-10-29 |
20150311272 | INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM GATE METAL AND METHODS FOR FABRICATING SAME - Integrated circuits having resistor structures formed from gate metal and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a transistor area. The method deposits a gate metal over the resistor area and the transistor area of the semiconductor substrate, and the gate metal forms a gate metal layer in the resistor area. The method includes etching the gate metal to form a resistor structure from the gate metal layer in the resistor area. Further, the method includes forming contacts to the resistor structure in the resistor area. | 2015-10-29 |
20150311273 | Film Scheme for MIM Device - The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a multi-layer capacitor dielectric layer including an amorphous dielectric layer configured to mitigate the formation of leakage paths, and a method of formation. In some embodiments, the MIM (metal-insulator-metal) capacitor has a capacitor bottom metal layer. A multi-layer capacitor dielectric layer is disposed over the capacitor bottom metal layer. The multi-layer capacitor dielectric layer has an amorphous dielectric layer abutting a high-k dielectric layer. A capacitor top metal layer is disposed over the multi-layer capacitor dielectric layer. The high-k dielectric layer within the capacitor dielectric layer provides the MIM capacitor with a high capacitance density, while the amorphous dielectric layer prevents leakage by blocking the propagation of grain boundaries between the capacitor top metal layer and the capacitor bottom metal layer. | 2015-10-29 |
20150311274 | SEMICONDUCTOR DEVICE - To effectively prevent short circuit between capacitors adjacent to each other. A semiconductor device has a substrate, an interlayer insulating film, a plurality of capacitors, and an isolation insulating film. The interlayer insulating film is located over the substrate. The capacitors are located in a plurality of recesses, respectively. The recesses each have an opening in the surface of the interlayer insulating film. The isolation insulating film lies in the interlayer insulating film. The isolation insulating films are located between recesses adjacent to each other in plan view. Further, the isolation insulating film is made of a material different from that of the interlayer insulating film. | 2015-10-29 |
20150311275 | EMBEDDED SHEET CAPACITOR - A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die. | 2015-10-29 |
20150311276 | SEMICONDUCTOR DEVICES HAVING SELF-ALIGNED CONTACT PADS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad. | 2015-10-29 |
20150311277 | PMOS TRANSISTOR WITH IMPROVED MOBILITY OF THE CARRIERS - A substrate includes an active region oriented along a crystallographic face (100) and limited by an insulating region. A MOS transistor includes a channel oriented longitudinally along a crystallographic direction of the <110> type. A basic pattern made of metal and formed in the shape of a T is electrically inactive and situated over an area of the insulating region adjacent a transverse end of the channel. A horizontal branch of the T-shaped basic pattern is oriented substantially parallel to the longitudinal direction of the channel. | 2015-10-29 |
20150311278 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device of the present invention includes a semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode being in contact with a surface of the semiconductor layer. The semiconductor layer includes a drift layer that forms the surface of the semiconductor layer and a high-resistance layer that is formed on a surface layer portion of the drift layer and that has higher resistance than the drift layer. The high-resistance layer is formed by implanting impurity ions from the surface of the semiconductor layer and then undergoing annealing treatment at less than 1500° C. | 2015-10-29 |
20150311279 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A front surface element structure is formed on the front surface side of an n | 2015-10-29 |
20150311280 | A HIGH VOLTAGE DEVICE WITH COMPOSITE STRUCTURE AND A STARTING CIRCUIT - A high voltage device with composite structure comprises a high voltage power MOS transistor HVNMOS and a JFET. The high voltage power MOS transistor HVNMOS comprises a drain, a source, a gate and a substrate, and a P-type well region Pwell as a conducting channel which is arranged between the source and the drain. The JFET comprises the drain, the source, the gate and the substrate, and an N-type well region Nwell as a conducting channel which is arranged between the source and the drain. The high voltage power MOS transistor HVNMOS and the JFET share the same drain, and the drain is processed by using N-type double diffusion process. The embodiment of the present invention further presents a starting circuit using the high voltage device with composite structure. | 2015-10-29 |
20150311281 | HIGH BREAKDOWN N-TYPE BURIED LAYER - A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer. | 2015-10-29 |
20150311282 | Super Junction Semiconductor Device Including Edge Termination - A super junction semiconductor device includes a super junction structure and a channel stopper structure. The super junction structure includes first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction. Each one of the first areas includes a first semiconductor region of a first conductivity type. Each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type. The channel stopper structure includes a doped semiconductor region electrically coupled to a field plate. The second semiconductor regions extend along the second lateral direction from the transistor cell area through the edge termination area overlap with the field plate. | 2015-10-29 |
20150311283 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Device structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates. | 2015-10-29 |
20150311284 | SPATIAL SEMICONDUCTOR STRUCTURE - A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening. | 2015-10-29 |
20150311285 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE, EVALUATION METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A fabrication method of a semiconductor device that includes trench gate structures each having a gate electrode extending in a depth-direction of an element, where first trench gate structures contribute to controlling the element and second trench gate structures do not contribute. The fabrication method includes forming the trench gate structures on a front face of a semiconductor substrate; forming on the front face, an electrode pad connected to the gate electrode of at least one trench gate structure; executing screening by applying a predetermined voltage between the electrode pad and an electrode portion having a potential other than a gate potential, to apply the predetermined voltage to gate insulator films in contact with each gate electrode connected to the electrode pad; and forming the second trench gate structures having the gate electrodes connected to the electrode pad, by short-circuiting the electrode portion to the electrode pad after executing screening. | 2015-10-29 |
20150311286 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher. | 2015-10-29 |
20150311287 | FABRICATION METHOD OF A TRANSISTOR WITH IMPROVED FIELD EFFECT - Fabrication of a field-effect transistor is performed on a substrate comprising a film made from first semiconductor material, a gate dielectric covered by a gate electrode, source and drain areas separated by the gate electrode, a protection layer covering gate electrode and source and drain areas, and an access hole to the source area and/or to drain area. Metallic material is deposited in the access hole in contact with the first semiconductor material of the source and/or drain area. An electrically conducting barrier layer that is non-reactive with the first semiconductor material and with the metallic material is deposited before reaction of metallic material with first semiconductor material. Transformation heat treatment of the metallic material with the semiconductor material is performed to form a metallic material having a base formed by the semiconductor material generating a set of stresses on a conduction channel arranged between the source and drain areas. | 2015-10-29 |
20150311288 | MULTI-GATE VDMOS TRANSISTOR - Various embodiments provide multi-gate VDMOS transistors. The transistor can include a substrate having a first surface and a second surface opposite to the first surface, a drift layer on the first surface of the substrate, and an epitaxial layer on the drift layer. The transistor can further include a plurality of trenches. Each trench can pass through the epitaxial layer and a thickness portion of the drift layer. The transistor can further include a plurality of gate structures. Each gate structure can fill the each trench. The transistor can further include a plurality of doped regions in the epitaxial layer. Each doped region can surround a sidewall of the each gate structure. The transistor can further include a source metal layer on the epitaxial layer to electrically connecting the plurality of doped regions, and a drain metal layer on the second surface of the substrate. | 2015-10-29 |
20150311289 | Tailoring the Optical Gap and Absorption Strength of Silicon Quantum Dots by Surface Modification with Conjugated Organic Moieties - The present invention relates to semiconductor materials that include a silicon-based quantum dot; and a conjugated organic ligand connected to the silicon-based quantum dot to obtain a functionalized quantum dot. An additional aspect of the present invention is to provide methods that include providing a silicon-based quantum dot; and connecting a conjugated organic ligand connected to the silicon-based quantum dot to obtain a functionalized quantum dot. | 2015-10-29 |
20150311290 | EPITAXIAL WAFER AND SWITCH ELEMENT AND LIGHT-EMITTING ELEMENT USING SAME - An epitaxial wafer comprises an epitaxial layer disposed on a substrate. The epitaxial layer comprises first to third semiconductor layers. The third semiconductor layer has a thickness that is thicker than that of the first semiconductor layer. A second doping density of the second semiconductor layer is between a first doping density of the first semiconductor layer and a third doping density of the third semiconductor layer. | 2015-10-29 |
20150311291 | SEMICONDUCTOR DEVICE - A highly reliable semiconductor device including an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first region having a crystal whose size is less than or equal to 10 nm and a second region which overlaps with the insulating layer with the first region provided therebetween and which includes a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the surface of the oxide semiconductor layer. | 2015-10-29 |
20150311292 | UTILIZATION OF ANGLED TRENCH FOR EFFECTIVE ASPECT RATIO TRAPPING OF DEFECTS IN STRAIN-RELAXED HETEROEPITAXY OF SEMICONDUCTOR FILMS - Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors. | 2015-10-29 |
20150311293 | SOURCE/DRAIN PROFILE ENGINEERING FOR ENHANCED P-MOSFET - P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film. Methods of forming the pMOSFET's include: providing a semiconductor substrate; depositing a SiGe film on the semiconductor substrate, thereby forming a lower interface of the SiGe film in contact with the semiconductor substrate, and an upper surface of the SiGe film; and doping the SiGe film with boron to form a SiGe film having a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film. | 2015-10-29 |
20150311294 | Method for Producing a Controllable Semiconductor Component Having a Plurality of Trenches - A method of producing a controllable semiconductor component includes providing a semiconductor body with a top side and a bottom side, and forming a first trench protruding from the top side into the semiconductor body and a second trench protruding from the top side into the semiconductor body. The first trench has a first width and a first depth, and the second trench has a second width greater than the first width and a second depth greater than the first depth. The method further includes forming, in a common process, an oxide layer in the first trench and in the second trench such that the oxide layer fills the first trench and electrically insulates a surface of the second trench, and removing the oxide layer from the first trench completely or at least partly such that the semiconductor body comprises an exposed first surface area arranged in the first trench. | 2015-10-29 |
20150311295 | SPLIT POLY CONNECTION VIA THROUGH-POLY-CONTACT (TPC) IN SPLIT-GATE BASED POWER MOSFETS - Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top electrode in its upper portions. The bottom electrode and the top electrode are separated by an insulating material. A contact structure filled with conductive materials is formed in each trench in an area outside of an active region of the device to connect the top electrode and the bottom electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2015-10-29 |
20150311296 | Memory Devices and Method of Forming Same - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 2015-10-29 |
20150311297 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THEREOF - Provided are a semiconductor device and a method of forming thereof. The semiconductor device includes a substrate having an isolating trench defining active areas, gate structures formed in the active area and crossing the isolating trench, a first protection layer formed on the active area of the substrate, and a second protection layer formed on the first protection layer, wherein, in a first isolating area in which the gate structure and the isolating trench cross, the first protection layer is conformally formed on an inner wall and bottom of the isolating trench, and the second protection layer is formed on the first protection layer formed on the bottom of the isolating trench. | 2015-10-29 |
20150311298 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern. | 2015-10-29 |
20150311299 | NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A non-volatile memory device and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a floating gate insulating layer and a floating gate disposed on a substrate, a dielectric layer formed perpendicular to the floating gate insulating layer and at two sides of the floating gate, and a first control gate at a first side of the dielectric layer distal from the floating gate and a second control gate at a second side of the dielectric layer distal from the floating gate, wherein the first control gate and the second control gate are connected to each other, and a second width of the second control gate is wider than a first width of the first control gate. A length of a control gate of a non-volatile memory device may be extended to effectively preventing the generation of leakage current when a control gate is off. | 2015-10-29 |
20150311300 | Uniformity Control for SI Dot Size in Flash Memory - Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a tunnel oxide is formed over a semiconductor substrate. A layer of silicon dot nucleates is formed on the tunnel oxide. The layer of silicon dots includes silicon dot nucleates having respective initial sizes which differ according to a first size distribution. An etching process is performed to reduce the initial sizes of the silicon dot nucleates so reduced-size silicon dot nucleates have respective reduced sizes which differ according to a second size distribution. The second size distribution has a smaller spread than the first size distribution. | 2015-10-29 |
20150311301 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns. | 2015-10-29 |
20150311302 | LOW INTERFACIAL DEFECT FIELD EFFECT TRANSISTOR - A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer. | 2015-10-29 |
20150311303 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 2015-10-29 |
20150311304 | INNER L-SPACER FOR REPLACEMENT GATE FLOW - An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity. | 2015-10-29 |
20150311305 | SPIN MOSFET - An MOSFET according to an embodiment includes: a source and drain electrodes each including a magnetic layer; a gate insulating film; and a gate electrode provided on the gate insulating film, a junction resistance on a source electrode side being greater than that on a drain electrode side, when the MOSFET is of n-channel type, the source and drain electrodes contain a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is greater than that between the Fermi surface and a conduction band minimum, and when the spin-transfer-torque switching MOSFET is of p-channel type, the source and drain electrodes containing a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is less than that between the Fermi surface and a conduction band minimum. | 2015-10-29 |
20150311306 | METAL-OXIDE-SEMICONDUCTOR (MOS) TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND THE MANUFACTURING METHODS THEREOF - The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor forms a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient. | 2015-10-29 |
20150311307 | HIGH-K DIELECTRICS WITH A LOW-K INTERFACE FOR SOLUTION PROCESSED DEVICES - A device, including a substrate, an electronically active component on the substrate, an interface dielectric on the semiconductor, and a relaxor dielectric on the interface dielectric. The relaxor dielectric includes a surfactant that is solid at room temperature. | 2015-10-29 |
20150311308 | ALTERNATIVE GATE DIELECTRIC FILMS FOR SILICON GERMANIUM AND GERMANIUM CHANNEL MATERIALS - Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al | 2015-10-29 |
20150311309 | Ferroelectric Devices including a Layer having Two or More Stable Configurations - Ferroelectric semiconductor devices are provided by including a ferroelectric layer in the device that is made of a material that is not ferroelectric in bulk. Such layers can be disposed at interfaces to promote ferroelectric switching in a semiconductor device. Switching of conduction in the semiconductor is effected by the polarization of a mechanically bi-stable material. This material is not ferroelectric in bulk but can be considered to be when the thickness is sufficiently reduced down to a few atomic layers. Devices including such ferroelectric layers are suitable for various applications, such as transistors and memory cells (both volatile and non-volatile). | 2015-10-29 |
20150311310 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer. | 2015-10-29 |
20150311311 | STATIC MEMORY CELL AND FORMATION METHOD THEREOF - The present disclosure provides a static memory cell and fabrication method. A first fin part is formed on a semiconductor substrate. An isolation layer is formed to cover a lower portion of sidewalls of the first fin part. A first dummy gate structure is formed across the first fin part. A dielectric layer is formed on the isolation layer. A mask layer is formed on the dielectric layer with a first opening to expose the top surface of the first dummy gate structure. The first dummy gate structure is removed through the first opening to form a first trench exposing the first fin part. A portion of the isolation layer is removed through the first opening to form a second trench exposing a portion of sidewalls of the first fin part below the top surface of the isolation layer. A first gate structure is formed by filling up the first and the second trenches. | 2015-10-29 |
20150311312 | Method of Manufacturing a High Breakdown Voltage III-Nitride Device - A method of manufacturing a semiconductor device includes forming a semiconductor body including a compound semiconductor material on a substrate, the compound semiconductor material having a channel region, forming a source region extending to the compound semiconductor material, forming a drain region extending to the compound semiconductor material and spaced apart from the source region by the channel region, and forming an insulating region buried in the semiconductor body below the channel region between the compound semiconductor material and the substrate in an active region of the semiconductor device such that the channel region is uninterrupted by the insulating region. The active region includes the source, the drain and the channel region. The insulating region is discontinuous over a length of the channel region between the source region and the drain region. | 2015-10-29 |
20150311313 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device is provided. The method includes providing a substrate; forming a well region on the substrate; forming at least one first gate structure on the well region, wherein the first gate structure includes a gate insulating layer and a first gate electrode formed on the gate insulating layer, wherein the first gate electrode is formed having a first enclosed pattern on a surface of the well region; wherein an area inside the first enclosed pattern is defined as a first region, and an area outside the first enclosed pattern is defined as a second region; performing ion implantation on the first region such that the first region has a first conductivity type, and performing ion implantation on the second region such that the second region has a second conductivity type, wherein the first conductivity type and the second conductivity type are different. | 2015-10-29 |
20150311314 | SEMICONDUCTOR DEVICES UTILIZING PARTIALLY DOPED STRESSOR FILM PORTIONS - A method includes providing a gate structure over a semiconductor substrate and forming a source/drain region associated with the gate structure by etching an opening in the semiconductor substrate, performing a first epitaxial growth process while an entirety of a sidewall of the opening is exposed to grow a first epitaxy material in the opening. The first epitaxial growth process is free of a first dopant impurity. A second epitaxial growth process is performed after first epitaxial growth process to grow a second epitaxy material on the first epitaxy material. The second epitaxy material has the first dopant impurity at a first concentration. Further, a third epitaxial growth process is performed after the second epitaxial growth process that includes introducing the first dopant impurity at a second concentration, the second concentration greater than the first concentration. | 2015-10-29 |
20150311315 | Contact Structure of Semiconductor Device - The embodiments described above provide mechanisms of forming contact structures with low resistance. A strained material stack with multiple sub-layers is used to lower the Schottky barrier height (SBH) of the conductive layers underneath the contact structures. The strained material stack includes a SiGe main layer, a graded SiG layer, a GeB layer, a Ge layer, and a SiGe top layer. The GeB layer moves the Schottky barrier to an interface between GeB and a metal germanide, which greatly reduces the Schottky barrier height (SBH). The lower SBH, the Ge in the SiGe top layer forms metal germanide and high B concentration in the GeB layer help to reduce the resistance of the conductive layers underneath the contact structures. | 2015-10-29 |
20150311316 | VARIABLE RESISTIVE MEMORY DEVICE INCLUDING VERTICAL CHANNEL PMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a vertical channel, a variable resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device having a vertical channel includes a vertical pillar formed on a semiconductor substrate and including an inner portion and an outer portion surrounding the inner portion, junction regions formed in the outer portion of the vertical pillar, and a gate formed to surround the vertical pillar. The inner portion of the vertical pillar has a lattice constant smaller than that of the outer portion of the vertical pillar. | 2015-10-29 |
20150311317 | Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode. | 2015-10-29 |
20150311318 | THIN-FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING SAME, AND ORGANIC LIGHT-EMITTING DISPLAY APPARATUS INCLUDING THIN-FILM TRANSISTOR SUBSTRATE - A thin film transistor (TFT) substrate, an organic light-emitting display apparatus including the TFT substrate, and a method of manufacturing the TFT substrate that enable simple manufacturing processes and a decrease in the interference between a capacitor and other interconnections are disclosed. The TFT substrate may include a substrate, a TFT arranged on the substrate, the TFT including an active layer, a gate electrode, a source electrode, and a drain electrode, a pixel electrode electrically connected to one of the source electrode and the drain electrode, and a capacitor including a lower capacitor electrode and an upper capacitor electrode, the lower capacitor electrode formed from the same material as the active layer and arranged on the same layer as the active layer, and the upper capacitor electrode formed from the same material as the pixel electrode. | 2015-10-29 |
20150311319 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings. | 2015-10-29 |
20150311320 | FIN FORMATION IN FIN FIELD EFFECT TRANSISTORS - A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure. | 2015-10-29 |
20150311321 | Novel Fin Structure of FinFet - A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature. | 2015-10-29 |
20150311322 | METHOD OF MANUFACTURING THIN FILM TRANSISTOR AND ORGANIC LIGHT EMITTING DIODE DISPLAY - A method of manufacturing transistor having a first and second thin film transistor by creating the second thin film transistor by forming a second gate of the second thin film transistor on a substrate, depositing an insulating layer and a semiconductor layer in order to cover the second gate. A photoresist layer is deposited above the semiconductor layer and exposed. The semiconductor layer and the insulating layer are etched, thereby forming a second active layer of the second thin film transistor and a first connection window disposed above the second gate. A second source and a second drain of the second thin film transistor is deposited above the insulating layer and the second active layer. The present method enables the manufacturing of an organic light emitting diode display. The method reduces the times of using a photomask, thereby saving the manufacture time, improving the productivity and economizing the manufacture cost. | 2015-10-29 |
20150311323 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential. | 2015-10-29 |
20150311324 | SELF-ALIGNED EMITTER-BASE-COLLECTOR BIPOLAR JUNCTION TRANSISTORS WITH A SINGLE CRYSTAL RAISED EXTRINSIC BASE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench. | 2015-10-29 |
20150311325 | IGBT STRUCTURE ON SIC FOR HIGH PERFORMANCE - An IGBT device includes an IGBT stack including a first surface and a second surface opposite the first surface, a collector contact over the first surface of the IGBT stack, a gate contact on the second surface of the IGBT stack, and an emitter contact on the second surface of the IGBT stack. The IGBT stack includes an injector region, which provides the first surface of the IGBT stack, a drift region over the injector region opposite the first surface, a pair of junction implants in the IGBT stack along the second surface of the IGBT stack, and a field termination region between the pair of junction implants in the IGBT stack along the second surface of the IGBT stack. | 2015-10-29 |
20150311326 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region. | 2015-10-29 |
20150311327 | ITC-IGBT AND MANUFACTURING METHOD THEREFOR - An ITC-IGBT and a manufacturing method therefor. The method comprises: providing a heavily doped substrate, forming a Ge | 2015-10-29 |
20150311328 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes semiconductor layers of a first conductivity-type and a second conductivity-type stacked on a silicon carbide semiconductor and having differing impurity concentrations. Trenches disposed penetrating the semiconductor layer of the second conductivity-type form a planar striped pattern; and a gate electrode is disposed therein through a gate insulation film. First and second semiconductor regions respectively of the first and the second conductivity-types have impurity concentrations exceeding that of the semiconductor layer of the second conductivity-type and are selectively disposed therein. The depth of the second semiconductor region exceeds that of the semiconductor layer of the second conductivity-type, but not that of the trenches. The second semiconductor region is arranged at given intervals along the length of the trenches. In the silicon carbide semiconductor below the trench bottoms, a third semiconductor region of the second conductivity-type and having a floating potential is disposed covering the trench bottoms. | 2015-10-29 |
20150311329 | FIELD EFFECT TRANSISTOR - Provided is a field-effect transistor (FET) that achieves compatibility between a higher current density and lower contact resistance and exhibits excellent properties, and a method for producing the FET. The FET includes: a channel layer above a substrate; an InAlN layer above the channel layer; an In | 2015-10-29 |
20150311330 | FET TRANSISTOR ON A III-V MATERIAL STRUCTURE WITH SUBSTRATE TRANSFER - A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material. | 2015-10-29 |