43rd week of 2017 patent applcation highlights part 63 |
Patent application number | Title | Published |
20170309681 | IMPLEMENTATION OF VMCO AREA SWITCHING CELL TO VBL ARCHITECTURE - Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array. | 2017-10-26 |
20170309682 | Side Bottom Contact RRAM Structure - The present disclosure relates to an integrated circuits device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect line disposed within a lower inter-level dielectric (ILD) layer and an upper metal interconnect line disposed within an upper inter-level dielectric (ILD) layer. The integrated circuit device also has a memory cell array disposed between the lower metal interconnect line and the upper metal interconnect line, including memory cells arranged in rows and columns, the memory cells respectively includes a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance. A bottom contact structure is disposed on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode. | 2017-10-26 |
20170309683 | MEMORY DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME - The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase. | 2017-10-26 |
20170309684 | PHOTOELECTRIC CONVERSION DEVICE AND IMAGING SYSTEM - The present disclosure provides a photoelectric conversion device including a semiconductor substrate including a signal output portion, an electrode, and an organic compound layer disposed between the signal output portion and the electrode and including a photoelectric conversion layer, wherein the signal output portion is in contact with the organic compound layer. | 2017-10-26 |
20170309685 | Optical Element Stack Assemblies - The present disclosure describes optical element stack assemblies that include multiple substrates stacked one over another. At least one of the substrates includes an optical element, such as a DOE, on its surface. The stack assemblies can be fabricated, for example, in wafer-level processes. | 2017-10-26 |
20170309686 | Organic Light Emitting Display Device and Method of Manufacturing the Same - An organic light emitting display device includes first and second electrodes facing each other on a substrate, a charge generation layer formed between first and second electrodes, a first light emitting unit including a first emission layer formed between the first electrode and the charge generation layer, a hole transport layer supplying holes from the first electrode to the first emission layer, and a second light emitting unit including a second emission layer formed between the second electrode and the charge generation layer, a hole transport layer supplying holes from the charge generation layer to the second emission layer, wherein a total thickness of the hole transport layer of the first light emitting unit is greater than that of the hole transport layer of the second light emitting unit. | 2017-10-26 |
20170309687 | LIGHT-EMITTING ELEMENT, DISPLAY DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE - Providing a light-emitting element emitting light in a broad emission spectrum. A combination of a first organic compound and a second organic compound forms an exciplex. The first organic compound has a function of converting triplet-excitation energy into light emission. The lowest triplet excitation level of the second organic compound is higher than or equal to the lowest triplet excitation level of the first organic compound, and the lowest triplet excitation level of the first organic compound is higher than or equal to the lowest triplet excitation level of the exciplex. Light emission from a light-emitting layer includes light emission from the first organic compound and light emission from the exciplex. | 2017-10-26 |
20170309688 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - Discussed is an organic light emitting display device including a first pixel, and a second pixel being adjacent to the first pixel, wherein each of the first pixel and the second pixel includes a plurality of subpixels, the first pixel and the second pixel share at least one subpixel of the plurality of subpixels. | 2017-10-26 |
20170309689 | DISPLAY DEVICE AND PACKAGING METHOD - A display device and a display device packing method are provided. The display device comprises a display panel having a display region and a non-display region; a cover lens disposed on a light-emitting surface of the display panel; and a buffer layer disposed between the cover lens and the display panel and in the non-display region of the display panel, wherein the buffer layer is selectively filled with a plurality of bubbles to enhance a buffering effect. | 2017-10-26 |
20170309690 | FLEXIBLE DISPLAY APPARATUS AND METHOD OF FABRICATING THE SAME - A method of forming a flexible display apparatus includes: forming a flexible substrate on a support substrate; forming a light-emitting diode on the flexible substrate; forming a first encapsulation layer on the light-emitting diode; forming a second encapsulation layer; bonding the first encapsulation layer to the second encapsulation layer using an adhesive layer between the first encapsulation layer and the second encapsulation layer; separating the support substrate from the flexible substrate and cutting the flexible substrate to form the flexible display apparatus; and forming a polarizing plate on the second encapsulation layer. | 2017-10-26 |
20170309691 | High Resolution Organic Light-Emitting Diode Devices, Displays, and Related Method - In accordance with an exemplary embodiment of the present disclosure, a method of manufacturing an organic light-emissive display can be provided. A plurality of electrodes can be provided on a substrate. A first hole conducting layer can be deposited via inkjet printing over the plurality of electrodes on the substrate. A liquid affinity property of selected surface portions of the first hole conducting layer can be altered to define emissive layer confinement regions. Each emissive layer confinement region can have a portion that respectively corresponds to each of the plurality of electrodes provided on the substrate. An organic light-emissive layer can be deposited via inkjet printing within each emissive layer confinement region. | 2017-10-26 |
20170309692 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An organic light emitting diode display device includes a substrate including a display region, wherein a plurality of pixel regions are defined in the display region; a first electrode over the substrate and in each of the plurality of pixel regions; a bank including a lower layer and an upper layer on the first electrode, the lower layer disposed on edges of the first electrode and having a first width and a first thickness, the upper layer disposed on the lower layer and having a second width smaller than the first width; an organic emitting layer on the first electrode and a portion of the lower layer; and a second electrode on the organic emitting layer and covering an entire surface of the display region. | 2017-10-26 |
20170309693 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is an organic light emitting display device including an anode, a cathode, a plurality of organic layers and a partition member. The plurality of organic layers is disposed between the anode and the cathode, where at least one layer is separated to minimize current leakage into neighboring pixels. The partition member is disposed between the neighboring pixels and configured to separate the plurality of organic layers. The least one separated layer includes a charge generation layer. Because at least one layer is separated, current leakage into neighboring pixels can be minimized. Accordingly, defects resulting from light leakage and the mixing of colors of light from neighboring pixels may be reduced and display quality is enhanced. | 2017-10-26 |
20170309694 | ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE - An organic electroluminescent display device includes a display area including a plurality of pixels, a peripheral area as an area on the outside of the display area, a circuit layer including a circuit formed in the display area and a circuit formed in the peripheral area, a planarization film formed in the display area, the planarization film covering the circuit in the display area but not covering at least a portion of the circuit in the peripheral area, and an inorganic insulating layer formed of an inorganic material, the inorganic insulating layer being formed in the peripheral area and covering the at least a portion of the circuit in the peripheral area. | 2017-10-26 |
20170309695 | AREA SENSOR AND DISPLAY APPARATUS PROVIDED WITH AN AREA SENSOR - An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the area sensor. Furthermore, a photoelectric conversion layer of a photodiode according to the present invention is made of an amorphous silicon film and an N-type semiconductor layer and a P-type semiconductor layer are made of a polycrystalline silicon film. The amorphous silicon film is formed to be thicker than the polycrystalline silicon film. As a result, the photodiode according to the present invention can receive more light. | 2017-10-26 |
20170309696 | ACTIVE-MATRIX DISPLAY DEVICE - An active-matrix display device according to the present disclosure includes a plurality of pixels. Each of the pixels includes: a drive transistor disposed on a substrate; and an organic EL element that is caused by the drive transistor to emit light and includes an AM layer disposed above the substrate and a transparent electrode layer disposed above the AM layer. The active-matrix display device further includes: a source line that supplies data to the pixels; and a power supply line that supplies electric power to the pixels. The power supply line is shared by, among the plurality of pixels, two pixels that are adjacent to each other in a second direction that crosses a first direction in which the power supply line is extended. The source line and the AM layer are disposed not to overlap each other in a plan view of the substrate. | 2017-10-26 |
20170309697 | DISPLAY MODULE - An organic display device includes a pixel driving circuit having a thin film transistor connected to a current supply line and a capacitor. A first insulation layer, with a first electrode thereon, covers a source electrode of the transistor. The first electrode is connected to the transistor through a contact hole the insulation layer. A second insulation layer including an aperture is formed on the first insulation layer and electrode layers. An organic light emitting layer, with a second electrode thereon is formed in the aperture and connected to the first electrode. The second insulation layer includes an inner wall at the aperture, said inner will having a surface of a convex plane on an edge of the recessed part of the first electrode. The convex plane is located between the organic light emitting layer and the edge of the first electrode, and the second electrode is formed over plurality of pixels. | 2017-10-26 |
20170309698 | DISPLAY TILE STRUCTURE AND TILED DISPLAY - A display tile structure includes a tile layer with opposing emitter and backplane sides. A light emitter having first and second electrodes for conducting electrical current to cause the light emitter to emit light is disposed in the tile layer. First and second electrically conductive tile micro-wires and first and second conductive tile contact pads are electrically connected to the first and second tile micro-wires, respectively. The light emitter includes a plurality of semiconductor layers and the first and second electrodes are disposed on a common side of the semiconductor layers opposite the emitter side of the tile layer. The first and second tile micro-wires and first and second tile contact pads are disposed on the backplane side of the tile layer. | 2017-10-26 |
20170309699 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - An organic light-emitting display apparatus and a manufacturing method thereof. The organic light-emitting display apparatus includes a substrate, a display unit arranged on the substrate, a dam unit arranged at a periphery of the display unit and on the substrate and an encapsulating layer to encapsulate the display unit, wherein the encapsulating layer includes an organic film covering the display unit, and an inorganic film covering the organic film and the dam unit, and wherein a hardness of the dam unit is lower than that of the inorganic film. According to this, lateral moisture-proof characteristics of the organic light-emitting display apparatus are improved. | 2017-10-26 |
20170309700 | INTEGRATED INDUCTOR FOR INTEGRATED CIRCUIT DEVICES - A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described. | 2017-10-26 |
20170309701 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR - A semiconductor device comprises a capacitor that includes a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode. The dielectric layer comprises a first high-k dielectric layer between the first electrode and the second electrode, a first silicon oxide layer between the first high-k dielectric layer and the second electrode, and a first aluminum oxide layer between the first high-k dielectric layer and the second electrode. | 2017-10-26 |
20170309702 | METHODS AND APPARATUS FOR HIGH VOLTAGE INTEGRATED CIRCUIT CAPACITORS - High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed. | 2017-10-26 |
20170309703 | METHOD FOR CREATING THE HIGH VOLTAGE COMPLEMENTARY BJT WITH LATERAL COLLECTOR ON BULK SUBSTRATE WITH RESURF EFFECT - Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs. | 2017-10-26 |
20170309704 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR | 2017-10-26 |
20170309705 | SUPER-JUNCTION SEMICONDUCTOR DEVICE - A super junction semiconductor device is provided. The super-junction semiconductor device includes a substrate, a drift layer disposed on the substrate, an insulating layer, a lightly-doped region, and a main loop-shaped field plate. The drift layer includes a plurality of n- and p-type doped regions alternately arranged in parallel to form a super-junction structure, and defines a cell region and a termination region surrounding the cell region. The lightly-doped region is formed in the drift layer and connected to a surface of the drift layer. The lightly-doped region has a first end portion closer to the cell region and a second end portion farther away from the cell region. The insulating layer disposed on the drift layer covers the termination region. The main loop-shaped field plate is disposed on the insulating layer and covers the second end portion. | 2017-10-26 |
20170309706 | Bulk Nanosheet with Dielectric Isolation - Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided. | 2017-10-26 |
20170309707 | Semiconductor Device Including a Semiconductor Sheet Interconnecting a Source Region and a Drain Region - A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D region is disposed above the first S/D region. The semiconductor sheet interconnects the first and second S/D regions and includes a plurality of turns. A method for fabricating the semiconductor device is also disclosed. | 2017-10-26 |
20170309708 | FIELD EFFECT TRANSISTOR - A field effect transistor is provided in the present invention with an active area including a source region, a drain region, and a channel region. The width of the channel region is larger than the width of the source/drain regions, and at least one of the source region and the drain region is comb-shaped. | 2017-10-26 |
20170309709 | SUBSTRATE STRUCTURE WITH EMBEDDED LAYER FOR POST-PROCESSING SILICON HANDLE ELIMINATION - The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure includes a silicon handle layer, a first silicon oxide layer over the silicon handle layer, a buried dielectric layer over the first silicon oxide layer, where the buried dielectric layer is not formed from silicon oxide, a second silicon oxide layer over the buried dielectric layer, and a silicon epitaxy layer over the second silicon oxide layer. The buried dielectric layer provides extremely selective etch stop characteristics with respect to etching chemistries for silicon and silicon oxide. | 2017-10-26 |
20170309710 | INTEGRATED GRAPHITE-BASED STRUCTURE - A structure is provided that comprises a substrate, a plurality of elements, and a plurality of trenches disposed on the substrate. Each element is separated from adjacent elements by a trench in the plurality of trenches and has a top surface with a first and an opposing second side. A first portion of the top surface is on the first side and a second portion of the top surface is on the opposing second side. The structure further comprises a plurality of first graphene layers, each of which is formed on the first portion of the top surface of an element in the plurality of elements. The structure further comprises a plurality of second graphene layers, each of which is formed on the second portion of the top surface of a corresponding element so that each element is separately overlayed by a first graphene layer and a second graphene layer. | 2017-10-26 |
20170309711 | INSULATED GATE SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0° as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0° in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same. | 2017-10-26 |
20170309712 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first semiconductor layer formed over the substrate, a second semiconductor layer formed over the first semiconductor layer, a third semiconductor layer formed over the second semiconductor layer, and a gate electrode, a source electrode, and a drain electrode that are formed over the third semiconductor layer. The first semiconductor layer includes a first nitride semiconductor. The second semiconductor includes a second nitride semiconductor. The third semiconductor layer includes a third nitride semiconductor. The concentration of oxygen included in the second semiconductor layer is less than 5.0×10 | 2017-10-26 |
20170309713 | Semiconductor Device Having Stripe-Shaped Gate Structures and Spicular or Needle-Shaped Field Electrode Structures - A semiconductor device includes a pair of stripe-shaped gate structures formed lengthwise in parallel in a first surface of a semiconductor body and extending into the semiconductor body, each stripe-shaped gate structure including a gate electrode and a gate dielectric separating the gate electrode from the semiconductor body. The semiconductor device further includes a plurality of field electrode structures formed in the semiconductor body between the pair of stripe-shaped gate structures, a body zone of a second conductivity type formed in the semiconductor body and extending between the pair of stripe-shaped gate structures, and a source zone of a first conductivity type opposite the second conductivity type formed in the body zone. Each field electrode structure includes a spicular or needle-shaped field electrode and a field dielectric adjacent the field electrode. Each spicular or needle-shaped field electrode has a diameter of at most 500 nm. | 2017-10-26 |
20170309714 | METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION - One illustrative method disclosed includes, among other things, forming an initial conductive source/drain structure that is conductively coupled to a source/drain region of a transistor device, performing a recess etching process on the initial conductive source/drain structure to thereby define a stepped conductive source/drain structure with a cavity defined therein, forming a non-conductive structure in the cavity, forming a layer of insulating material above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, forming a gate contact opening in the layer of insulating material and forming a conductive gate contact in the gate contact opening that is conductively coupled to the gate structure. | 2017-10-26 |
20170309715 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact, a separator, a plug contacting the source/drain contact and a wiring contacting the plug. The fin structure protrudes from an isolation insulating layer and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact is disposed on the first source/drain region. The separator is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact are in contact with a same face of the separator. | 2017-10-26 |
20170309716 | SEMINCONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a semiconductor substrate in which a semiconductor element is provided and a covering insulation film provided on the semiconductor substrate. The semiconductor substrate includes a first portion and a second portion which has a thickness thinner than a thickness of the first portion. A step portion is provided at a part where the first portion and the second portion adjoin to each other. A corner member is provided at a corner between a side surface of the step portion and an upper surface of the second portion. An upper surface of the corner member slopes downward from the side surface of the step portion toward the second portion. The covering insulation film extends over from the first portion to the second portion, and covers the corner member. | 2017-10-26 |
20170309717 | SEMICONDUCTOR DEVICE - The bottom surface of the trench is provided so that a center part of the bottom surface protrudes upward with respect to a peripheral part of the bottom surface in a short direction. A thickness of the gate insulating film covering the peripheral part is thicker than a thickness of the gate insulating film covering the center part. | 2017-10-26 |
20170309718 | LOADING EFFECT REDUCTION THROUGH MULTIPLE COAT-ETCH PROCESSES - First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches. | 2017-10-26 |
20170309719 | HORIZONTAL GATE ALL AROUND DEVICE NANOWIRE AIR GAP SPACER FORMATION - The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack. | 2017-10-26 |
20170309720 | Carbon Based Contact Structure for Silicon Carbide Device Technical Field - A method of forming a contact structure includes providing a silicon-carbide substrate having a highly doped silicon-carbide contact region formed in the substrate and extending to a main surface of the substrate. A carbon-based contact region is formed which is in direct contact with the highly doped silicon-carbide contact region and which extends to the main surface. A conductor is formed on the carbon-based contact region such that the carbon-based contact region is interposed between the conductor and the highly doped silicon-carbide contact region. A thermal budget for forming the carbon-based contact region is maintained below a level that induces metal silicidization of the highly doped silicon-carbide contact region. | 2017-10-26 |
20170309721 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a cause of a variation in electric characteristics of a transistor including an oxide semiconductor, the concentration of hydrogen in the oxide semiconductor, the density of oxygen vacancies in the oxide semiconductor, or the like can be given. A source electrode and a drain electrode are formed using a conductive material which is easily bonded to oxygen. A channel formation region is formed using an oxide layer formed by a sputtering method or the like under an atmosphere containing oxygen. Thus, the concentration of hydrogen in a stack, in particular, the concentration of hydrogen in a channel formation region can be reduced. | 2017-10-26 |
20170309722 | SEMICONDUCTOR DEVICE HAVING METAL GATE STRUCTURE - A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer. | 2017-10-26 |
20170309723 | STRUCTURES AND METHODS FOR EQUIVALENT OXIDE THICKNESS SCALING ON SILICON GERMANIUM CHANNEL OR III-V CHANNEL OF SEMICONDUCTOR DEVICE - A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor. | 2017-10-26 |
20170309724 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE TO PREVENT DEFECTS - A method of manufacturing a semiconductor device includes forming dummy gate structures including a dummy gate insulating layer and dummy gate electrodes, on a first region of a semiconductor substrate, the first region including a patterning region, forming spacers on two side walls of each of the dummy gate structures, forming an interlayer insulating layer on the semiconductor substrate and the dummy gate structures, forming a protective insulating layer on a second region of the semiconductor substrate, the second region including a non-patterning region, forming a liner layer on the protective insulating layer, planarizing the interlayer insulating layer by using the liner layer as an etching mask to expose top surfaces of the dummy gate structures, forming openings by removing the dummy gate structures to expose the semiconductor substrate between the spacers, and forming gate structures including a gate insulating layer and metal gate electrodes, in the openings. | 2017-10-26 |
20170309725 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and methods of formation are provided. The semiconductor device includes a gate over a channel portion of a fin. The fin includes a first active area of the fin having a first active area top surface coplanar with a first shallow trench isolation (STI) top surface of a first STI portion of STI, and a second active area of the fin having a second active area top surface coplanar with a second STI top surface of a second STI portion of the STI. The method herein negates a need to recess at least one of the fin, the first STI portion or the second STI portion during device formation. Negating a need to recess at least one of the fin, the first STI portion or the second STI portion enhances the semiconductor device formation and is more efficient than a semiconductor device formation that requires the recessing of at least one of a fin, a first STI portion or a second STI portion. | 2017-10-26 |
20170309726 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device includes a substrate, a source/drain region, an etch stop layer, an oxide layer, an interlayer dielectric layer, and a contact plug. The source/drain region is in the substrate. The etch stop layer is over the source/drain region. The oxide layer is over the etch stop layer. The interlayer dielectric layer is over the oxide layer. The contact plug is electrically connected to the source/drain region through the interlayer dielectric layer, the oxide layer, and the etch stop layer. | 2017-10-26 |
20170309727 | MANUFACTURING METHOD OF PATTERNED STRUCTURE OF SEMICONDUCTOR - A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus. | 2017-10-26 |
20170309728 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a process of implanting ions of an n-type impurity for threshold control into a semiconductor substrate surrounded by an element isolation portion, a resist pattern is formed such that the resist pattern covers a divot formed at a boundary portion of the element isolation portion with an SOI layer. Thus, since ions of the n-type impurity are not implanted into the divot, an etching rate of the divot in a cleaning process or the like is not accelerated, and etching can be suppressed. As a result, a BOX layer is prevented from becoming thin, so that degradation of a TDDB characteristic of the BOX layer can be prevented. | 2017-10-26 |
20170309729 | GATE PLANARITY FOR FINFET USING DUMMY POLISH STOP - A method for forming a semiconductor device includes depositing a dielectric layer over fins formed in a semiconductor substrate. The dielectric layer includes a screen layer over tops of the fins. An etch stop feature is formed on the screen layer. The etch stop feature is patterned down to the screen layer in regions across the device. A dummy gate material formed over the fins is planarized down to the etch stop feature, a dielectric fill between gate structures patterned from the dummy gate material is planarized down to the etch stop feature and a gate conductor is planarized to the etch stop feature. | 2017-10-26 |
20170309730 | Apparatus and Method for FinFETs - A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region. | 2017-10-26 |
20170309731 | SEPARATION METHOD AND MANUFACTURING METHOD OF FLEXIBLE DEVICE - A low-cost separation method with high mass productivity is provided. A first layer with a thickness of 0.1 μm or more and 3 μm or less can be formed by using a photosensitive and thermosetting material over the formation substrate, a resin layer comprising an opening is formed by forming an opening in the first layer by using a photolithography method, a silicon layer or an oxide layer is formed so as to overlap with the opening of the resin layer, a transistor including a metal oxide is formed over the resin layer, a conductive layer formed in the same manufacturing steps as the source or drain of the transistor is formed over the silicon layer or the oxide layer, the resin layer and one of the silicon layer and the oxide layer are irradiated with the laser light, and the transistor and the conductive layer are separated from the formation substrate. | 2017-10-26 |
20170309732 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device having favorable reliability. A manufacturing method of a semiconductor device comprising the steps of: forming a first oxide semiconductor having an island shape; forming a first conductor and a second conductor over the first oxide semiconductor; forming an oxide semiconductor film over the first oxide semiconductor, the first conductor, and the second conductor; forming a first insulating film over the oxide semiconductor film; forming a conductive film over the first insulating film; removing part of the first insulating film and part of the conductive film to form a first insulator and a third conductor; forming a second insulating film covering the first insulator and the third conductor; removing part of the oxide semiconductor film and part of the second insulating film to form a second oxide semiconductor and a second insulator and to expose a side surface of the first oxide semiconductor; forming a third insulator in contact with the side surface of the first oxide semiconductor and with a side surface of the second oxide semiconductor; forming a fourth insulator in contact with the third insulator; and performing a microwave-excited plasma treatment to the third insulator and the fourth insulator. | 2017-10-26 |
20170309733 | METHODS AND DEVICES FOR FABRICATING AND ASSEMBLING PRINTABLE SEMICONDUCTOR ELEMENTS - The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations. | 2017-10-26 |
20170309734 | EXTREME HIGH MOBILITY CMOS LOGIC - A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate. | 2017-10-26 |
20170309735 | TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS - Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material. | 2017-10-26 |
20170309736 | GAN-BASED POWER ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted. | 2017-10-26 |
20170309737 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate, a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer, a gate trench formed in the second semiconductor layer or in the second and first semiconductor layers, a gate electrode formed at the gate trench, and a source electrode and a drain electrode formed on the second semiconductor layer. The gate trench has terminal parts of a bottom of the gate trench formed shallower than a center part of the bottom. A part of a sidewall of the gate trench is formed of a surface including an a-plane. The center part of the bottom is a c-plane. The terminal parts of the bottom form a slope from the c-plane to the a-plane. | 2017-10-26 |
20170309738 | VERTICALLY STRUCTURED POWER TRANSISTOR WITH TRENCH SUPPLY ELECTRODE - The invention relates to a vertically structured power transistor, such as a VD-MOS or an IGBT, having a cell comprising: two symmetrical source layers ( | 2017-10-26 |
20170309739 | Semiconductor Device Having First and Second Circuits Integrated in a Semiconductor Body - A semiconductor device includes at least one wiring layer disposed on a semiconductor body, a field effect transistor integrated in the semiconductor body, the field effect transistor having a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body, a first circuit integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit integrated in the semiconductor body and remote from the first circuit. The semiconductor device further includes a first additional trench formed in the semiconductor body and at least one conductive pad formed in the at least one wiring layer. The first additional trench includes at least one connecting line which electrically connects the first circuit and the second circuit. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line. | 2017-10-26 |
20170309740 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate; a fourth step of forming a fifth insulating film and a sixth insulating film; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film, depositing metal, and performing etch back to form a gate electrode and a gate line; a seventh step of forming a seventh insulating film; and an eighth step of forming insulating film sidewalls, forming a first epitaxially grown layer on the fin-shaped semiconductor layer, and forming a second epitaxially grown layer on the pillar-shaped semiconductor layer. | 2017-10-26 |
20170309741 | ILLUMINATION APPARATUS - A point light source is converted into a plane light source having a satisfactory uniformity. The point light source is converted into a line light source by means of a linear light guiding plate, and further into the plane light source by means of a plane-like light guiding plate. Light from the point light source is reflected at a lamp reflector to be incident on at least two side surfaces of the plane-like light guiding plate. | 2017-10-26 |
20170309742 | Lateral MOSFET with Dielectric Isolation Trench - A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region. | 2017-10-26 |
20170309743 | TRENCH DMOS TRANSISTOR WITH REDUCED GATE-TO-DRAIN CAPACITANCE - A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance. | 2017-10-26 |
20170309744 | P-CHANNEL DEMOS DEVICE - A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+source and a second pwell is on an opposite side of the nwell finger including a p+drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary. | 2017-10-26 |
20170309745 | HIGH VOLTAGE DEVICE WITH LOW RDSON - High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region. | 2017-10-26 |
20170309746 | SEMICONDUCTOR PACKAGING STRUCTURE AND SEMICONDUCTOR POWER DEVICE THEREOF - A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin. | 2017-10-26 |
20170309747 | SYSTEM AND METHOD FOR THRESHOLD LOGIC WITH ELECTROSTATICALLY FORMED NANOWIRE TRANSISTORS - An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates. | 2017-10-26 |
20170309748 | METHOD FOR IMPROVING TRANSISTOR PERFORMANCE - A method to improve transistor performance uses a wafer ( | 2017-10-26 |
20170309749 | CRYSTALLIZATION METHOD FOR OXIDE SEMICONDUCTOR LAYER, SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is discussed. The method includes forming a gate electrode on a substrate, forming a gate insulating film over the substrate, depositing an In—Ga—Zn oxide over the gate insulating film while heating the substrate to a temperature of 200 to 300° C., an atomic percent ratio of Zn in the In—Ga—Zn oxide as-deposited being higher than that of In or Ga, heat-treating the deposited In—Ga—Zn oxide at a temperature of 200 to 350° C., thereby forming an active layer crystallized throughout an entire thickness of the active layer, and forming a source electrode and a drain electrode. | 2017-10-26 |
20170309750 | SEMICONDUCTOR DEVICE - A transistor whose channel is formed in a semiconductor having dielectric anisotropy is provided. A transistor having a small subthreshold swing value is provided. A transistor having normally-off electrical characteristics is provided. A transistor having a low leakage current in an off state is provided. A semiconductor device includes an insulator, a semiconductor, and a conductor. In the semiconductor device, the semiconductor includes a region overlapping with the conductor with the insulator positioned therebetween, and a dielectric constant of the region in a direction perpendicular to a top surface of the region is higher than a dielectric constant of the region in a direction parallel to the top surface. | 2017-10-26 |
20170309751 | SEMICONDUCTOR DEVICE - A highly reliable semiconductor device including an oxide semiconductor is provided by preventing a change in its electrical characteristics. A semiconductor device which includes a first oxide semiconductor layer which is in contact with a source electrode layer and a drain electrode layer and a second oxide semiconductor layer which serves as a main current path (channel) of a transistor is provided. The first oxide semiconductor layer serves as a buffer layer for preventing a constituent element of the source and drain electrode layers from diffusing into the channel. By providing the first oxide semiconductor layer, it is possible to prevent diffusion of the constituent element into an interface between the first oxide semiconductor layer and the second oxide semiconductor layer and into the second oxide semiconductor layer. | 2017-10-26 |
20170309752 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly reliable semiconductor device is provided. The semiconductor device includes a first barrier insulating film; a first gate electrode thereover; a first gate insulating film thereover; an oxide semiconductor film thereover; source and drain electrodes over the oxide semiconductor film; a second gate insulating film over the oxide semiconductor film; a second gate electrode over the second gate insulating film; a second barrier insulating film that covers the oxide semiconductor film, the source and the drain electrodes, and the second gate electrode, and is in contact with side surfaces of the oxide semiconductor film and the source and drain electrodes; and a third barrier insulating film thereover. The first to third barrier insulating films are less likely to transmit hydrogen, water, and oxygen than the first and second gate insulating films. The third barrier insulating film is thinner than the second barrier insulating film. The source and drain electrodes each includes a conductive oxide film in contact with the oxide semiconductor film. The conductive oxide film has more oxygen vacancies than the oxide semiconductor film. | 2017-10-26 |
20170309753 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer. | 2017-10-26 |
20170309754 | OXIDE SEMICONDUCTOR FILM AND SEMICONDUCTOR DEVICE - An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm | 2017-10-26 |
20170309755 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a semiconductor substrate including a main surface, an element separation film formed over the main surface, and a fin protruding from the element separation film and extending in the first direction in plan view. The semiconductor device further includes a control gate electrode extending in the second direction that is orthogonal to the first direction along the surface of the fin through a gate insulating film and overlaps with a first main surface of the element separation film, and a memory gate electrode extending in the second direction along the surface of the fin through an insulating film and overlaps with a second main surface of the element separation film, in which the second main surface is lower than the first main surface relative to the main surface. | 2017-10-26 |
20170309756 | SEMICONDUCTOR PACKAGE, SENSOR MODULE, AND PRODUCTION METHOD - The present disclosure relates to a semiconductor package, a sensor module, and a production method for dissipating heat generated by a chip. In a solid-state image sensing element package, an image sensing element chip is bonded and fixed to a heat dissipation plate with a die bond material, the heat dissipation plate having positioning holes and mounting holes for accurately mounting on a lens barrel unit. A circuit board is bonded to a bottom surface of the heat dissipation plate with circuit board adhesive resin. Bonding pads that are electrodes of the image sensing element chip are electrically connected to lead terminals that are electrodes of the circuit board by conduction wires through conduction wire connection clearance holes formed through the heat dissipation plate. The present disclosure is applicable to a CMOS solid-state image sensing apparatus used for an image sensing apparatus such as a camera, for example. | 2017-10-26 |
20170309757 | MULTI-WAVELENGTH DETECTOR ARRAY INCORPORATING TWO DIMENSIONAL AND ONE DIMENSIONAL MATERIALS - A method of forming a wavelength detector that includes forming a first transparent material layer having a uniform thickness on a first mirror structure, and forming an active element layer including a plurality of nanomaterial sections and electrodes in an alternating sequence atop the first transparent material layer. A second transparent material layer is formed having a plurality of different thickness portions atop the active element layer, wherein each thickness portion correlates to at least one of the plurality of nanomaterials. A second mirror structure is formed on the second transparent material layer. | 2017-10-26 |
20170309758 | DEVICE FOR DETECTING ELECTROMAGNETIC RADIATION HAVING AN ENCAPSULATING STRUCTURE INCLUDING AT LEAST ONE INTERFERENCE FILTER - A device for detecting electromagnetic radiation includes at least one thermal detector, placed on a substrate; an encapsulating structure forming a cavity housing the thermal detector, including at least one thin encapsulating layer; and at least one Fabry-Perot interference filter, formed by first and second semi-reflective mirrors that are separated from each other by a structured layer. A high-index layer of one of the semi-reflective mirrors is at least partially formed from the thin encapsulating layer. | 2017-10-26 |
20170309759 | EPITAXIAL SILICON SOLAR CELLS WITH MOISTURE BARRIER - A thin epitaxial silicon solar cell includes one or more layers of doped oxides on the backside. A silicon nitride layer that serves as a moisture barrier is formed on the one or more layers of doped oxides. The doped oxides provide dopants for forming doped regions in an epitaxial silicon layer. Metal contacts are electrically coupled to the doped regions through the silicon nitride layer and the one or more layers of doped oxides. | 2017-10-26 |
20170309760 | SURFACE PREPARATION AND UNIFORM PLATING ON THROUGH WAFER VIAS AND INTERCONNECTS FOR PHOTOVOLTAICS - Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell. | 2017-10-26 |
20170309761 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a solar cell can include a tunnel layer forming step of forming a tunnel layer on a first surface of a semiconductor substrate, a first conductive type semiconductor region forming step of forming a first conductive type semiconductor region on the first surface of the semiconductor substrate, a second conductive type semiconductor region forming step of forming a second conductive type semiconductor region by doping impurities of a second conductive type into a second surface of the semiconductor substrate, a first passivation film forming step of forming a first passivation film on the first conductive type semiconductor region and an electrode forming step of forming a first electrode connected to the first conductive type semiconductor region and a second electrode connected to the second conductive type semiconductor region. | 2017-10-26 |
20170309762 | TWO-DIMENSIONAL LAYERED MATERIAL QUANTUM WELL JUNCTION DEVICES - A quantum well device includes a first layer of a first two-dimensional material, a second layer of a second two-dimensional material, and a third layer of a third two-dimensional material disposed between the first layer and second layer. The first layer, the second layer, and the third layer are adhered predominantly by van der Waals force. | 2017-10-26 |
20170309763 | DEVICE WITH QUANTUM WELL LAYER - A device for guiding and absorbing electromagnetic radiation, the device including: absorbing means for absorbing the electromagnetic radiation; and a coupled to the absorbing means for guiding the electromagnetic radiation to the absorbing means, wherein the waveguide and the absorbing means are formed from a structure including a first cladding layer, a second cladding layer over the first cladding layer, and a quantum-well layer between the first and second cladding layers, the quantum-well layer being formed of a material having a different composition to the first and second cladding layers, wherein the thickness and the composition of the quantum-well layer is optimised to provide an acceptable level of absorption of electromagnetic radiation in the waveguide while providing an appropriate band gap for absorption of the electromagnetic radiation in the absorbing means. | 2017-10-26 |
20170309764 | ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF - To provide an electronic component having a protective film formed with good uniformity, over the entire surface thereof. The electronic component has a protective film formed over the entire surface thereof, and the electronic component has elements and wirings formed on a base body. The protective film is formed by a CVD method, over an entire surface of the electronic component, by: arranging an electrode in a chamber; grounding one side of the chamber and the electrode; accommodating the electronic component in the chamber; supplying a raw material gas to the chamber; rotating or swinging the chamber and thereby moving the electronic component in the chamber; supplying high-frequency power to the other side of the chamber and the electrode; and generating a raw-material-gas-based plasma between the electrode and the chamber. | 2017-10-26 |
20170309765 | INCREMENTAL SOLAR ANTENNA ARRAY FABRICATION - A solar antenna array may comprise an array of antennas that may capture and convert sunlight into electrical power. Methods for constructing the solar antenna array may initially use range of semiconductor processing steps to minimize development costs, and may subsequently use a combination of stamps and low cost materials to reduce manufacturing costs. Designs may be optimized for capturing a broad spectrum of visible light and non-polarized light. Continuous flow Fabrication and Testing is also described. | 2017-10-26 |
20170309766 | SOLAR ANTENNA ARRAY FABRICATION - A solar antenna array may comprise an array of carbon nanotube antennas that may capture and convert sunlight into electrical power. A method for constructing the solar antenna array from a glass top down to aluminum over a plastic bottom such that light passing through the glass top and/or reflected off the aluminum both may be captured by the antennas sandwiched between. Techniques for patterning the glass to further direct the light toward the antennas and techniques for continuous flow fabrication and testing are also described. | 2017-10-26 |
20170309767 | INCREMENTAL SOLAR ANTENNA ARRAY FABRICATION - A solar antenna array may comprise an array of carbon nanotube antennas that may capture and convert sunlight into electrical power. A method for constructing the solar antenna array from a glass top down to an aluminum covered plastic bottom such that light passing through the glass top and/or reflected off the aluminum bottom both may be captured by the antennas sandwiched between. Techniques for patterning the glass to further direct the light toward the antennas and techniques for continuous flow fabrication and testing are also described. | 2017-10-26 |
20170309768 | SILICON HETEROJUNCTION PHOTOVOLTAIC DEVICE WITH WIDE BAND GAP EMITTER - A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm. | 2017-10-26 |
20170309769 | MULTI-WAVELENGTH DETECTOR ARRAY INCORPORATING TWO DIMENSIONAL AND ONE DIMENSIONAL MATERIALS - A method of forming a wavelength detector that includes forming a first transparent material layer having a uniform thickness on a first mirror structure, and forming an active element layer including a plurality of nanomaterial sections and electrodes in an alternating sequence atop the first transparent material layer. A second transparent material layer is formed having a plurality of different thickness portions atop the active element layer, wherein each thickness portion correlates to at least one of the plurality of nanomaterials. A second mirror structure is formed on the second transparent material layer. | 2017-10-26 |
20170309770 | AN APPARATUS AND METHOD FOR SENSING - An apparatus and method wherein the apparatus comprises: a sensing material configured to produce a non-random distribution of free charges in response to a parameter; an electric field sensor; a first conductive electrode comprising a first area over-lapping the sensing material; an insulator provided between the first conductive electrode and the sensing material; a second electrode comprising a second area adjacent the electric field sensor; and a conductive interconnection between the first conductive electrode and the second conductive electrode. | 2017-10-26 |
20170309771 | OPTICAL SENSOR MODULE AND SENSOR CHIP THEREOF - An optical sensor module and a sensor chip thereof are provided. The optical sensor module includes a substrate, a sensor chip and a passive chip. The sensor chip is disposed on the substrate, and the sensor chip includes a chip body having an active region located at a top side thereof and a recess portion depressed from a top surface of the chip body. The passive chip is accommodated in the recess portion, and a depth of the recess portion is greater than a thickness of the passive chip. | 2017-10-26 |
20170309772 | METHOD FOR MANUFACTURING A LARGE-AREA THIN FILM SOLAR CELL - A method for manufacturing a large-area thin film solar cell includes the steps of: (a) forming a first contact layer on a substrate; (b) forming a multi-layer metal precursor film on the first contact layer, which includes the sub-steps of (b | 2017-10-26 |
20170309773 | Nitride Light Emitting Diode and Fabrication Method Thereof - A nitride light-emitting diode (LED) fabrication method includes: providing a glass substrate; stacking a buffer layer structure composed of circular SiAlN layers and AlGaN layers with the number of cycles 1-5; growing a non-doped GaN layer, an N-type layer, a quantum well layer and a P-type layer. By using the low-cost glass the substrate that has a mature processing technology, and growing a SiAlN and an AlGaN buffer layer thereon, lattice mismatch constant between the substance and the epitaxial layer can be improved. Therefore, photoelectric property of the LED can be improved. | 2017-10-26 |
20170309774 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor light-emitting device comprises a substrate; a first adhesive layer on the substrate; multiple epitaxial units on the first adhesive layer; a second adhesive layer on the multiple epitaxial units; multiple first electrodes between the first adhesive layer and the multiple epitaxial units, and contacting the first adhesive layer and the multiple epitaxial units; and multiple second electrodes between the second adhesive layer and the multiple epitaxial units, and contacting the second adhesive layer and the multiple epitaxial units; wherein the multiple epitaxial units are totally separated. | 2017-10-26 |
20170309775 | LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME - Exemplary embodiments of the present invention disclose a light emitting diode including an n-type contact layer doped with silicon, a p-type contact layer, an active region disposed between the n-type contact layer and the p-type contact layer, a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers, an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer, and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer. Only a final layer of the superlattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer. | 2017-10-26 |
20170309776 | Deep Ultraviolet Light Emitting Diode - A carbon doped short period superlattice is provided. A heterostructure includes a short period superlattice comprising a plurality of quantum wells alternating with a plurality of barriers. One or more of the quantum wells and/or the barriers includes a carbon doped layer (e.g., a non-percolated or percolated carbon atomic plane). | 2017-10-26 |
20170309777 | Optoelectronic Semiconductor Chip Comprising a Multi-Quantum Well Comprising at Least One High Barrier Layer - An optoelectronic semiconductor chip including a multi-quantum well including at least one high barrier layer is disclosed. In an embodiment, the chip includes a p-type semiconductor region, an n-type semiconductor region and an active layer suitable for emission of radiation arranged between the p-type region and the n-type region, wherein the active layer is in the form of a multiple quantum well structure. The multiple quantum well structure has a plurality of alternating quantum well layers and barrier layers, wherein a barrier layer arranged closer to the p-type region than to the n-type region is a high barrier layer having an electronic band gap E | 2017-10-26 |
20170309778 | HIGH VOLTAGE MONOLITHIC LED CHIP - Monolithic LED chips are disclosed comprising a plurality of active regions on submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another with at least some of the active regions having a space between adjacent ones of the active regions that is 10 percent or less of the width of one or more of the active regions. The space is substantially not visible when the LED chip is emitting, such that the LED chips emits light similar to a filament. | 2017-10-26 |
20170309779 | RESONANT OPTICAL CAVITY LIGHT EMITTING DEVICE - Resonant optical cavity light emitting devices and method of producing such devices are disclosed. The device includes a substrate, a first spacer region, a light emitting region, a second spacer region, and a reflector. The light emitting region is configured to emit a target emission deep ultraviolet wavelength, and is positioned at a separation distance from the reflector. The reflector has a metal composition comprising elemental aluminum. Using a three-dimensional electromagnetic spatial and temporal simulator, it is determined if an emission output at an exit plane relative to the substrate meets a predetermined criterion. The light emitting region is placed at a final separation distance from the reflector, where the final separation distance results in the predetermined criterion being met. | 2017-10-26 |
20170309780 | VERTICAL ULTRAVIOLET LIGHT EMITTING DEVICE - A UV light emitting device is disclosed. The UV light emitting device includes: a substrate; an n-type semiconductor layer disposed on the substrate; an active layer disposed on the n-type semiconductor layer; a hole injection layer disposed on the active layer and comprising Al; an Al-delta layer disposed on the hole injection layer and comprising Al; and a first p-type contact layer disposed on the Al-delta layer and having a higher doping concentration of p-type dopants than the hole injection layer, wherein the first p-type contact layer has a lower Al content than the hole injection layer, a band-gap of the first p-type contact layer is lower than or equal to energy of light emitted from the active layer, and the Al-delta layer has a higher Al content than the hole injection layer and allows holes to enter the active layer by tunneling therethrough. | 2017-10-26 |