43rd week of 2012 patent applcation highlights part 57 |
Patent application number | Title | Published |
20120271960 | SYSTEM AND METHOD FOR PROVIDING PRINT READY CONTENT TO A PRINTING DEVICE - A script file is maintained on a server system. The script file captures semantics of a task previously performed by a user on a web browser. The server system executes the script file to reproduce the task in response to a request for print ready content where the request is associated with performing the task. The server system converts content obtained from reproducing the task into print ready content and provides the print ready content via a network connection to a printing device. | 2012-10-25 |
20120271961 | AUTOMATED PROTOCOL SELECTION FOR HOST ADAPTER CARD - A method is disclosed, wherein a host adapter is selectively connected to a network using either a four-channel connection or a single-channel connection. Whether the four-channel connection or the single-channel connection has been made to the host adapter is automatically detected. A default four-channel protocol is automatically invoked in response to detecting the four-channel connection has been made. An alternative single-channel protocol is automatically invoked, instead, in response to detecting the single-channel connection has been made. The host adapter communicates over the network using the selected one of the default, four-channel protocol and the alternative, single-channel connection using the same host adapter. | 2012-10-25 |
20120271962 | Achieving Lossless Data Streaming in a Scan Based Industrial Process Control System - A system for lossless sequence of events data streaming in a scan based process control system is provided. The system comprises a digital interface component, the digital interface component configured to receive a plurality of sequence of events data collected during one scan period, to produce a sequence of events data buffer comprising a plurality of sequence of events data, and to make the sequence of events data buffer available to at least one system component. The digital interface component comprises a storage component, the storage component configured to store a sequence of events data buffer. The system further comprises a processing component that accesses the sequence of events data from the storage component and processes the sequence of events data. | 2012-10-25 |
20120271963 | TRANSPORT MECHANISMS FOR DYNAMIC RICH MEDIA SCENES - A transport mechanism for supporting the download of SVG over FLUTE or UDP. A RTP payload format is specified that enables live streaming and the streaming of rich media content. According to the present invention, rich media content is encapsulated in RTP packets based upon the payload format at the sender. With the present invention, an efficient framework is provided for satisfying several use cases or scenarios that involve rich media transmission. | 2012-10-25 |
20120271964 | Load Balancing for Network Devices - In one embodiment, an electronic device receives a request; obtains a current state from each of a plurality of electronic devices; and selects one of the plurality of electronic devices to service the request based on the current state of each of the plurality of electronic devices. The current state of each of the plurality of electronic devices is one of a plurality of states in a state model. Each of the plurality of states in the state model indicates a discrete level of workload for the plurality of electronic devices. | 2012-10-25 |
20120271965 | PROVISIONING MOBILITY SERVICES TO LEGACY TERMINALS - Facilitating access to a Host Identity Protocol security procedure by a legacy host | 2012-10-25 |
20120271966 | NETWORK TRANSCODING SYSTEM - The system is a distributed video transcoding system that allows content to be transformed from one digital format to another close to the ingest and delivery points to minimize the time and cost of the transfer between end points. Additionally by making transcoding an integral part of the distribution of content itself, significant efficiencies can be gained. The distribution can be improved by transcoding at different phases of the transfer. Within the system decisions can be made to utilize different transcoding resources based on various business rules and priorities. | 2012-10-25 |
20120271967 | MULTI-CONFIGURATION COMPUTER - A method for configuring computer operational parameters comprising detecting with at least one processor at least one peripheral device in communication with the at least one processor; receiving, with the at least one processor from at least one of a plurality of communication ports constructed and arranged to interface with the at least one peripheral device, data about the at least one peripheral device, the data comprising at least one location of the at least one peripheral device; identifying with the at least one processor at least one profile associated with the peripheral device data; and adjusting at least one operational parameter based on the at least one profile. | 2012-10-25 |
20120271968 | LOGIC DEVICE FOR COMBINING VARIOUS INTERRUPT SOURCES INTO A SINGLE INTERRUPT SOURCE AND VARIOUS SIGNAL SOURCES TO CONTROL DRIVE STRENGTH - A processor includes a RISC CPU core and a plurality of peripherals including a configurable logic cell peripheral. The configurable logic cell peripheral may be configured to combine a plurality of inputs into a single output. The configurable logic cell may be programmable to function as one of a plurality of predetermined logic functions. | 2012-10-25 |
20120271969 | MULTIFUNCTIONAL TOUCH-ENABLED DEVICES - Example embodiments disclosed herein relate to multifunctional touch-enabled devices. A device includes a touch-enabled display. The device further includes an external connection to connect to a graphics bus of a computing device or an input bus of the computing device. The device also includes a selection module to determine a mode of the peripheral device from a plurality of modes. The modes include a display mode in which the device identifies itself to the computing device as a display. The modes also include an input mode in which the peripheral device identifies itself to the computing device as a dedicated input device. | 2012-10-25 |
20120271970 | SITUATIONAL PLAYBACK - Broadly speaking, the embodiments disclosed herein describe an apparatus, system, and method for processing a media asset by a media asset player in accordance with situational information related to a previous relationship between an identified external device and the media asset player. In one of the described embodiments, the identified external device is physically connected to the media asset player. In another embodiment, the identified external device is wirelessly connected to the portable communication device. In any case, the relational processing of the media asset takes place only while the media asset player is in communication with the external device. | 2012-10-25 |
20120271971 | NON-CONTACT SENSING DEVICE AND ITS METHOD FOR COMPUTER PERIPHERALS - A non-contact sensing device for computer peripherals comprises a sensing unit, a controller and a transmitting unit. The sensing unit can detect a digital pointing device and generate a sensing signal. The controller outputs a starting signal and a stopping signal in different time ratios according to the sensing signal and makes the transmitting unit to generate an oscillating signal dynamically to be sent to the digital pointing device. Thereby, the electric power consumed by the non-contact sensing device can be reduced substantially. | 2012-10-25 |
20120271972 | ADAPTIVE SEMAPHORE - Aspects of the subject matter described herein relate to semaphores. In aspects, a feedback mechanism is described that uses a semaphore to attempt to maximize throughput of a computer system. Throughput is tracked over periods of time. At or after the end of a period of time, the throughput of the period of time together with other data is used to determine whether a max count for a semaphore is to be changed and by how much. This monitoring of throughput and modifying of the max count may continue over subsequent periods of time to attempt to maximize throughput. | 2012-10-25 |
20120271973 | DATA TRANSFER SYSTEM AND DATA TRANSFER METHOD - A data transfer system includes: a processor; a main memory that is connected to the processor; a peripheral controller that is connected to the processor; and a peripheral device that is connected to the peripheral controller and includes a register set, wherein the peripheral device transfers data stored in the register set to a predetermined memory region of the main memory or the processor by a DMA (Data Memory Access) transfer, and the processor reads out the data transferred to the memory region by the DMA transfer without accessing to the peripheral device. | 2012-10-25 |
20120271974 | SATA MASS STORAGE DEVICE EMULATION ON A PCIe INTERFACE - A mass storage device, system, and method for operating a mass storage device are disclosed. In one such mass storage device, a host bus adaptor emulates a SATA mass storage device over a PCIe interface with a host system. The host system generates commands with the PCIe mass storage device in the same format as if communicating with a SATA mass storage device. The PCIe mass storage device responds in the same SATA format. | 2012-10-25 |
20120271975 | DEFINITION OF WAKEUP BUS MESSAGES FOR PARTIAL NETWORKING - A method of encoding a digital bus message information, in particular a wake-up bus message information or configuring data, on a bus system, the method comprising: encoding a predetermined part of digital bus message information bits by means of sub-patterns in a stream of line symbols on at least one bus line, wherein sub-patterns consist of successive dominant and recessive phases, comprised of recessive and dominant line symbols, wherein a recessive phase is comprised of at least two recessive line symbols in order to establish a ratio of successive dominant and recessive phases that corresponds to a value of the predetermined part. A respective digital bus message, particularly for use on a bus system, is to be encoded in accordance with the method. | 2012-10-25 |
20120271976 | Variable Length Arbitration - In one embodiment, a method determines a plurality of categories for requests for a shared resource being shared by a plurality of entities. A request for the resource is received from an entity in the plurality of entities. The method determines a category in the plurality of categories for the received request. If the received request is determined to be in a first category, the method dispatches the received request to a first arbitration scheme configured to determine an arbitration decision in a first time cycle. If the received request is determined to be in a second category, the method dispatches the received request to a second arbitration scheme configured to determine an arbitration decision in a second time cycle of a different length from the first time cycle. | 2012-10-25 |
20120271977 | EXCEPTION HANDLING IN A CONCURRENT COMPUTING PROCESS - A system initiates multiple instances of a concurrent computing process, establishes a communication channel among the multiple instances, initiates execution of a computational job on the multiple instances, detects an interrupt request on one of the multiple instances, and terminates execution of the computational job while maintaining communication among the multiple instances via the communication channel. | 2012-10-25 |
20120271978 | Resource Sharing Expansion Card - An expansion card is provided that allows resources allocated to the expansion card to be shared with a different card. The expansion card comprises a coupling device that couples the expansion card to a data processing system. The expansion card also includes an identifier data structure that when queried by the data processing system, identifies the expansion card as a resource sharing expansion card. The data processing system reallocates one or more resources allocated to the expansion card to a different card coupled to the data processing system. | 2012-10-25 |
20120271979 | SYSTEMS AND METHODS FOR ENABLING COMMUNICATION BETWEEN AN ACCESSORY CHARGER ADAPTER (ACA) AND AN ACA-AGNOSTIC UNIVERSAL SERIAL BUS CONTROLLER - A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus (USB) cable having at least an ID pin and a VBUS pin. The PHY is also to communicate with an ACA-agnostic USB controller configured to act as an A-device or as a B-device. The ACA includes a USB accessory port. The ACA bridge circuit includes detection and control logic configured to detect, based on a resistance sensed on the ID pin, that a B-device is connected to the USB accessory port of the ACA and, as a result of such a detection, generate a signal to the USB controller that causes the USB controller to act as an A-device and ignore a VBUS drive signal from the USB controller. | 2012-10-25 |
20120271980 | TEST DEVICE AND METHOD FOR TESTING SERIAL PORTS OF COMPUTING DEVICE - A test device for testing serial ports of the computing device includes a multiplexer, a USB interface, a signal conversion unit, a switch unit, and multiple serial port interfaces. The USB interface is connected to a USB port of the computing device. Each of the serial port interfaces is connected to a serial port of the computing device. The signal conversion unit is connected to the USB interface of the test device, and connected to the serial port interfaces through the multiplexer. The signal conversion unit converts serial signals into USB signals, or converts USB signals into serial signals, to transmit testing signals between the USB port and the serial ports. The switch unit controls a serial port to be tested to connect to the signal conversion unit through the multiplexer, to form a test channel to test functions of the serial port. | 2012-10-25 |
20120271981 | DIRECT MEMORY ACCESS-LIKE DATA TRANSFER BETWEEN GUEST OPERATING SYSTEMS - A computer system with a memory containing a first guest operating system, including a first portion of the memory and a second guest operating system, including a second portion of the memory. The memory further contains an address exchange module for exchanging memory address handles, a data mover for moving data between the first and second portions of the memory, and an emulated input output memory management unit for controlling the data mover. Instructions in the memory cause the processor to: register accessible memory with the emulated input output memory management unit, write address handles to the address exchange module, read the address handles from the address exchange module, and move the data into the second portion of the memory. | 2012-10-25 |
20120271982 | INTELLIGENT FLASH REPROGRAMMING - Apparatus, methods, and computer-readable media for programming, reading, and servicing non-volatile storage device to improve data retention time and data density are disclosed. According to one embodiment, a method of managing a non-volatile memory storage device includes generating output values based on an expected pattern of discrete states stored in memory cells of the storage device, comparing output values for the memory cells to expected output values using a pre-selected threshold, and based on the comparing, programming other memory cells of the storage device to refresh the programming of the other memory cells. Methods of performing service and management operations for interrupting a host system coupled a non-volatile memory storage device are also disclosed. | 2012-10-25 |
20120271983 | COMPUTING DEVICE AND DATA SYNCHRONIZATION METHOD - A server includes a Southbridge chip, a first storage device, and a baseboard management controller (BMC) electrically connected to the Southbridge chip. A field replacement unit (FRU) is electrically connected to the BMC and the first storage device. The BMC reads data from a second storage device electrically connected to the BMC, writes the data into the FRU, sends a first control signal to a switch positioned between the BMC, the first storage device and the FRU, to switch on an electrical connection between the BMC and the first storage device for reading data stored within the first storage device. If the data stored within the first storage is different from the data stored within the FRU, the BMC reads the data from the FRU, and writes the data into the first storage device, to synchronize the data within the first storage device and the FRU. | 2012-10-25 |
20120271984 | MEMORY ELEMENT AND MEMORY DEVICE - An object is to provide a memory element having a novel structure where data can be held even after power supply is stopped. The memory element includes a latch circuit, a first selection circuit, a second selection circuit, a first nonvolatile memory circuit, and a second nonvolatile memory circuit. The first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor and a capacitor. The transistor included in each of the first nonvolatile memory circuit and the second nonvolatile memory circuit is a transistor in which a channel is formed in an oxide semiconductor film. The off-state current of such a transistor is extremely small. The transistor is turned off after data is input to a node where the transistor and the capacitor are connected to each other, and data can be held for a long time even after supply of power supply voltage is stopped. | 2012-10-25 |
20120271985 | SEMICONDUCTOR MEMORY SYSTEM SELECTIVELY STORING DATA IN NON-VOLATILE MEMORIES BASED ON DATA CHARACTERSTICS - A semiconductor memory device includes a memory block and memory transmission and reception unit. The memory block includes a first non-volatile memory allocated to a first region having a first address range of physical addresses and a second non-volatile memory allocated to a second region having a second address range different from the first address range, which are mapped to logical addresses of a storing region in a host device. The memory transmission and reception unit performs data input and output operations between the host device and the first non-volatile memory using a first data input and output type, and performs data input and output operations between the host device and the second non-volatile memory using a second data input and output type. The first data input and output type performs the data input and output operations by access units corresponding to the first non-volatile memory. | 2012-10-25 |
20120271986 | Flash Memory Device and Data Protection Method Thereof - A data protection method for a flash memory device. In one embodiment, the flash memory device comprises a flash memory for storing protected data. After the flash memory device is coupled to a host, a plurality of current read addresses of a plurality of read commands sent from the host to the flash memory device are recorded. The current read addresses are then compared with a plurality of predetermined read addresses. When the current read addresses are not identical to the predetermined read addresses, the flash memory device is made to enter a data protection mode. When the flash memory device is in the data protection mode, if the flash memory device receives a plurality of data access commands, the data access commands are processed according to a protection mode setting parameter to prevent the protected data from being accessed by the host. | 2012-10-25 |
20120271987 | Memory Module, Memory System, and Inforamtion Device - A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction. | 2012-10-25 |
20120271988 | METHODS CIRCUITS DATA-STRUCTURES DEVICES AND SYSTEM FOR OPERATING A NON-VOLATILE MEMORY DEVICE - Disclosed are methods, data-structures, circuits, devices and system for operating a non-volatile memory device. According to some embodiments, a controller may operate on different portions (e.g. clusters) of a NVM memory array differently, depending upon a designation of a given portion within a table stored on the array. Portions of the array may be operated in OTP page write mode, while other portions of the array may be operated in either bit level or byte level append modes. | 2012-10-25 |
20120271989 | SYSTEMS AND METHODS OF MEDIA MANAGEMENT, SUCH AS MANAGEMENT OF MEDIA TO AND FROM A MEDIA STORAGE LIBRARY, INCLUDING REMOVABLE MEDIA - A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed. | 2012-10-25 |
20120271990 | Non-Volatile Memory Module - Certain embodiments described herein include a memory system which can communicate with a host system such as a disk controller of a computer system. The memory system can include volatile and non-volatile memory and a controller which are configured such that the controller backs up the volatile memory using the non-volatile memory in the event of a trigger condition. In order to power the system in the event of a power failure or reduction, the memory system can include a secondary power source which is not a battery and may include, for example, a capacitor or capacitor array. The memory system can be configured such that the operation of the volatile memory is not adversely affected by the non-volatile memory or the controller when the volatile memory is interacting with the host system. | 2012-10-25 |
20120271991 | RELOCATING DATA IN A MEMORY DEVICE - Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others. | 2012-10-25 |
20120271992 | STORAGE SYSTEM THAT EXECUTES PERFORMANCE OPTIMIZATION THAT MAINTAINS REDUNDANCY - One storage area is selected from two or more storage areas of a high load physical storage device, a physical storage device with a lower load than that of the physical storage device is selected, and it is judged whether the redundancy according to the RAID level corresponding to the logical volume decreases when the data elements stored in the selected storage area are transferred to the selected low load physical storage device. If the result of this judgment is that the redundancy does not decrease, the data elements stored in the selected storage area are transferred to a buffer area of the selected low load physical storage device and the logical address space of the logical volume that corresponds to the selected storage area is associated with the buffer area. | 2012-10-25 |
20120271993 | VIRTUAL TAPE SYSTEMS USING PHYSICAL TAPE CACHING - According to one embodiment, a system includes a virtual tape server coupled to at least one tape library, a library manager in communication with the at least one tape library and the virtual tape server, a memory adapted for acting as logical tape storage and a physical tape drive for processing physical tape media adapted for buffering deduplication operations, logic adapted for receiving a data stream from a host system, logic adapted for sending data from the data stream when the data stream is active to at least one of the memory and the tape drive based on whether at least one of a plurality of conditions is met, and logic adapted for sending previously stored data stream data from the tape drive to the memory when the data stream is inactive during a deduplication operation. Other systems and methods are also described according to more embodiments. | 2012-10-25 |
20120271994 | METHOD AND DATA STORAGE SYSTEM FOR PROVIDING MULTIPLE PARTITION SUPPORT - An apparatus of the present invention includes partition selection circuitry configured to selectably provide individual access to multiple ones of a plurality of partitions of a data storage component by a host device without multiple partition support. The apparatus can also include the data storage component and/or the host device. The partition selection circuitry uses a logical block addressing (LBA) address generated by the host device, and an operating mode indicator indicative of a particular partition, to allow the partitions of the data storage component to be accessed by the host device without multiple partition support. Methods implemented by the apparatus are also disclosed. | 2012-10-25 |
20120271995 | INFORMATION PROCESSING APPARATUS, DRIVE CONTROL PROGRAM, AND DRIVE CONTROL METHOD - In an information processing apparatus which associates logical drives with physical drives and performs processing using the physical drives, a control unit assigns logical drive identification information identifying a logical drive corresponding to a target drive to a physical drive (target drive) that needs to be used in the processing. Then, the control unit performs the processing using the target drive based on the logical drive identification information. | 2012-10-25 |
20120271996 | MEMORY RESOURCE PROVISIONING USING SAS ZONING - An example method for memory resource provisioning using SAS zoning can include a serial attached Small Computer System Interface (SCSI) (SAS) switch and a provisioning manager (PM) executing on the SAS switch. A plurality of servers are communicatively coupled to the SAS switch, each server executing an operating system (OS) having access to one or more OS volumes. A host provisioning agent (HPA) executes on the OS of each of the plurality of servers. A plurality of memory resources are communicatively coupled to the SAS switch. Each memory resource can have a number of physical hard drives. A first portion of the memory resources is associated with zone groups corresponding to the plurality of servers. A second portion of the memory resources is associated with a provisioning zone group (PZG) hidden from the plurality of servers but available to the PM. | 2012-10-25 |
20120271997 | Method and System for Distributed RAID Implementation - Embodiments of the systems and methods disclosed provide a distributed RAID system comprising a set of data banks. More particularly, in certain embodiments of a distributed RAID system each data bank has a set of associated storage media and executes a similar distributed RAID application. Each data bank may have a high speed memory where a write cache is stored. In certain embodiments, a virtualization layer may be executed on a data bank and the distributed RAID application may execute on the virtualization layer. The distributed RAID application may control access to the high speed memory on which the write cache is stored. | 2012-10-25 |
20120271998 | METHOD AND SYSTEM FOR DISTRIBUTED RAID IMPLEMENTATION - Embodiments of the systems and methods disclosed provide a distributed RAID system comprising a set of data banks. More particularly, in certain embodiments of a distributed RAID system each data bank has a set of associated storage media and executes a similar distributed RAID application. Each data bank may have a high speed memory where a write cache is stored. In certain embodiments, a virtualization layer may be executed on a data bank and the distributed RAID application may execute on the virtualization layer. The distributed RAID application may control access to the high speed memory on which the write cache is stored. | 2012-10-25 |
20120271999 | STORAGE SUBSYSTEM THAT CONNECTS FIBRE CHANNEL AND SUPPORTS ONLINE BACKUP - The storage system includes first and second disk arrays. The first disk array has a first port coupled to a second port of the second disk array, a port controller controlling the first port, a plurality of disk devices to store data, and a controller managing a plurality of logical units on the plurality of disk drives. The first port controller controls the first port so as to execute, in a time-sharing manner, data transfer corresponding to a initiator task and data transfer corresponding to a target task. The initiator task is generated to execute the data transfer from a first logical unit on the plurality of disk drives of the first disk array to a second logical unit on a plurality of disk drives of the second disk array. The target task is generated to execute the data transfer to receive data from the second disk array. | 2012-10-25 |
20120272000 | EFFICIENT DATA STORAGE IN STORAGE DEVICE ARRAYS - A method for data storage includes encoding data with an inter-device Error Correction Code (ECC), and sending the encoded data for storage on two or more storage devices. The data to be stored on each of the storage devices, and which has been encoded with the inter-device ECC, is encoded with an intra-device ECC, and the data encoded with the inter-device and intra-device ECCs is stored on the storage device. After storing the data, at least part of the stored data is retrieved and output by decoding the intra-device and inter-device ECCs, while using information related to one of the intra-device and inter-device ECCs in decoding the other of the intra-device and inter-device ECCs. | 2012-10-25 |
20120272001 | DYNAMIC USE OF RAID LEVELS RESPONSIVE TO WORKLOAD REQUIREMENTS - Data associated with a workload is stored in a first composite array of data storage devices that meets first data storage requirements of the workload, and is automatically stored in a second composite array in response to detecting second data storage requirements of the workload, wherein the second composite array of data storage devices meets the second data storage requirements. The data may be stored in the second composite array by either converting the first array or migrating the data to another array that more closely meets the current data storage requirements of the workload. Alternatively, the array conversion or the data migration may be performed in response to a predictive failure alert from one of the data storage devices in the first composite array. | 2012-10-25 |
20120272002 | Detection and Control of Resource Congestion by a Number of Processors - In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period. | 2012-10-25 |
20120272003 | EFFICIENT DATA PREFETCHING IN THE PRESENCE OF LOAD HITS - A microprocessor configured to access an external memory includes a first-level cache, a second-level cache, and a bus interface unit (BIU) configured to interface the first-level and second-level caches to a bus used to access the external memory. The BIU is configured to prioritize requests from the first-level cache above requests from the second-level cache. The second-level cache is configured to generate a first request to the BIU to fetch a cache line from the external memory. The second-level cache is also configured to detect that the first-level cache has subsequently generated a second request to the second-level cache for the same cache line. The second-level cache is also configured to request the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted ownership of the bus to fulfill the first request. | 2012-10-25 |
20120272004 | EFFICIENT DATA PREFETCHING IN THE PRESENCE OF LOAD HITS - A memory subsystem in a microprocessor includes a first-level cache, a second-level cache, and a prefetch cache configured to speculatively prefetch cache lines from a memory external to the microprocessor. The second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both. If a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache. | 2012-10-25 |
20120272005 | SAVING LOG DATA USING A DISK SYSTEM AS PRIMARY CACHE AND A TAPE LIBRARY AS SECONDARY CACHE - Various embodiments save a plurality of log data in a hierarchical storage management system using a disk system as a primary cache with a tape library as a secondary cache. The user data is stored in the primary cache and written into the secondary cache at a subsequent period of time. The plurality of blank tapes in the secondary cache is prepared for storing the user data and the plurality of log data based on priorities. At least one of the plurality of blank tapes is selected for copying the plurality of log data and the user data from the primary cache to the secondary cache based on priorities. The plurality of log data is stored in the primary cache. The selection of at least one of the plurality of blank tapes completely filled with the plurality of log data is delayed for writing additional amounts of user data. | 2012-10-25 |
20120272006 | DYNAMIC LOCKSTEP CACHE MEMORY REPLACEMENT LOGIC - To facilitate dynamic lockstep support, replacement states and/or logic used to select particular cache lines for replacement with new allocations in accord with replacement algorithms or strategies may be enhanced to provide generally independent replacement contexts for use in respective lockstep and performance modes. In some cases, replacement logic that may be otherwise conventional in its selection of cache lines for new allocations in accord with a first-in, first-out (FIFO), round-robin, random, least recently used (LRU), pseudo LRU, or other replacement algorithm/strategy is at least partially replicated to provide lockstep and performance instances that respectively cover lockstep and performance partitions of a cache. In some cases, a unified instance of replacement logic may be reinitialized with appropriate states at (or coincident with) transitions between performance and lockstep modes of operation. | 2012-10-25 |
20120272007 | CACHE MEMORY WITH DYNAMIC LOCKSTEP SUPPORT - Cache storage may be partitioned in a manner that dedicates a first portion of the cache to lockstep mode execution, while providing a second (or remaining) portion for non-lockstep execution mode(s). For example, in embodiments that employ cache storage organized as a set associative cache, partition may be achieved by reserving a subset of the ways in the cache for use when operating in lockstep mode. Some or all of the remaining ways are available for use when operating in non-lockstep execution mode(s). In some embodiments, a subset of the cache sets, rather than cache ways, may be reserved in a like manner, though for concreteness, much of the description that follows emphasizes way-partitioned embodiments. | 2012-10-25 |
20120272008 | STORAGE SYSTEM AND ITS DATA PROCESSING METHOD - A cache memory is utilized effectively because data redundancy elimination is executed. | 2012-10-25 |
20120272009 | METHODS AND APPARATUS FOR HANDLING A CACHE MISS - In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided. | 2012-10-25 |
20120272010 | STABLE ADAPTIVE REPLACEMENT CACHE PROCESSING - A process for caching data in a cache memory includes upon detecting that a first page is in a first or second list, the first page is moved to a most recently used (MRU) position in the second list. Upon detecting that the first page is in a first history list, a first target size is updated to a second target size for the first and second lists, the first page is moved from the first history list to the MRU position in the second list, and the first page is fetched to the cache memory. Upon detecting that the first page is in a second history list, the second target size is updated to a third target size for the first and second lists, and the first page is moved from the second history list to the MRU position in the second list. | 2012-10-25 |
20120272011 | PROCESSOR CACHE TRACING - A method for refining multithread software executed on a processor chip of a computer system. The envisaged processor chip has at least one processor core and a memory cache coupled to the processor core and configured to cache at least some data read from memory. The method includes, in logic distinct from the processor core and coupled to the memory cache, observing a sequence of operations of the memory cache and encoding a sequenced data stream that traces the sequence of operations observed. | 2012-10-25 |
20120272012 | DISTRIBUTED SHARED MEMORY - Systems and methods for implementing a distributed shared memory (DSM) in a computer cluster in which an unreliable underlying message passing technology is used, such that the DSM efficiently maintains coherency and reliability. DSM agents residing on different nodes of the cluster process access permission requests of local and remote users on specified data segments via handling procedures, which provide for recovering of lost ownership of a data segment while ensuring exclusive ownership of a data segment among the DSM agents detecting and resolving a no-owner messaging deadlock, pruning of obsolete messages, and recovery of the latest contents of a data segment whose ownership has been lost. | 2012-10-25 |
20120272013 | DATA ACCESS SYSTEM WITH AT LEAST MULTIPLE CONFIGURABLE CHIP SELECT SIGNALS TRANSMITTED TO DIFFERENT MEMORY RANKS AND RELATED DATA ACCESS METHOD THEREOF - A data access system includes a memory controller, a first memory rank, a second memory rank, a first chip select bus coupled between the memory controller and the first memory rank, a second chip select bus coupled between the memory controller and the second memory rank, a group of shared buses shared by the first and second memory ranks and coupled between the memory controller and each of the first and second memory ranks, a first group of dedicated buses dedicated to the first memory rank and coupled between the memory controller and the first memory rank, and a second group of dedicated buses dedicated to the second memory rank and coupled between the memory controller and the second memory rank. | 2012-10-25 |
20120272014 | DISTRIBUTED SHARED MEMORY - Systems and methods for implementing a distributed shared memory (DSM) in a computer cluster in which an unreliable underlying message passing technology is used, such that the DSM efficiently maintains coherency and reliability. DSM agents residing on different nodes of the cluster process access permission requests of local and remote users on specified data segments via handling procedures, which provide for recovering of lost ownership of a data segment while ensuring exclusive ownership of a data segment among the DSM agents detecting and resolving a no-owner messaging deadlock, pruning of obsolete messages, and recovery of the latest contents of a data segment whose ownership has been lost. | 2012-10-25 |
20120272015 | VIRTUAL MACHINE TRIGGER - A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition. | 2012-10-25 |
20120272016 | MEMORY AFFINITIZATION IN MULTITHREADED ENVIRONMENTS - A method, system, and computer program product for memory affinitization in a multithreaded environment are provided in the illustrative embodiments. A first affinity domain formed in a computer receives from a second thread executing in a second affinity domain a request to access a unit of memory in the first affinity domain. The computer determines whether to migrate the unit of memory to the second affinity domain. The computer migrates, responsive the determining being affirmative, the unit of memory to the second affinity domain, thereby affinitizing the unit of memory with the second thread. | 2012-10-25 |
20120272017 | NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM AND RANDOM DATA READ METHOD THEREOF - A random data reading method of a nonvolatile memory device includes receiving an initial seed corresponding to a selected page of the nonvolatile memory device and relative location information of read-requested random data in the selected page. The method further includes generating a seed for randomizing the random data by subjecting the initial seed and the location information to a finite field arithmetic operation, and de-randomizing the random data based on a random sequence generated from the seed. | 2012-10-25 |
20120272018 | STORAGE DEVICE, HOST APPARATUS, CIRCUIT SUBSTRATE, LIQUID CONTAINER, AND SYSTEM - A storage device includes a control unit that performs a process of communicating with a host apparatus which is connected to the storage device through a bus, a storage unit into which data transmitted from the host apparatus are written, and a storage control unit that performs access control on the storage unit. The control unit receives an ID information item from the host apparatus after the end of a period of writing data from the host apparatus to m (m is an integer equal to or greater than 1) storage devices of a plurality of the storage devices connected to the bus, and returns an acknowledgement to the host apparatus if the data transmitted from the host apparatus have been successfully written to the storage unit of the storage device. | 2012-10-25 |
20120272019 | SCHEDULING READ OPERATIONS DURING DRIVE RECONSTRUCTION IN AN ARRAY OF REDUNDANT DISK DRIVES - Some embodiments of the present invention provide a system that schedules read operations for disk drives in a set of disk drives. During operation, the system monitors a write rate for write operations to a given disk drive in the set of disk drives, wherein vibrations generated by the read operations directed to disk drives in the set of disk drives are transmitted to the given disk drive. Then, the read operations for disk drives in the set of disk drives are scheduled based on the write rate for the given disk drive, thereby limiting interference between the write operations and the vibrations generated by the read operations. | 2012-10-25 |
20120272020 | STORAGE APPARATUS, CONTROLLER, AND METHOD OF CONTROLLING CONTROLLER - Provided are a processor generates a plurality of pieces of divided notification information, based on notification information including target information about a plurality of communication adaptors in a storage apparatus; a processor stores the plurality of pieces of divided notification information; and sends the divided notification information stored in the memory, in response to a target information obtainment request from a host apparatus, thereby, the load for notifying notification information to the host apparatus can be reduced, as well as preventing any inconsistency in notifying the notification information. | 2012-10-25 |
20120272021 | MANAGEMENT SYSTEM AND CONTROL METHOD FOR COMPUTER SYSTEM - To provide a storage management technique for creating and managing, with single operation by a user, a large quantity of writable snapshots, which satisfy a requirement desired by the user, while controlling a use form of a storage apparatus not to exceed limits of the performance and the capacity of the storage apparatus. Therefore, a management computer manages configuration information and performance information of plural storage apparatuses and an operation state of a writable snapshot. When a writable snapshot is created, the management computer controls, concerning an original snapshot, a use form of the storage apparatuses not to exceed a disk performance limit and a controller performance limit and a capacity limit of a storage on the basis of the number of writable snapshots to be created and a performance requirement (IOPS) and a capacity requirement of the writable snapshot. | 2012-10-25 |
20120272022 | DATA ACCESS PROCESSING METHOD AND APPARATUS - A data access processing method and apparatus, the method comprising: copying a kernel code and a global descriptor table on a memory of each of nodes respectively ( | 2012-10-25 |
20120272023 | STORAGE APPARATUS, CONTROLLER, AND METHOD OF CONTROLLING CONTROLLER - Provided are a processor generates second notification information by copying first notification information including target information about all communication adaptors in a storage apparatus; updates the first notification information, upon configuration information on the communication adaptors being modified; updates, when receiving a target information obtainment request, the second notification information with second notification information; blocks, when a predetermined copy prevention condition is met, copy of the first notification information to the second notification information; and sends, when receiving the target information obtainment request, the second notification information to the host apparatus, thereby, the load for notifying notification information to the host apparatus can be reduced, as well as preventing any inconsistency in notifying the notification information. | 2012-10-25 |
20120272024 | DATA STORAGE SYSTEM AND A DATA RETENTION METHOD THEREOF - A data retention method that includes sampling a plurality of nonvolatile memory devices included in a data storage device to detect retention information for each of the nonvolatile memory devices in response to a request of a host and outputting, from the data storage device to the host, sampling data based on a result of the sampling, determining, at the host, whether to perform a retention operation on each of the nonvolatile memory devices based on the sampling data, and performing the retention operation on each of the nonvolatile memory devices based on a result of the determination. | 2012-10-25 |
20120272025 | SELECTING DATA NODES USING MLUTILPE STORAGE POLICIES IN CLOUD STORAGE SYSTEM - Provided are a method and a server for selecting data nodes for storing an object and replicas thereof in a cloud storage system having a plurality of data nodes grouped in a plurality of storage areas. The method may include selecting at least one storage area for storing the object and the replicas thereof sequentially with a locality policy, a low-cost policy, a load-balancing policy, and a space-balancing policy and selecting at least one data node from the selected at least one storage area sequentially using a load-balancing policy and a space-balancing policy. | 2012-10-25 |
20120272026 | MANAGING WRITE OPERATIONS TO AN EXTENT OF TRACKS MIGRATED BETWEEN STORAGE DEVICES - Provided are a computer program product, system, and method for managing write operations to an extent of tracks migrated from a second storage to a first storage. An extent object exists if the extent was previously migrated from the first storage to the second storage at a previous time. In response to determining that the extent object exists, a determination is made of the tracks in the extent having a write indicator indicating that the track was updated in the second storage since the previous time. The data for the determined tracks is copied from the second storage to free locations in the first storage. For each determined track, the entry for the determined track in the extent object is updated to indicate the free location to which the data for the track was copied as an active address for the track. | 2012-10-25 |
20120272027 | Memory Protection Unit with Support for Distributed Permission Checks - A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the permissions assigned to the request based on the memory segment being accessed. The decision to allow or disallow access is made by the extended memory controller by merging the permissions assigned to the memory segment being accessed, and the permissions assigned to the access request by the originating memory controller or other endpoint. | 2012-10-25 |
20120272028 | WIRELESS COMMUNICATION DEVICE - In this wireless communication device, a storage unit stores writing identification information relating to permission and prohibition of writing. An acquisition unit acquires device identification information that uniquely specifies an arbitrary wireless communication device from the arbitrary wireless communication device. A determination unit determines permission or prohibition of writing to a recording medium on the basis of the device identification information acquired by the acquisition unit and the writing identification information stored in the storage unit when a communication protocol of a session layer that performs writing to and readout from the recording medium in sector units is selected. A recording medium control unit controls permission and prohibition of writing to the recording medium on the basis of a result determined by the determination unit. | 2012-10-25 |
20120272029 | MEMORY ACCESS MONITORING METHOD AND DEVICE - A memory access monitoring method and a memory access monitoring method device are disclosed, The method comprises: performing coarse grain monitoring on local memory pages, if a hot page with coarse grain monitoring exists in the local memory pages, requesting an operating system to perform an optimized migration for the content of the hot page, and if a half hot page with coarse grain monitoring exists in the local memory pages, initiating fine grain monitoring to the half hot page; and performing fine grain monitoring on the half hot page, if a hot area with fine grain monitoring exists in the half hot page, requesting the operating system to perform an optimized migration for the content of the hot area. | 2012-10-25 |
20120272030 | SYNCHRONOUS EXTENT MIGRATION PROTOCOL FOR PAIRED STORAGE - Extent migration is provided in a data storage environment configured for synchronous replication between a primary and secondary pair of storage entities, each having tiered storage devices. In one embodiment, by way of example only, a migration instruction is sent, by the primary storage entity, to the secondary storage entity, the migration instruction including a relative priority based on a primary ordered heat map of the tiered storage devices of the primary storage entity. The relative priority is used against a secondary ordered heat map of the tiered storage devices of the secondary storage entity to perform the extent migration, regardless of whether the primary and secondary storage entities are identical. | 2012-10-25 |
20120272031 | CHANNEL DEPTH ADJUSTMENT IN MEMORY SYSTEMS - Memory devices, systems and methods are described, such as those including a dynamically configurable channel depth. Devices, systems and methods are described that adjust channel depth based on hardware and/or software requirements. One such device provides for virtual memory operations where a channel depth is adjusted for the same physical memory region responsive to requirements of different memory processes. | 2012-10-25 |
20120272032 | Dynamic Allocation of a Buffer Across Multiple Clients in a Threaded Processor - A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data. | 2012-10-25 |
20120272033 | System and Method for Managing Space Allocation within a File System - A chassis management controller includes a root file system, a shared memory, a daemon process module, and an interposer library. The root file system includes a plurality of directories associated with firmware applications of the chassis management controller. The daemon process module is configured to read the parameters of the directories, and to create, in the shared memory, a table including parameters of the directories. The interposer library is configured to intercept an input/output library call for an operation associated with one of the firmware applications, to read table entries associated the one or the firmware applications, to determine whether the operation associated with the input/output library call would result in an over-allocation of a parameter in the entries of the table, and if the operation would not result in the over-allocation, pass the output operation to a standard system library, otherwise to return an out of space error message. | 2012-10-25 |
20120272034 | METHOD AND DEVICE FOR STORING AND READING/WRITING COMPOSITE DOCUMENT - A method and device for storing and reading/writing composite document are disclosed. The method includes: an initial storing area is pre-allocated for an inner controlling stream of the composite document and the initial storing area is continuous sectors or sector clusters; the inner controlling stream is stored in the initial storing area. The patches of a user data stream and the inner controlling stream in the composite document are reduced using the method or device. Correspondingly, pre-allocating storing area makes the probability of continuously storing the user data stream and the inner controlling stream in the composite document increased. The I/O can be optimized by introducing a strategy of reading cache and writing in a batch size, which can improve the efficiency of reading and writing. | 2012-10-25 |
20120272035 | STORAGE APPARATUS AND DATA CONTROL METHOD OF THE SAME - The relay unit splits the storage area in the buffer into a plurality of partitioned areas, manages the same and, upon receiving a read request from the access request source, selects and allocates one or more from the plurality of partitioned areas and, on condition that the relevant partitioned areas are allocated, transmits the read request to the memory control unit, wherein the memory control unit reads the data requested in the received read request from the memory, splits the data which is read into a plurality of units, and transmits the same to the relay unit, wherein the relay unit stores each of the data transmitted from the memory control unit in each of the allocated partitioned areas sequentially, on condition that all of the data is stored, reads each of the data from each of the allocated partitioned areas, compiles each of the data which is read into one, transmits the same as read data to the access request source, and releases all of the respective allocated partitioned areas. | 2012-10-25 |
20120272036 | ADAPTIVE MEMORY SYSTEM - An adaptive, memory system is provided. The adaptive memory system has a number of physical-memory devices and a memory controller that creates and maintains a logical address space to which the physical-memory devices and data-storage allocations are mapped, and through which mapping the memory controller matches static, dynamic, and dynamically-adjustable retention and resiliency characteristics of portions of the physical-memory devices with specified retention and resiliency characteristics specified for the data-storage allocations. | 2012-10-25 |
20120272037 | TECHNIQUES FOR MAPPING DEVICE ADDRESSES TO PHYSICAL MEMORY ADDRESSES - A data processing system includes a main storage, an input/output memory management unit (IOMMU) coupled to the main storage, a peripheral component interconnect (PCI) device coupled to the IOMMU, and a mapper. The system is configured to allocate an amount of physical memory in the main storage and the IOMMU is configured to provide access to the main storage and to map a PCI address from the PCI device to a physical memory address within the main storage. The mapper is configured to perform a mapping between the allocated amount of physical memory of the main storage and a contiguous PCI address space. The IOMMU is further configured to translate PCI addresses of the contiguous PCI address space to the physical memory address within the main storage. | 2012-10-25 |
20120272038 | LOGICAL BLOCK ADDRESS MAPPING - A mapping table is modified to match one or more specified storage conditions of data stored in or expected to be stored in one or more logical block address ranges to physical addresses within a storage drive having performance characteristics that satisfy the specified storage conditions. For example, the performance characteristics may be a reliability of the physical location within the storage drive or a data throughput range of read/write operations. Existing data is moved and/or new data is written to physical addresses on the storage media possessing the performance characteristic(s), according to the mapping table. Further, a standard seeding or a seeding override for the re-mapped logical block addresses can prevent read operations from inadvertently reading incorrect physical addresses corresponding to the re-mapped logical block addresses. | 2012-10-25 |
20120272039 | RETENTION-VALUE ASSOCITED MEMORY - A memory component or subsystem is provided. The memory comprises one or more memory devices and one or more write controllers within each of the one or more memory devices that each controls memory-device components to write input data values into a plurality of memory cells within a memory device that represents a unit of stored data addressed by a logical-address-space address, the write controller applying a current to the plurality of memory cells during a WRITE operation with a magnitude that corresponds to a retention value associated with the logical-address-space address. | 2012-10-25 |
20120272040 | Enhanced Modularity in Heterogeneous 3D Stacks - A computer program product for generating and implementing a three-dimensional (3D) computer processing chip stack plan. The computer readable program code includes computer readable program code configured for receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to at least one layer in the 3D computer processing chip stack plan. The computer readable program code is also configured for identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The computer readable program code is further configured for determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment forms the 3D computer processing chip stack. | 2012-10-25 |
20120272041 | MULTIPROCESSING OF DATA SETS - Various arrangements for processing data sets using multiple processors are presented. A plurality of constraints may be received by a computer system. Each constraint may identify a data relationship that requires a subset of records of one or more data sets to be processed by a same processing device. A plurality of final constraints may be calculated. Each final constraint of the plurality of final constraints may be linked with a record. Each final constraint of the plurality of final constraints may be at least partially based on the plurality of constraints. Final constraints of the plurality of final constraints having a same value may be linked with records that are to be processed by the same processing device. At least partially based on the final constraint, the set of records may be distributed to a plurality of processing devices for processing. | 2012-10-25 |
20120272042 | DISTRIBUTED MICRO INSTRUCTIONS SET PROCESSOR ARCHITECTURE FOR HIGH-EFFICIENCY SIGNAL PROCESSING - A wireless communication base station comprising a plurality of application specific instruction set processors (ASISPs) configured to support one or more processes hosted by the base station, and to track process state information associated with each of the processes; and a memory configured to store the tracked process state information, and when an ASISP of the plurality of ASISPs is reallocated from a first process to a second process, the respective ASISP is configured to retrieve from the memory process state information for the second process. | 2012-10-25 |
20120272043 | REQUEST COALESCING FOR INSTRUCTION STREAMS - Sequential fetch requests from a set of fetch requests are combined into longer coalesced requests that match the width of a system memory interface in order to improve memory access efficiency for reading the data specified by the fetch requests. The fetch requests may be of different classes and each data class is coalesced separately, even when intervening fetch requests are of a different class. Data read from memory is ordered according to the order of the set of fetch requests to produce an instruction stream that includes the fetch requests for the different classes. | 2012-10-25 |
20120272044 | PROCESSOR FOR EXECUTING HIGHLY EFFICIENT VLIW - A 32-bit instruction | 2012-10-25 |
20120272045 | CONTROL METHOD AND SYSTEM OF MULTIPROCESSOR - A control method and a system for dispatching the execution sequence of the processes in a multiprocessors system so as to dispatch an operation sequence for executing different operation programs by a monitoring processor and a plurality of target processors. The monitoring processor obtains operation status of other processors from a buffer; the monitoring processor selects at least one target processor according to the operation status; the monitoring processor assigns the target processor to execute a corresponding slave operation program, and modifies the operation status of the target processors in the buffer module; and the monitoring processor repeats the setting the operation status and assigning other target processors to execute corresponding operation programs, till a master operation program is completed. | 2012-10-25 |
20120272046 | Vector Completion Mask Handling - Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for execution with the operation, then the corresponding mask field within the data structure is cleared. The processor can reset if any field remains set within the data structure and can re-process the operation with operands that were not previously handled with the operation. | 2012-10-25 |
20120272047 | METHOD AND APPARATUS FOR SHUFFLING DATA - Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set. | 2012-10-25 |
20120272048 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD THEREFOR AND STORAGE MEDIUM - There is provided an information processing apparatus which validates addition of hardware even if the addition takes place before activation of the apparatus, a control method therefor, and a program. To accomplish this, the information processing apparatus includes a monitoring circuit that is supplied with a power from a backup power supply, monitors addition of the hardware, and temporarily holds, when addition of the hardware occurs, information of the addition. If the information of the addition is held, the information processing apparatus initializes the added hardware in activation of the information processing apparatus. | 2012-10-25 |
20120272049 | TOUCH CONTROL METHOD FOR SETTING BASIC INPUT OUTPUT SYSTEM AND COMPUTER SYSTEM USING THE SAME - A touch control method for setting the basic input output system (BIOS) is provided. The setting method includes the following steps. The BIOS transmits an initial configuration data to a memory. An application program reads the initial configuration data from the memory and evocates an input interface displaying on a touch panel. The input interface includes a plurality of selecting items corresponding to the initial configuration data. The application program receives a setting signal from the touch panel and executes the selecting item according to the setting signal. The application program produces a renewal configuration data and the application program stores the renewal configuration data in the memory. The application program rewrites the renew configuration data back to the BIOS. | 2012-10-25 |
20120272050 | ELECTRONIC DEVICE AND BOOTING METHOD THEREOF - An electronic device and a method of booting the electronic device is provided. The electronic device and method include a power supply unit, a volatile memory, a non-volatile memory, and a controller which, in response to power being supplied by the power supply unit, performs booting in a first booting mode that uses a suspend image stored in the volatile memory; and, in response to an error occurring in the first booting mode, performs a next booting in a second booting mode that uses a suspend image stored in the non-volatile memory. In response to power being supplied by the power supply unit, performing booting in a first booting mode that uses a suspend image stored in the volatile memory; and in response to an error occurring in the first booting mode, performing a next booting in a second booting mode using a suspend image stored in the non-volatile memory. | 2012-10-25 |
20120272051 | SECURITY KEY DISTRIBUTION IN A CLUSTER - Provided are techniques for the fast and reliable distribution of security keys within a cluster of computing devices, or computers. One embodiment provides a method for secure distribution of encryption keys, comprising generating a symmetric key for the encryption of communication among a plurality of nodes of a cluster of nodes; encrypting the symmetric key with a plurality of public keys, each public key corresponding to a particular node of the plurality of modes, to generate a plurality of encrypted symmetric keys; storing the plurality of encrypted symmetric keys in a central repository; and distributing the encrypted symmetric keys to the nodes such that each particular node receives an encrypted symmetric key corresponding to a corresponding public key of the particular node. | 2012-10-25 |
20120272052 | METHOD FOR GENERATING A CRYPTOGRAPHIC KEY FOR A PROTECTED DIGITAL DATA OBJECT ON THE BASIS OF CURRENT COMPONENTS OF A COMPUTER - A method for coupling protected digital data object, for example an application program, and a specified computer, which allows for, if desired, individual components of the computer to be modified. A cryptographic key is generated on the basis of current components of a computer in order to decrypt an encrypted, computer-specific authorization code for executing a protected digital data object on the computer. The computer-specific authorization code is encrypted with a key based on original components of the computer. The key can be determined from the current components of the computer even if they are different from the original components of the computer. | 2012-10-25 |
20120272053 | Virtual private network for real-time data - The present disclosure describes a method for protecting real-time data exchanged between a mobile electronic device and a VPN gateway over a communications link. The method comprises: establishing a first VPN connection between the mobile electronic device and the VPN gateway through the communications link; establishing, while the first VPN connection is established, a second VPN connection between the mobile electronic device and the VPN gateway through the communications link; providing key information to at least one of the mobile electronic device or VPN gateway through the first VPN connection; and exchanging real-time data packets between the mobile electronic device and the VPN gateway through the second VPN connection, wherein the key information is for encrypting and decrypting the real-time data packets exchanged through the second VPN connection. | 2012-10-25 |
20120272054 | Method and system for protecting security of the third layer mobility user plane data in NGN - The disclosure discloses a method for protecting security of layer-3 mobility user plane data in Next Generation Network (NGN), includes: performing authentication by a terminal with an authentication server; after the authentication is passed, obtaining a shared key material by both the terminal and the authentication server; generating, by the terminal and the authentication server, a mobility data security key according to the shared key material; transmitting, by the authentication server, the generated mobility data security key to a mobility data transmission module; protecting security of the layer-3 mobility user plane data, by the terminal and the mobility data transmission module, by using the mobility data security key. The disclosure also discloses a system for protecting security of layer-3 mobility user plane data in NGN. By using the method and the system provided by the disclosure, the protection for security of user plane data between the NGN user and the NGN network side is realized, and the security of user plane data of the terminal in layer-3 mobility session is enhanced. | 2012-10-25 |
20120272055 | METHOD AND APPARATUS FOR ESTABLISHING SECURED LINK BETWEEN DEVICES - A method and apparatus for establishing a secured link between devices. In the establishing of the secured link, a coordinator respectively receives from the first and second devices first pairing information indicating that a first device is to establish a secured link and second pairing information indicating that a second device is to establish a secured link. The coordinator further receives via a first secured link established between the first device and the coordinator shared secured information. The shared secured information is shared between the first and second devices. The coordinator establishes a second secured link with the second device based on the shared secured information; and broadcasts partner notice information indicating that the first and second devices are partner devices. The broadcast partner notice information is then used to establish a third secured link. | 2012-10-25 |
20120272056 | KEY MANAGEMENT USING QUASI OUT OF BAND AUTHENTICATION ARCHITECTURE - To provide key management layered on a quasi-out-of-band authentication system, a security server receives a request for activation of a user interface window for a particular user from a network device via a communication channel. It then transmits an activation PIN to an out of band authentication system for forwarding to the user's telephone via a voice or text message. It next receives the previously transmitted PIN from the network device via the communication channel, and authenticates the user based on the received PIN. After authenticating the user, it establishes a secure, independent, encrypted communication channel between the user interface window and the security server on top of the original communication channel. It then generates and transmits to the user interface window and/or receives from the user interface window via the secure communication channel, key material and certificate material for public key and/or symmetric key cryptography based operations. | 2012-10-25 |
20120272057 | Method and Apparatus for Secured Embedded Device Communication - In a computing device that includes a host operating system and a management engine separate from the host operating system, if the primary operating system is not operating, a management engine may obtain from a credential server via a first network connection logon information for a secured network and the management engine connects to the secure network through a secured connection using the logon information. If the operating system is operating the operating system provides the logon information to the management engine. Certificate verification may be performed by a remote server on behalf of the management engine. Other embodiments are disclosed and claimed. | 2012-10-25 |
20120272058 | TRANSPARENT PROXY OF ENCRYPTED SESSIONS - In one embodiment, a proxy device located between a first device and a second device intercepts a security session request for a security session between the first device and the second device. The proxy device obtains security information from the first device that includes at least a subject name of the first device. The proxy device creates a dynamic certificate using the subject name of the first device and a trusted proxy certificate of the proxy device. The proxy device establishes a security session between the proxy device and the second device using the dynamic certificate. Further, the proxy device establishes a security session between the first device and the proxy device using the trusted proxy certificate of the proxy device. The two security sessions collectively operate as a security session between the first device and the second device. | 2012-10-25 |
20120272059 | SYSTEM AND METHOD FOR SECURE EXCHANGE OF INFORMATION IN A COMPUTER SYSTEM - A system and method for secure exchange of information in a computing system is described. In one embodiment, the method includes receiving a request to switch to a safe mode from a target application. Encryption/decryption keystring is generated based on the request. The target application is responded with the decryption keystring. A key-stroke is encrypted using the encryption keystring. The encrypted key-stroke is stored in a keyboard buffer. The target application retrieves the encrypted key-stroke and decrypts the encrypted key-stroke using the decryption keystring. | 2012-10-25 |