43rd week of 2012 patent applcation highlights part 41 |
Patent application number | Title | Published |
20120270346 | ASYMMETRIC DBR PAIRS COMBINED WITH PERIODIC AND MODULATION DOPING TO MAXIMIZE CONDUCTION AND REFLECTIVITY, AND MINIMIZE ABSORPTION - Methods for fabricating an optical device that exhibits improved conduction and reflectivity, and minimized absorption. Steps include forming a plurality of mirror periods designed to reflect an optical field having peaks and nulls. The formation of a portion of the plurality of minor periods includes forming a first layer having a thickness of less than one-quarter wavelength of the optical field; forming a first compositional ramp on the first layer; and forming a second layer on the compositional ramp, the second layer having a different index of refraction than the first layer and having a thickness such that the nulls of the optical field occur within the second layer and not within the compositional ramp, and wherein forming the second layer further comprises heavily doping the second layer at a location of the nulls of the optical field. | 2012-10-25 |
20120270347 | METHOD OF MANUFACTURING RIDGE-TYPE SEMICONDUCTOR LASER - A method of manufacturing a ridge-type semiconductor laser includes the steps of forming a stacked semiconductor layer including an active layer and an etch stop layer on first and second surfaces of a substrate, etching the stacked semiconductor layer on the second surface, forming a semiconductor portion on the second surface, forming a ridge waveguide portion by etching the stacked semiconductor layer on the first surface to a first depth, forming semiconductor diffraction grating portions by etching the semiconductor portion to a second depth, and forming a diffraction grating section by providing resin diffraction grating portions between the semiconductor diffraction grating portions. The etching of the stacked semiconductor layer on the first surface and the etching of the semiconductor portion are performed simultaneously by using first and second mask portions. | 2012-10-25 |
20120270348 | Semiconductor Device and Method for Manufacturing the Same - It is an object to obtain a liquid crystal display device in which a contact defect is reduced, increase in contact resistance is suppressed, and an opening ratio is high. The present invention relates to a liquid crystal display device having a substrate; a thin film transistor provided over the substrate, which includes a gate wiring, a gate insulating film, an island-shaped semiconductor film, a source region, and a drain region; a source wiring which is provided over the substrate and is connected to the source region; a drain electrode which is provided over the substrate and is connected to the drain region; an auxiliary capacitor provided over the substrate; a pixel electrode connected to the drain electrode; and a protective film formed so as to cover the thin film transistor and the source wiring, where the protective film has an opening, and the auxiliary capacitor is formed in the area where the opening is formed. | 2012-10-25 |
20120270349 | LIQUID COMPOSITIONS FOR INKJET PRINTING OF ORGANIC LAYERS OR OTHER USES - A method of forming an organic layer for an organic electronic device (e.g., an OLED) by using a liquid composition comprising a small molecule organic semiconductor material mixed in a solvent preparation in which the content of higher boiling impurities is reduced. The solvent preparation comprises a high boiling point solvent and 0.1 wt % or less of impurities having a higher boiling point than the solvent. The liquid composition is deposited on a surface by inkjet printing to form the organic layer. Also, provided are liquid compositions which can be used to make organic layers. | 2012-10-25 |
20120270350 | SEMICONDUCTOR BIO-SENSORS AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening. | 2012-10-25 |
20120270351 | LOW TEMPERATURE BI-CMOS COMPATIBLE PROCESS FOR MEMS RF RESONATORS AND FILTERS - A method of removal of a first and second sacrificial layer wherein an O | 2012-10-25 |
20120270352 | FABRICATING MEMS COMPOSITE TRANSDUCER INCLUDING COMPLIANT MEMBRANE - A method of fabricating a MEMS composite transducer includes providing a substrate having a first surface and a second surface opposite the first surface. A transducing material is deposited over the first surface of the substrate. The transducing material is patterned by retaining transducing material in a first region and removing transducing material in a second region. A polymer layer is deposited over the first region and the second region. The polymer layer is patterned by retaining polymer in a third region and removing polymer in a fourth region. A first portion of the third region is coincident with a portion of the first region and a second portion of the third region is coincident with a portion of the second region. A cavity is etched from the second surface to the first surface of the substrate. An outer boundary of the cavity at the first surface of the substrate intersects the first region where transducing material is retained, so that a first portion of the transducing material is anchored to the first surface of the substrate and a second portion of the transducing material extends over at least a portion of the cavity. | 2012-10-25 |
20120270353 | COUPLING PIEZOELECTRIC MATERIAL GENERATED STRESSES TO DEVICES FORMED IN INTEGRATED CIRCUITS - A coupling structure for coupling piezoelectric material generated stresses to an actuated device of an integrated circuit includes a rigid stiffener structure formed around a piezoelectric (PE) material and the actuated device, the actuated device comprising a piezoresistive (PR) material that has an electrical resistance dependent upon an applied pressure thereto; and a soft buffer structure formed around the PE material and PR material, the buffer structure disposed between the PE and PR materials and the stiffener structure, wherein the stiffener structure clamps both the PE and PR materials to a substrate over which the PE and PR materials are formed, and wherein the soft buffer structure permits the PE material freedom to move relative to the PR material, thereby coupling stress generated by an applied voltage to the PE material to the PR material so as change the electrical resistance of the PR material. | 2012-10-25 |
20120270354 | METHODS FOR FABRICATING SENSOR DEVICE PACKAGE USING A SEALING STRUCTURE - Fabrication methods are provided for a sensor device packages. An exemplary fabrication method involves bonding a sensor structure and another structure using a sealing structure. The sealing structure surrounds a diaphragm region of the sensor structure and provides an airtight seal between the sensor structure and the other structure to establish a fixed reference pressure on one side of the diaphragm region. | 2012-10-25 |
20120270355 | INERTIAL SENSOR AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is an inertial sensor, which includes a diaphragm having a piezoelectric element or a piezoresistive element formed on one surface thereof, a mass element integrated with the center of the other surface of the diaphragm in which the distal end of the mass element has a larger width than the width of the proximal end in contact with the diaphragm, and a supporter formed along the edge of the other surface of the diaphragm, so that the use of the mass element having the above shape results in decreased spring constant and increased distance from the center of the diaphragm to the center of the mass element, thereby simultaneously realizing a reduction in the size of the inertial sensor and an increase in performance thereof. A method of manufacturing the inertial sensor is also provided. | 2012-10-25 |
20120270356 | METHOD FOR MANUFACTURING A SOLAR CELL - The present invention provides a method for manufacturing a solar cell. The method for manufacturing a solar cell comprises: forming via holes in a silicon wafer; forming a shallow emitter on the front surface and the rear surface of the wafer, connecting the inner walls of the via holes and the via holes; and selectively forming an emitter through the heavy doping of a dopant to provide a plurality of regions along a direction linking the via holes of the shallow emitter with a certain concentration or higher. Accordingly, the present invention can selectively form an emitter on an MWT solar cell by performing laser doping or etching on a region contacting a front surface electrode having a certain width and height. | 2012-10-25 |
20120270357 | METHODS OF MANUFACTURING SOLAR ENERGY MODULES - A solar energy module includes one or more solar cells, each having a front side for receiving light and an opposite back side. An encapsulant material covers at least the front side of each of the solar cells. The solar energy module also includes a backskin layer formed from a cross-linked mixture of high density polyethylene (HDPE) and acid copolymer bonded to the back side of each of the solar cells. | 2012-10-25 |
20120270358 | Method for Fabrication of an Array of Chip-Sized Photovoltaic Cells for a Monolithic Low Concentration Photovoltaic Panel Based on Crossed Compound Parabolic Concentrators - Method for determining the dimensions of a plurality of chip-size photovoltaic cells diced out of a photovoltaic wafer, the method includes the procedures of determining the field of view angle of a plurality of crossed compound parabolic concentrators of an optical layer, determining the index of refraction of the material forming the optical layer, determining the dimensions of the optical entry aperture and the optical exit aperture of the crossed compound parabolic concentrators, as well as the distance separating the optical entry apertures of adjacent ones of the crossed compound parabolic concentrators, determining a dicing width for dicing the photovoltaic wafer into the plurality of chip-size photovoltaic cells, and determining the dimensions of the plurality of chip-size photovoltaic cells according to the dimensions of the optical entry aperture of the plurality of crossed compound parabolic concentrators, the distance separating the optical entry apertures of adjacent ones of the crossed compound parabolic concentrators, the index of refraction of the optical layer, the field of view angle of the plurality of crossed compound parabolic concentrators and according to the dicing width. | 2012-10-25 |
20120270359 | METHOD OF FORMING P-N JUNCTION IN SOLAR CELL SUBSTRATE - Embodiments of the present invention relate to a single step diffusion process used in selective emitter solar cell fabrication. In one embodiment, a dopant paste is selectively applied on a front surface of a substrate having opposite conductivity type from the dopant paste. The substrate is then exposed to a dopant containing vapor to deposit a doping layer having opposite conductivity type from the substrate on the front surface of the substrate. While the substrate is exposed to the dopant containing vapor, a portion of the dopant paste also contribute to deposition of the doping layer via gas phase transport of doping atoms from the dopant paste. The substrate is then heated in an atmosphere comprising oxygen and/or nitrogen to a temperature sufficient to cause the dopant atoms in the dopant paste and the doping layer to diffuse into the substrate, forming heavily and lightly doped emitter regions. | 2012-10-25 |
20120270360 | MULTIPLEXED OUTPUT TWO TERMINAL PHOTODIODE ARRAY FOR IMAGING APPLICATIONS AND RELATED FABRICATION PROCESS - A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel. | 2012-10-25 |
20120270361 | METHOD AND SYSTEM FOR LARGE SCALE MANUFACTURE OF THIN FILM PHOTOVOLTAIC DEVICES USING MULTI-CHAMBER CONFIGURATION - A method for large scale manufacture of photovoltaic devices includes loading a substrate into a load lock station and transferring the substrate in a controlled ambient to a first process station. The method includes using a first physical deposition process in the first process station to cause formation of a first conductor layer overlying the surface region of the substrate. The method includes transferring the substrate to a second process station, and using a second physical deposition process in the second process station to cause formation of a second layer overlying the surface region of the substrate. The method further includes repeating the transferring and processing until all thin film materials of the photovoltaic devices are formed. In an embodiment, the invention also provides a method for large scale manufacture of photovoltaic devices including feed forward control. | 2012-10-25 |
20120270362 | NEW INTRINSIC ABSORBER LAYER FOR PHOTOVOLTAIC CELLS - So as to manufacture an intrinsic absorber layer of amorphous hydrogenated silicon within a p-i-n configuration a solar cell by PeCvD deposition upon a base structure, thereby improving throughput an simultaneously maintaining quality of the absorber layer, a specific processing regime is proposed, wherein in the reactor for depositing the addressed absorber layer a pressure of between 1 mbar and 1.8 mbar is established and a flow of silane and of hydrogen with a dilution of silane to hydrogen of 1:4 up to 1:10 and generating an RF plasma with a generator power of between 600W and 1200W per 1.4 m | 2012-10-25 |
20120270363 | MULTI-NARY GROUP IB AND VIA BASED SEMICONDUCTOR - Methods and devices are provided for forming an absorber layer. In one embodiment, a method is provided comprising of depositing a precursor material onto a substrate, wherein the precursor material may include or may be used with an additive to minimize concentration of group IIIA material such as Ga in the back portion of the final semiconductor layer. The additive may be a non-copper Group IB additive in elemental or alloy form. Some embodiments may use both selenium and sulfur | 2012-10-25 |
20120270364 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device includes a semiconductor substrate having at least one surface provided with a semiconductor element, wherein the semiconductor substrate includes a region of a first conductivity type, the region being formed in a surface layer portion of the semiconductor substrate; a first diffusion region of a second conductivity type, the first diffusion region having a first impurity concentration and being formed in the surface layer portion, and a pn junction being formed between the first diffusion region and the region of the first conductivity type; and a first metal silicide film formed on part of a portion of the surface corresponding to the first diffusion region. | 2012-10-25 |
20120270365 | METHOD FOR MANUFACTURING SOLAR CELL - A method for manufacturing a solar cell according to an exemplary embodiment includes: forming a first doping film on a substrate; patterning the first doping film so as to form a first doping film pattern and so as to expose a portion of the substrate; forming a diffusion prevention film on the first doping film pattern so as to cover the exposed portion of the substrate; etching the diffusion prevention film so as to form spacers on lateral surfaces of the first doping film pattern; forming a second doping film on the first doping film pattern so as to cover the spacer and exposed substrate; forming a first doping region on the substrate surface by diffusing an impurity from the first doping film pattern into the substrate; and forming a second doping region on the substrate surface by diffusing an impurity from the second doping film pattern into the substrate. | 2012-10-25 |
20120270366 | Layered Contact Structure For Solar Cells - Formulations and methods of making semiconductor devices and solar cell contacts are disclosed. The invention provides a method of making a semiconductor device or solar cell contact including ink jet printing onto a silicon wafer an ink composition, typically including a high solids loading (20-80 wt %) of glass frit and preferably a conductive metal such as silver. The wafer is then fired such that the glass frit fuses to form a glass, thereby forming a contact layer to silicon. | 2012-10-25 |
20120270367 | Component Stacking for Integrated Circuit Electronic Package - Component stacking for increasing packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a component layer parallel to and aligned with a surface area of the substrate. An integrated circuit die is positioned adjacent to the component layer such that a face of the die is substantially parallel to the surface area of the substrate. The face of the die is aligned with at least a portion of the component layer, and terminals of the die are connected to the substrate. | 2012-10-25 |
20120270368 | MOLD ARRAY PROCESS METHOD TO ENCAPSULATE SUBSTRATE CUT EDGES - Disclosed is a mold array process (MAP) method to encapsulate cut edges of substrate units. A substrate strip includes a plurality of substrate units arranged in a matrix. Scribe lines are defined between adjacent substrate units and at the peripheries of the matrix where pre-cut grooves are formed along the scribe lines with a width greater than the width of the scribe lines. An encapsulant is formed on the matrix of the substrate strip to continuously encapsulate the substrate units and the scribe lines to enable the encapsulant to fill into the pre-cut grooves to further encapsulate the cut edges of the substrate units. The cut edges of the substrate units are still encapsulated by the encapsulant even after singulation processes where substrate units are singulated into individual semiconductor packages to prevent the exposure of the plated traces of the substrate units to enhance the moisture resistance capability of the semiconductor packages. | 2012-10-25 |
20120270369 | Methods for Lead Free Solder Interconnections for Integrated Circuits - Methods for forming lead free solder interconnections for integrated circuits. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of material is formed on the input/output terminal of the integrated circuit. A lead free solder connector is formed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. An intermetallic compound is formed at the interface between the cap layer and the lead free solder connector. A solder connection is formed between input/output terminal of the integrated circuit and the metal finish pad that is less than 0.5 weight percent copper, and the intermetallic compound is substantially free of copper. | 2012-10-25 |
20120270370 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A disclosed semiconductor device includes a wiring board, a semiconductor element mounted on a principal surface of the wiring board with flip chip mounting, a first conductive pattern formed on the principal surface along at least an edge portion of the semiconductor element, a second conductive pattern formed on the principal surface along the first conductive pattern and away from the first conductive pattern, a passive element bridging between the first conductive pattern and the second conductive pattern on the principal surface of the wiring board, and a resin layer filling a space between the wiring board and the semiconductor chip, wherein the resin layer extends between the semiconductor element and the first conductive pattern on the principal surface of the wiring board. | 2012-10-25 |
20120270371 | Method for Encapsulating Microelectronic Devices - According to an embodiment disclosed herein, a microelectronic device to be encapsulated is built on, or alternatively in, a substrate. The device is then coated with a sacrificial layer. A lid layer is deposited over the sacrificial layer, and then appropriately perforated to optimize the removal of the sacrificial layer. The sacrificial layer is then removed using one of several etching or other processes. The perforations in the lid layer are then sealed using a viscous sealing material, thereby fixing the environment that encapsulates the device. The sealing material is then cured or hardened. An optional moisture barrier may be deposited over the cured sealing layer to provide further protection for the encapsulation if needed. | 2012-10-25 |
20120270372 | ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer. | 2012-10-25 |
20120270373 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer. | 2012-10-25 |
20120270374 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - A method of producing a semiconductor device including a MOS transistor includes steps of forming a plurality of pillar semiconductor layers and forming a gate electrode formed around each of the pillar-shaped semiconductor layers. The method also includes steps of forming a source or drain region in an upper portion of each of the pillar-shaped semiconductor layers and forming a first silicide layer for connecting at least a part of a surface of a drain or source region formed in a planar semiconductor layer. | 2012-10-25 |
20120270375 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a semiconductor device which prevents defects and achieves miniaturization. A projecting portion or a trench (a groove portion) is formed in an insulating layer and a channel formation region of a semiconductor layer is provided in contact with the projecting portion or the trench, so that the channel formation region is extended in a direction perpendicular to a substrate. Thus, miniaturization of the transistor can be achieved and an effective channel length can be extended. In addition, before formation of the semiconductor layer, an upper-end corner portion of the projecting portion or the trench with which the semiconductor layer is in contact is subjected to round chamfering, so that a thin semiconductor layer can be formed with good coverage. | 2012-10-25 |
20120270376 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE COMPRISING A DUMMY WELL - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well. | 2012-10-25 |
20120270377 | METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE - A method of fabricating a semiconductor structure, in which after an etching process is performed to form at least one recess within a semiconductor beside a gate structure, a thermal treatment is performed on the recess in a gas atmosphere including an inert gas before a silicon-containing epitaxial layer is formed in the recess through an epitaxy growth process. | 2012-10-25 |
20120270378 | Method for Producing Silicon Semiconductor Wafers Comprising a Layer for Integrating III-V Semiconductor Components - The invention relates to a method for producing silicon semiconductor wafers and components having layer structures of III-V layers for integrating III-V semiconductor components. The method employs SOI silicon semiconductor wafers having varying substrate orientations, and the III-V semiconductor layers are produced in trenches ( | 2012-10-25 |
20120270379 | METHOD OF FABRICATING A DUMMY GATE STRUCTURE IN A GATE LAST PROCESS - A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate. | 2012-10-25 |
20120270380 | METHOD FOR FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE - A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate. A liner layer that includes a liner nitride layer and a liner oxide layer is formed on an exposed surface of the trench. A flowable insulation layer is formed to fill the trench. The flowable insulation layer is recessed to expose a portion of the liner nitride layer on an upper portion of the trench. A first preheating process is performed to release stress of the liner layer. A second preheating process is performed to oxidize the exposed liner nitride layer. A buffer layer is formed on a portion of the liner layer that is formed on a sidewall of the trench and exposed after the flowable insulation layer is recessed. The buffer layer is etched to smoothen a rough portion of the liner layer that is formed when the flowable insulation layer is recessed. A buried insulation layer is deposited in the trench. | 2012-10-25 |
20120270381 | DIE ATTACH FILM - Provided are a die attach film, a semiconductor wafer, and a semiconductor packaging method. The die attach film can prevent generation of burrs or scattering of chips in a dicing process, and exhibits excellent expandability and pick-up characteristics in a die pressure-sensitive adhesive process. Further, the die attach film can prevent release, shifting, or deflection of a chip in a wire pressure-sensitive adhesive or molding process. Thus, it is possible to improve embeddability, inhibit warpage of a wafer or wiring substrate, and enhance productivity in a semiconductor packaging process. | 2012-10-25 |
20120270382 | METHOD OF FABRICATING AN EPITAXIAL LAYER - A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C. | 2012-10-25 |
20120270383 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND PLASMA OXIDATION TREATMENT METHOD - Provided is a method for manufacturing a semiconductor device, in which a degradation of characteristics of a thin film transistor can be suppressed by performing plasma oxidation treatment on a gate insulating film containing nitrogen. An embodiment of the present invention is a method for manufacturing a semiconductor device comprising a thin film transistor including a gate electrode, a gate insulating film containing nitrogen, and a channel region in microcrystalline semiconductor films. The method includes the steps of performing plasma treatment on the gate insulating film in an oxidizing gas atmosphere containing hydrogen and an oxidizing gas containing an oxygen atom, and forming the microcrystalline semiconductor film over the gate insulating film. Formula (1), a/b≧2, and Formula (2), b>0, are satisfied, where the amount of hydrogen and the amount of the oxidizing gas in the oxidizing gas atmosphere are a and b, respectively. | 2012-10-25 |
20120270384 | APPARATUS FOR DEPOSITION OF MATERIALS ON A SUBSTRATE - Methods and apparatus for deposition of materials on a substrate are provided herein. In some embodiments, an apparatus for processing a substrate may include a process chamber having a substrate support disposed therein to support a processing surface of a substrate, an injector disposed to a first side of the substrate support and having a first flow path to provide a first process gas and a second flow path to provide a second process gas independent of the first process gas, wherein the injector is positioned to provide the first and second process gases across the processing surface of the substrate, a showerhead disposed above the substrate support to provide the first process gas to the processing surface of the substrate, and an exhaust port disposed to a second side of the substrate support, opposite the injector, to exhaust the first and second process gases from the process chamber. | 2012-10-25 |
20120270385 | SWITCHING DEVICE HAVING A MOLYBDENUM OXYNITRIDE METAL GATE - A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate. | 2012-10-25 |
20120270386 | METHOD FOR PREPARING CONTACT PLUG STRUCTURE - In a further embodiment of the present invention, a method for preparing a contact structure includes the steps of forming a conductive stack on the semiconductor substrate; forming a patterned mask on the conductive stack; forming a depression in an upper portion of the conductive stack; forming a spacer layer on the surface of the depression and the patterned mask; forming a mask block filling the depression; removing a portion of the spacer layer not covered by the mask block; and removing a portion of the conductive stack by using the mask block and the patterned mask to form the contact structure including at least one tall contact plug under the patterned mask and at least one the short contact plug under the mask block. | 2012-10-25 |
20120270387 | METHOD AND STRUCTURE FOR IMPROVED FLOATING GATE OXIDE INTEGRITY IN FLOATING GATE SEMICONDUCTOR DEVICES - Methods for forming floating gate transistors provide for using a self-aligned plug formed over a floating gate electrode without use of an additional photolithography operation. The plug is centrally disposed and is formed and aligned using spacers. The spacers are formed alongside edges of a patterned sacrificial, oxidation resistant layer that includes an opening that defines the floating gate region. The plug may be formed of a silicon material and which becomes oxidized along with the floating gate such that the plug eventually forms part of the floating gate electrode or the plug may be formed of a nitride or other oxidation resistant material to retard or prevent oxidation in the central portion of the floating gate in which the plug is aligned. | 2012-10-25 |
20120270388 | ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress. | 2012-10-25 |
20120270389 | METHOD FOR MANUFACTURING INTERCONNECTION STRUCTURE AND OF METAL NITRIDE LAYER THEREOF - A method for manufacturing a metal nitride layer including the following steps is provided. Firstly, a substrate is provided. Then, a physical vapor deposition process is performed at a temperature between 210° C. and 390° C. to form a metal nitride layer on the substrate. Also, the physical vapor deposition process can be performed on a pressure between 21 mTorr and 91 mTorr. The method can be used in the manufacturing process of an interconnection structure for decreasing the film stress of the metal nitride layer. Therefore, the interconnection structure can be prevented from line distortion and film collapse. | 2012-10-25 |
20120270390 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP. | 2012-10-25 |
20120270391 | SCHEME FOR PLANARIZING THROUGH-SILICON VIAS - Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method disclosed herein includes forming a layer of isolation material above a via opening formed in a semiconductor device, the via opening extending into a substrate of the semiconductor device. The method also includes performing a first planarization process to remove at least an upper portion of the layer of isolation material formed outside of the via opening, and forming a conductive via element inside of the via opening after performing the first planarization process. | 2012-10-25 |
20120270392 | FABRICATING METHOD OF ACTIVE DEVICE ARRAY SUBSTRATE - A fabricating method of an active device array substrate is provided. The active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°. | 2012-10-25 |
20120270393 | METAL SILICIDE, METAL GERMANIDE, METHODS FOR MAKING THE SAME - In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD. | 2012-10-25 |
20120270394 | METHOD OF BEVEL TRIMMING THREE DIMENSIONAL SEMICONDUCTOR DEVICE - A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias. | 2012-10-25 |
20120270395 | METHOD FOR FABRICATING METAL PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a metal pattern in a semiconductor device includes forming a metal layer over a substrate, forming a hard mask layer over the metal layer, forming a sacrifice pattern over the hard mask layer, forming a spacer pattern on sidewalks of the sacrifice pattern, removing the sacrifice pattern, forming a hard mask pattern by etching the hard mask layer using the spacer pattern as an etch barrier, forming an etching protection layer over the hard mask pattern and on sidewalks of the hard mask pattern, and forming the metal pattern by performing primary and secondary etching processes on the metal layer using the etching protection layer as an etch barrier. | 2012-10-25 |
20120270396 | ETCHANT AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SAME - Disclosed are an etchant which is used for the manufacture of a semiconductor device using a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel, and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant to be used for the manufacture of a semiconductor device using a semiconductor substrate having an electrode, including hydrogen peroxide, an organic acid, and an organic phosphonic acid, wherein the organic acid is at least one member selected from citric acid and malic acid; a content of hydrogen peroxide is from 0.75 to 12% by mass; a content of the organic acid is from 0.75 to 25% by mass; and a content of the organic phosphonic acid is from 0.0005 to 1% by mass, and a method for manufacturing a semiconductor device using the etchant. | 2012-10-25 |
20120270397 | Photomask and Method for Fabricating Source/Drain Electrode of Thin Film Transistor - A method is provided for fabricating source/drain electrodes of a thin film transistor. The method generally provides a substrate having a first gate electrode and a second gate electrode adjacent and electrically connected. The method further provides coating a photoresist layer on the metal layer, and performing an exposure process on the photoresist layer by a photomask. The method further performs a development process on the exposed photoresist layer to form a photoresist pattern layer with different thicknesses on the metal layer, and then etches the metal layer using the photoresist pattern layer as an etch mask, to form a pair of first source/drain electrodes on the first gate electrode and a pair of second source/drain electrodes on the second gate electrode. | 2012-10-25 |
20120270398 | PLANARIZATION METHOD FOR HIGH WAFER TOPOGRAPHY - A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed. | 2012-10-25 |
20120270399 | SLURRY COMPOSITION FOR CMP, AND POLISHING METHOD - The present invention relates to a CMP slurry composition comprising an abrasive particle; a dispersant; an ionic polymer additive; and a non-ionic polymer additive including a polyolefin-polyethylene glycol copolymer including at least two polyethylene glycol repeat unit as a backbone and at least a polyethylene glycol repeating unit as a side chain, and a polishing method with using the slurry composition. The CMP slurry composition shows a low polishing rate to a single-crystalline silicon layer or a polysilicon layer and a high polishing rate to a silicon oxide layer, resulting in having an excellent polishing selectivity. | 2012-10-25 |
20120270400 | SLURRY FOR CHEMICAL MECHANICAL POLISHING AND POLISHING METHOD FOR SUBSTRATE USING SAME - The present invention provides a slurry for chemical mechanical polishing comprising water-soluble clathrate compound (a), polymer compound (b) having an acidic group optionally in a salt form as a side chain, polishing abrasive grain (c) and water (d), wherein the content of the water-soluble clathrate compound (a) is 0.001 mass %-3 mass % of the total amount of the slurry, the polymer compound (b) has a weight average molecular weight of not less than 1,000 and less than 1,000,000, and the content of the polymer compound (b) is 0.12 mass %-3 mass % of the total amount of the slurry, and a polishing method for substrate using the slurry. | 2012-10-25 |
20120270401 | CHEMICAL MECHANICAL POLISHING SLURRY, ITS PREPARATION METHOD AND USE FOR THE SAME - A chemical mechanical polishing slurry for polishing a copper layer without excessively or destructively polishing a barrier layer beneath the copper layer is disclosed and includes an acid, a surfactant, and a silica sol having silica polishing particles that are surface modified with a surface charge modifier and that have potassium ions attached thereto. A method for preparing the chemical mechanical polishing slurry and a chemical mechanical polishing method using the chemical mechanical polishing slurry are also disclosed. | 2012-10-25 |
20120270402 | METHOD OF MAKING AN ARRAY COLUMNAR HOLLOW SEMICONDUCTOR STRUCTURE - A method of making an array columnar hollow semiconductor structure includes: providing an oxide layer; placing a chromeless mask on the oxide layer, wherein the chromeless mask is a bank-shaped frame; forming a silicone nitride layer to cover the first partial top surface of the oxide layer and the whole outer surface of the bank-shaped frame; removing one part of the silicone nitride layer to expose a second partial top surface of the oxide layer and a top surface of the bank-shaped frame; removing the bank-shaped frame to expose a third partial top surface of the oxide layer; removing a first part of the oxide layer under the second partial top surface and a second portion of the oxide layer under the third partial top surface to form a plurality of columnar hollow bodies; and removing the other silicone nitride layer to completely expose the columnar hollow bodies. | 2012-10-25 |
20120270403 | METHOD OF FABRICATING OPENINGS - A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed. | 2012-10-25 |
20120270404 | METHODS FOR ETCHING THROUGH-SILICON VIAS WITH TUNABLE PROFILE ANGLES - The present disclosure provides methods for etching through-silicon vias (TSVs) in a substrate. The method employs a cyclic polymer passivation layer deposition, depassivation process and plasma etching process. By alternating the duration performed in the plasma etching process and the polymer passivation deposition process during the TSVs formation process, a good sidewall profile and via depth control may be obtained. | 2012-10-25 |
20120270405 | SYSTEMS AND METHODS FOR EXPOSING SEMICONDUCTOR WORKPIECES TO VAPORS FOR THROUGH-HOLE CLEANING AND/OR OTHER PROCESSES - Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other processes are disclosed. A representative method includes exposing a semiconductor workpiece to a vapor, with the semiconductor workpiece having an opening extending from a first surface of the workpiece through the workpiece to a second surface facing opposite from the first surface. The opening can include a contaminant, and the method can further include drawing the vapor and the contaminant through at least a portion of the opening and away from the second surface of the semiconductor workpiece. | 2012-10-25 |
20120270406 | CLEANING METHOD OF PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus in which a cleaning method is performed includes a plasma generating chamber, having a silicon-containing member, for generating therein plasma by exciting a processing gas; a plasma processing chamber communicating with the plasma generating chamber via a partition member; and a high frequency antenna, having a planar shape, provided at an outside of a dielectric window of the plasma generating chamber. The cleaning method includes exciting a hydrogen-containing processing gas into plasma in the plasma generating chamber, introducing hydrogen radicals in the plasma into the plasma processing chamber through the partition member, performing a plasma process on a processing target substrate by allowing the hydrogen radicals to act on the processing target substrate, unloading the processing target substrate, and removing silicon-based deposits generated in the plasma generating chamber by introducing a tetrafluoride (tetrafluoromethane) gas into the plasma generating chamber. | 2012-10-25 |
20120270407 | SUSCEPTOR FOR SUPPORTING A SEMICONDUCTOR WAFER AND METHOD FOR DEPOSITING A LAYER ON A FRONT SIDE OF A SEMICONDUCTOR WAFER - A susceptor for supporting a semiconductor wafer during deposition of a layer on a front side of the semiconductor wafer, the semiconductor wafer having a diameter D and, at its edge, a notch having a depth T, comprising:
| 2012-10-25 |
20120270408 | MANUFACTURING METHOD OF GATE DIELECTRIC LAYER - A manufacturing method of a gate dielectric layer that includes a nitride layer and an oxide layer is provided. A substrate is provided. A nitridation treatment is performed to form the nitride layer on the substrate. An oxidation treatment is performed subsequent to the formation of the nitride layer to form the oxide layer between the nitride layer and the substrate. | 2012-10-25 |
20120270409 | Methods For Manufacturing High Dielectric Constant Films - Provided are methods for depositing a cerium doped hafnium containing high-k dielectric film on a substrate. The reagents of specific methods include hafnium tetrachloride, an organometallic complex of cerium and water. | 2012-10-25 |
20120270410 | METHOD FOR FORMING THE GATE INSULATOR OF A MOS TRANSISTOR - A method for forming the gate insulator of a MOS transistor, including the steps of: a) forming a thin silicon oxide layer at the surface of a semiconductor substrate; b) incorporating nitrogen atoms into the silicon oxide layer by plasma nitridation at a temperature lower than 200° C., to transform this layer into a silicon oxynitride layer; and c) coating the silicon oxynitride layer with a layer of a material of high dielectric constant, wherein steps b) and c) follow each other with no intermediate anneal step. | 2012-10-25 |
20120270411 | MANUFACTURING METHOD OF GATE DIELECTRIC LAYER - A manufacturing method of a gate dielectric layer is provided. An oxidation treatment is performed to form an oxide layer on a substrate. A nitridation treatment is performed to form a nitride layer on the oxide layer. An annealing treatment is performed in a mixing gas of N | 2012-10-25 |
20120270412 | OXIDIZING METHOD AND OXIDIZING APPARATUS - An oxidizing method and oxidizing apparatus in which a plasma generating chamber having an oxidizing gas supply port and a substrate processing chamber having an exhaust port and internally having a substrate susceptor are connected via a partition having a number of through holes, a plasma of an oxidizing gas supplied into the plasma generating chamber is generated, and an oxide layer is formed on a substrate surface by supplying the generated active species onto a substrate are characterized in that the partition is connected to a power supply via a switching mechanism such that a positive, negative, or zero voltage is applied to the partition, and an oxidation process is performed by changing the ratio of radicals, positive ions, and negative ions in the active species supplied onto the substrate by switching the voltages at least once during the oxidation process. | 2012-10-25 |
20120270413 | Silicon Nitride Film, A Semiconductor Device, A Display Device and a Method for Manufacturing a Silicon Nitride Film - The present invention provides a method for forming by plasma CVD a silicon nitride film that can be formed over heat-sensitive elements as well as an electroluminescent element and that has favorable barrier characteristics. Further, the present invention also provides a semiconductor device, a display device and a light-emitting display device formed by using the silicon nitride film. In the method for forming a silicon nitride film by plasma CVD, silane (SiH | 2012-10-25 |
20120270414 | Freely Rotatable Electrical Conduction Structure And Receptacle Using The Same - The present invention provides a freely rotatable electrical conduction structure including at least two cylindrical electrical conduction portions, an insulated material portion and at least two electrical conduction terminals. The at least two cylindrical electrical conduction portions are arranged separately along an axis, wherein the inner surface of each cylindrical electrical conduction portion is welded with an end of a conducting wire. The insulated material portion is combined with the at least two cylindrical electrical conduction portions via injection molding to form a circular shaft assembly. The at least two electrical conduction terminals correspond to the at least two cylindrical electrical conduction portions respectively, and each electrical conduction terminal partially projects to form an arc contact portion configured to abut onto the outer peripheral surface of its corresponding cylindrical electrical conduction portion. Each electrical conduction terminal is allowed to rotate around its corresponding cylindrical electrical conduction portion with its arc contact portion keeping contacting and conducting with the outer peripheral surface. | 2012-10-25 |
20120270415 | PROCESS OF FABRICATING A SLIP RING COMPONENT, A SLIP RING COMPONENT AND MOLDED INTERCONNECT DEVICE INCLUDING A SLIP RING COMPONENT - A process of fabricating a slip ring component, a slip ring component, and a slip ring assembly are disclosed. The process includes forming a first shot, forming a second shot, and immersion bathing the first shot and the second shot. The immersion bathing applies an electrically conductive plating to exposed surfaces of the second shot. | 2012-10-25 |
20120270416 | REORIENTABLE ELECTRICAL RECEPTACLE - There is provided systems and methods for a reorientable electrical outlet. In one embodiment, a system includes a housing configured to be coupled to an electrical power source, the housing having a first rotation stop, and an electrical plug receptacle, mountable within the housing, the insert having a second rotation stop, the first and second rotation stops configured to cooperate with each other to limit rotation of the insert within the aperture at a number of degrees, wherein the plug receptacle is configured to receive an electrical plug. | 2012-10-25 |
20120270417 | COMPUTER POWER SUPPLY UNIT - A Plug and Play adaptor for adding a PSU to a first PSU in a computer system. An ATX connector and a relay are contained in the adaptor. A second PSU can be added via the ATX connector in a plug-and-play manner, and the relay is energized and closes its circuit when it is powered by the first PSU and therefore turns on the second PSU through the ATX connector. | 2012-10-25 |
20120270418 | PRINTED CIRCUIT BOARD USED IN SERVER - A printed circuit board used in server, which has a golden finger interface at one side thereof. The golden finger interface includes a plurality of parallelly arranged metal sheets which conform to the USB standard. The golden finger interface is used to be engaged with a USB socket for transmitting the electrical signal. | 2012-10-25 |
20120270419 | UNIVERSAL CONNECTOR - Circuits, methods, and apparatus that limit the number of types of connectors needed by an electronic device. One example may provide a connector receptacle capable of adapting to multiple types of connector inserts. In this way, connector inserts conveying one of a number of interfaces can be accepted by the same connector receptacle. This may reduce the number and types of connector receptacles needed on an electronic device. | 2012-10-25 |
20120270420 | Board Mounted Connector - A board mounted connector is provided in which a skew occurrence can be prevented between adjacent sets of contacts. The board mounted connector having a housing and a plurality of contacts provided in the housing that are connected to a printed circuit board. Each of the plurality of contacts include a contact portion, a securing portion, and a board connecting portion that connect to the printed circuit board. The plurality of contacts include a first signal contact and a second signal contact positioned next to the first signal contact such that the first signal contact and the second signal contact form a first set of signal contacts positioned along the printed circuit board. The first signal contact is arranged on an inner side of the printed circuit board while the second signal contact is arranged on an outer side of the printed circuit board. | 2012-10-25 |
20120270421 | FASTENING DEVICE AND PRINTED CIRCUIT BOARD ASSEMBLY HAVING SAME - A PCB assembly includes an FPCB, a connector, a rigid PCB, and a fastening device. The rigid PCB includes a loading surface, a bottom surface opposite to the loading surface, and two pins protruding from the bottom surface. The loading surface contacts the FPCB. The FPCB is electrically connected to the rigid PCB through the connector. The fastening device includes a pressing plate, two fastening bars and two connecting arms. The pressing plate includes a pressing surface contacting the FPCB. The fastening bars are parallel to the pressing surface. Each fastening bar includes a hook grappling with a corresponding pin. Each hook includes a resisting surface resisting on the bottom surface. Each connecting arm connects the pressing plate and a corresponding fastening bar. | 2012-10-25 |
20120270422 | VERTICAL CONNECTOR AND ASSEMBLY HAVING THE SAME - A vertical connector including an insulating body, a conductive casing and a terminal set. The insulating body has a plurality of spaced formed terminal grooves thereon. The conductive casing is assembled with the insulating body and has an insertion opening. The terminal set has a plurality of terminals disposed on the terminal grooves. Each terminal has a fixing segment assembled on the bottom surface of the insulating body, an extending segment formed by bending the free end of the fixing segment toward the insertion opening and a connecting segment formed by extending from the free end of the extending segment. | 2012-10-25 |
20120270423 | MALE CONNECTOR BLOCK, FEMALE CONNECTOR BLOCK, AND CONNECTOR - The connector includes a male connector block and a female connector block. The male connector block includes a base substrate formed of an insulating flat member; a conductive projection arranged on one surface of the base substrate; a first circuit pattern led out from the conductive projection; and a soldering terminal section electrically connected to the conductive projection through the first circuit pattern. The female connector block includes: an insulating film having a fitting insertion section; a conductive section formed on one surface of the insulating film and electrically connected to the conductive projection inserted into the fitting insertion section; a second circuit pattern led out from the conductive section; a soldering terminal section electrically connected to the conductive section through the second circuit pattern; and a second base substrate making close contact with the other surface of the insulating film. | 2012-10-25 |
20120270424 | EDGE CONNECTOR FOR SHIELDED ADAPTER - Electrical connections that provide a highly manufacturable, well-shielded path from a cable to a printed circuit board. One example provides a path that includes a card and a connector. Conductors in a cable may be attached to a card. The card may be shielded with a ground plane on one or more sides and edges. The card may insert into a connector that may be attached to a printed circuit board. The connector may include a shield that may have a top portion that forms electrical contact with a ground plane on a top of a card inserted in the connector. The connector may have an opening for accepting the card that is defined by the top portion of the shield and a plurality of rows of contacts. The rows of contacts may include an outer row of ground contacts, and an inner row of signal contacts. | 2012-10-25 |
20120270425 | METALLIC BOSS - A bi-metallic boss is provided. The bi-metallic boss includes a first portion and a second portion. The first portion is made of a first metal powder. The second portion is integrated with the first portion. Moreover, the second portion made of a second metal powder, such that the second metal powder is different from the first metal powder. | 2012-10-25 |
20120270426 | REPLACEABLE CONNECTION FOR PORTABLE ELECTRONIC DEVICES - Systems and methods electrically connect a first electronic device or electrical component, having a external electrical connector, to a circuit board of a second electronic device. A low-cost, user-installable connection system isolates mechanical stresses imposed on the external electrical connector to within the user-installable connection system, thereby preventing the mechanical stresses from reaching the circuit board in the second electronic device. If the connection becomes faulty, only the low-cost, user-installable connection system must be replaced. | 2012-10-25 |
20120270427 | Block-Out Cover and Removal Tool - A block-out cover is installed in a jack module to prevent entry of undesirable objects. The block-out cover includes at least one window and at least one locking arm. The locking arm secures the cover to the jack module. The window receives a removal tool designed to remove the cover from the jack module. The removal tool includes a body, a lever secured to the body to engage the cover and a prong with a cam surface. The cam surface of the prong deflects the cover from locking engagement with the jack module allowing the removal tool to remove the block-out cover. | 2012-10-25 |
20120270428 | COAXIAL CABLE CONNECTOR HAVING ELECTRICAL CONTINUITY MEMBER - A coaxial cable connector comprising a connector body; a post engageable with the connector body; a nut, rotatable with respect to the post and the connector body, the nut having a first end and an opposing second end, wherein the nut includes an internal lip; and a continuity member disposed within a second end portion of the nut and contacting the post and the nut, so that the continuity member extends electrical grounding continuity through the post and the nut is provided. | 2012-10-25 |
20120270429 | LOCK STRUCTURE OF PLUG OF CABLE - The present invention provides a lock structure of plug of cable including a main body and a key. The main body has a locking area, an elastic area with an elastic element, and a lower room which is able to receive a plug of cable. The elastic element tends to stay at a first position. When the key is not inserted into the locking area, the elastic element is at the first position, and a latch of the plug of the cable is unable to be compressed due to the fixation by the elastic element. When the key is inserted into the locking area and is rotated, the elastic element is pushed to a second position, and the latch is able to be compressed. Thereby, the lock structure of plug of cable can be used to control the availability of the plug for a jack. | 2012-10-25 |
20120270430 | CONNECTOR - A connector includes a housing, a cavity formed in the housing, a terminal to which a cable is connected and which is inserted into the cavity from a rear end side of the housing, and a nut held at a front end portion of the housing, wherein the terminal has a plate-like connection portion extended in an insertion direction to the cavity and an insertion hole formed in the connection portion, and the connection portion, which is inserted into the cavity and protruded from a front end portion of the housing, is bent and arranged along a front end surface of the housing, whereby the insertion hole is communicated with an internal thread of the nut. | 2012-10-25 |
20120270431 | MULTI-PORT CONNECTOR ASSEMBLY - A multi-port connector assembly includes a housing that has a front end and a back end. The housing has a plurality of openings therethrough that extend between the front end and the back end. The housing has a shelf that extends from the back end. The shelf has a plurality of channels formed therein. A plurality of contact subassemblies are received in corresponding openings. The contact subassemblies have center conductors and outer shells surrounding the center conductors. The outer shells have rails that extend outward therefrom. The rails are received in corresponding channels to orient the contact subassemblies with respect to the housing. | 2012-10-25 |
20120270432 | SOLDERLESS ELECTRICAL CONNECTION - The invention relates to a solderless electrical connection ( | 2012-10-25 |
20120270433 | HARNESS CONNECTOR - A harness connector having a header assembly that includes a header housing that extends between a plug end and a mounting end. The header housing holds header contacts. Optionally, the header housing may be mounted to a printed circuit board at the mounting end with the header contacts being electrically connected to the printed circuit board. One or more plug assemblies are received in the plug end of the header housing along a plug axis. The plug assembly includes a plug housing holding receptacle terminals. The receptacle terminals extend along terminal axes parallel to the plug axis between mating ends and terminating ends. The mating ends are mated with corresponding header contacts. The terminating ends have insulation displacement contacts configured to receive, and be electrically connected to, corresponding wires. The wires extend from the insulation displacement contacts along wire axes that are generally perpendicular to the terminal axes. | 2012-10-25 |
20120270434 | CABLE CLAMP FOR CABLE CONNECTOR - A cable connector includes a cable clamp having a cable end and a mating end. The cable clamp has an upper housing and a lower housing joined to the upper housing. An aperture is formed in at least one of the upper housing or the lower housing. The upper housing and the lower housing are moveable between a pre-assembled position and an assembled position. An insert is provided having a wire end and a mating end. The insert has a tab configured to engage the aperture to secure the insert within the mating end of the cable clamp in the pre-assembled position. The upper housing and the lower housing are moveable to the assembled position to retain the insert within the mating end of the cable clamp and a cable within the cable end of the cable clamp. | 2012-10-25 |
20120270435 | ELECTRICAL SAFETY PLUG WITH GRIP WINGS FOR ELECTRICAL PLUGS AND DATA CORD PLUGS - The grip wings provide a push/pull insertion and withdrawal of plugs that eliminates the need for grip strength; obvious visual and tactile alignment of plugs; a finger stop that is safely away from the prongs of the plug. These features are provided while preserving the original cord/plug integrity; adapting to the international variety of existing plugs; allowing fit in multiple close outlets; giving easy installation; and enduring for the life of the plug. The grip wings consist of a rigid bar positioned perpendicular to the line of the cord and plug, and an attachment of the bar to the plug. The grip wings can be provided as either an accessory to existing plugs or included in the original manufacturing of the plug. The grip wings are adaptable to consumer or industrial use. It is adaptable to options for shape, texture, appearance, self-illumination, and orientation to appeal to many markets. | 2012-10-25 |
20120270436 | IDENTIFYING INDIVIDUAL COPPER NETWORK CABLES ON A PATCH PANEL - Cables of large scale network installation are efficiently identified for labeling or verification or correct connection in relation to the patch panel of a distribution frame by providing transmitter at each remote cable end to be tested and light identification devices (LIDs) as plugs at patch panel ports, the transmitter providing closed circuit activation at a patch panel end to light up a LID plug at the patch panel port end of the cable. | 2012-10-25 |
20120270437 | CIRCUIT ELEMENT COUPLING DEVICES AND METHODS FOR FLEXIBLE AND OTHER CIRCUITS - Embodiments relate to coupling and/or holding devices for electrically and/or mechanically contacting circuit elements, such as power sources, sensors, transducers and other devices. In one embodiment, a coupling device comprises a substrate having at least one printed conductive element and at least one fold, flap, slit, slot, perforation or other alteration configured to encourage contact between a circuit element, such as a battery, sensor, transducer or other element, and the at least one printed conductive element. | 2012-10-25 |
20120270438 | CONNECTOR CONTACT FOR TUBULAR CENTER CONDUCTOR - A contact assembly for connecting a cable connector to a tubular center conductor of a coaxial cable includes a contact pin, a core insert, and a guided insert. The contact pin includes a proximal end, an opposing distal end, and an intermediate segment therebetween. The contact pin defines a first internal cavity on the proximal end having an inner diameter. The contact pin further includes a central bore extending from the first internal cavity into the intermediate segment. The core insert includes a proximal end, an opposing distal end, and a support section therebetween. The support section includes an axial section having a diameter greater than the distal end, and the distal end is configured for coupling with the central bore of the contact pin. The guided insert includes a body having a proximal end, an opposing distal end, and defines a central cavity at least on the distal end. The central cavity has an inner diameter smaller than the diameter of the core insert support section. | 2012-10-25 |
20120270439 | COAXIAL CABLE CONNECTOR HAVING A COLLAPSIBLE PORTION - A coaxial cable connector is configured to connect a coaxial cable to a mating connector. The coaxial cable connector includes a connector body having a forward end and a rearward end opposite the forward end, the rearward end configured to receive a coaxial cable; an annular post disposed at least partially within the connector body; and a sleeve configured to be received within the connector body and movable from a first position to a second position relative to the connector body. The sleeve includes a collapsible portion configured to collapse radially inward in an asymmetric fashion toward the post as the collapsible sleeve is moved from the first position to the second position. | 2012-10-25 |
20120270440 | COAXIAL CABLE CONNECTOR HAVING SLOTTED POST MEMBER - A coaxial cable connector includes a connector body and a post member disposed within the connector body. A coupling nut is threadingly attached to the post member wherein a flanged portion of the post member provides an axial biasing force with regard to an attached interface port. In one version, the flanged portion is slotted. | 2012-10-25 |
20120270441 | ELECTRICAL CONNECTOR WITH GROUNDING MEMBER - A coaxial cable connector includes tubular post, a coupler secured over an end of the tubular post for securing the connector to an appliance, and an outer body secured to the tubular post. An electrical grounding path is maintained between the coupler and the tubular post whether or not the coupler is tightly fastened to the appliance. The electrical grounding path is provided by a resilient, electrically-conductive grounding member disposed between the tubular post and the coupler. Alternatively, the connector includes conductive grease at a point where mating portions of the tubular post and coupler have closely matching dimensions. | 2012-10-25 |
20120270442 | UNIVERSAL CABLE CONNECTOR WITH INTERCHANGEABLE COLOR BANDS - A connector of termination assembly for a mini-coaxial cable in different embodiments is made up of an extension tip which is preassembled in a connector body to receive the inner conductor pin on the cable, a first inner sleeve which fits over an exposed end of the dielectric layer, a second outer sleeve which surrounds a compression ring, and a crimping ring is mounted on the outside of the outer sleeve to force the sleeves to be radially contracted into crimping engagement with the cable. Variations of the connector body may be employed for different types of connectors including modifications in the extension tip to facilitate insertion of the conductor into the assembly and color bands to signify the size of cable and intended application. | 2012-10-25 |
20120270443 | Electronic Connector - An electronic connector comprises an insulated housing, a first terminal pin set, a second terminal pin set, a third terminal pin set, a detective terminal pin and a metal shell. The insulated housing contains a base plate and defines a first space and a second space. The first, second and third terminal pin sets are located in the first and second spaces and work together to conform to the standards of USB 2.0 and 3.0. The detective terminal pin is disposed on an inner surface defining the first space. The metal shell encases the insulated housing and is electrically grounded. Thereby, when an interface is reversely inserted into the first space, the detective terminal pin can be electrically grounded. Such manner will allow the terminal pin sets to be selectively activated or deactivated according to the way of insertion of the interface into the connector to achieve a reliable communication. | 2012-10-25 |
20120270444 | SHIELD CONNECTOR - A shield connector ( | 2012-10-25 |
20120270445 | CONNECTOR - The invention provides a connector including a body having insulation properties and a terminal group arranged in a row in a first direction of the body. The terminal group includes a pair of first signal terminals, a second signal terminal, and a ground terminal. The first signal terminals extend in a second direction and are adjacent to each other in the first direction. The second signal terminal extends in the second direction. The ground terminal extends in the second direction and is disposed between one of the first signal terminals and the second signal terminal. A widthwise dimension in the first direction of the ground terminal is less than twice that of each of the first signal terminals. A thicknesswise dimension of at least a part of the ground terminal in a third direction is larger than that of each of the first and second signal terminals. | 2012-10-25 |