43rd week of 2012 patent applcation highlights part 27 |
Patent application number | Title | Published |
20120268944 | Backlight Module and Light Emitting Diode Module Thereof - A light emitting diode contains a package structure and a light emitting diode die embedded in the package structure. The package structure has an elliptic bottom surface having a semi-major axes and a semi-minor axis and a semi-ellipsoidal surface connecting and surrounding the edge of the elliptic bottom surface, wherein the maximum height of the ellipsoidal surface from the elliptic bottom surface is between the semi-major axes and the semi-minor axis. | 2012-10-25 |
20120268945 | LED ILLUMINATION DEVICES AND METHODS - Lens elements having a generally curved shape with a flat surfacemounted adjacent an LED for improving the light transmission efficiency and the dispersal pattern of radiation emitted by the LED are disclosed. | 2012-10-25 |
20120268946 | LENS AND ILLUMINATION DEVICE - A lens includes a light incident surface and a light exiting surface. The light exiting surface includes a first concave surface, a first convex surface, a second convex surface, a first curved surface, and a second curved surface. The first concave surface is located at the center of the light exiting surface for diverging the light exiting therefrom. The first and second convex surface are arranged at two opposite sides of the first concave surface respectively for converging the light exiting therefrom; the first convex surface, the first concave surface, and the second convex surface connect in sequence along a first direction. The first and second curved surfaces are arranged at another two opposite sides of the first concave surface respectively; the first curved surface, the first concave surface, and the second curved surface connect in sequence along a second direction perpendicular to the first direction. | 2012-10-25 |
20120268947 | PROJECTION DEVICE FOR VARIETY OF LIGHT DEVICE - A projection assembly is arranged to be added onto or built into at least one LED-unit or other light-unit of an illuminated object that has more than one LED or other light source to cause the object to be illuminated and show the object's design or appearance while also offering illumination to people. The illuminated object may include all kinds of seasonal lighting, regular light fixtures, track lights, desktop lights, and battery operated lights having more than one light-unit or LED-unit. | 2012-10-25 |
20120268948 | LIGHTING CONTROL APPARATUS AND METHOD - A lighting control apparatus, comprising a shield having a reflective inner surface that blocks light emanating from a light fixture in a first direction, and redirects light emanating from the light fixture to a second direction; a clamp attached to the socket of the light fixture and deriving support therefrom; and a support structure attached to the clamp that supports the shield in a position suitable for blocking and redirecting the light emanating from the light fixture | 2012-10-25 |
20120268949 | Free-Form Catadioptric Illumination Lens - An illumination lens for hemispherically emitting light emitting diodes is disclosed that produces a square illumination pattern too narrow for a refractive lens to produce by itself. The lens is freeform in that it departs from circular symmetry in order to produce a square pattern. It is catadioptric in that it comprises a central refractive lens with a square output of desired angular width and a surrounding TIR prism that produces the same square output, overlapping the first for better uniformity of the sum. The central lens and circumambient TIR prism are joined in a monolithic configuration suitable for injection molding. Vector equations are disclosed for generating the shapes of the five optically active surfaces of the invention, two internal surfaces forming a central cavity surrounding the LED and three external surfaces, all five departing from circular symmetry. | 2012-10-25 |
20120268950 | Wide-Angle Non-Imaging Illumination Lens Arrayable for Close Planar Targets - An illumination lens for hemispherically emitting light emitting diodes is disclosed that produces a circular illumination pattern of wide extent on a relatively close target. Exemplary applications are in commercial refrigerator-case lighting and in LED backlights for liquid crystal displays. This illumination lens is designed to be installed in arrays, such that the multiple patterns overlap to sum up to a nearly uniform illumination pattern. The individual lens produces an illumination ramp which monotonically declines to zero at or close to the location of the adjacent lens in the array. Design methods are disclosed whereby this illumination ramp is translated into a source-image size function that is the basis for generating any particular lens. Preferred embodiments include a cusp at the center of the outer surface. Design methods are disclosed for numerically generating the lens surfaces for any particular combination of array spacing and target distance. | 2012-10-25 |
20120268951 | FIXING MECHANISM FOR BACKLIGHT MODULE AND BACKLIGHT MODULE - A fixing mechanism for a backlight module and a backlight module are provided in the present invention. The fixing mechanism comprises a plurality of retaining posts and a plurality of retaining sheets. The retaining posts are protruded from a back plate. The retaining sheet is engaged with an upper end of the retaining post for fixing an optical assembly. Moreover, the part of the fixing structure is made of elastic materials, so that it besides can steadily fix the optical film and make no clearance to be created, and also can prevent the optical film from escaping from orientation under the effect of hot-expansion and cold-shrinkage. | 2012-10-25 |
20120268952 | Wall Pack Light Fixture - A lighting fixture includes a first housing portion and a second housing portion. The first housing portion includes a base and a wall extending outwardly from substantially the perimeter of the base. A top portion of the wall includes one or more hinges extending outwardly therefrom. The second housing portion includes a front panel and a side panel extending outwardly from substantially the perimeter of the front panel. A top portion of the front panel includes at least one slot. The second housing is coupled to the first housing in an open position when the hinge is inserted into the slot and the front panel is disposed elevationally above the base. The second housing is coupled to the first housing in an operational position when the hinge is inserted into the slot and the front panel covers the base. | 2012-10-25 |
20120268953 | Lighting Device and Method for Assembling a Lighting Device - A lighting device, comprising a cooling body with at least one receiving area for a printed circuit board in each case, and at least one printed circuit board inserted into the at least one receiving area, with the at least one printed circuit board having a light source on its front face and with at least one part of a rear face making at least thermal contact with the cooling body. The at least one printed circuit board has a rotational locking means in each case which engages with at least one rotational locking mating means of its receiving area. | 2012-10-25 |
20120268954 | LIGHTING DEVICE - The lighting device includes: a heat radiating part provided with a cavity that accommodates a part of a plurality of drive circuit components driving a light source module; and a base part provided with a cavity that accommodates another part (e.g., a transistor) of the drive circuit components. Then, the drive circuit components are accommodated in the cavity of the heat radiating part and the cavity of the base part. | 2012-10-25 |
20120268955 | LAMP HOLDER STRUCTURE WITH UNIVERSAL ACCOMMODATING SLOT - The present invention relates to a lamp holder structure comprising a main body having a universal accommodating slot and an accommodating space concavely formed at the top and the bottom of the main body respectively, and a first electrically conductive plate and a second electrically conductive plate both installed at the top of the main body proximate to the universal accommodating slot, wherein the second electrically conductive plate is electrically coupled with a lamp holder base contained in the accommodating space, a metal spring plate is embedded into the main body, and a pressing element is contained in the universal accommodating slot and can be rotated or moved back and forth in the universal accommodating slot for pressing against a flange of the metal spring plate, such that the metal spring plate can be electrically coupled to or detached from the first electrically conductive plate. | 2012-10-25 |
20120268956 | ILLUMINATION DEVICE - Provided is an illumination device including a light emitting portion including a light source, an intermediate portion connected to the light emitting portion, a supporting portion connected to the intermediate portion and supporting the light emitting portion and the intermediate portion; a connecting portion connecting the light emitting portion and the intermediate portion to be rotatable with respect to each other, and another connecting portion connecting the intermediate portion and the supporting portion to be rotatable with respect to each other. The light emitting portion, the intermediate portion, and the supporting portion connected to the connecting portions may rotate with respect to each other based on the connecting portions to form a three-dimensional (3D) shape, and may be arranged in a single plane when the light emitting portion, the intermediate portion, and the supporting portion are unfolded based on the connecting portions. | 2012-10-25 |
20120268957 | REFLOW SOLDERABLE, SURFACE MOUNT OPTIC MOUNTING - Reflow solderable, surface mount LED optic mounting devices are provided. Embodiments that include turnings (e.g., made on a swiss turning machine) and stampings (e.g., made with a progressive die) are provided. The LED optic mounting devices are suitably positioned by the same pick-and-place machine that is used to mount LED on planar surface with circuitry and solder pads and are attached to the solder pads by soldering. | 2012-10-25 |
20120268958 | CONTROL DEVICE FOR VEHICLE LAMP AND VEHICLE LAMP SYSTEM - A control device ( | 2012-10-25 |
20120268959 | CONTROL-SURFACE-MOUNTED LANDING AND TAXI LIGHTS - A lighting assembly for movable control surfaces of a vehicle. The light assembly includes a lens, a plurality of light-emitting diodes (LEDs) and a housing that receives the plurality of LEDs and the lens. The housing of the light assembly is received within the movable control surface, such that the lens is flush with a surface of the movable control surface. The light assembly includes a plurality of reflectors. The plurality of LEDs is rotatably mounted within the housing. The light assembly includes a controller that controls the position of the LEDs relative to the housing, based on a received control signal. | 2012-10-25 |
20120268960 | SAFETY LIGHT FOR TRAILERS - Trailer illumination device | 2012-10-25 |
20120268961 | CLEAR BEZEL - A rearview assembly having a mounting structure configured to be operably coupled with a vehicle. A housing is operably connected with the mounting structure and a rearward viewing device is supported by one of the housing and the mounting structure. The rearward viewing device provides a rearward view to a vehicle driver and includes a front substrate and a rear substrate. The entire front surface of the front substrate is exposed and the entire rear substrate is positioned behind the front substrate. A concealing layer is disposed about a periphery of the rearward viewing device between the front substrate and the rear substrate. A partially optically transparent bezel is disposed adjacent to both the rearward viewing device and the housing, the optically transparent bezel having an edge radius greater than 2.5 mm and the optically transparent bezel being substantially flush with the front surface of the front substrate. | 2012-10-25 |
20120268962 | VEHICLE HEADLAMP - A vehicle headlamp includes a light source and a reflector. A light emitting surface of the light source includes a linear side. The light source is disposed so that the linear side of the light emitting surface is oblique with respect to an optical axis. | 2012-10-25 |
20120268963 | LIGHT GUIDES - This invention relates to light guide devices and methods of manufacture. The light guide device is suitable for use in a range of applications, particularly in connection with the backlighting of displays, for example, liquid crystal displays. | 2012-10-25 |
20120268964 | DIFFUSER FILM WITH CONTROLLED LIGHT COLLIMATION - In one embodiment, a diffuser film with controlled light collimation comprises: a plastic layer having a first side and a second side, the first side having a first textured surface, wherein 20 to 50 percent of slope angles on the first textured surface proximate a first axis have a value of zero to five degrees. In one embodiment, a back lighted device, comprises: a light source, a light guide disposed proximate the light source for receiving light from the light source, and the diffuser film. In one embodiment, a method of controlling collimation in a diffusing film, comprises: determining a desired degree of collimation of the diffusing film; and texturing a plastic layer to form a first textured surface, wherein 20 to 50 percent of slope angles on the first textured surface proximate a first axis have a value of zero to five degrees. | 2012-10-25 |
20120268965 | LIGHT EMITTING DEVICE WITH A POINT-LIKE LIGHT SOURCE - A light emitting device comprises: a light guiding plate including two facing principal surfaces and circumferential end surfaces connecting the principal surfaces; and a point-like light source facing at least one surface of the circumferential end surfaces of the light guiding plate. One surface of the circumferential end surfaces except the surface where the light source is arranged is a light emitting surface, the thickness of the light guiding plate facing the light source is smaller than the thickness of a portion constituting the light emitting surface and is smaller than the thickness of a light emitting surface of the light source, a diffusing unit is formed on at least one of the principal surfaces; and a reflection member covering peripheries of the light source and the light guiding plate except portions constituting the light emitting surfaces of the light source and the light guiding plate is provided. | 2012-10-25 |
20120268966 | LIGHTING ASSEMBLY - A lighting assembly includes a light guide having a first major surface, a second major surface opposite the first major surface, a light input edge, and an end edge distal the light input edge. Light input to the light guide through the light input edge propagates by total internal reflection toward the end edge. The lighting assembly further includes light extracting elements at least one of the major surfaces of the light guide, the light extracting elements configured to extract light through the first major surface in a direction away from the light input edge and away from the first major surface, and a banding reduction element at the end edge configured to redirect light incident thereon in a direction away from the light input edge. | 2012-10-25 |
20120268967 | LIGHT GUIDES - Lightguides are disclosed. More particularly, lightguides that include a lightguiding layer and a light extracting layer having a structured surface are disclosed. The light guiding layer is optically coupled to a first set of structures of the structured surface at given locations, and is not optically coupled to a second set of structures at given locations, thereby producing total internal reflection at the second locations. The selective optical coupling may be achieved by a number of different contemplated means as discussed herein. The lightguides allow for distribution of light along with redirection towards an image viewer without a number of commonly required optical elements in backlights. | 2012-10-25 |
20120268968 | HEAT RADIATING PRINTED CIRCUIT BOARD AND CHASSIS ASSEMBLY HAVING THE SAME - The present invention relates to a heat radiating printed circuit board (PCB) and a chassis assembly having the same, the heat-radiating PCB characterized by: a circuit pattern unit mounted with a light emitting diode; and one or more mounting units bent from the circuit pattern unit to be fixed at a chassis providing a lightguide path of a backlight unit, where one of the mounting units is mounted to the chassis via a thermal interface material to maximize the heat radiating characteristic of the PCB and to reduce the manufacturing cost. | 2012-10-25 |
20120268969 | DC-AC INVERTER WITH HIGH FREQUENCY ISOLATION TRANSFORMER - The novel DC-AC inverter topology with high frequency isolation transformer consists of an input DC-DC converter with high frequency isolation transformer and an output full-bridge unfolding converter with four transistors provides the output AC voltage from a DC source. The input DC-DC converter has two primary side controllable switches and a single rectifier on the secondary side, two resonant capacitors, a resonant inductor, an output inductor and a high-frequency isolation transformer, which does not store DC energy. The duty ratio D of the primary side switches is modulated by the rectified AC voltage to result in an output rectified AC voltage, which is unfolded into an AC sinusoidal output voltage by the output full-bridge unfolding converter. | 2012-10-25 |
20120268970 | ELECTRIC GENERATING SYSTEM USING SOLAR CELL - An electric generating system using a solar cell improves the quality of output power by including a converter for converting an output voltage generated from the solar cell into a DC voltage in a pulse shape. An inverter converts the DC voltage in the pulse shape into an AC voltage and applies the AC voltage to a power system and a control device for determining whether an erroneous operation of the electric generating system using the solar cell is generated or not based on an output voltage of the solar cell, an output current of the solar cell and a voltage of the power system. At least one inverter switching device among a plurality of inverter switching devices performs a switching at a frequency higher than a frequency during a normal operation at an interval where the erroneous operation is generated. | 2012-10-25 |
20120268971 | POWER SUPPLY FOR CONTROLLING CURRENT - The present invention relates to a power supply for controlling current that uses a flyback converter for electrical insulation between a load line unit and the power supply for controlling current. In a transformer (a flyback converter) having a flyback structure in the present invention, disclosed is a device which expects a current of the second coil by sensing a current of the first coil of the transformer, and controls the current flowing through the load line unit. A level detector is included, which updates a duty time or an on-time of the switch by transferring a reset signal to an integrator and a second sampler in accordance with a cycle of an input power. As a result, it is possible to reduce power loss by increasing a power factor through the adjustment of the phase of the current of the load line unit and an input voltage. | 2012-10-25 |
20120268972 | POWER SUPPLY APPARATUS - A power supply apparatus capable of setting a ripple current to be not more than an acceptable value regardless of an input voltage is obtained. The apparatus calculates switching frequency by a current detected by a current detector so that the switching frequency is set to be low if the current is large and the switching frequency is set to be high if the current is small. The switching frequency is set to be high if the input voltage is high and switching frequency is set to be low if the input voltage is low depending on a voltage inputted to an input terminal; and a switching element is controlled by restricting the switching frequency so that the switching frequency to be set by the current detected by the current detector is not lower than the switching frequency to be set by the input voltage. | 2012-10-25 |
20120268973 | POWER REGULATING APPARATUS - Disclosed is a power regulating apparatus, which is connected between an AC power and a load, for supplying the regulated AC power to the load. The power regulating apparatus includes a first regulating means provided to regulate the input AC power source when the AC power is at a normal power level, and a second regulating means provided to transmit an electric power to the load from a power storage means when the AC power is at a power level lower than the normal power level. Thus, the power regulating apparatus is capable of providing the load with an expected high quality electric power in all cases of AC power variation. | 2012-10-25 |
20120268974 | HIGH-RESOLUTION AND LOW-RESOLUTION SENSORS FOR PHASE DETECTION - A phase detection system includes a low-resolution sensor and a high-resolution sensor for monitoring an alternating current (AC) voltage. A phase detector receives voltage samples from both the low-resolution sensor and the high-resolution sensor. The phase detector monitors the low-resolution sensor to detect approaching zero cross events (i.e., monitored voltage values approaching zero). In response to an approaching zero-cross event, the phase detector uses the magnitude of the high-resolution voltage samples measured on either side of the zero cross event to determine the phase of the monitored AC voltage. | 2012-10-25 |
20120268975 | Power Conversion with Current Sensing Coupled through Saturating Element - An architecture for current-modulating power-handling circuits, such as power converters, where a small saturating inductance is used to obtain a pulse edge when the main current value crosses zero. | 2012-10-25 |
20120268976 | THREE-PHASE RECTIFIER CIRCUIT - In one aspect of the invention, a three-phase rectifier circuit having three input terminals and two output terminals includes a three-phase diode bridge, three switching circuits, and a voltage source. The three-phase diode bridge has three pairs of first diodes electrically parallel-connected to the two output terminals. Each pair of first diodes has two first diodes series-connected defining a first node therebetween, and electrically connected to a corresponding input terminal at the first node. Each switching circuit has a first terminal, a second terminal and a plurality of switches electrically series-connected between the first and second terminals. The first and second terminals are respectively electrically connected to a second node and a third node, respectively between the first node and the two first diodes of the corresponding pair of first diodes. The voltage source is electrically parallel-connected between the two output terminals and electrically connected to each switching circuit. | 2012-10-25 |
20120268977 | SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A semiconductor memory device includes a memory cell block configured to include a plurality of main cells and a plurality of CAM cells, a plurality of page buffers configured to store data to be programmed into the memory cell block, and a Y decoder configured to transfer CAM data to respective page buffers, selected from among the plurality of page buffers, in response to a data determination signal and CAM column addresses whenever the CAM data is inputted in a CAM data input mode. | 2012-10-25 |
20120268978 | SEMICONDUCTOR MEMORY DEVICE IN WHICH CAPACITANCE BETWEEN BIT LINES IS REDUCED, AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines for selecting a plurality of memory cells, and a plurality of bit lines for selecting a plurality of memory cells. Of the plurality of bit lines, first bit lines and second bit lines are arranged in different layers. | 2012-10-25 |
20120268979 | SEMICONDUCTOR DEVICE - A nonvolatile memory is provided. A semiconductor device (a nonvolatile memory) has a circuit configuration similar to that of a general SRAM. By providing a transistor whose off-state current is small between a stored data holding portion and a power supply line of the SRAM, leakage of electric charge from the stored data holding portion is prevented. As the transistor whose off-state current is small provided for preventing leakage of electric charge from the stored data holding portion, a transistor including an oxide semiconductor film is preferably used. Such a configuration can also be applied to a shift register, whereby a shift register with low power consumption can be obtained. | 2012-10-25 |
20120268980 | NONVOLATILE VARIABLE RESISTIVE ELEMENT AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A large-capacity and inexpensive nonvolatile semiconductor memory device that prevents a leak current and is operated at high speed is implemented with a nonvolatile variable resistive element. A memory cell array includes the nonvolatile variable resistive elements each including a variable resistor composed of a metal oxide film to cause a resistance change according to an oxygen concentration in the film, an insulation film formed on the variable resistor, first and second electrodes to sandwich the variable resistor, and a third electrode opposite to the variable resistor across the insulation film. A writing operation is performed by applying a voltage to the third electrode to induce an electric field having a threshold value or more, in a direction perpendicular to an interface between the variable resistor and the insulation film, and a resistance state of the variable resistor is read by applying a voltage between the first and second electrodes. | 2012-10-25 |
20120268981 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided. | 2012-10-25 |
20120268982 | METHODS AND APPARATUS OF STACKING DRAMS - Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards. | 2012-10-25 |
20120268983 | RANDOM-ACCESS MEMORY WITH DYNAMICALLY ADJUSTABLE ENDURANCE AND RETENTION - A memory device is provided. The memory device comprises an array of memory cells, each including a volume of material that can stably exhibit at least two different physical states that are each associated with a different data value, word lines that each interconnects a row of memory cells within the array of memory cells to a word-line driver, and bit lines that each interconnects a column of memory cells, through a bit-line driver, to a write driver that is controlled, during a WRITE operation, to write an input data value to an activated memory cell at the intersection of the column of memory cells and an activated row of memory cells by generating a current density within the memory cells that corresponds to retention/endurance characteristics of the memory cell dynamically assigned to the memory cell by a memory controller, operating system, or other control functionality. | 2012-10-25 |
20120268984 | Adaptive Wordline Programming Bias of a Phase Change Memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell. | 2012-10-25 |
20120268985 | RESONANCE NANOELECTROMECHANICAL SYSTEMS - Systems and methods for operating a nanometer-scale cantilever beam with a gate electrode. An example system includes a drive circuit coupled to the gate electrode where a drive signal from the circuit may cause the beam to oscillate at or near the beam's resonance frequency. The drive signal includes an AC component, and may include a DC component as well. An alternative example system includes a nanometer-scale cantilever beam, where the beam oscillates to contact a plurality of drain regions. | 2012-10-25 |
20120268986 | MAGNETIC MEMORY ELEMENT AND NON-VOLATILE STORAGE DEVICE - The present invention provides a magnetic memory element that has a spin valve structure formed using a free layer, a non-magnetic layer, and a pinned layer. The free layer has a three-layer structure having a first magnetic layer, an intermediate layer, and a second magnetic layer arranged in this order viewed from the non-magnetic layer. The first magnetic layer is made of a ferromagnetic material. The intermediate layer is made of a non-magnetic material. The second magnetic layer is made of an N-type ferromagnetic material having a magnetic compensation point in the temperature range where a memory storage operation can be available. The magnetization direction of the first magnetic layer and the magnetization direction of the second magnetic layer are parallel to each other at the temperature lower than the magnetic compensation point T | 2012-10-25 |
20120268987 | System and Method for Detecting Disturbed Memory Cells of a Semiconductor Memory Device - A method of detecting a disturb condition of a memory cell includes application of multiple sets of conditions to the memory cell and determining whether the memory cell behaves as a programmed memory cell in response to the sets of conditions. A disturbed memory cell can be detected if the memory cell responds as a programmed memory cell in response to one of the sets of conditions, but responds as an erased memory cell in response to another of the sets of conditions. | 2012-10-25 |
20120268988 | NONVOLATILE MEMORY DEVICE INCLUDING MEMORY CELL ARRAY WITH UPPER AND LOWER WORD LINE GROUPS - A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group. | 2012-10-25 |
20120268989 | NOVEL HIGH SPEED HIGH DENSITY NAND-BASED 2T-NOR FLASH MEMORY DESIGN - A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor with poly1 and poly2 being shorted or a single-poly poly1 or poly2 NMOS transistor. The flash cell is programmed and erased by using a Fowler-Nordheim channel tunneling scheme. A NAND-based flash memory device includes an array of the flash cells arranged with parallel bit lines and source lines that are perpendicular to word lines. Write-row-decoder and read-row-decoder are designed for the flash memory device to provide appropriate voltages for the flash memory array in pre-program with verify, erase with verify, program and read operations in the unit of page, block, sector or chip. | 2012-10-25 |
20120268990 | SELECTIVE RE-PROGRAMMING OF ANALOG MEMORY CELLS - A method for data storage includes defining, in a memory that includes multiple analog memory cells, an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states. Data is initially stored in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states. After initially storing the data, a second group of the analog memory cells, which potentially cause interference to the first group, is programmed. After programming the second group, the first group is selectively re-programmed with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset. | 2012-10-25 |
20120268991 | DATA STORAGE DEVICE AND BLOCK SELECTION METHOD FOR A FLASH MEMORY - The invention provides a block selection method for a flash memory. First, a flash memory is divided into a plurality of great block groups. Each of the great block groups is then divided into a plurality of block groups. Scores corresponding to the blocks of the flash memory are then recorded in a score table. When the score of a target block selected from the blocks of the flash memory has been amended, the amended score of the target block is compared with a first extreme value and a second extreme value corresponding to the block group and the great block group comprising the target block and the total extreme value. A victim block is then determined from the blocks of the flash memory according to an extreme value table. | 2012-10-25 |
20120268992 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array configured to include a plurality of memory blocks, a voltage generator configured to output operating voltages for data input and output to global lines, and a row decoder configured to transfer the operating voltages to local lines of a memory block, selected from among the plurality of memory blocks, and supply a ground voltage to local lines of unselected memory blocks in response to address signals. | 2012-10-25 |
20120268993 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second memory planes that each include a plurality of memory blocks, a first page buffer group coupled to the memory blocks of the first memory plane through first bit lines and configured to perform a read operation and a program operation, a second page buffer group coupled to the memory blocks of the second memory plane through second bit lines and configured to perform the read operation and the program operation, a coupling circuit configured to couple the first bit lines of the first memory planes and the second bit lines of the second memory planes, respectively, in response to a coupling signal, and a control circuit configured to generate the coupling signal for controlling the coupling circuit in a copyback operation of data, read from a source page of the first memory plane, in a target page of the second memory plane. | 2012-10-25 |
20120268994 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time. | 2012-10-25 |
20120268995 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC APPARATUS - A memory cell array including non-volatile memory cells is divided into a first block including a non-volatile memory cell for accumulating a degradation over time and a second block including a non-volatile memory cell for storing data. A word line select circuit and a bit line select circuit select a first word line and a first bit line connected to the second block to access the non-volatile memory cell for storing data of the second block, and selects a second word line or a second bit line connected to the first block to apply a stress voltage to the non-volatile memory cell for accumulating the degradation over time of the first block, thereby automatically detecting ambient temperature and storing accumulated stress. | 2012-10-25 |
20120268996 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array including memory block groups each coupled to bit lines, a page buffer group coupled to first bit lines of a first memory block group and configured to control voltages of the first bit lines of the first memory block group depending on data to be stored in memory cells in a program operation and configured to sense the voltage of the first bit lines in a read operation, at least one bit line coupling circuit configured to couple first bit lines of a n | 2012-10-25 |
20120268997 | NONVOLATILE SEMICONDUCTOR DEVICE - A nonvolatile memory device includes a plurality of global word lines, a voltage pump configured to generate a plurality of voltages, a control unit configured to divide the plurality of global word lines into a first group and a second group in response to an input row address and generate control signals, a first selection unit configured to output at least two different voltages that are to be applied to global word lines of the first group, a second selection unit configured to output a voltage that is to be applied to global word lines of the second group, and a third selection unit configured to apply output voltages of the first selection unit to the global word lines of the first group, and apply an output voltage of the second selection unit to the global word lines of the second group. | 2012-10-25 |
20120268998 | Flash Memory Device and Method for Handling Power Failure Thereof - A flash memory device. In one embodiment, the flash memory device comprises a flash memory, a diode, a controller, and a capacitor. The flash memory has a voltage source pin. The diode is coupled between a voltage source and the voltage source pin of the flash memory. The controller is coupled to the flash memory via a data bus. The capacitor is coupled between the voltage source pin of the flash memory and a ground, and supplies power to the flash memory to enable the flash memory to complete writing of at least one data page when the level of the voltage source is lowered. | 2012-10-25 |
20120268999 | DYNAMIC PROGRAMMING FOR FLASH MEMORY - A method is for operating a memory having a group of non-volatile memory cells. A first programming pulse is applied to a subset of the group of non-volatile memory cells. The subset needs additional programming. A portion of the subset still needing additional programming is identified. A ratio of the number of memory cells in the subset and the number of memory cells in the portion is determined. A size of a second programming pulse based on the ratio is selected. The second programming pulse is applied to the portion. | 2012-10-25 |
20120269000 | NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A method for programming a non-volatile memory device including a plurality of memory cells includes verifying whether the memory cells are programmed or not by applying a program verification bias voltage, which is calculated and stored during an initialization operation preformed before the programming of the memory cells, after a program voltage is applied to word lines of the memory cells. | 2012-10-25 |
20120269001 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number2012-10-25 | |
20120269002 | PROGRAMMING METHOD FOR NONVOLATILE MEMORY DEVICE - A method of programming memory cells (transistors) of a nonvolatile memory device from a first set of (previous) logic states to a second set of (final) logic states. The method includes applying program voltages to selected memory transistors; and applying a pre-verification voltage and a target verification voltage for verifying the current logic state of the selected memory transistors. The voltage interval between logic states of the second set of logic states is less than the voltage interval between logic states of the first set of logic states. A target verification voltage for verifying a first memory transistor is at one logic state of the second set is used as a pre-verification voltage for verifying that a second memory transistor to be programmed to higher logic state of the second set. | 2012-10-25 |
20120269003 | DATA DECISION METHOD AND MEMORY - A data decision method including checking whether threshold voltages of a plurality of memory cells are greater than a first verification voltage, checking whether the threshold voltages of the plurality of memory cells are greater than a second verification voltage, wherein the second verification voltage is greater than the first verification voltage, and checking threshold voltages of memory cells adjacent to memory cells having threshold voltages greater than the first verification voltage and lower than the second verification voltage among the plurality of memory cells. | 2012-10-25 |
20120269004 | MULTIPLE LEVEL PROGRAM VERIFY IN A MEMORY DEVICE - A series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold. | 2012-10-25 |
20120269005 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - A semiconductor memory device includes a plurality of first pads and a plurality of memory unit blocks. The plurality of first pads are configured to input/output data in a test mode. The plurality of memory unit blocks each include a plurality of second pads configured to input/output data in a normal mode, and a plurality of data path selection units configured to connect internal circuits of the corresponding memory unit block to the plurality of first pads or the plurality of second pads in response to a unit block selection flag signal, a write enable signal, a read enable signal, and a mode control signal. | 2012-10-25 |
20120269006 | SEMICONDUCTOR DEVICE - A semiconductor device is capable of reducing the coupling capacitance between adjacent bit lines by forming an air-gap at an opposite side of a one side contact when forming a buried bit line or increasing a thickness of an insulating layer, thereby improving characteristics of the semiconductor devices. The semiconductor device includes a plurality of line patterns including one side contacts, a bit line buried in a lower portion between the line patterns, a bit line junction region formed within each of the line patterns at one side of the bit line, and an air-gap formed between the other side of the bit line and each of the line patterns. | 2012-10-25 |
20120269007 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING OUT THE SAME - A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation. | 2012-10-25 |
20120269008 | DATA INPUT DEVICE FOR SEMICONDUCTOR MEMORY DEVICE - A data input device for use in a memory device to avoid false data being written due to a postamble ringing phenomenon in a write operation is provided. The data input device comprises a buffer, a combinational logic circuit and a flip-flop unit. The buffer receives the data and outputs internal data to the flip-flop unit. The combinational logic circuit receives an external data strobe signal to generate a first data strobe signal and a second data strobe signal. The flip-flop unit stores the data in synchronization with the first data strobe signal and outputs the stored data in synchronization with the second data strobe signal. A last rising edge of the second data strobe signal is generated prior to onset of the postamble ringing on the external data strobe signal, so that a data transferred path in the flip-flop unit is closed prior to onset of the postamble ringing. | 2012-10-25 |
20120269009 | MEMORY ARRAY WITH TWO-PHASE BIT LINE PRECHARGE - An integrated circuit includes an array of memory cells with a plurality of columns and rows. A plurality of data lines is coupled to the columns in the array and a plurality of word lines is coupled to the rows in the array. Clamp transistors are coupled to respective data lines in the plurality of data lines, and adapted to prevent voltage on the respective bit lines from overshooting a target level during a precharge interval. A bias circuit is coupled to the clamp transistors on the plurality of bit lines, and arranged to apply the bias voltage in at least two phases within a precharge interval, and to prevent overshoot of the target level on the bit line. | 2012-10-25 |
20120269010 | MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A memory includes at least one first flag cell configured to store first flag data, at least one second flag cell configured to store second flag data, at least one first sensing node having a voltage level determined by the first flag data of the first flag cell, at least one second sensing having a voltage level determined by the second flag data of the second flag cell, a selection circuit configured to select the first sensing node or the second sensing node in response to a flag address; and a determination circuit having an internal node through which current corresponding to a voltage level of a selected sensing node flows and configured to determine a logic value of flag data corresponding to the selected sensing node among the first and second flag data by using an amount of current flowing through the internal node. | 2012-10-25 |
20120269011 | VOLTAGE SWITCHING IN A MEMORY DEVICE - Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage. | 2012-10-25 |
20120269012 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME - A semiconductor integrated circuit includes a first signal generator configured to generate a third active signal that is selectively enabled in a first duration in response to a first active signal enabled during the first duration and a second active signal enabled during at least one second duration within the first duration an internal circuit configured to cease operating in response to the third active signal, and a second signal generator configured to generate the second active signal in response to a mode determination signal and a strobe signal. | 2012-10-25 |
20120269013 | SIGNAL PROCESSING CIRCUIT - A signal processing circuit including a nonvolatile storage circuit with a novel structure. The signal processing circuit includes a circuit that is supplied with a power supply voltage and has a first node to which a first high power supply potential is applied, and a nonvolatile storage circuit for holding a potential of the first node. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer, and a second node that is brought into a floating state when the transistor is turned off. A second high power supply potential or a ground potential is input to a gate of the transistor. When the power supply voltage is not supplied, the ground potential is input to the gate of the transistor and the transistor is kept off. The second high power supply potential is higher than the first high power supply potential. | 2012-10-25 |
20120269014 | DELAY CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A delay control circuit includes a delay locked loop configured to delay an external clock by a first delay amount and generate an internal clock, a first delay unit configured to delay an input signal by a first delay amount, a first replica delay unit having a replica delay amount corresponding to a modeled delay amount of a system, a delay control unit configured to control the replica delay amount in response to a latency of an input signal, a measurement unit configured to measure the first delay amount and the controlled replica delay amount and generate path information, an operation unit configured to generate delay information in response to the latency of the input signal and the path information, and a latency delay unit configured to delay the delayed input signal of the first delay unit by the delay information and generate a latency signal. | 2012-10-25 |
20120269015 | COMMAND PATHS, APPARATUSES, MEMORIES, AND METHODS FOR PROVIDING INTERNAL COMMANDS TO A DATA PATH - Command paths, apparatuses, memories, and methods for providing an internal command to a data path are disclosed. In an example method, a command is received and propagated through a command path to provide an internal command. Further included in the method is determining a difference between a latency value and a path delay difference, the path delay difference representing a modeled path delay difference between the command path and the data path measured in terms of a number of clock periods. The propagation of the command through the command path to the data path is delayed by a delay based at least in part on the difference between the latency value and the path delay difference. The internal command is provided to the data path responsive to an internal clock signal. | 2012-10-25 |
20120269016 | LATENCY CONTROL CIRCUIT, LATENCY CONTROL METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information, and a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock. | 2012-10-25 |
20120269017 | DELAY CIRCUIT AND LATENCY CONTROL CIRCUIT OF MEMORY, AND SIGNAL DELAY METHOD THEREOF - A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal. | 2012-10-25 |
20120269018 | MEMORY SYSTEM HAVING MEMORY AND MEMORY CONTROLLER AND OPERATION METHOD THEREOF - An operation method of a memory system including a memory and a memory controller includes transmitting defective-cell address information to the memory controller from the memory at an initial operation of the memory, wherein the defective-cell address information includes an address of a defective cell of the memory, and accessing, by the memory controller, an area of the memory excluding an area indicated by the defective-cell address information inside the memory. | 2012-10-25 |
20120269019 | SEMICONDUCTOR DEVICE HAVING CONTROL BITLINE TO PREVENT FLOATING BODY EFFECT - A vertical semiconductor device is provided. The semiconductor device includes a cell array including a control bit line connected to cells and electrically isolated from a bit line, and a floating body control circuit for applying a floating control voltage to the control bit line in a predetermined period. | 2012-10-25 |
20120269020 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A method for operating a non-volatile memory device includes selecting a word line of a plurality of word lines in response to a program command and an received address, determining whether the selected word line is a word line set among the word lines, performing an erase operation on a second word line group of the word lines in response to a result of the determining, and performing a program operation on the selected word line. | 2012-10-25 |
20120269021 | MEMORY DEVICE USING A VARIABLE RESISTIVE ELEMENT - A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different. | 2012-10-25 |
20120269022 | INTERNAL POWER SOURCE VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY AND METHOD FOR GENERATING INTERNAL POWER SOURCE VOLTAGE - An internal power source voltage generating circuit of a semiconductor memory and a corresponding method shorten an access delay upon transition of a data reading operation in an address period shorter than a prescribed minimum period to an operation in the prescribed minimum period. While a boosted voltage of an external power source voltage is supplied to the semiconductor memory as the internal power source voltage via an output line connected to one end of a condenser. A reference low potential is applied to the other end of the condenser and the external power source voltage is applied to the output line, thereby charging the condenser. If the internal power source voltage is lower than a threshold voltage, the internal power source voltage on the output line is boosted by applying the external power source voltage to the other end of the condenser. | 2012-10-25 |
20120269023 | SYSTEM WITH CONTROLLER AND MEMORY - According to the system of the present invention, data (DQ) signals are outputted/received between a controller | 2012-10-25 |
20120269024 | KNEADING SEGMENT AND KNEADING EQUIPMENT - A kneading segment kneads materials such that insufficiently kneaded portions would not remain as gel. The kneading segment is rotatably disposed on a kneading screw housed in a barrel having an inner cavity, and is provided with a kneading flight which kneads the material in the barrel by rotating according to the kneading screw's rotation. The top surface of the kneading flight is formed with a concaved cutout section. The cutout section is surrounded by two side surfaces, which face the axial direction, and a bottom surface, which is disposed between the side surfaces. The bottom surface of the cutout section is formed in a tilted planar shape in relation to the top surface. The opening of the cutout section, which faces one side of the rotational direction of the kneading screw, has a larger area than the opening which faces the other side. | 2012-10-25 |
20120269025 | BEVERAGE CONTAINER - A beverage container includes: a pitcher body configured with an inner receiving space for receiving a beverage; an annular lid mounted removably on an open upper end of the pitcher body; an elongate hollow cylinder mounted coaxially and rotatably in the annular lid and configured with an inner accommodating space; a stirring member externally formed on the hollow cylinder; and a plug cap plugged into the hollow cylinder through an open upper end of the hollow cylinder for closing the inner accommodating space in the hollow cylinder. | 2012-10-25 |
20120269026 | AUTOMATED SOLUTION MAKER APPARATUS - An automated solution maker is provided. The automated solution maker mixes a chemical with a solvent to a desired concentration. The concentration of the solution is monitored by measuring the conductivity of the solution. Based upon this measurement, the concentration of the solution may be adjusted. | 2012-10-25 |
20120269027 | MICROFLUIDIC MIXING APPARATUS AND METHOD - A microfluidic mixing device for mixing at least two fluids to form a mixed fluid comprising; a first mixing chamber ( | 2012-10-25 |
20120269028 | Animal feed Mechanism - An animal feed mechanism includes a manually operated slide valve interposed between a set of upper agitators and a set of lower screw conveyors. In some examples, two upper agitators are installed within a plastic funnel, and two lower screw conveyors are disposed within a metal auger housing. Each screw conveyor includes an auger driven by its own separate motor. Thus, there are two motors for rotating the two augers. The two motors can be energized individually to selectively rotate either auger or to rotate them concurrently. In some examples, a transmission coupling the two augers to the two agitators conveys power to rotate both agitators regardless of whether either one or both motor driven augers are operating. | 2012-10-25 |
20120269029 | PROGRAMMABLE MIXER AND METHOD FOR THE OPERATION THEREOF - The invention relates to a programmable mixer for producing pharmaceutical or cosmetic recipes. The mixer includes a controller, a motor-driven mixing unit having a mixing tool engaging in a mixing vessel, and a lift unit. The lift unit induces an axial relative motion between the mixing tool and the mixing vessel to displace the mixing tool in the mixing vessel at a constant lift speed. The control method includes counting the lift strokes performed by the lift unit during an initial mixing process for each mixing period, and using the identifying data determined in the initial mixing process during a repeated mixing process. The identification data matching the recipe are read in, and the number of lift strokes per mixing period determined in the initial stirring process is used for implementing the corresponding mixing period of the repeated mixing process. | 2012-10-25 |
20120269030 | Mixing Chamber, Cartridge, and Method for Mixing a First and a Second Component - A mixing chamber includes a container for receiving a first and a second component; an obstacle structure, which is designed such that, under the effect of a centrifugal force or magnetic force acting on the mixing chamber, it moves through the first and second components in the container and mixes them with each other; and a connection piece, which is connected at one end to the container and at the other end to the obstacle structure. | 2012-10-25 |
20120269031 | ULTRASONIC TRANSMITTER AND RECEIVER WITH COMPLIANT MEMBRANE - An ultrasonic transmitter and receiver includes a MEMS composite transducer. The MEMS composite transducer includes a substrate. Portions of the substrate define an outer boundary of a cavity. A first MEMS transducing member includes a first size. A first portion of the first MEMS transducing member is anchored to the substrate. A second portion of the first MEMS transducing member extends over at least a portion of the cavity and is free to move relative to the cavity. A second MEMS transducing member includes a second size that is smaller than the first size of the first MEMS transducing member. A first portion of the second MEMS transducing member is anchored to the substrate. A second portion of the second MEMS transducing member extends over at least a portion of the cavity and is free to move relative to the cavity. A compliant membrane is positioned in contact with the first and second MEMS transducing members. A first portion of the compliant membrane covers the first and second MEMS transducing members. A second portion of the compliant membrane is anchored to the substrate. | 2012-10-25 |
20120269032 | Magnetic Mass-Lift Impulsive Seismic Energy Source Including Attracting and Repulsing Electromagnets - A seismic energy source includes a base plate and a block fixedly coupled in a frame. The base plate is configured for contact with a part of the Earth's subsurface to be seismically energized. The frame has a first electromagnet associated therewith. A second electromagnet is disposed in a travelling reaction mass, which is movably disposed in the frame between the first electromagnet assembly and the top block. The reaction mass includes at least a third electromagnet associated therewith. The source has circuits for selectively energizing the first, second and at least a third electromagnets, and which are configured to energize the first and second electromagnets to repel each other such that the traveling reaction mass is lifted from the first electromagnet, and configured to energize the at least a third electromagnet after a selected delay time to cause attraction between the traveling reaction mass and the top block | 2012-10-25 |
20120269033 | DUAL AXIS GEOPHONES FOR PRESSURE/VELOCITY SENSING STREAMERS FORMING A TRIPLE COMPONENT STREAMER - A seismic streamer includes a sensor comprises an axially oriented body including a plurality of axially oriented channels arranged in opposing pairs; a plurality of hydrophones arranged in opposing pairs in the channels; a pair of orthogonally oriented acoustic particle motion sensors; and a tilt sensor adjacent or associated with the particle motion sensors. The streamer has a plurality of hydrophones, as previously described, aligned with a plurality of accelerometers which detect movement of the streamer in the horizontal and vertical directions, all coupled with a tilt sensor, so that the marine seismic system can detect whether a detected seismic signal is a reflection from a geologic structure beneath the streamer or a downward traveling reflection from the air/seawater interface. | 2012-10-25 |
20120269034 | Separation and Noise Removal For Multiple Vibratory Source Seismic Data - The invention discloses a way to recover separated seismograms with reduced interference noise by processing vibroseis data recorded (or computer simulated) with multiple vibrators shaking simultaneously or nearly simultaneously ( | 2012-10-25 |
20120269035 | Evaluating Prospects from P-Wave Seismic Data Using S-Wave Vertical Shear Profile Data - The present disclosure relates to methods and systems for evaluating potential hydrocarbon prospect locations within a subsurface formation. First and second opposite polarity directional seismic signals are propagated from a seismic source through the subsurface formation and recorded. A pure shear wave record is derived from the recorded signals and compared to a compression wave record for at least one potential hydrocarbon reservoir location within the formation. | 2012-10-25 |
20120269036 | Method and Device for Measuring a Profile of the Ground - A method for measuring a profile of the ground involves using a transmitting arrangement, which is attached to a watercraft, for the directed emission of sound signals into an underwater area and a receiving arrangement having at least two transducers for receiving sound waves reflected by the profile of the ground. | 2012-10-25 |
20120269037 | BROADBAND SOUND SOURCE FOR LONG DISTANCE UNDERWATER SOUND PROPAGATION - The systems described include a light-weight, low frequency (200 Hz-1000 Hz), broadband underwater sound sources that comprise an inner resonator tube with thin walls tuned to a certain frequency surrounded by a shorter, larger-diameter, lower frequency tuned outer resonator tube that has an acoustic source suspended off-center inside the inner resonator tube. | 2012-10-25 |
20120269038 | SYSTEM AND METHOD FOR REDUCING DATA RECEPTION ERROR IN ACOUSTIC COMMUNICATION IN AUDIBLE FREQUENCY RANGE, AND APPARATUS APPLIED THERETO - Provided is a data reception error reduction system and method in acoustic communication in audible frequency range, and an apparatus applied thereto. The data reception error reduction system in the acoustic communication in audible frequency range may be configured to reduce a data reception error in a receiver by taking into consideration that a sound signal is noisy and is significantly affected by a change in the ambient environment when the acoustic communication is performed in the audio frequency band through modification of an audio signal or adding of a predetermined signal to an audio signal. Accordingly, the data reception error may be reduced in the receiver even in an environment where a sound signal is noisy and is significantly affected by a change in the ambient environment, and reliability of data transmission may increase. | 2012-10-25 |
20120269039 | AIRBORNE ULTRASONIC SENSOR - An airborne ultrasonic sensor capable of obtaining an asymmetric directivity pattern in a predetermined direction with a simple structure. The airborne ultrasonic sensor includes: a case whose one end is open and another end is a closed surface, so as to have a hollow portion; and a piezoelectric element which is disposed on an inner side of the closed surface, the closed surface being a vibration surface, in which the case has a side surface at least partially provided with a region which is obtained by removing the side surface from an opening surface side. The closed surface has a circular, elliptical, oval, square, or rectangular shape. | 2012-10-25 |
20120269040 | Seismic Vibrator Having Composite Baseplate - A seismic vibrator has a baseplate composed at least partially of a composite material. The baseplate has a body composed of the composite material and has top and bottom plates composed of a metallic material. The top plate supports isolators for isolating the vibrator's mass and frame from the baseplate. Internally, the composite body has a central structure to which couple stilts for supporting the mass and a piston for the vibrator's actuator. A lattice structure surrounds the central structure. This lattice structure has radial ribs extending from the central structure and has radial ribs interconnecting the radial ribs. | 2012-10-25 |
20120269041 | LED LIGHT MEANS WITH TIME PIECE - An LED light with a time piece uses a simple light-medium body with a very rough finish to allow light from LED(s) to pass though input-end(s) of the light-medium body and travel within the body and obtain a very even brightness on all surfaces of the light medium that are seen by a viewer. The movement for the time display can include analog indicators with a built-in light-medium on the top cover to achieve a super slim LED illumination for the time piece. For night light application, the sealed-unit may consist of prong-means and an LED related circuit sealed within a safety standard plastic material and assembled with the night light body to save a lot of cost enable use of all kinds of materials. The invention may also be adapted to an LCD display timepiece. | 2012-10-25 |
20120269042 | Electronic Timepiece and Time Adjustment Method - An electronic timepiece efficiently receives satellite signals, reduces power consumption, and displays the correct time. A GPS wristwatch | 2012-10-25 |
20120269043 | REGULATING MEMBER FOR A WRISTWATCH, AND TIMEPIECE COMPRISING SUCH A REGULATING MEMBER - Regulating member for a wristwatch movement, including:
| 2012-10-25 |