43rd week of 2013 patent applcation highlights part 17 |
Patent application number | Title | Published |
20130277801 | CHIP PACKAGE - According to an embodiment of the invention, a chip package is provided. The chip package includes: a lower chip package; an upper chip package disposed on an upper surface of the lower chip package; at least one conducting element disposed between the lower chip package and the upper chip package; and at least one decoupling capacitor disposed on the upper surface of the lower chip package, wherein the decoupling capacitor is not covered by the upper chip package, and the decoupling capacitor is electrically connected to a power line or a ground line in the lower chip package. | 2013-10-24 |
20130277802 | INTEGRATED CIRCUIT DEVICES WITH CAPACITOR AND METHODS OF MANUFACTURING THE SAME - An integrated circuit device with capacitors and methods of forming the integrated circuit device are provided. The methods may include forming a first lower capacitor electrode pattern on an inner surface of a hole in a mold layer. The first lower capacitor electrode pattern may have a hollow cylindrical shape and an opening in an upper surface. The method may further include forming a second lower capacitor electrode pattern plugging the opening and an upper surface of the second lower capacitor electrode pattern may be planar. The first and the second lower capacitor electrode patterns may comprise a lower capacitor electrode including a void. Additionally, the method may include removing the mold layer to expose the lower capacitor electrode, forming a dielectric layer on the lower capacitor electrode, and forming an upper capacitor electrode layer on the dielectric layer. | 2013-10-24 |
20130277803 | CONNECTION STRUCTURE FOR AN INTEGRATED CIRCUIT WITH CAPACITIVE FUNCTION - An embodiment, in a single structure, combines a pad including a connection terminal suitable for coupling the circuit elements integrated in a chip to circuits outside of the chip itself and at least one capacitor. By combining a connection pad and a capacitor in a single structure, it may be possible to reduce the overall area of the chip that otherwise in common integrated circuits would be greater due to the presence of the capacitor itself. In this way, the costs and size of the chip can be reduced. | 2013-10-24 |
20130277804 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Methods for fabricating a device structure such as a bipolar junction transistor, device structures for a bipolar junction transistor, and design structures for a bipolar junction transistor. The device structure includes a collector region formed in a substrate, an intrinsic base coextensive with the collector region, an emitter coupled with the intrinsic base, a first isolation region surrounding the collector region, and a second isolation region formed at least partially within the collector region. The first isolation region has a first sidewall and the second isolation region having a second sidewall peripherally inside the first sidewall. A portion of the collector region is disposed between the first sidewall of the first isolation region and the second sidewall of the second isolation region. | 2013-10-24 |
20130277805 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions. | 2013-10-24 |
20130277806 | LASER SUBMOUNTS FORMED USING ETCHING PROCESS - A wafer is formed having a plurality of laser-to-slider submount features on a first surface. An etching process is used to form scribe lines between the submounts on the first surface of the wafer. The wafer is separated at the scribe lines to form the submounts. | 2013-10-24 |
20130277807 | ELECTRONIC DEVICE INCLUDING A FEATURE IN AN OPENING - A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the filled trench may be exposed during a substrate thinning operation. In another embodiment, the trench can be filled with a thermal oxide. The feature can have a shape that reduces the likelihood that a distance between the feature and a wall of the trench will be changed during subsequent processing. A structure can be at least partly formed within the trench, wherein the structure can have a relatively large area by taking advantage of the depth of the trench. The structure can be useful for making electronic components, such as passive components and through-substrate vias. The process sequence to define the trenches and form the structures can be tailored for many different process flows. | 2013-10-24 |
20130277808 | DIPPING SOLUTION FOR USE IN PRODUCTION OF SILICEOUS FILM AND PROCESS FOR PRODUCING SILICEOUS FILM USING THE DIPPING SOLUTION - This invention relates to a dipping solution used in a process for producing a siliceous film. The present invention provides a dipping solution and a siliceous film-production process employing the solution. The dipping solution enables to form a homogeneous siliceous film even in concave portions of a substrate having concave portions and convex portions. The substrate is coated with a polysilazane composition, and then dipped in the solution before fire. The dipping solution comprises hydrogen peroxide, a foam-deposit inhibitor, and a solvent. | 2013-10-24 |
20130277809 | METHOD OF MANUFACTURING SILICON SINGLE CRYSTAL, SILICON SINGLE CRYSTAL, AND WAFER - P-type silicon single crystals from which wafers having high resistivity, good radial uniformity of resistivity and less variation in resistivity can be obtained, are manufactured by the Czochralski method from an initial silicon melt in which boron and phosphorus are present, the boron concentration is not higher than 4E14 atoms/cm | 2013-10-24 |
20130277810 | METHOD FOR FORMING HEAT SINK WITH THROUGH SILICON VIAS - Semiconductor devices are formed with through silicon vias extending into the semiconductor substrate from a backside surface for improved heat dissipation. Embodiments include forming a cavity in a backside surface of a substrate, the substrate including a gate stack on a frontside surface, and filling the cavity with a thermally conductive material. | 2013-10-24 |
20130277811 | STACKED INTERPOSER LEADFRAMES - A method of manufacturing integrated circuit (IC) devices includes the steps of providing a first frame that has openings each having a perimeter with shaped notches, placing a first die in at least one of the openings, and placing a second frame over the first frame. The second frame has a first partial dam bar with a first shaped tip that fits into a first shaped notch of the first frame. The method also includes the step of placing a third frame over the second frame. The third frame has a second partial dam bars with a second shaped tip that fits into a second shaped notch of the first frame. Each perimeter and the respective first and second partial dam bars cooperate to form a continuous dam completely encircling the die within the respective opening. | 2013-10-24 |
20130277812 | ELECTRONIC ASSEMBLY WITH IMPROVED THERMAL MANAGEMENT - The invention relates to an electronic assembly comprising a leadframe ( | 2013-10-24 |
20130277813 | CHIP PACKAGE AND METHOD OF FORMING THE SAME - Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip. | 2013-10-24 |
20130277814 | METHOD FOR FIXING SEMICONDUCTOR CHIP ON CIRCUIT BOARD AND STRUCTURE THEREOF - A method for fixing a semiconductor chip on a circuit board is provided, which includes following steps. The circuit board is provided, which sequentially includes a substrate having a chip connecting portion, at least one metal wire and an insulating layer. An organic insulating material is formed on the insulating layer of the outside edge of the chip connecting portion. An anisotropic conductive film (ACF) is then formed to cover the chip connecting portion and a portion of the organic insulating material. Finally, a semiconductor chip is hot-pressed on the ACF. The organic insulating material formed on the insulating layer is used to prevent the metal wires beneath the insulating layer from occurring of corrosion. A semiconductor chip package structure is also provided. | 2013-10-24 |
20130277815 | METHOD OF FORMING A THIN SUBSTRATE CHIP SCALE PACKAGE DEVICE AND STRUCTURE - In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure. | 2013-10-24 |
20130277816 | PLASTIC-PACKAGED SEMICONDUCTOR DEVICE HAVING WIRES WITH POLYMERIZED INSULATOR SKIN - The assembly of a chip ( | 2013-10-24 |
20130277817 | LEAD FRAME, SEMICONDUCTOR PACKAGE, AND MANUFACTURING METHOD OF THE SAME - A semiconductor package includes a lead frame including a chip mounting portion and a terminal portion, a semiconductor chip, which is mounted on the chip mounting portion and connected to the terminal portion, a through groove penetrating the terminal portion from one surface on a side of the semiconductor chip to another surface in a thickness direction of the terminal portion, a lid portion covering an end portion of the through groove on the side of the semiconductor chip, and a resin portion sealing the semiconductor chip, wherein the another surface of the terminal portion and a side surface of the terminal portion facing an outside of the semiconductor package are coated by a plating film. | 2013-10-24 |
20130277818 | CHIP CARRIER SUPPORT SYSTEMS - In one embodiment, a chip carrier support system includes a chip carrier support structure and a chip carrier. The chip carder forms a complementary fit with the chip carder support structure and includes an integrated circuit and a plurality of leads in communication with the integrated circuit. | 2013-10-24 |
20130277819 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a housing made of a thermoplastic resin and having an internal space that is opened on one side and an inner wall portion that has an inner peripheral surface defining the internal space; and a core portion engaged in the internal space of the housing. The core portion includes a substrate, a semiconductor element mounted on the substrate, a wire electrically connecting the substrate and the semiconductor element, and a mold resin sealing the substrate, the semiconductor element and the wire. The core portion has a side surface provided with a convex portion that is in contact with the inner peripheral surface of the inner wall portion. Accordingly, a semiconductor device allowing a lengthened life and improved productivity, and a method of manufacturing the semiconductor device can be provided. | 2013-10-24 |
20130277820 | SEMICONDUCTOR DEVICE - A semiconductor device configured to enable efficient cooling of an element and downsizing of the device. The semiconductor device including an element unit connected to a surface of a cooler. A support member that has a condenser housing chamber that houses the condenser. The condenser has two parallel planar surfaces that are parallel with each other. The condenser housing chamber has a parallel opposing surface that is arranged in parallel with the element unit arrangement surface and faces the element unit arrangement surface, and houses the condenser in a state where the two parallel planar surfaces are arranged in parallel with the parallel opposing surface. The support member is fixed to the cooler in a state where the parallel opposing surface presses the element unit toward the cooler. | 2013-10-24 |
20130277821 | THERMAL PACKAGE WTH HEAT SLUG FOR DIE STACKS - A semiconductor assembly comprises a package, which in turn comprises at least one substrate, a first die stacked onto the substrate, at least one further die stacked onto the first die, at least one heat spreader in the package, and TSV:s extending through the stacked dies. The ends of the TSV:s are exposed at the further die. | 2013-10-24 |
20130277822 | INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS AND THEIR FORMATION - An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric between the first and second conductors, and a conductive underpass under and coupled to the first and second conductors and passing under the dielectric or a conductive overpass over and coupled to the first and second conductors and passing over the dielectric. The second conductor would be floating but for its coupling to the conductive underpass or the conductive overpass. In other embodiments, another dielectric might be included that would electrically isolate the second conductor but for its coupling to the conductive underpass or the conductive overpass. | 2013-10-24 |
20130277823 | Split Loop Cut Pattern For Spacer Process - A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or trenches. Each quadrant can include one loop, or multiple nested loops. Further, the space pattern includes a single cross, or multiple nested crosses, which extend between the loops. A cut out area is defined which extends outward from the reference point to closed ends of the loops, also encompassing a central portion of the cross. When a metal wiring layer pattern is formed using the spacer pattern with the cut out area, metal wiring is excluded from the cut out area. The loop ends in the metal wiring layer are broken and can be used as independent active lines. | 2013-10-24 |
20130277824 | Manufacturing Method for Semiconductor Device and Semiconductor Device - In a method of manufacturing a semiconductor device, a first semiconductor element is mounted on a carrier. A b-stage curable polymer is deposited on the carrier. A second semiconductor element is affixed on the polymer. | 2013-10-24 |
20130277825 | Method for Preventing Corrosion of Copper-Aluminum Intermetallic Compounds - The packaging of an electric contact including a semiconductor chip ( | 2013-10-24 |
20130277826 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING BUMP-ON-LEAD INTERCONNECTION - A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate. | 2013-10-24 |
20130277827 | Semiconductor Device and Method of Forming Composite Bump-on-Lead Interconnection - A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The interconnect site has a width between 1.0 and 1.2 times a width of the trace. The composite interconnect is tapered. The composite interconnects have a fusible portion connected to the interconnect site and non-fusible portion connected to the bump pad. The non-fusible portion can be gold, copper, nickel, lead solder, or lead-tin alloy. The fusible portion can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead. An underfill material is deposited between the semiconductor die and substrate. A finish such as Cu—OSP can be formed over the substrate. | 2013-10-24 |
20130277828 | Methods and Apparatus for bump-on-trace Chip Packaging - Methods and apparatus for a solder mask trench used in a bump-on-trace (BOT) structure to form a semiconductor package are disclosed. A solder mask layer is formed on a trace and on a substrate. An opening of the solder mask layer, called a solder mask trench, is formed to expose the trace on the substrate. The solder mask trench has a width about a size of a diameter of a solder bump. A solder bump is landed directly on the exposed trace to connect a chip to the trace by an interconnect. With the formation of the solder mask trench, the trace exposed in the solder mask trench have a better grab force, which reduces the trace peeling failure for the semiconductor package. A plurality of solder mask trench rings may be formed in a package. | 2013-10-24 |
20130277829 | Method of Fabricating Three Dimensional Integrated Circuit - A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component. | 2013-10-24 |
20130277830 | Bump-on-Trace Interconnect - Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance. | 2013-10-24 |
20130277831 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package including a circuit board including a plurality of pads; a support structure disposed on the circuit board; and a plurality of semiconductor chips stacked on the circuit board and the support structure, each semiconductor chip including at least one pad. For each semiconductor chip, the at least one pad is aligned with a corresponding pad of the circuit board; and an electrical connection is formed between the at least one pad and the corresponding pad of the circuit board through the support structure. | 2013-10-24 |
20130277832 | METHOD OF MAKING CAVITY SUBSTRATE WITH BUILT-IN STIFFENER AND CAVITY SUBSTRATE MANUFACTURED THEREBY - The present invention relates to a method of making a cavity substrate. In accordance with a preferred embodiment, the method includes: preparing a supporting board including a stiffener, a bump/flange sacrificial carrier and an adhesive, wherein the adhesive bonds the stiffener to the sacrificial carrier; forming a coreless build-up circuitry on the supporting board in contact with the bump and the stiffener; and removing the bump and a portion of the flange to form a cavity and expose a conductive via of the coreless build-up circuitry from a closed end of the cavity, wherein the cavity is laterally covered and surrounded by the adhesive. A semiconductor device can be mounted on the cavity substrate and electrically connected to the conductive via. The coreless build-up circuitry provides signal routing for the semiconductor device while the stiffener can provide adequate mechanical support for the coreless build-up circuitry and the semiconductor device. | 2013-10-24 |
20130277833 | PAD STRUCTURE OF A SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE PAD STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE PAD STRUCTURE - A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion- to provide high roughness and firm connection. | 2013-10-24 |
20130277834 | FLIP CHIP PACKAGE WITH SHELF AND METHOD OF MANUFACTURING THEREOF - The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of the excess underfill by providing a shelf in the semiconductor chip. | 2013-10-24 |
20130277835 | SEMICONDUCTOR DEVICE - A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad. | 2013-10-24 |
20130277836 | METHOD AND STRUCTURE OF SENSORS AND MEMS DEVICES USING VERTICAL MOUNTING WITH INTERCONNECTIONS - A method and structure for fabricating sensor(s) or electronic device(s) using vertical mounting with interconnections. The method includes providing a resulting device including at least one sensor or electronic device, formed on a die member, having contact region(s) with one or more conductive materials formed thereon. The resulting device can then be singulated within a vicinity of the contact region(s) to form one or more singulated dies, each having a singulated surface region. The singulated die(s) can be coupled to a substrate member, having a first surface region, such that the singulated surface region(s) of the singulated die(s) are coupled to a portion of the first surface region. Interconnections can be formed between the die(s) and the substrate member with conductive adhesives, solder processes, or other conductive bonding processes. | 2013-10-24 |
20130277837 | CONTROLLED SOLDER-ON-DIE INTEGRATIONS ON PACKAGES AND METHODS OF ASSEMBLING SAME - A process of bumping a die backside includes opening a recess in a die backside film (DBF) to expose a through-silicon via (TSV) contact in a die, followed by filling the recess with a conductive material that contacts the TSV contact. Added solder is coupled to the conductive material at a level of the DBF. A subsequent die is coupled to the first die at the added solder to form an electrical coupling consisting of the TSV contact, the conductive material, and the added solder, an electrical bump coupled to the subsequent die. Apparatus and computer systems are assembled using the process. | 2013-10-24 |
20130277838 | Methods and Apparatus for Solder Connections - Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed. | 2013-10-24 |
20130277839 | CHIP PACKAGE AND METHOD FOR ASSEMBLING SAME - A chip package includes a PCB, a chip positioned on the PCB and bonding wires electrically connecting the chip to the PCB. The PCB includes a number of first bonding pads formed thereon. Each first bonding pad includes a first soldering ball. The chip includes a number of second bonding pads. Each second bonding pad includes a second bonding ball. Each bonding wire electrically connects a first bonding pad to a corresponding second bonding ball. Each bonding wire forms a vaulted portion upon the first bonding ball. | 2013-10-24 |
20130277840 | Thermally Enhanced Structure for Multi-Chip Device - A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved. | 2013-10-24 |
20130277841 | Rigid Interconnect Structures in Package-on-Package Assemblies - System and method are disclosed for creating a rigid interconnect between two substrate mounted packages to create a package-on-package assembly. A solid interconnect may have a predetermined length configured to provide a predetermined package separation, may be cylindrical, conical or stepped, may be formed by extrusion, casting, drawing or milling and may have an anti-oxidation coating. The interconnect may be attached to mounting pads on the top and bottom packages via an electrically conductive adhesive, including, but not limited to solder and solder paste. A solder preservative or other anti-oxidation coating may be applied to the mounting pad. A package-on-package assembly with solid interconnects may have a top package configured to accept at least one electronic device, with the solid interconnects mounted between the top package and a bottom package to rigidly hold the package about parallel to each other. | 2013-10-24 |
20130277842 | COPPER INTERCONNECT WITH CVD LINER AND METALLIC CAP - A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap. | 2013-10-24 |
20130277843 | FLIP CHIP MOUNTED MONOLITHIC MICROWAVE INTEGRATED CIRCUIT (MMIC) STRUCTURE - A MMIC flip chip mounted to a circuit board having an underfill material disposed between the MMIC and the circuit board and a barrier structure for preventing the underfill material from being disposed under an electronic device of the MMIC while providing a cavity under the electronic device. | 2013-10-24 |
20130277844 | THROUGH VIA PROCESS - A semiconductor component having a semiconductor substrate including an integrated circuit (IC) component, an interlayer dielectric (ILD) layer formed on the semiconductor substrate, a contact plug formed in the ILD layer and electrically connected to the IC component, a via plug formed in the ILD layer and extending through a portion of the semiconductor substrate, wherein the top surfaces of the ILD layer, the via plug and the contact plug are leveled off, and an interconnection structure comprising a plurality of metal layers formed in a plurality of inter-metal dielectric (IMD) layers, wherein a lowermost metal layer of the interconnection structure is electrically connected to the exposed portions of the contact plug and the via plug. | 2013-10-24 |
20130277845 | STRUCTURE OF BACKSIDE COPPER METALLIZATION FOR SEMICONDUCTOR DEVICES AND A FABRICATION METHOD THEREOF - An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, in which the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, at least one thermal expansion buffer layer, a backside metal layer, and at least one oxidation resistant layer, in which the backside metal seed layer is formed of Pd, and the thermal expansion coefficient of the thermal expansion buffer layer is in the range between the thermal expansion coefficients of the backside metal seed layer and of the backside metal layer. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations. | 2013-10-24 |
20130277846 | CIRCUIT ARRANGEMENT FOR A THERMALLY CONDUCTIVE CHIP ASSEMBLY AND A MANUFACTURING METHOD - The circuit arrangement according to the invention provides a substrate ( | 2013-10-24 |
20130277847 | CHIP PACKAGE AND METHOD FOR ASSEMBLING CHIP PACKAGE - A chip package includes a PCB, a connecting pad fixed on a surface of the PCB and a chip fixed on the connecting pad. The connecting pad includes a first metal film on its surface facing away from the PCB. The chip includes a second metal film formed on its surface opposite to the PCB. The first and the second metal are connected to each other via a eutectic manner. | 2013-10-24 |
20130277848 | METHOD OF FORMING CONTACT AND SEMICONDUCTOR DEVICE MANUFACTURED BY USING THE METHOD - A method of forming a contact includes forming an inter-layer dielectric layer to cover a gate formed on a semiconductor substrate; and forming a first hole which passes through the inter-layer dielectric layer to expose the gate, a second hole which exposes an active region of the semiconductor substrate, and a third hole which exposes the semiconductor substrate at a preset depth. Further, the method includes forming a shielding layer on the semiconductor substrate including the bottom and sidewalls of the first hole, the second hole, and the third hole; and removing the shielding layer at the bottom of the first hole and the second hole to expose the gate and the active region. Furthermore, the method includes filling the first hole, the second hole, and the third hole with a conductive material. | 2013-10-24 |
20130277849 | INTERNAL WIRING STRUCTURE OF SEMICONDUCTOR DEVICE - Aspects of the invention provide an internal wiring structure of a power semiconductor device, which is capable of reducing a mutual inductance between two wiring conductors and improving the heat dissipation effect, the two wiring conductors being disposed so as to oppose each other and having currents flowing in the same direction. In some aspects, notches can be formed alternately from side walls of two flat plates, on the flat plates, to obtain two wiring conductors. The two wiring conductors can be disposed so as to oppose each other and in parallel to each other so that currents flow along the notches in directions opposite to each other. Accordingly, in some circumstances, the mutual inductance can be reduced. Further, in some circumstances, the dimensions of the planes of the wiring conductors obtained by forming the notches can be increased to improve the heat dissipation. | 2013-10-24 |
20130277850 | ELECTRONIC DEVICE - An electronic device includes a substrate and an electronic component. The substrate has a metallization trace. The metallization trace has a metallization layer and a synthetic resin layer. The metallization layer has a high-melting-point metallic component and a low-melting-point metallic component. The high-melting-point metallic component and the low-melting-point metallic component are diffusion bonded together and adhered to a surface of the substrate. The synthetic resin layer is formed simultaneously with the metallization layer to cover a surface of the metallization layer with a thickness in the range of 5 nm to 1000 nm. The electronic component is electrically connected to the metallization layer. | 2013-10-24 |
20130277851 | Semiconductor Method and Device of Forming a Fan-Out Device with PWB Vertical Interconnect Units - A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die. | 2013-10-24 |
20130277852 | Method for Creating a 3D Stacked Multichip Module - A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2 | 2013-10-24 |
20130277853 | Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Forming Conductive Features - Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof. | 2013-10-24 |
20130277854 | 3D INTEGRATED CIRCUIT SYSTEM WITH CONNECTING VIA STRUCTURE AND METHOD FOR FORMING THE SAME - A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars. | 2013-10-24 |
20130277855 | HIGH DENSITY 3D PACKAGE - Embodiments of the present provide an integrated circuit system, which includes an interposer having a plurality of electrical conductive vias running through the interposer, one or more high-power chips mounted on a first surface of the interposer, wherein the one or more high-power chips generate at least 10 W of heat during normal operation, one or more low-power chips mounted on a second surface of the interposer, wherein the one or more low-power chips generate less than 5 W of heat during normal operation, and the first surface and the second surface are opposite and substantially parallel to each other, and an encapsulating material formed over and configured to encapsulate the one or more high-power chips and the one or more low-power chips. Since low-power chips and high-power chips are respectively mounted on front side and back side of the interposer, the footprint of the interposer and manufacturing cost associated therewith is reduced. | 2013-10-24 |
20130277856 | METHOD FOR STABILIZING EMBEDDED SILICON - A method for disclosing an integrated circuit embedded in a resin is disclosed. In one embodiment, stabilizing vias can be formed within the resin and can couple to corresponding pads in the integrated circuit. The stabilizing vias can be used in areas prone to failure when the combined resin/integrated circuit is stressed or undergoes some amount of displacement. In one embodiment, the stabilizing vias can be non-functional vias that do not carry electrical signals or power to or from the integrated circuit. | 2013-10-24 |
20130277857 | STACK TYPE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING AND TESTING THE SAME - There are proposed a stack type semiconductor device and a method of fabricating and testing the same. A stack type semiconductor device according to an embodiment of the present invention includes a plurality of contact pads externally exposed, a via array electrically connected to the contact pads, a semiconductor substrate configured to have vias, forming the via array, electrically conductive with each other or insulated from each other, and a bias pad configured to supply a bias to the semiconductor substrate, wherein the semiconductor substrate may be subject to back-grinding. | 2013-10-24 |
20130277858 | ELECTRICAL INTERCONNECTION STRUCTURE AND ELECTRICAL INTERCONNECTION METHOD - An electrical interconnection structure includes: a signal transmission structure having a first through silicon via (TSV) and signal circuits connected to two opposite ends of the first TSV, respectively; and a grounding structure having a second TSV and grounding layers connected to two opposite ends of the second TSV, respectively. The grounding layers surround the signal circuits along the pathways thereof such that the ends of the first TSV are surrounded by the grounding layers with gaps therebetween. By changing the gaps between the grounding layers and the ends of the first TSV, the capacitance between the grounding layers and the signal circuits is adjusted so as to regulate the impedance therebetween. | 2013-10-24 |
20130277859 | FABRICATION OF SEMICONDUCTOR DEVICE INCLUDING CHEMICAL MECHANICAL POLISHING - A method of fabricating a semiconductor device includes forming a first insulation film over a semiconductor substrate, the semiconductor substrate including an outer region and an inner region located at an inner side of the outer region, forming a first wiring over the first insulation film in the inner region, forming a second insulation film over the first wiring and over the first insulation film, decreasing a film thickness of the second insulation film in the inner region with regard to a film thickness of the second insulation film in the outer region, and polishing the second insulation film after the decreasing of the film thickness of the second insulation film. | 2013-10-24 |
20130277860 | Chip Pad Resistant to Antenna Effect and Method - A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC. | 2013-10-24 |
20130277861 | VERTICALLY STACKABLE DIES HAVING CHIP IDENTIFIER STRUCTURES - A particular device includes a first die that includes a portion of a chip identifier structure, the portion including a first set of at least two through vias that are each connected to a corresponding external electrical contact of a first set of external electrical contacts. Each of the first set of through vias has a pad configured to be coupled to an adjacent through via of a second die in the chip identifier structure. Each external electrical contact of the first set of external electrical contacts is configured to transmit a chip select signal. The first die further includes at least a portion of a chip communication structure including a second set of at least one through via. Each via of the second set is connected to one external electrical contact of a second set of external electrical contacts. | 2013-10-24 |
20130277862 | INTERMEDIATE FOR ELECTRONIC COMPONENT MOUNTING STRUCTURE, ELECTRONIC COMPONENT MOUNTING STRUCTURE, AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT MOUNTING STRUCTURE - An implementing structure intermediate body including: a first chip having a first connection terminal; a second chip having a second connection terminal in a face that faces the first chip; and a film wiring substrate having a third connection terminal in one face, which is arranged between the first chip and the second chip, is loaded on a chip loading substrate having a fifth connection terminal so that another one face of the first chip is confronted thereby. In the film wiring substrate, there is a portion that is located outside any of the first chip and the second chip, at the tip part, is provided a fourth connection terminal connected to the third connection terminal by wiring, one part of the first connection terminal is connected with the second connection terminal, the third connection terminal is connected with another one part of the first connection terminal, and the fifth connection terminal is connected to the fourth connection terminal. | 2013-10-24 |
20130277863 | SOLDERABLE PAD FABRICATION FOR MICROELECTRONIC COMPONENTS - Two microelectronic components can be attached by flowing solder between solderable pads patterned on interfacing surfaces. According to one implementation, the microelectronic components can include the solderable pads patterned onto first respective surfaces and other surface features patterned onto second respective surfaces. In another implementation, the solderable pads can include an adhesion layer, a diffusion barrier layer, and surface oxidation layer. | 2013-10-24 |
20130277864 | METHOD FOR PRODUCING A COMPONENT AND DEVICE COMPRISING A COMPONENT - A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit. | 2013-10-24 |
20130277865 | MULTI DIE PACKAGE STRUCTURES - Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies. | 2013-10-24 |
20130277866 | Methods for Multi-Wire Routing and Apparatus Implementing Same - A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels. | 2013-10-24 |
20130277867 | EPOXY RESIN COMPOSITION FOR SEALING, AND ELECTRONIC COMPONENT DEVICE - The present invention provides an epoxy resin composition for sealing that demonstrates favorable adhesion to a copper lead frame in which oxidation has progressed and has superior mold release and continuous moldability. The epoxy resin composition for sealing includes (A) an epoxy resin, (B) a phenolic resin-based curing agent, (C) an inorganic filler, and (D) a curing accelerator. The curing accelerator (D) has an average particle diameter of 10 μm or less, and the ratio of particles having a particle diameter in excess of 20 μm is 1% by weight or less. Also, the curing accelerator (D) includes at least one type of curing accelerator selected from the group consisting of a phosphobetaine compound having a specific structure; adduct of a phosphine compound having a specific structure, and quinone compound; and an adduct of a phosphonium compound having a specific structure, and a silane compound. An electronic component device in which an electronic component is sealed by a cured product of the aforementioned epoxy resin composition for sealing is provided. | 2013-10-24 |
20130277868 | PARTITIONED DISTRIBUTOR TRAY FOR OFFSHORE GAS/LIQUID CONTACT COLUMN - The invention is a distributor tray for a column ( | 2013-10-24 |
20130277869 | DISTRIBUTOR TRAY FOR OFFSHORE GAS/LIQUID CONTACT COLUMN - The invention is a distributor tray for a column ( | 2013-10-24 |
20130277870 | METHOD OF MANUFACTURING A NANO-LAYERED LIGHT GUIDE PLATE - The present invention provides a method of manufacturing a nano-layered light guide plate comprising, forming by a coextrusion method a multi-layered molten sheet comprising a plurality of two or more different alternating material layers and casting the coextruded sheet into a nip between a pressure roller and a pattern roller to form a nano-layered sheet having a discrete micro-pattern on at least one principal surface thereof. In addition, the invention further provides cutting and finishing the extruded micro-patterned sheet to form the nano-layered light guide plate, comprising a plurality of two or more different alternating material layers, with each layer having a thickness of less than a quarter wavelength of visible light. | 2013-10-24 |
20130277871 | PROCESS FOR PRODUCING WATER-RESISTANT POLARIZING FILM - To obtain a water-resistant polarizing film free from deterioration in dichroic ratio caused by water-resistant treatment, it is critical that adjacent sulfonic acid groups or sulfonate groups in the organic dyes to be used for the polarizing film are spaced at moderate intervals. In a process for producing a water-resistant polarizing film of the present invention, the polarizing film before water-resistant treatment includes an organic dye which comprises an azo compound | 2013-10-24 |
20130277872 | PROCESS FOR THE PRODUCTION OF ACTIVE SUBSTANCE BEADS - The present invention relates to a process for the automated production of active substance beads having a gel-like carrier material, preferably a biopolymer, such as agarose, and having embedded in the carrier material a biologically active material, such as an active substance and/or a material which generates an active substance, comprising the following steps: | 2013-10-24 |
20130277873 | METHOD FOR MANUFACTURING A DENTAL PROSTHESIS - A method of fabricating a dental prosthesis, the method comprising the following steps:
| 2013-10-24 |
20130277874 | METHODS OF MAKING MULTILAYER ANATOMICAL ALL-CERAMIC DENTAL APPLIANCES - A method of making a multilayer all-ceramic dental appliance. A first article can be formed of a first material based on a first digital surface representation having a desired outer shape of the dental appliance. A portion of the first article can be removed to form an outer layer comprising a cavity dimensioned to accommodate an inner layer. A second article can be formed by filling the cavity of the first article with a second material. The second article can be further processed, as desired. For example, a desired inner shape can be formed in the second article. Such a desired inner shape can be based on a second digital surface representation of a dental object configured to receive the dental appliance. At least one of the first article, the outer layer, and the second article can be fired, for example, while still being coupled to a support. | 2013-10-24 |
20130277875 | Method and Apparatus for Producing Carbon Fiber - A carbon fiber centrifugal head includes an interior mechanism that at least partially controls flow of precursor material to exterior holes of the head during spinning. | 2013-10-24 |
20130277876 | AUTOMATED HARDNESS AND MOISTURE CONTROL IN RAW MATERIAL PROCESSING SYSTEMS - In accordance with one embodiment of the present invention, a system for controlling the properties of an extrusion from a production line is provided. The production line comprises a raw material feed, a mixer, and an extruder. The control system comprises one or more ammeters electrically coupled to an electrically driven mixing motor and an electrically driven extrusion motor. Output signals indicative of the load amperes I | 2013-10-24 |
20130277877 | FOAM MOLDED BODY PRODUCTION DEVICE AND FOAM MOLDED BODY PRODUCTION METHOD - A production device ( | 2013-10-24 |
20130277878 | Permselective Membrane and Process for Manufacturing Thereof - A method for preparing by solvent phase inversion spinning a hollow fiber membrane suitable for dialysis. The membrane includes at least one hydrophobic polymer and at least one hydrophilic polymer. An outer surface of the membrane is characterized by pores having sizes in the range of 0.5-3 μm, with the density of the pores on the outer surface of the membrane being in the range of 10,000 to 150,000 pores per mm | 2013-10-24 |
20130277879 | ELEVATOR LOAD BEARING MEMBER HAVING A JACKET WITH AT LEAST ONE ROUGH EXTERIOR SURFACE - An illustrative method of making a load bearing member for use in an elevator system includes mechanically roughening at least one surface on an exterior of a jacket of the load bearing member to establish a friction characteristic that facilitates engagement between an elevator system sheave and the roughened surface. | 2013-10-24 |
20130277880 | Process for Manufacturing a Rubber Strip for a Tire, Comprising Water-Cooling Means - In the method of manufacturing a strip ( | 2013-10-24 |
20130277881 | METHOD FOR MANUFACTURING LIGHT TRANSMISSIVE FILM, ACTIVE ENERGY RAY-CURABLE COMPOSITION, AND LIGHT TRANSMISSIVE FILM - A method for manufacturing a light transmissive film having a cured resin layer with a fine concavo-convex structure on a surface of a base material film is provided. The method includes sandwiching an active energy ray-curable composition including a mold dissolving component between a mold having an inversion structure of the fine concavo-convex structure and the base material film, obtaining a light transmissive film in which a cured resin layer having the inversion structure of the mold transferred is formed on one surface of the base material film, and separating the obtained light transmissive film and the mold. Thus, it is possible to productively manufacture a light transmissive film, and to prevent the deposition of an attachment on the mold surface and the contamination of the mold surface. Moreover, a light transmissive film can be manufactured having excellent performances, such as antireflection properties. | 2013-10-24 |
20130277882 | INORGANIC HOLLOW YARNS AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a method of manufacturing inorganic hollow yarns, such as cermets, oxide-non oxide composites, poorly sinterable non-oxides, and the like, at low costs. The method includes preparing a composition comprising a self-propagating high temperature reactant, a polymer and a dispersant, wet-spinning the composition through a spinneret to form wet-spun yarns, washing and drying the wet-spun yarns to form polymer-self propagating high temperature reactant hollow yarns, and heat-treating the polymer-self propagating high temperature reactant hollow yarns to remove a polymeric component from the polymer-self propagating high temperature reactant hollow yarns while inducing self-propagating high temperature reaction of the self-propagating high temperature reactant to form inorganic hollow yarns. The composition comprises 45˜60 wt % of the self-propagating high temperature reactant, 6˜17 wt % of the polymer, 0.1˜4 wt % of the dispersant, and the balance of an organic solvent. | 2013-10-24 |
20130277883 | METHOD AND DEVICE FOR ARRANGING A LABEL IN A MOULD - Methods and structures are shown for a variety of ways to arrange a label in a mould cavity. One is a method for arranging a label in a mould cavity of a mould, which mould cavity is delimited by an internal peripheral surface that defines a first axial axis of the mould cavity, the method comprising: providing a mandrel having a peripheral wall that defines an axial direction and a peripheral direction, wherein the peripheral wall further defines a second axial axis, the peripheral wall being provided with: a peripheral part having a shape that substantially corresponds to a shape of a part of the internal peripheral surface of the mould cavity, and a non-convex part that extends in the axial direction of the peripheral wall of the mandrel, arranging the label around the peripheral wall of the mandrel, which label comprises a first side edge part and a second side edge part, in which the label is arranged around the peripheral wall of the mandrel in such a manner that the second side edge part overlaps the first side edge part viewed in the peripheral direction of the mandrel at a location of the non-convex part of the peripheral wall of the mandrel, introducing the mandrel with the label arranged around the peripheral wall thereof into the mould cavity, transferring the label from the peripheral wall of the mandrel to the internal peripheral surface of the mould cavity, wherein the mandrel and the mould are arranged with respect to one another in such a manner during transfer of the label from the peripheral wall of the mandrel to the internal peripheral surface of the mould cavity, that the first axial axis of the internal peripheral surface of the mould cavity and the second axial axis of the peripheral wall of the mandrel are eccentric with respect to one another. | 2013-10-24 |
20130277884 | METHOD AND APPARATUS FOR CREATING FORMED ELEMENTS USED TO MAKE WOUND STENTS - A method for forming a wave form for a stent includes moving a first forming portion of a first forming member across an axis along which a formable material is provided in a first direction substantially perpendicular to the axis to engage and deform the formable material while engaging the formable material with a first forming portion of the second forming member. The method includes moving the first forming portion of the first forming member and the first forming portion of the second forming member across the axis in a second direction that is substantially opposite the first direction to draw and form the formable material over the first forming portion of the second forming member, disengaging the first forming member from the formable material, and moving the first forming member to position a second forming portion of the first forming member to face the formable material. | 2013-10-24 |
20130277885 | CONTROL DEVICE FOR MOLDING MACHINE AND MANUFACTURING METHOD FOR MOLDED ARTICLE - A molding machine is provided with a display section with a touchpanel. A first storage section of a storage device is stored with molding conditions corresponding to molded articles each affixed with identification information. A second storage section is stored with image data on the molded articles each affixed with identification information. A third storage section is stored with memo information corresponding to the molded articles each affixed with identification information. When an image selection switch section on the display section is operated, the screen is changed to an image list screen and a plurality of images called up from the second storage section are listed. If one of these images is touched, the screen is changed to a detail display screen. | 2013-10-24 |
20130277886 | MOLD FOR VEHICLE BUMPER FASCIA AND ASSOCIATED MOLDING TECHNIQUE - A mold for producing a vehicle bumper fascia and methods for releasing the bumper fascia are provided. The mold includes a core mold half having a primary mold core. A first movable mold core is slidingly engaged to the primary mold core. A second movable mold core is slidingly engaged to the first movable mold core. A third movable mold core is slidingly engaged to the second movable mold core. Portions of the primary mold core and the movable mold cores together define cavities for forming the mounting rib, a wing portion, and a wheel well flange of the bumper fascia. Methods of releasing the bumper fascia include the steps of providing the mold, disengaging the movable mold cores from each other and from the primary mold core. | 2013-10-24 |
20130277887 | PROCESS FOR PRODUCING INFUSION PACKETS - Provided is a process for thermoforming a gas and liquid permeable layer of thermoplastic material ( | 2013-10-24 |
20130277888 | PROCESS FOR THERMOFORMING INFUSION PACKETS - Provided is a process for thermoforming a gas and liquid permeable layer ( | 2013-10-24 |
20130277889 | METHOD AND APPARATUS FOR MANUFACTURING SILICON SEED RODS - A method and apparatus for manufacturing high-purity long silicon seed rods with controlled resistivity for Siemens and similar processes with using a film of silicon dioxide, wherein a film of silicon dioxide is formed on the seed rod in the course of a reaction between a silicon melt and oxygen. The rod is formed with a quartz die and cooled by direct immersion into a cooling fluid, such as de-ionized water and/or by cooling fluid vapor in the gas cooling zone. | 2013-10-24 |
20130277890 | Dual-Cure Polymer Systems - The present invention includes compositions that are useful to prepare dual-cure shape memory polymer systems. The present invention further provides methods of generating a shape memory polymer, optical device, polymer pad with an imprint, or suture anchor system. | 2013-10-24 |
20130277891 | METHOD FOR MANUFACTURING AN OBJECT BY SOLIDIFYING A POWDER USING A LASER - This process for manufacturing an object by solidifying a powder (P) includes steps of: a) depositing a powder layer (P) on a working zone (Z); b) compacting this layer; c) solidifying a first zone ( | 2013-10-24 |
20130277892 | METHOD OF TREATING PLASTICS MATERIAL CONTAINERS WITH REDUCTION OF TIME DURING THE SYNCHRONIZATION OF PARTS OF THE PLANT - A method of treating plastics material pre-forms may include conveying plastics material pre-forms by means of a conveying device, heating the plastics material pre-forms, during said conveying step, by a heating device, and treating the plastics material pre-forms, after said heating step, by a further treatment device in a further pre-set manner. The heating device and the further treatment device are operated in a synchronized manner at least for a time. In the event of an error state occurring in said further treatment device arranged downstream of the heating device, a supply of the plastics material pre-forms to the heating device is interrupted by means of a blocking device. Chronologically after the occurrence of the error state the further treatment device is brought into synchronism again with the heating device during a pre-set synchronization period. The supply of the plastics material pre-forms to the heating device is permitted again during the synchronization period or at the start of the synchronization. | 2013-10-24 |
20130277893 | MICROTITRE PLATE - A method of manufacturing a microtitre plate with wells having transparent bottoms, where the microtitre plate includes at least one physical deformation between at least two adjacent wells. | 2013-10-24 |
20130277894 | Method of Preparing Silver-Based Electrical Contact Materials with Directionally Arranged Reinforcing Particles - A method of preparing silver-based electrical contact materials with directionally arranged reinforcing particles includes steps of: (1) preparing composite powders with Ag coating on the reinforcing phase by chemical plating coating; (2) granulating; (3) placing the granulated powders and the matrix silver powders into the powder mixer for mixing; (4) cold-isostatically pressing; (5) sintering; (6) hot-presssing; (7) hot-extruding, thereby obtaining the reinforcing silver-based electrical contact materials with directionally arranged particles. Regardless of the size of reinforcing particles, the present invention can obtain particle-reinforced silver-based materials with excellent electrical performance The process is simple and easy to operate, and places no special requirements on the equipment. Furthermore, the resistance to welding and arc erosion, and the conductivity of the material prepared by the present invention can be greatly improved. Moreover, the processing performance is excellent. | 2013-10-24 |
20130277895 | SPUTTERING TARGET AND MANUFACTURING METHOD THEREOF, AND TRANSISTOR - One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×10 | 2013-10-24 |
20130277896 | PROCESS AND INSTALLATION FOR HEATING A METALLIC STRIP, NOTABLY FOR AN ANNEALING - The invention pertains to the heating of a metal strip, and relates to equipment for heating a metal strip that comprises a pre-heating housing provided with a device for projecting hot gases towards the strip, a heating housing with regenerative burners, a duct for discharging the gases from the heating housing, a three-way adjustable valve and an adjustment device including a sensor for detecting the setpoint temperature of the metal strip and a member for adjusting the three-way valve so that it can adjust the amount of hot gases fed to the projection device. The invention can be used in equipment for heating narrow strips before annealing the same. | 2013-10-24 |
20130277897 | STEEL WIRE TEMPERING LIQUID WIPING DEVICE - The present invention discloses a steel wire tempering liquid wiping device. The device comprises a shell. A thermal insulation layer is provided on an inner wall of the shell, and a steel wire inlet and a steel wire outlet are provided on the shell. A wiping fiber rack is installed in a wiping cavity, and a tempering liquid wiping fiber is installed on the wiping fiber rack and is high temperature resistant fibers. After tempering, the steel wires pass through the tempering liquid wiping fiber. At the bottom of the wiping fiber rack, a tempering liquid recovery device is arranged. A heating device is installed in the shell. The steel wires come out from a high temperature tempering furnace, and then enter the steel wire tempering liquid wiping device. | 2013-10-24 |
20130277898 | SAFETY DEVICE DESIGNED TO WITHHOLD THE ELASTIC SUPPORT ASSOCIATED TO THE TOP END OF THE STEM OF A SHOCK ABSORBER IN THE CORRESPONDING SEAT OF THE BODY OF A MOTOR VEHICLE - A safety device withholds an elastic support associated to the top end of the stem of a motor vehicle shock absorber. The device includes a safety member configured for engaging a metal reinforcement of the elastic support. The safety member includes a metal structure provided with a coating of elastomeric material, so as to close completely and in a fluid-tight way the cavity in which the stem of the shock absorber is received, thus also reducing noise. | 2013-10-24 |
20130277899 | Attaching Device for End of Spring - There is disclosed a device for fixing a U-shaped end of at least one spring for supporting a cushion for a seat, to a seat frame of the seat which includes opposing frame sections, one of the frame sections being formed from a shaft, and the spring being stretched between the frame sections. The device comprises a collar fitted over the shaft and a retainer including a body having a geometry of similar figure with the collar and fitted over the collar on the shaft, and at least one pair of first and second spring engagement pieces provided at both edges of the body. A first axial region and second axial region of the U-shaped end of the spring are engaged with the first piece and the second piece, respectively, whereby the end of the spring is fixed to the shaft through the device. | 2013-10-24 |
20130277900 | LIQUID-FILLED VIBRATION DAMPING DEVICE - An excellent liquid-filled vibration damping device is provided, which is capable of effectively suppressing cavitation, which may otherwise cause abnormal noises, without impairing a vibration damping effect. The inventive liquid-filled vibration damping device includes a liquid-filled space partitioned into a primary liquid chamber and a secondary liquid chamber communicating with each other through an orifice, a molded vulcanized rubber member which defines at least a part of the liquid-filled space, and a first retention member and a second retention member retaining the molded vulcanized rubber member. Liquid (P) to be sealingly contained in the liquid-filled space comprises a polar organic solvent as a major component, and not less than 0.2 cm | 2013-10-24 |