43rd week of 2014 patent applcation highlights part 17 |
Patent application number | Title | Published |
20140312446 | SEMICONDUCTOR STRUCTURE ABLE TO RECEIVE ELECTROMAGNETIC RADIATION, SEMICONDUCTOR COMPONENT AND PROCESS FOR FABRICATING SUCH A SEMICONDUCTOR STRUCTURE - A semiconducting structure configured to receive electromagnetic radiation and transform the received electromagnetic radiation into an electric signal, the semiconductor structure including a semiconducting support within a first surface defining a longitudinal plane, a first zone with a first type of conductivity formed in the support with a second zone with a second type of conductivity that is opposite of the first type of conductivity to form a semiconducting junction. A mechanism limiting lateral current includes a third zone formed in the support in lateral contact with the second zone, the third zone having the second type of conductivity for which majority carriers are electrons. The third zone has a sufficient concentration of majority carriers to have an increase in an apparent gap due to a Moss-Burstein effect. | 2014-10-23 |
20140312447 | LATERAL LIGHT SHIELD IN BACKSIDE ILLUMINATED IMAGING SENSORS - A backside illuminated image sensor includes a semiconductor layer and a trench disposed in the semiconductor layer. The semiconductor layer has a frontside surface and a backside surface. The semiconductor layer includes a light sensing element of a pixel array disposed in a sensor array region of the semiconductor layer. The pixel array is positioned to receive external incoming light through the backside surface of the semiconductor layer. The semiconductor layer also includes a light emitting element disposed in a periphery circuit region of the semiconductor layer external to the sensor array region. The trench is disposed in the semiconductor layer between the light sensing element and the light emitting element. | 2014-10-23 |
20140312448 | Integrated Avalanche Photodiode Arrays - The present disclosure includes devices for detecting photons, including avalanche photon detectors, arrays of such detectors, and circuits including such arrays. In some aspects, the detectors and arrays include a virtual beveled edge mesa structure surrounded by resistive material damaged by ion implantation and having side wall profiles that taper inwardly towards the top of the mesa structures, or towards the direction from which the ion implantation occurred. Other aspects are directed to masking and multiple implantation and/or annealing steps. Furthermore, methods for fabricating and using such devices, circuits and arrays are disclosed. | 2014-10-23 |
20140312449 | LATERAL AVALANCHE PHOTODIODE DEVICE AND METHOD OF PRODUCTION - A lateral avalanche photodiode device comprises a semiconductor substrate ( | 2014-10-23 |
20140312450 | Small Size, Weight, and Packaging of Image Sensors - A method and structure of an image sensor device including a read out integrated circuit (ROIC) and a photodiode array (PDA). An embodiment may include a package substrate having a recess and a raised pedestal within the recess; a read out integrated circuit (ROIC) physically attached to the raised pedestal; a photodiode array (PDA) physically attached to the ROIC and electrically coupled therewith; and a printed circuit board (PCB) within the recess in the package substrate, wherein the PCB has an opening therein and the raised pedestal at least partially extends through the opening in the PCB. | 2014-10-23 |
20140312451 | SOLID-STATE IMAGING ELEMENT, MANUFACTURING METHOD, AND ELECTRONIC DEVICE - A solid-state imaging element includes a pixel having a photoelectric conversion section and a side pinning layer. The photoelectric conversion section is formed in a semiconductor substrate. The side pinning layer is formed on a side of the photoelectric conversion section. The side pinning layer is formed by performing ion implantation in a state of a trench being open, the trench being formed in a part on a side of a region in which the photoelectric conversion section is formed. | 2014-10-23 |
20140312452 | SEMICONDUCTOR DEVICE AND TERMINATION REGION STRUCTURE THEREOF - A termination region structure of a semiconductor device is provided, which includes: a semiconductor layer; a plurality of trenches, formed on a surface of the semiconductor layer; a connecting trench, formed on the surface of the semiconductor layer, for connecting two adjacent trenches in the plurality of trenches; a first insulating layer, formed on surfaces of the plurality of trenches, the connecting trench, and the semiconductor layer; a conductive material, formed in the plurality of trenches and the connecting trench; a second insulating layer, covering part of a surface of the first insulating layer and part of a surface of the conductive material; and a metal layer, covering part of a surface of the second insulating layer. | 2014-10-23 |
20140312453 | SCHOTTKY BARRIER DIODES WITH A GUARD RING FORMED BY SELECTIVE EPITAXY - Schottky barrier diodes, methods for fabricating Schottky barrier diodes, and design structures for a Schottky barrier diode. A guard ring for a Schottky barrier diode is formed with a selective epitaxial growth process. The guard ring for the Schottky barrier diode and an extrinsic base of a vertical bipolar junction diode on a different device region than the Schottky barrier diode may be concurrently formed using the same selective epitaxial growth process. | 2014-10-23 |
20140312454 | Structure Designs and Methods for Integrated Circuit Alignment - Devices and methods for pattern alignment are disclosed. The device includes an assembly isolation region, a seal ring region around the assembly isolation region, and a scribe line region around the seal ring region, and a plurality of die alignment marks disposed within the seal ring region that are alternately disposed adjacent the scribe line region and the assembly isolation region. | 2014-10-23 |
20140312455 | PATTERNS OF A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a plurality of active patterns, a plurality of first isolation layer patterns and a plurality of second isolation layer patterns may be provided. In particular, the active patterns may be arranged both in a first direction and in a second direction, and may protrude from a substrate and have a length in the first direction. The first isolation layer patterns may fill a first space, the first space provided between the active patterns and arranged in the first direction, and support two opposing sidewalls of neighboring active patterns. The second isolation layer patterns may fill a second space between the active patterns and the first isolation layer patterns. Accordingly, the active patterns of the semiconductor device may not collapse or incline because the first isolation layer patterns support the active patterns. | 2014-10-23 |
20140312456 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines. | 2014-10-23 |
20140312457 | INTEGRATED CIRCUIT CHIP WITH DISCONTINUOUS GUARD RING - An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap. | 2014-10-23 |
20140312458 | METHODS AND APPARATUS RELATED TO AN IMPROVED PACKAGE INCLUDING A SEMICONDUCTOR DIE - In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar. | 2014-10-23 |
20140312459 | VERTICAL MEANDER INDUCTOR FOR SMALL CORE VOLTAGE REGULATORS - Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography. | 2014-10-23 |
20140312460 | STACKED CAPACITOR STRUCTURE AND A FABRICATING METHOD FOR FABRICATING THE SAME - A stacked capacitor structure of the instant disclosure comprises a substrate and a plurality of stacked capacitors. The substrate has an insulating layer formed thereon and a plurality of contact plugs in the insulating layer, wherein the contact plugs are exposed on the upper surface of the insulating layer. Specially, each of the stacked capacitors comprises a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is arranged on one of the contact plugs and has a columnar base portion and a crown shaped upper portion. The dielectric layer is arranged on the lower electrode and covers the outer surface of the lower electrode. The upper electrode is arranged above the lower electrode, wherein the dielectric layer is intermediately between the upper electrode and the lower electrode. | 2014-10-23 |
20140312461 | DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET - Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased. | 2014-10-23 |
20140312462 | SEMICONDUCTOR DEVICE - A first impurity diffusion region is provided within a semiconductor substrate, a second impurity diffusion region is provided within the first impurity diffusion region, a third impurity diffusion region is provided within the second impurity diffusion region, a first portion of a fourth impurity diffusion region is provided within the second impurity diffusion region so as to be spaced from the third impurity diffusion region, and a second portion of the fourth impurity diffusion region is provided in a third portion of the first impurity diffusion region on a side of a surface of the semiconductor substrate, a first contact is provided so as to be in contact with the second portion, the first contact and the third portion overlap in plan view, and a first power supply is connected to the third impurity diffusion region. | 2014-10-23 |
20140312463 | SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN - Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure. | 2014-10-23 |
20140312464 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a molding die for molding a resin case for a semiconductor device is prepared such that the molding die has protrusions to fix each of a plurality of terminals having a leg portion in a predetermined position. Each of the plurality of terminals is held to the corresponding protrusions in the molding die, and resin is injected into the molding die to integrally mold the plurality of terminals and the resin case. | 2014-10-23 |
20140312465 | Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device - A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area allowing the die seal area to he disregarded for purposes of calculating a process window. | 2014-10-23 |
20140312466 | INTEGRATED CIRCUIT SEALING SYSTEM WITH BROKEN SEAL RING - The amount of signal propagation and moisture penetration and corresponding reliability problems due to moisture penetration degradation in an IC can be reduced by fabricating a wide seal ring with a channel having offset ingress and egress portions. | 2014-10-23 |
20140312467 | THROUGH-VIAS FOR WIRING LAYERS OF SEMICONDUCTOR DEVICES - Through-via structures and methods of their formation are disclosed. One such structure includes a conductor structure, a dielectric via lining and a stress-abating dielectric material. The conductor structure is formed of conducting material extending through a wiring layer of a semiconductor device and through a semiconductor layer below the wiring layer. Here, the wiring layer of the semiconductor device includes a first dielectric material. The dielectric via lining extends along the conductor structure at least in the semiconductor layer. Further, the stress-abating dielectric material is disposed between the conductor structure and the first dielectric material in at least the wiring layer, where the stress-abating dielectric material is disposed over portions of the semiconductor layer that are outside outer boundaries of the via lining. | 2014-10-23 |
20140312468 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a device layer and a least one conductive post. The substrate includes a first surface, a second surface opposite to the first surface, and at least one through hole penetrating the substrate. The substrate includes a first side wall portion and a second side wall portion at the through hole. The first side wall portion is connected to the first surface and includes a plurality of first scallops. The second side wall portion is connected to the second surface and includes a non-scalloped surface. The device layer is disposed on the second surface, and the second side wall portion of the substrate further extends into the device layer along the non-scalloped surface. The conductive post is disposed in the through hole, wherein the conductive post is electrically connected to the device layer. | 2014-10-23 |
20140312469 | LASER-BASED MATERIAL PROCESSING METHODS AND SYSTEMS - Various embodiments may be used for laser-based modification of target material of a workpiece while advantageously achieving improvements in processing throughput and/or quality. Embodiments of a method of processing may include focusing and directing laser pulses to a region of the workpiece at a pulse repetition rate sufficiently high so that material is efficiently removed from the region and a quantity of unwanted material within the region, proximate to the region, or both is reduced relative to a quantity obtainable at a lower repetition rate. Embodiments of an ultrashort pulse laser system may include a fiber amplifier or fiber laser. Various embodiments are suitable for at least one of dicing, cutting, scribing, and forming features on or within a semiconductor substrate. Workpiece materials may include metals, inorganic or organic dielectrics, or any material to be micromachined with femtosecond, picosecond, and/or nanosecond pulses. | 2014-10-23 |
20140312470 | SEAL RING STRUCTURE WITH CAPACITOR - A semiconductor device includes a semiconductor substrate of a first conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. And, a plurality of doping regions are located beneath the first seal ring structure. | 2014-10-23 |
20140312471 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a plurality of closely spaced fins each coated at its top and sidewalls with a SiGe layer used for improving charge carrier mobility in a channel portion of the device. The sidewalls of the closely adjacent Fins are selectively thinned so as to prevent an undesired bridging of SiGe material between immediately adjacent ones of the Fins. A method of manufacturing the same comprises: providing a substrate having a plurality of tri-gate transistors, at least two fins of the tri-gate transistors being closely adjacent to each other, where respective top and sidewall surfaces of the fins are coated with a SiGe layer; performing a tilted ion implantation on the SiGe coated fins so as to partially convert the SiGe material into a predetermined etch resistant material (e.g., and oxide of the SiGe); and etching away the non-converted sidewall parts of the SiGe coating layers so as to provide greater spacing between the immediately adjacent sidewalls of the SiGe coated fins. | 2014-10-23 |
20140312472 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device which includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion; a second step of forming an insulation layer such that the insulation layer covers the pn junction exposure portion; and a third step of forming a glass layer on the insulation layer where a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked. | 2014-10-23 |
20140312473 | SHIELD, PACKAGE STRUCTURE AND SEMICONDUCTOR PACKAGE HAVING THE SHIELD AND FABRICATION METHOD OF THE SEMICONDUCTOR PACKAGE - A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a substrate having at least a carrying region and a cutting region defined on a surface thereof, wherein the cutting region surrounds the carrying region; disposing at least an electronic element on the carrying region of the substrate; disposing a shield having a recess portion and at least a positioning member extending outwards, on the carrying region of the substrate with the electronic element received in the recess portion and the positioning member extending outwards to the cutting region; and performing a cutting process along the cutting region to remove portions of the positioning member and the substrate. Therefore, the shield is precisely positioned on the substrate. | 2014-10-23 |
20140312474 | SEMICONDUCTOR PACKAGE WITH WIRE BONDING - A semiconductor package having a die having a plurality of electrically continuous die wire bonding sites includes a first die wire bonding site and a second die wire bonding site. The package includes a substrate having a plurality of electrically continuous substrate wire bonding sites including a first substrate wire bonding site and a second substrate wire bonding site. A first bondwire is connected between the first die wire bonding site and the first substrate wire bonding site and a second bondwire is connected between the second die wire bonding site and the second substrate wire bonding site. The first and second bondwires lie in adjacent, substantially parallel bondwire planes. The second bondwire is substantially skewed with respect to said first bondwire. | 2014-10-23 |
20140312475 | DIE REUSE IN ELECTRICAL CIRCUITS - A die having multiple sets of contact pads, with each such set having two or more contact pads distributed over the die and electrically interconnected using a respective electrical intra-die path to enable die reuse in a manner that causes electrical inter-die buses to be relatively short in length. Each electrical intra-die path can optionally include one or more respective buffer circuits configured to reduce degradation of the various signals that are being shared by the reused dies. In some embodiments, multiple reused dies can be arranged in a linear or two-dimensional array on an interposer or on the package substrate and packaged together with one or more non-reused dies in a single integrated-circuit package. | 2014-10-23 |
20140312476 | NO-EXPOSED-PAD BALL GRID ARRAY (BGA) PACKAGING STRUCTURES AND METHOD FOR MANUFACTURING THE SAME - A no-exposed-pad ball grid array (BGA) packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of outer leads formed on the metal substrate and extending to the proximity of the die. A metal layer that contains a plurality of inner leads corresponding to the plurality of outer leads and extending to the proximity of the die is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Furthermore, the die and the plurality of inner leads are connected by metal wires, and a plurality of solder balls is attached to a back surface of the plurality of outer leads and a die pad. The die, the plurality of inner leads, and the metal wires are sealed with a molding compound. | 2014-10-23 |
20140312477 | Lead And Lead Frame For Power Package - A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions. | 2014-10-23 |
20140312478 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided. | 2014-10-23 |
20140312479 | ESCAPE ROUTES - Methods of and devices for providing escaping routes for the flux and gases generated to move away from the solder joint in the process of solder joint formation. | 2014-10-23 |
20140312480 | DOUBLE-SIDE EXPOSED SEMICONDUCTOR DEVICE - A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device. | 2014-10-23 |
20140312481 | INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked integrated circuit package and a method for manufacturing the same are provided. | 2014-10-23 |
20140312482 | WAFER LEVEL ARRAY OF CHIPS AND METHOD THEREOF - A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided. | 2014-10-23 |
20140312483 | SEMICONDUCTOR PACKAGE HAVING IC DICE AND VOLTAGE TUNERS - A semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via the interposer. A first IC die has a clock speed rating that is greater than a clock speed rating of another of the IC dice. A plurality of programmable voltage tuners are coupled to the plurality of IC dice, respectively. A first voltage tuner is coupled to the first IC die, and the first voltage tuner is programmed to reduce a voltage level of voltage input to the first voltage tuner and output the reduced voltage to the first IC die. | 2014-10-23 |
20140312484 | ELECTRONIC ASSEMBLY FOR MOUNTING ON ELECTRONIC BOARD - An embodiment of an electronic assembly for mounting on an electronic board includes a plurality of electric contact regions exposed on a mounting surface of the electronic board. The electronic assembly includes a chip of semiconductor material in which at least one electronic component is integrated, at least one support element including a first main surface and a second main surface opposite to the first main surface, the chip being enclosed by the at least one support element, a heat dissipation plate thermally coupled to said chip to dissipate the heat produced by it, exposed on the first main surface of the support element, a plurality of contact elements, each electrically coupled to a respective electric terminal of the electronic component integrated in the chip, exposed on the same first main surface of which is exposed to the dissipation plate. Also included are a plurality of electric connection elements, each adapted to electrically intercouple a respective contact element of the electronic assembly with a corresponding electric contact region of the electronic board, in such a way that the second main surface of the at least one support element faces the mounting surface of the electronic board. | 2014-10-23 |
20140312485 | SEMICONDUCTOR MODULE SYSTEM, SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR MOUNTING A SEMICONDUCTOR MODULE ON A HEAT SINK - A semiconductor module system has a semiconductor module and a protective cover. The semiconductor module has a bottom side with a heat dissipation surface and a top side opposite the bottom side, the top side being separated from the bottom side in a vertical direction. The protective cover can be mounted irreleasably on the semiconductor module in such a way that, in a mounted state, the top side is exposed and the protective cover covers the heat dissipation surface. By virtue of the protective cover, a thermal interface material applied onto the heat dissipation surface can be protected. | 2014-10-23 |
20140312486 | CHIP-ON-FILM PACKAGE AND DISPLAY DEVICE HAVING THE SAME - A chip-on-film package and a display device, the package including a base film that includes an upper surface and a lower surface, the lower surface facing the upper surface; an integrated circuit chip on the upper surface of the base film; an alignment line on the base film and being spaced apart from the integrated circuit chip; a heat discharge plate on the lower surface of the base film and having a plate shape; and at least one via pattern penetrating through the base film and electrically connecting the alignment line to the heat discharge plate. | 2014-10-23 |
20140312487 | UNDERFILL PROCESS AND MATERIALS FOR SINGULATED HEAT SPREADER STIFFENER FOR THIN CORE PANEL PROCESSING - A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed. | 2014-10-23 |
20140312488 | METHOD OF MANUFACTURING WIRING BOARD UNIT, METHOD OF MANUFACTURING INSERTION BASE, WIRING BOARD UNIT, AND INSERTION BASE - A method of manufacturing a wiring board unit, the wiring board unit including a semiconductor package that includes a memory chip, a wiring board on which the semiconductor package is mounted, and an insertion base inserted between the wiring board and the semiconductor package, the method includes: forming a plurality of connection portion groups in a base material, the connection portion groups each including a plurality of connection portions that each electrically connect a board-side pad of the wiring board and an external terminal of the semiconductor package to each other; forming the insertion base such that resistances of the connection portions included in the connection portion groups are adjusted in accordance with types of target memory chips; and connecting the external terminals and the board-side pads to one another by using the connection portion group selected in accordance with the type of the memory chip. | 2014-10-23 |
20140312489 | FLIP-CHIP SEMICONDUCTOR PACKAGE - A flip-chip semiconductor package is provided that includes a semiconductor chip, a package substrate having a chip attachment surface on which bond sites are formed, and bumps attached to an active surface of the semiconductor chip and bonded to the bond sites, wherein the bond sites are radially arranged around a middle portion of the package substrate. | 2014-10-23 |
20140312490 | ELECTRICAL SYSTEM AND CORE MODULE THEREOF - Disclosed is a core module, comprising: a package substrate, having a plurality of pads; a first component, connected to the pads of the package substrate corresponding to the first component with a plurality of first joint parts; a second component, connected to the pads of the package substrate corresponding to the first component with a plurality of second joint parts; and a third component, connected to the pads of the package substrate corresponding to the third component with a plurality of third joint parts, wherein the first component is positioned above the second component relative to the lower package substrate, and the first component, the second component and the third component are all electrically connected via the package substrate, and a main molding material is molding the first component, the second component and the third component. | 2014-10-23 |
20140312491 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND ELECTRONIC SYSTEM - Provided are a semiconductor device, a semiconductor package, and an electronic system. The device includes a substrate having a front side and a back side disposed opposite the front side. An internal circuit is disposed on or near to the front side of the substrate. Signal I/O through-via structures are disposed in the substrate. Back side conductive patterns are disposed on the back side of the substrate and electrically connected to the signal I/O through-via structures. A back side conductive structure is disposed on the back side of the substrate and spaced apart from the signal I/O through-via structures. The back side conductive structure includes parallel supporter portions. | 2014-10-23 |
20140312492 | Package with a Fan-out Structure and Method of Forming the Same - An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound. | 2014-10-23 |
20140312493 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surf ace protection film formed to cover the top wiring layer is flattened by CMP. | 2014-10-23 |
20140312494 | Wafer Backside Interconnect Structure Connected to TSVs - An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line. | 2014-10-23 |
20140312495 | FAN OUT INTEGRATED CIRCUIT DEVICE PACKAGES ON LARGE PANELS - A method of manufacturing an integrated circuit package. The method comprises providing a carrier substrate having a planar surface. The method comprises placing a plurality of semiconductor device dies active-side down at laterally spaced-apart locations on the planar surface. The method comprises covering the semiconductor device dies with a mold compound to define laterally spaced-apart mold sub-arrays on the planar surface. The method comprises curing the laterally spaced-apart mold sub-arrays, wherein the semiconductor device dies are retained at substantially the same laterally spaced-apart locations on the planar surface after the curing. | 2014-10-23 |
20140312496 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted. | 2014-10-23 |
20140312497 | Molding Material and Method for Packaging Semiconductor Chips - A method and apparatus for packaging a semiconductor chip is presented. A semiconductor device includes a chip, a lead, and an encapsulant. The encapsulant includes a stabilization layer, a laminate molding layer connected to the stabilization layer, and a conductive strip connected to the laminate molding layer. The conductive strip electrically connects the contact area of the chip to the lead. | 2014-10-23 |
20140312498 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having improved reliability. | 2014-10-23 |
20140312499 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. | 2014-10-23 |
20140312500 | COMBINING CUT MASK LITHOGRAPHY AND CONVENTIONAL LITHOGRAPHY TO ACHIEVE SUB-THRESHOLD PATTERN FEATURES - Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion. | 2014-10-23 |
20140312501 | NON-RANDOM ARRAY ANISOTROPIC CONDUCTIVE FILM (ACF) AND MANUFACTURING PROCESSES - Structures and manufacturing processes of an ACF array using a non-random array of microcavities of predetermined configuration, shape and dimension. The manufacturing process includes fluidic filling of conductive particles onto a substrate or carrier web comprising a predetermined array of microcavities, of selective metallization of the array followed by filling the array with a filler material and a second selective metallization on the filled microcavity array. The thus prepared filled conductive microcavity array is then over-coated or laminated with an adhesive film. Cavities in the array, and particles filling the cavities, can have a unimodal, bimodal, or multimodal distribution. | 2014-10-23 |
20140312502 | THROUGH-VIAS FOR WIRING LAYERS OF SEMICONDUCTOR DEVICES - Through-via structures and methods of their formation are disclosed. In one such method, a first etch through at least a first dielectric material of a wiring layer is performed such that a first hole outlining a collar structure for the through-via is formed. In addition, a stress-abating dielectric material is deposited in the hole such that the stress-abating dielectric material is disposed at least laterally from the first dielectric material. Further, a second etching through at least a semiconductor material of a semiconductor layer that is disposed below the wiring layer is performed, where the second etching forms a via hole in the semiconductor material. Additionally, at least a portion of the via hole is filled with conductive material to form the through-via such that the stress-abating dielectric material, at least in the wiring layer, provides a buffer between the conductive material and the first dielectric material. | 2014-10-23 |
20140312503 | SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - A semiconductor package comprises a package substrate including a package pad, the package pad being conductive. A semiconductor chip is on the package substrate including a chip pad, the chip pad being conductive, the semiconductor chip extending in a horizontal direction of extension. A transparent substrate is on the semiconductor chip. An insulative layer is at sides of the transparent substrate and on the package substrate. A vertical interconnect is through the insulative layer, the vertical interconnect in contact with at least one of the package pad and chip pad, the vertical interconnect extending in a substantially vertical direction of extension relative to the horizontal direction of extension of the semiconductor chip. | 2014-10-23 |
20140312504 | INTERCONNECT LINE SELECTIVELY ISOLATED FROM AN UNDERLYING CONTACT PLUG - A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration, and in subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line. | 2014-10-23 |
20140312505 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - A semiconductor device includes a first semiconductor chip, a first connection structure disposed on a first side of the first semiconductor chip, a second semiconductor chip disposed on a second side of the first semiconductor chip, and a second connection structure disposed between the first and second semiconductor chips, wherein a number of the second connection structures is less than a number of the first connection structures. | 2014-10-23 |
20140312506 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a semiconductor substrate including a first surface in which an integrated circuit and an I/O pad electrically connected to the integrated circuit are formed, and a second surface which is an opposite side to the first surface, where a two-stage through-hole is formed in the semiconductor substrate, the semiconductor substrate including a first shape portion having a tapered shape which has a wall surface and of which a diameter of an opening becomes smaller toward a bottom of the hole from the second surface side to a predetermined position of the semiconductor substrate in a thickness direction, and including a second shape portion having a cylindrical shape which extends from the first shape portion to the I/O pad on the first surface side, and that includes an inorganic insulating film which is formed on the wall surface of the two-stage through-hole and the second surface. | 2014-10-23 |
20140312507 | SEMICONDUCTOR DEVICE HAVING A MULTILAYER INTERCONNECTION STRUCTURE - A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure. | 2014-10-23 |
20140312508 | SEMICONDUCTOR INTERCONNECT STRUCTURES - Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etch stop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etch stop layer, and an interconnect feature may pass through the second insulator layer and the conformal etch stop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer. | 2014-10-23 |
20140312509 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region. | 2014-10-23 |
20140312510 | Semiconductor Device - The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other. | 2014-10-23 |
20140312511 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device that has a plurality of semiconductor components and a plurality of resin layers, the method including: a step in which resin layers and semiconductor components are laminated alternately on a substrate, and the same is adhered by being subjected to heating and pressurization at a temperature lower than the temperature at which the substrate and/or a solder layer of the semiconductor components melts; and a step in which heat and pressure are applied at a temperature at which the solder layer melts or a temperature higher than said temperature. | 2014-10-23 |
20140312512 | Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer - A semiconductor device has a substrate with a plurality of contact pads. A first insulation layer is formed over the substrate and contact pads. A portion of the first insulating layer is removed to form a toroid-shaped SRO over the contact pads while retaining a central portion of the first insulating layer over the contact pads. The central portion of the first insulating layer can extend above a surface of the first insulating layer outside the first conductive layer. A first conductive layer is formed over the central portion of the first insulating layer and through the SRO in the first insulating layer over the contact pads. The first conductive layer may extend above a surface of the first insulating layer outside the second conductive layer. A semiconductor die is mounted to the substrate with the bumps electrically connected to the first conductive layer. | 2014-10-23 |
20140312513 | SEMICONDUCTOR DEVICE, SUBSTRATE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane. | 2014-10-23 |
20140312514 | SEMICONDUCTOR DEVICE - [Object] A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution] A semiconductor device includes: a die pad | 2014-10-23 |
20140312515 | LOW PROFILE CASCADE AERATOR - A cascade aerator comprising a plurality of longitudinal channels that receive a fluid therethrough. The longitudinal channels are in fluid communication with a plurality of flow control gates, such that a first number of flow control gates are in fluid communication with a first longitudinal channel and a second number of flow control gates are in fluid communication with a second longitudinal channel. The first number of flow control gates may define a crest height that is lower, along a vertical direction, than a crest height defined by the second number of flow control gates. The flow control gates may define a crest length proximate a crest of the flow control gate and a nappe length defined proximate a first height above the crest. The nappe length may be greater than the crest length. The aerator may have a plurality of low head baffles. | 2014-10-23 |
20140312516 | Methods and Apparatus Useful in Manufacturing Lenses - Methods of manufacturing a contact lens are provided. Such methods include using an adjustable mandrel to fixedly retain a single mold section carrying a polymerized contact lens product and delensing the contact lens product from the single mold section. Adjustable mandrels are also provided. | 2014-10-23 |
20140312517 | Storage Stable Premixed Hydraulic Cement Compositions, Cements, Methods, and Articles - Refrigerated hydraulic cement compositions comprise a mixture of (a) β-tricalcium phosphate powder, (b) monocalcium phosphate comprising monocalcium phosphate anhydrous (MCPA), monocalcium phosphate monohydrate (MCPM), or a combination thereof, wherein a 0.1 g/ml saturated aqueous solution of the monocalcium phosphate has a pH less than 3.0, (c) non-aqueous water-miscible liquid, and (d) an aqueous hydrating liquid. The aqueous hydrating liquid is included in an amount of about 1-50 volume percent, based on the combined volume of the non-aqueous water-miscible liquid and the aqueous hydration liquid, and the refrigerated hydraulic cement composition is storage stable for greater than one day, without setting. Methods of forming hardened cements in vivo and/or for forming implants for use in vivo employ the hydraulic cement compositions. | 2014-10-23 |
20140312518 | COLD BENDING OF A LAMINATED GLAZING - The invention relates to a process for the preparation of bent glazed modules comprising a metal framework and a panel comprising a laminated glazing comprising glass substrates separated by an interlayer made of polymer material, the panel being bent, after the laminated glazing has been assembled, by a force which causes it to take the shape of the metal framework and then held in this shape by a holding means, the bending being carried out while the interlayer is at a temperature between 30 and 80° C. The invention reduces the loads necessary for the bending and also the shear stresses between the interlayer made of polymer material and the glass substrates, which reduces the risks of delamination. | 2014-10-23 |
20140312519 | TEMPERATURE CONTROL SEQUENCE DETERMINATION DEVICE, MOLDING DEVICE, RECORDING MEDIUM, AND TEMPERATURE CONTROL SEQUENCE DETERMINATION METHOD - A molding device ( | 2014-10-23 |
20140312520 | Control Structure for a Molding System - Disclosed herein, amongst other things, is a control structure for a molding system ( | 2014-10-23 |
20140312521 | MOLD, MOLDING MACHINE, AND FOAMED MOLDED BODY MANUFACTURING METHOD - A mold, a molding machine, and a foamed molded body manufacturing method are provided that are capable of more reliably preventing ingress of foamed resin into a gas discharge hole using a gas-impermeable member and capable of adequately discharging gas inside the cavity to the cavity outside through the gas discharge hole during foam molding, and that are also capable of achieving good design characteristics in a foamed molded body. A gas discharge hole | 2014-10-23 |
20140312522 | MACHINE AND METHOD TO PRODUCE STRUCTURAL ELEMENTS FOR THE BUILDING TRADE MADE OF CEMENT MATERIAL, HAVING ONE OR MORE POLYMER MATERIAL INSERTS - A machine and method to produce structural elements for the building trade made of cement material with one or more inserts made of polymer material. The machine comprises at least a molding member, a loading unit for loading the inserts and a depositing member to deposit the cement material. The molding member is open at the upper part and the loading unit and the depositing member are selectively positionable above the molding member in order to load and deposit from above, respectively, the inserts and the cement material into the molding member, in order to achieve the structural elements. | 2014-10-23 |
20140312523 | THICK RARE EARTH MAGNET FILM AND LOW-TEMPERATURE SOLIDIFYING AND MOLDING METHOD - A thick magnet film contains a rare earth magnet phase represented by formula R-M-X, where R contains at least one of Nd and Sm, M contains at least one of Fe and Co, and X contains at least one of N and B. The thick magnet film has a density of equal to or more than 80% but less than 95% of the theoretical density when R contains Nd as a main component and has the density of equal to or more than 80% but less than 97% of the theoretical density when R contains Sm as a main component. The magnet can achieve an increase in thickness when formed into a film, an increase in density and an improvement in magnetic properties such as residual magnetic flux density. | 2014-10-23 |
20140312524 | CONCRETE RUNWAYS, ROADS, HIGHWAYS AND SLABS ON GRADE AND METHODS OF MAKING SAME - The invention comprises a method of forming a slab on grade. The method comprises placing a first layer of insulating material horizontally on the ground and placing plastic concrete for a slab on grade on the first layer of insulating material. The plastic concrete is then formed into a desired shape having a top and sides. A second layer of insulating material is placed on the top of the plastic concrete and the first and second layers of insulating material are left in place until the concrete is at least partially cured. The second layer of insulating material is then removed. The product made by the method is also disclosed. A slab on grade is also disclosed. | 2014-10-23 |
20140312525 | COLOR CONTROL OF POLYESTER-COBALT COMPOUNDS AND POLYESTER-COBALT COMPOSITIONS - The present invention is to a composition made from a polyester produced by the acid or ester polyester process, a cobalt salt and a base, preferably an alkaline metal base. The composition can be made by blending a cobalt salt with a polyester which has been polymerized in the presence a alkaline metal ion derived from a basic alkaline metal compound, e.g. alkaline metal base or basic alkaline metal salt. The composition may optionally comprise an ionic compatibilizer, which may further be blended with a partially aromatic polyamide. This blend can be processed into a container having both active and passive oxygen barrier with an improved color and clarity than that achieved by cobalt alone. The use of the cobalt salt in combination with the base can also be used to improve the color of recycled polyester during processing. | 2014-10-23 |
20140312526 | METHOD FOR RECYCLING ARTIFICIAL GRASS CONTAINING FIBROUS MATERIAL - The present invention relates to a method for recycling artificial grass containing fibrous material, and comprises: a supplying step for supplying the artificial grass comprising a base material, and a yarn; a separation step for separating the filler from the artificial grass yarn and the base material; and a crushing step for crushing the yarn and the base material of the artificial grass from which the filler is separated; and a reconstruction step for forming the artificial grass yarn and the base material that are crushed into recycled material. As a result, provided is the method for recycling the artificial grass containing the fibrous material, which can completely separate the filler and foreign material from the base material and the yarn that comprise the artificial grass and recycle the artificial grass yarn, base material, and the filler, thereby preventing environmental pollution. | 2014-10-23 |
20140312527 | DIE ASSEMBLIES AND DIE ASSEMBLY COMPONENTS AND METHODS OF MAKING AND USING THE SAME - Die assemblies and die assembly components are disclosed. Methods of making and using die assemblies and die assembly components are also disclosed. | 2014-10-23 |
20140312528 | UTILITY TRUCK BASE REINFORCEMENT AND METHOD OF MANUFACTURE - A utility truck with arched reinforcing rods incorporated into the base of a plastic truck during molding. The reinforcing rods are held in place in a mold at a predetermined distance above the mold's inner surface by spacers attached to the ends of the rods. Plastic is molded around the rods, with more plastic provided below the rods than above them, so that, when the plastic truck is removed from the mold and allowed to cool, the plastic will contract to a greater extent than the metal rods, causing the base and the reinforcing rods to bow upward, creating a convex arch in the truck's base. The arch provides an inherently strong, bridge-type structure that substantially strengthens the load-bearing capability of the truck, yet requires less reinforcing material than conventional supplemental chassis structures. In another embodiment, caster base mounts are also molded into the bottom of the truck, providing a utility truck with a unitary chassis structure. | 2014-10-23 |
20140312529 | Form For Casting A concrete Light Pole Base - A process and form for casting a concrete light pole base having a decorative upper portion with a configuration for mounting a light pole. The form includes a base having an opening in which a resilient insert is positioned. The insert has openings for holding threaded ends of mounting bolts and for positioning wiring conduits. Ends of the bolts extend from the insert into the mold cavity. Different inserts may be used to accommodate different light pole mounting specifications. A first form section for shaping a decorative upper portion of the light pole base is positioned on the base, and forms for shaping the cylindrical lower end of the light pole base are secured above the first form section. | 2014-10-23 |
20140312530 | SYSTEM AND METHOD FOR LAMINATING PHOTOVOLTAIC STRUCTURES - A method for forming a laminated photovoltaic structure includes providing a sheet of transparent material having light concentrating features, disposing adhesive material adjacent to the sheet of transparent material, disposing photovoltaic strips adjacent to the adhesive material, wherein the photovoltaic strips are positioned relative to the sheet of transparent material in response to exitant light characteristics of the light concentrating features, wherein photovoltaic strips are coupled via associated bus bars, wherein gap regions are located between bus bars of neighboring photovoltaic strips, disposing a rigid layer of material adjacent to the photovoltaic strips to form a composite photovoltaic structure; and thereafter laminating the composite photovoltaic structure to fill the gap regions with adhesive material and to form the laminated photovoltaic structure, wherein adhesive material adheres to the bus bars. | 2014-10-23 |
20140312531 | Corrugation device for sheets of paper material - Provided is a corrugation device for sheets of paper material including two corrugation cylinders having work surfaces configured to substantially engage reciprocally so as to define a deformation zone and impress a deformation force on sheets of paper material and at least one thrust member suitable to define a working configuration in which it exerts on one of the work surfaces an additional pressure able to vary the deformation force and a rest configuration in which it does not exert the additional pressure. | 2014-10-23 |
20140312532 | IMPRINT APPARATUS AND ARTICLE MANUFACTURING METHOD - Provided is an imprint apparatus that imprints a pattern formed on a mold onto a substrate. The imprint apparatus includes a substrate holder that holds the substrate and can move in a direction along the surface of the substrate; a gas supply unit for supplying a gas into a space between a pattern part of the mold and the substrate; and a wall part that is disposed so as to enclose the space that is supplied with gas, wherein at a position opposed to the substrate and the mold, the wall part faces the substrate holder or the substrate with a gap therebetween. | 2014-10-23 |
20140312533 | Molded Article Extractor and Method - A tire tread extractor used in the manufacture of treads includes a frame, a first nip roller rotatably associated with the frame, and a second nip roller rotatably associated with the frame. The first and second nip rollers are adapted to engage a tire tread at least partially resident in a mold. A driving mechanism associated with the first and/or second nip rollers operates to impart rotational motion thereto. The frame is configured for longitudinal movement along a substantial portion of a longitudinal length of the mold while maintaining the first and second nip rollers in a spaced relation to the mold. | 2014-10-23 |
20140312534 | METHOD OF MAKING A DROPLET-GENERATING DEVICE - Method of making a droplet-generating device. In the method, a first droplet-generating device may be produced. The first droplet-generating device may include a molded portion created at least in part with a mold and also may include a plurality of droplet generators each formed at least in part by the molded portion. A set of droplets may be generated with each of one or more of the droplet generators. A property of at least one set of generated droplets may be determined. The mold may be modified based on the property. A second droplet-generating device may be produced that includes a molded portion created at least in part with the modified mold. | 2014-10-23 |
20140312535 | SYSTEM AND METHOD FOR FABRICATING A BODY PART MODEL USING MULTI-MATERIAL ADDITIVE MANUFACTURING - A method for physically reconstructing a body part using multi-material additive manufacturing includes receiving image data of the body part in the form of arrays of voxels, each array of voxels representing image data pertaining to cross-section of the body part, translating the image data in the arrays of voxels to printable bitmap images representing combinations of modeling materials for reconstructing the body part, and dispensing the combinations of modeling materials responsive to the bitmap images in a layerwise manner. | 2014-10-23 |
20140312536 | EPOXY RESIN COMPOSITION FOR NEUTRON SHIELDING, AND METHOD FOR PREPARING THE SAME - Provided is an epoxy resin composition including a nano-sized radioactive radiation shielding material which has superior shielding effects for against radiation, and to a method for preparing same. In particular, the method for preparing the epoxy resin composition for neutron shielding, includes the steps of: a step of mixing a boron compound powder for absorbing neutrons, optionally a high density metal powder for shielding from against gamma rays and a flame retardant powder, respectively separately or in combination, with an amine-based curing agent to obtain a mixture of a curing agent and a powder; an ultrasonic wave treating step of applying ultrasonic waves to the mixture to coat the surface of the powder with the amine-based curing agent and to disperse the powder in the curing agent; and a dispersing step of mixing and dispersing the amine-based curing agent, that was dispersed and includes the powder treated with ultrasonic waves, in an epoxy resin. | 2014-10-23 |
20140312537 | CONTAINER FORMED VIA PLURAL BLOW MOLDING - A system for forming a container from a preform includes a first mold operable to receive the preform and operable to blow mold a first form of the container from the preform. The system also includes a second mold operable to receive the first form and operable to blow mold a second form of the container from the first form. The preform, the first form, and the second form each include a substantially common transitional wall. Also, the first form can include various features that ensure that material will be distributed as desired throughout the container, to ensure high wall strength, and to ensure high crystallinity. | 2014-10-23 |
20140312538 | PLURAL BLOW UTILIZATION OF COUNTER STRETCH ROD AND/OR BASE PUSHUP - A molding system for molding a container includes a first blow mold operable for blow molding a first form of the container and a second blow mold operable for blow molding a second form of the container. The system further includes a counter stretch rod and/or a base pushup operable for reducing a height of the first form of the container before blow molding the second form of the container. A corresponding method of forming a container is also disclosed. | 2014-10-23 |
20140312539 | CERAMIC MULTILAYER SUBSTRATE AND METHOD FOR PRODUCING THE SAME - A ceramic multilayer substrate incorporating a chip-type ceramic component, in which, even if the chip-type ceramic component is mounted on the surface of the ceramic multilayer substrate, bonding strength between the chip-type ceramic component and an internal conductor or a surface electrode of the ceramic multilayer substrate is greatly improved and increased. The ceramic multilayer substrate includes a ceramic laminate in which a plurality of ceramic layers are stacked, an internal conductor disposed in the ceramic laminate, a surface electrode disposed on the upper surface of the ceramic laminate, and a chip-type ceramic component bonded to the internal conductor or the surface electrode through an external electrode. The internal conductor or the surface electrode is bonded to the external electrode through a connecting electrode, and the connecting electrode forms a solid solution with any of the internal conductor, the surface electrode, and the external electrode. | 2014-10-23 |
20140312540 | APPARATUS AND METHOD FOR POSITIONING LANCES OF ELECTRIC ARC FURNACE, ELECTRIC ARC FURNACE COMPRISING SUCH APPARATUS - A positioning apparatus ( | 2014-10-23 |
20140312541 | LOADING DOCK BUMPER ASSEMBLY - A loading dock bumper assembly for securement to a loading dock wall includes a dock bumper and a mounting provision coupled to the bumper. The dock bumper includes a mounting portion, an impact-absorbing portion opposing the mounting portion, and a deformable spanning portion joining the mounting portion and the impact-absorbing portion. The mounting portion is adapted for coplanar alignment with the loading dock wall, the impact-absorbing portion is adapted for direct contact with a rear frame of a vehicle, and the bumper defines an internal cavity that is filled with a fluid. | 2014-10-23 |
20140312542 | CHIPPING-RESISTANT VIBRATION DAMPER IN FORM OF SHEET - It provides that a vibration-damping material in form of sheet which can be adhered to even at locations such as underfloor or engine room of a vehicle where both vibration-damping performance and chipping-resistant performance are required by self-adhesive bonding or heat melt adhesive bonding through an adhesive layer composed of a adhesive or a hotmelt adhesive. A vibration-damping material in form of sheet with chipping-resistant performance having both of vibration-damping performance and chipping-resistant performance includes a thermosetting vibration-damping sheet and an adhesive layer, the thermosetting vibration-damping sheet includes one or more than synthetic rubber selected from the group consisting of a styrene-butadiene rubber, a butadiene rubber and a high-styrene rubber; a polybutadienic elastomer; a curing agent; a petroleum resin and an inorganic filler. | 2014-10-23 |
20140312543 | SILENCER FOR LAMINATED LEAF SPRING, AND LAMINATED LEAF SPRING - Provided is a silencer for a laminated leaf spring, with which it is possible to more effectively reduce abnormal noise generated in conjunction with deflection of the laminated leaf spring, as compared to when a conventional silencer for a laminated leaf spring is used. This silencer ( | 2014-10-23 |
20140312544 | EFFICIENT ENERGY ACCUMULATION ELEMENT FOR ACTUATORS AND OTHER DEVICES - An efficient energy accumulation element comprising compression spring which uses end caps and flexible rope to pre-compress spring for using in actuators and other devices. The efficient energy accumulation element is independent of external surfaces or end construction of spring. The accumulation and release of energy happens noiselessly. | 2014-10-23 |
20140312545 | SPRING ISOLATOR - A spring isolator may include a first portion and second portion joined together or integrally formed and configured to dampen and absorb loads from a coil spring. The first portion may be a microcellular polyurethane material and the second portion may be a thermoplastic polyurethane material. The first portion and second portion may be chemically bonded together along at least one boundary by injection molding the second portion into a mold already containing the first portion. The spring isolator made from chemically bonded portions may provide effective resistance to radial and longitudinal migration of the isolator upon introduction of coil spring forces and vibration. | 2014-10-23 |