43rd week of 2008 patent applcation highlights part 16 |
Patent application number | Title | Published |
20080258178 | Method of forming a MOS transistor - A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of CO, CO | 2008-10-23 |
20080258179 | Hybrid molecular electronic device for switching, memory, and sensor applications, and method of fabricating same - A hybrid molecular electronic device having switching, memory, and sensor application is disclosed. In one embodiment, the device resembles a conventional field-effect transistor (FET) formed on a silicon-on-insulator (SOI) substrate. Source and drain doped regions are formed in an upper surface of the SOI substrate, and a metallization layer which can serve as a gate contact is formed on a lower surface of the SOI substrate. A channel region spanning between the doped source and drain regions is left exposed, in order that a monolayer of molecules may be formed therein. Upon application of appropriate gating voltages to the gate contact, conduction between the source and drain regions can be modulated, possibly as a result of the reduction and oxidation of the molecules grafted to the gate region. | 2008-10-23 |
20080258180 | CROSS-SECTION HOURGLASS SHAPED CHANNEL REGION FOR CHARGE CARRIER MOBILITY MODIFICATION - A semiconductor structure and a method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally compressive stressed by the stress imparting layer. | 2008-10-23 |
20080258181 | Hybrid Substrates and Methods for Forming Such Hybrid Substrates - Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions. | 2008-10-23 |
20080258182 | Bicmos Compatible Jfet Device and Method of Manufacturing Same - A BiCMOS-compatible JFET device comprising source and drain regions ( | 2008-10-23 |
20080258183 | Method of manufacturing a device by locally heating one or more metallization layers and by means of selective etching - A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device. | 2008-10-23 |
20080258184 | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making - Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described. | 2008-10-23 |
20080258185 | Semiconductor structure with dielectric-sealed doped region - Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired. | 2008-10-23 |
20080258186 | Source and Drain Formation in Silicon on Insulator Device - A silicon on insulator device has a silicon layer ( | 2008-10-23 |
20080258187 | METHODS, SYSTEMS AND APPARATUSES FOR THE DESIGN AND USE OF IMAGER SENSORS - An imager sensor cell design having readout circuitry contained within the photodiode region. | 2008-10-23 |
20080258188 | METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating an MOS device is provided. First, gates and source/drain regions of transistors are formed on a substrate. A photodiode doped region and a floating node doped region are formed in the substrate. Thereafter, a spacer stacked layer including a bottom layer, an inter-layer and a top layer is formed to cover each gate of the transistors. Afterwards, a first mask layer having an opening exposing at least the photodiode doped region is formed on the substrate, and then the top layer exposed by the opening is removed. Next, the first mask layer is removed, and then a second mask layer is formed on a region correspondingly exposed by the opening. A portion of the top layer and the inter-layer exposed by the second mask layer is removed to form spacers on sidewalls of the gates. | 2008-10-23 |
20080258189 | Image Sensor and Method of Manufacturing the Same - An image sensor and a method of manufacturing the same are provided. The image sensor includes a semiconductor substrate, a metal line layer, a first conduction type conducting layer, a first pixel isolation layer, an intrinsic layer, and second conduction type conducting layer. The semiconductor substrate includes a circuit region. The metal line layer including a plurality of metal lines and an interlayer insulating layer is formed on the semiconductor substrate. The first conductive layer having patterns separated from each other by the pixel isolation layer is formed on the metal lines. The first pixel isolation layer is formed between the separated patterns of the first conduction type conducting layer. The intrinsic layer is formed on the first conductive layer and the first pixel isolation layer. The second conduction type conducting layer is formed on the intrinsic layer. | 2008-10-23 |
20080258190 | SOLID-STATE IMAGE SENSING DEVICE AND CAMERA SYSTEM USING THE SAME - A solid-state image sensing device includes a plurality of pixels. Each pixel has a photodiode, a first transistor, and a second transistor. The photodiode is constituted by a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first and second conductivity types are opposite to each other. The first transistor has a first-conductivity-type drain region formed in the second-conductivity-type semiconductor region to transfer signal charge to the drain region. The second transistor has a source region and a drain region which are formed in the second-conductivity-type semiconductor region and which have the first conductivity type. At least one second-conductivity-type potential barrier is provided under the drain region of the first transistor and the source region and/or the drain region of the second transistor. | 2008-10-23 |
20080258191 | CAPACITOR DEVICE PROVIDING SUFFICIENT RELIABILITY - A capacitor device includes a dielectric layer configured to have a composition represented as (Ba | 2008-10-23 |
20080258192 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a semiconductor device comprising an insulating film provided on a semiconductor substrate; a lower contact formed in the insulating film; a ferroelectric capacitor including a first lower electrode provided on the lower contact and connected to the lower contact, a second lower electrode provided on the first lower electrode and made of SRO (Strontium Ruthenium Oxide), a ferroelectric film including crystals, and an upper electrode provided on the ferroelectric film, grain diameters of the crystals being set to 30 nm to 150 nm by forming the ferroelectric film on the second lower electrode; and a wiring connected to the upper electrode. | 2008-10-23 |
20080258193 | FERROELECTRIC MEMORY AND METHOD OF MANUFACTURING THE SAME - A ferroelectric memory that stores information by using a hysteresis characteristic of a ferroelectric, has a semiconductor substrate; a lower electrode formed above said semiconductor substrate; a ferroelectric film formed on said lower electrode; and an upper electrode formed on said ferroelectric film, wherein said upper electrode includes an AO | 2008-10-23 |
20080258194 | FLIP FERAM CELL AND METHOD TO FORM SAME - A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure. | 2008-10-23 |
20080258195 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A ferroelectric capacitor is formed above a semiconductor substrate ( | 2008-10-23 |
20080258196 | SEMICONDUCTOR STRUCTURE OF A DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode. | 2008-10-23 |
20080258197 | SEMICONDUCTOR-INSULATOR-SILICIDE CAPACITOR - A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area. | 2008-10-23 |
20080258198 | STABILIZATION OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HAFNIUM OXIDE BASED SILICON TRANSISTORS FOR CMOS - The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising:
| 2008-10-23 |
20080258199 | FLASH MEMORY DEVICE AND FABRICATING METHOD THEREOF - The present invention relates to a flash memory device and its fabrication method, in more detail, it relates to a novel device structure for improving a scaling-down characteristic/performance and increasing memory capacity of the MOS-based flash memory device. | 2008-10-23 |
20080258200 | Memory cell having a shared programming gate - A semiconductor memory device includes a substrate, and a trench formed in the substrate. First and second floating gates, each associated with corresponding first and second memory cells, extend into the trench. Since the trench can be made relatively deep, the floating gates may be made relatively large while the lateral dimensions of the floating gates remains small. Moreover, the insulator thickness between the floating gate and a sidewall of the trench where a channel region is formed can be made relatively thick, even though the lateral extent of the memory cell is reduced. A programming gate extends into the trench between the first and second floating gates, and is shared, along with a source region, by the two memory cells. | 2008-10-23 |
20080258201 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for exposing part of said peripheral circuit region. | 2008-10-23 |
20080258202 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a semiconductor substrate having a first trench, an element isolation insulating film, a floating gate electrode, a second gate insulating film and a control gate electrode. The element isolation insulating film includes a sidewall having such a height as to be in contact with the floating gate electrode. The floating gate electrode includes a sidewall further including a lower portion opposed to the control gate electrode with the element isolation insulating film and the second gate insulating film being interposed between them. The control gate electrode is buried in the second trench with the second gate insulating film being interposed between them. | 2008-10-23 |
20080258203 | STACKED SONOS MEMORY - An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell. | 2008-10-23 |
20080258204 | MEMORY STRUCTURE AND OPERATING METHOD THEREOF - A memory structure including a substrate, a charge trapping layer, a block layer, a conducting layer and two doped regions is provided in the present invention. The charge trapping layer is disposed on the substrate. The block layer is disposed on the charge trapping layer. The conducting layer is disposed on the block layer. The doped regions are disposed respectively in the substrate on the two sides of the conducting layer. | 2008-10-23 |
20080258205 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - An erase current of a non-volatile semiconductor memory device is decreased. A memory cell of the non-volatile semiconductor memory device comprises a source region and a drain region formed in a semiconductor substrate. Over a portion of the semiconductor substrate between the source region and the drain region, a select gate electrode is formed via a gate dielectric film. On a side wall of the select gate electrode, a memory gate electrode is formed via a bottom silicon oxide film and a charge-trapping silicon oxynitride film. In the memory cell configured as above, erase operation is performed as follows. By applying a positive voltage to the memory gate electrode, holes are injected from the memory gate electrode into the silicon oxynitride film to decrease a threshold voltage in a program state to a certain level. Thereafter, hot holes generated by a band-to-band tunneling phenomenon are injected into the silicon oxynitride film and the erase operation is completed. | 2008-10-23 |
20080258206 | Self-Aligned Gate Structure, Memory Cell Array, and Methods of Making the Same - A self-aligned gate structure includes a first gate region and a second gate region. The first gate region extends in semiconductor substrate portions to a lesser depth than in isolation trenches that are adjacent to the semiconductor substrate portions. The first gate region comprises a first conductive material. The second gate region is adjacent to the first gate region and extends above a surface of the semiconductor substrate. The second gate region includes a second conductive material. | 2008-10-23 |
20080258207 | Block Contact Architectures for Nanoscale Channel Transistors - A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch. | 2008-10-23 |
20080258208 | SEMICONDUCTOR COMPONENT INCLUDING COMPENSATION ZONES AND DISCHARGE STRUCTURES FOR THE COMPENSATION ZONES - A semiconductor component including compensation zones and discharge structures for the compensation zones. One embodiment provides a drift zone of a first conduction type, at least one compensation zone of a second conduction type, complementary to the first conduction type, the at least one compensation zone being arranged in the drift zone, at least one discharge structure which is arranged between the at least one compensation zone and a section of the drift zone that surrounds the compensation zone or in the compensation zone and designed to enable a charge carrier exchange between the compensation zone and the drift zone if a potential difference between an electrical potential of the compensation zone and an electrical potential of the section of the drift zone that surrounds the compensation zone is greater than a threshold value predetermined by the construction and/or the positioning of the discharge structure. | 2008-10-23 |
20080258209 | SEMICONDUCTOR DEVICE AND MANUFATURING METHOD THEREOF - A semiconductor device comprises a plurality of semiconductor pillars laid out in matrix in a first and a second directions parallel with a main surface of a semiconductor substrate, and extending to a direction substantially perpendicular to the main surface; gate insulating films covering each surface of the plurality of semiconductor pillars, respectively; upper diffusion layers formed in each upper part of the plurality of semiconductor pillars, respectively; lower diffusion layers formed in each lower part of the plurality of semiconductor pillars, respectively; gate electrodes encircling at least each channel region between each upper diffusion layer and each lower diffusion layer, respectively; and a plurality of lower electrodes short-circuiting the lower diffusion layers adjacent in the first direction. | 2008-10-23 |
20080258210 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material. | 2008-10-23 |
20080258211 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a MIS-type semiconductor device having a trench gate structure, a withstand voltage is ensured without changing the thickness of a drift layer and on-resistance can be reduced without applying a high gate drive voltage. The lower half of a trench extending through a p-base region into an n-drift region is filled with a high-permittivity dielectric having a relative permittivity that is higher than that of a silicon oxide film, preferably a silicon nitride film, and an insulated gate structure including a gate insulator and a gate electrode is fabricated on the high-permittivity dielectric. The depth d | 2008-10-23 |
20080258212 | TRENCH METAL OXIDE SEMICONDUCTOR WITH RECESSED TRENCH MATERIAL AND REMOTE CONTACTS - Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided. | 2008-10-23 |
20080258213 | Shielded Gate Field Effect Transistor - A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type and a first silicon region of a second conductivity type over the substrate. The first silicon region has a first portion extending to a depth intermediate top and bottom surfaces of the gate electrode. The first silicon region has a second portion extending to a depth intermediate top and bottom surfaces of the shield electrode. The semiconductor region further includes a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region that has a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the lower trench portion. | 2008-10-23 |
20080258214 | Semiconductor Device and Method of Fabricating the Same - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can provide a trench MOS transistor having an up-drain structure. The semiconductor device can include a first conductive type well in a semiconductor substrate, a second conductive type well on the first conductive type well, trenches formed by removing portions of the second conductive type well and the first conductive type well; gates provided in the trenches with a gate dielectric being between each gate and the walls of the trench, a first conductive type source region and a second conductive type body region on the second conductive type well, the first conductive type source region surrounding a lateral surface of the gate, and a common drain between the gates, the common drain being connected to the first conductive type well. | 2008-10-23 |
20080258215 | LDMOS Device - An LDMOS transistor comprises source, channel and extended drain regions. The extended drain region comprises a plurality of islands that have a conductivity type that is opposite to the extended drain region. The islands have a depth less than a depth of the extended drain region. | 2008-10-23 |
20080258216 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a field effect transistor including a semiconductor substrate having a channel-forming region, an insulating film formed on the semiconductor substrate, a gate electrode trench formed in the insulating film, a gate insulating film formed at the bottom of the gate electrode trench, a gate electrode formed by filling the gate electrode trench with a layer on the gate insulating film, offset spacers composed of silicon oxide or boron-containing silicon nitride and formed as a portion of the insulating film to constitute the sidewall of the gate electrode trench, sidewall spacers formed as a portion of the insulating film on both sides of the offset spacers on the side away from the gate electrode, and source-drain regions having an extension region and formed in the semiconductor substrate and below at least the offset spacers and the sidewall spacers. | 2008-10-23 |
20080258217 | Semiconductor device structure for anti-fuse - The present invention discloses a semiconductor device, the device comprising a semiconductor layer on a substrate. A gate oxide and a gate electrode are formed on the semiconductor substrate. A gate conductive layer is formed on the gate electrode. A first doped region is formed in the semiconductor layer. A dielectric spacer is optionally formed onto the sidewall of the gate electrode and part of the semiconductor layer. A second doped region is formed from a predetermined distance to the gate electrode, wherein the predetermined distance is no less than the distance between the first doped region and the gate electrode. A third doped region is formed adjacent to the first doped region in the semiconductor layer and between the first doped region and the second doped region. | 2008-10-23 |
20080258218 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer. | 2008-10-23 |
20080258219 | Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer - A semiconductor device is provided which comprises a semiconductor layer ( | 2008-10-23 |
20080258220 | ION IMPLANTATION COMBINED WITH IN SITU OR EX SITU HEAT TREATMENT FOR IMPROVED FIELD EFFECT TRANSISTORS - This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants. | 2008-10-23 |
20080258221 | SUBSTRATE SOLUTION FOR BACK GATE CONTROLLED SRAM WITH COEXISTING LOGIC DEVICES - A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device. | 2008-10-23 |
20080258222 | Design Structure Incorporating a Hybrid Substrate - Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions. | 2008-10-23 |
20080258223 | ESD PROTECTION DEVICE - An ESD protection device is provided. The ESD protection device of the present invention includes a semiconductor substrate/well, a first doped region, a second doped region and a third doped region. The first doped region doped with a first dopant is disposed in the semiconductor substrate/well. The second doped region doped with a second dopant is disposed in the semiconductor substrate/well, wherein a predetermined distance is maintained between the second doped region and the first doped region. The third doped region doped with the second dopant is disposed in the first doped region. The ESD protection device of the present invention is adapted for solving the reverse recovery problem of the conventional diode during the bipolar type ESD stressing. | 2008-10-23 |
20080258224 | Trenched MOSFETs with improved gate-drain (GD) clamp diodes - A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect. The MOSFET device further includes a second Zener diode connected between a gate metal and a source metal of the MOSFET device for functioning as a gate-source (GS) clamp diode, wherein the GD clamp diode includes multiple back-to-back doped regions in the polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on the insulation layer above the MOSFET device having a lower breakdown voltage than a gate oxide rupture voltage of the MOSFET device. | 2008-10-23 |
20080258225 | MOS TRANSISTORS HAVING HIGH-K OFFSET SPACERS THAT REDUCE EXTERNAL RESISTANCE AND METHODS FOR FABRICATING THE SAME - MOS transistors having high-k spacers and methods for fabricating such transistors are provided. One exemplary method comprises forming a gate stack overlying a semiconductor substrate and forming an offset spacer about sidewalls of the gate stack. The offset spacer is formed of a high-k dielectric material that results in a low interface trap density between the offset spacer and the semiconductor substrate. First ions of a conductivity-determining impurity type are implanted into the semiconductor substrate using the gate stack and the offset spacer as an implantation mask to form spaced-apart impurity-doped extensions. | 2008-10-23 |
20080258226 | METHODS FOR MANUFACTURING A TRENCH TYPE SEMICONDUCTOR DEVICE HAVING A THERMALLY SENSITIVE REFILL MATERIAL - Methods for manufacturing trench type semiconductor devices containing thermally unstable refill materials are provided. A disposable material is used to fill the trenches and is subsequently replaced by a thermally sensitive refill material after the high temperature processes are performed. Trench type semiconductor devices manufactured according to method embodiments are also provided. | 2008-10-23 |
20080258227 | STRAINED SPACER DESIGN FOR PROTECTING HIGH-K GATE DIELECTRIC - A semiconductor device pair is provided. The semiconductor device pair comprises a semiconductor substrate comprising a first gate structure with a first type polarity and a second gate structure with a second type polarity, the first and the second gate structures comprise a high-K gate dielectric. A plurality of oxygen-free offset spacer portions are adjacent either side of the respective first and second gate structures, each comprising a stressed dielectric layer, to induce a desired strain on a respective channel region while sealing respective high-K gate dielectric sidewall portions, wherein the oxygen-free offset spacer portions adjacent either side of the first gate structure and the oxygen-free offset spacer portions adjacent either side of the second gate structure are formed with different shapes. | 2008-10-23 |
20080258228 | Contact Scheme for MOSFETs - A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact. | 2008-10-23 |
20080258229 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an N-type MOS transistor and a P-type MOS transistor. The N-type MOS transistor has a first gate insulating film and a first gate electrode. The P-type MOS transistor has a second gate insulating film and a second gate electrode. The first gate insulating film and the second gate insulating film are made of silicon oxynitride, and the first gate insulating film and the second gate insulating film are different from each other in nitrogen concentration profile. | 2008-10-23 |
20080258230 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer. | 2008-10-23 |
20080258231 | SEMICONDUCTOR DEVICE - A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter. | 2008-10-23 |
20080258232 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes a substrate, an insulating film disposed on the substrate, a resistor groove disposed in the insulating film, and a resistor disposed in the resistor groove. The resistor is separated from all side surfaces of the resistor groove by a predetermined distance. | 2008-10-23 |
20080258233 | Semiconductor Device with Localized Stressor - A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors. | 2008-10-23 |
20080258234 | SEMICONDUCTOR STRUCTURE FOR LOW PARASITIC GATE CAPACITANCE - A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance. | 2008-10-23 |
20080258235 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. | 2008-10-23 |
20080258236 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n | 2008-10-23 |
20080258237 | SEMICONDUCTOR DEVICE HAVING MULTI-CHANNEL AND METHOD OF FABRICATING THE SAME - An embodiment of the present invention relates to a semiconductor device having a multi-channel and a method of fabricating the same. In an aspect, the semiconductor device includes a semiconductor substrate in which isolation layers are formed, a plurality of trenches formed within an active region of the semiconductor substrate, and a channel active region configured to connect opposite sidewalls within each trench region and having a surface used as a channel region. | 2008-10-23 |
20080258238 | Semiconductor Device Manufactured Using an Oxygenated Passivation Process During High Density Plasma Deposition - In one aspect, the method comprises forming trenches in a semiconductor substrate and filling the trenches with a dielectric material. The process of filling the trenches includes depositing the dielectric material with a plasma gas mixture, etching the dielectric material with a chemical etch including nitrogen fluoride and using a passivation process to passivate the dielectric material after etching with a gas mixture that includes oxygen and hydrogen. | 2008-10-23 |
20080258239 | METHODS FOR MANUFACTURING A TRENCH TYPE SEMICONDUCTOR DEVICE HAVING A THERMALLY SENSITIVE REFILL MATERIAL - Methods for manufacturing trench type semiconductor devices involve refilling the trenches after high temperature processing steps are performed. The methods allow thermally unstable materials to be used as refill materials for the trenches of the device. Trench type semiconductor devices containing thermally unstable refill materials are also provided. In particular, methods of manufacturing and devices of a trench type semiconductor devices containing organic refill materials are provided. | 2008-10-23 |
20080258240 | Integrated circuits and interconnect structure for integrated circuits - An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with respective ones of the N plane-like metal layers, where M is an integer greater than one, wherein the first plane-like metal layer and the N plane-like metal layers are located in separate planes. A first drain region has a generally rectangular shape. First, second, third and fourth source regions have a generally rectangular shape and that are arranged adjacent to sides of the first drain region. The first drain region and the first, second, third and fourth source regions communicate with at least two of the N plane-like metal layers. A first gate region is arranged between the first, second, third and fourth source regions and the first drain region. First, second, third and fourth substrate contact regions are arranged adjacent to corners of the first drain region. | 2008-10-23 |
20080258241 | Integrated circuits and interconnect structure for integrated circuits - An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first source region is arranged between first sides of the first and second drain regions and the second and third source regions are arranged adjacent to second sides of the first and second drain regions. A fourth source region is arranged adjacent to third sides of the first and second drain regions and a fifth source region is arranged adjacent to fourth sides of the first and second drain regions. First and second drain contacts are arranged in the first and second drain regions, respectively. At least two of the first, second, third, fourth and fifth source regions and the first and second drain regions communicate with at least two of the N plane-like metal layers. | 2008-10-23 |
20080258242 | Low contact resistance ohmic contact for a high electron mobility transistor and fabrication method thereof - A semiconductor device ( | 2008-10-23 |
20080258243 | FIELD EFFECT TRANSISTOR - A field effect transistor includes: a first nitride semiconductor layer having a plane perpendicular to a (0001) plane or a plane tilted with respect to the (0001) plane as a main surface; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider bandgap than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer; and a source electrode and a drain electrode formed so as to contact at least a part of the second nitride semiconductor layer or the third nitride semiconductor layer. A recess that exposes a part of the second nitride semiconductor layer is formed between the source electrode and the drain electrode in the third nitride semiconductor layer. A gate electrode is formed in the recess and an insulating film is formed between the third nitride semiconductor layer and the gate electrode. | 2008-10-23 |
20080258244 | SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a gate dielectric layer provided on the semiconductor substrate, a source region provided in the semiconductor substrate, a drain region provided in the semiconductor substrate, and a gate electrode provided on the gate dielectric layer having a metal containing layer and a polycrystalline silicon layer having an impurity ion, the polycrystalline silicon layer provided on the metal containing layer so as to cover an upper surface and side surface of the metal containing layer. | 2008-10-23 |
20080258245 | Semiconductor Constructions and Transistor Gates - One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first layered defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second layer defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide. | 2008-10-23 |
20080258246 | PASSIVE ELECTRICALLY TESTABLE ACCELERATION AND VOLTAGE MEASUREMENT DEVICES - Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to said nanotubes. | 2008-10-23 |
20080258247 | SPIN-TRANSFER MRAM STRUCTURE AND METHODS - A spin-transfer MRAM bit includes a free magnet layer positioned between a pair of spin polarizers, wherein at least one of the spin polarizers comprises an unpinned synthetic antiferromagnet (SAF). The SAF may include two antiparallel fixed magnet layers separated by a coupling layer. To improve manufacturability, the layers of the SAF may be non-symmetrical (e.g., having different thicknesses or different inherent anisotropies) to assist in achieving proper alignment during anneal. The total magnetic moment of the SAF may be greater than that of the free magnet layer. | 2008-10-23 |
20080258248 | Image Sensor and Method for Manufacturing the Same - An image sensor and a method for manufacturing the same are provided. A photodiode region and transistor region are vertically-integrated to improve the fill factor and resolution of the image sensor. Unit pixels can be isolated by a metal isolation layer arranged between adjacent photodiode areas. | 2008-10-23 |
20080258249 | CMOS image sensor and method for fabricating the same - A CMOS image sensor and a method for fabricating the same improve photosensitivity by imparting a color filter layer with the function of a microlens layer. The CMOS image sensor includes a semiconductor substrate; a plurality of photo-sensing elements formed in the semiconductor substrate; and a color filter layer comprised of a plurality of color filters for filtering light according to wavelength, wherein the plurality of color filters correspond to the plurality of photo-sensing elements and each color filter has a predetermined curvature for focusing light and for transmitting the focused light according to a corresponding wavelength. | 2008-10-23 |
20080258250 | Solid-state image capturing device, method of manufacturing the same, and electronic information device - A solid-state image capturing device is provided, in which a multilayered wiring section having a plurality of wiring layers laminated via respective interlayer insulation films is provided on a semiconductor substrate or a semiconductor region formed on the substrate where a plurality of light receiving sections for photoelectrically converting a subject light are arranged in matrix in a pixel section; and the interlayer insulation films in a pixel section are evenly engraved, so that the pixel section of the substrate is thinner than a peripheral circuit section; and a plurality of light receiving sections and respective microlenses facing with each other are arranged on the bottom surface of the engraved portion of the interlayer insulation film. | 2008-10-23 |
20080258251 | IMAGE SENSOR - An image sensor including a second line formed at an upper part of a photodiode region as a transparent electrode for passing light. The second line is composed of a polymeric material having transparency and conductivity. | 2008-10-23 |
20080258252 | CIRCUIT ARRANGEMENT HAVING A FREE-WHEEL DIODE - An object of the present invention is to reduce the conducting loss of an existing conversion circuit while suppressing its noise. The present invention is typically a circuit arrangement includes at least one switching device and a free-wheel diode connected in parallel with the switching device. The free-wheel diode is formed by connecting a silicon PiN diode in parallel with a Schottky barrier diode that uses a semiconductor material having a wider band gap than silicon as a base material. The silicon PiN diode and Schottky barrier diode are separate chips. | 2008-10-23 |
20080258253 | Integrated Microprocessor System for Safety-Critical Regulations - Disclosed is an integrated circuit arrangement for safety-critical applications, such as for regulating and controlling tasks in an electronic brake system for motor vehicles. The arrangement includes several electronic, cooperating functional groups ( | 2008-10-23 |
20080258254 | PROCESS FOR REALIZING AN INTEGRATED ELECTRONIC CIRCUIT WITH TWO ACTIVE LAYER PORTIONS HAVING DIFFERENT CRYSTAL ORIENTATIONS - A process for realizing an integrated electronic circuit makes it possible to obtain transistors with p-type conduction and transistors with n-type conduction, in respective active zones having crystal orientations adapted to each conduction type. In addition, each active zone is electrically insulated from a primary substrate of the circuit, so that the entire circuit is compatible with SOI technology. | 2008-10-23 |
20080258255 | Electromigration Aggravated Electrical Fuse Structure - A fuse structure with aggravated electromigration effect is disclosed, which comprises an anode area overlaying a first plurality of contacts that are coupled to a positively high voltage during a programming of the fuse structure, a cathode area overlaying a second plurality of contacts that are coupled to a complementary low voltage during a programming of the fuse structure, and a fuse link area having a first and second end, wherein the first end contacts the anode area at a predetermined distance to the nearest of the first plurality of contacts, and the second end contacts the cathode area at the predetermined distance to the nearest of the second plurality of contacts, wherein the cathode area is smaller than the anode area for the aggravating electromigration effect. | 2008-10-23 |
20080258256 | SEMICONDUCTOR ELECTRICALLY PROGRAMMABLE FUSE ELEMENT WITH AMORPHOUS SILICON LAYER AFTER PROGRAMMING AND METHOD OF PROGRAMMING THE SAME - A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer. | 2008-10-23 |
20080258257 | Electronic Device and Use Thereof - The integrated capacitor structure comprises a first branch with a first capacitor ( | 2008-10-23 |
20080258258 | SEMICONDUCTOR DEVICE - The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed on the side and back surfaces of the semiconductor substrate, and a capacitor electrode is formed between the back surface of the semiconductor substrate and the second insulation film, contacting the back surface of the semiconductor substrate. The second insulation film is covered by wiring layers electrically connected to the pad electrodes, and the wiring layers and the capacitor electrode overlap with the second insulation film being interposed therebetween. Thus, the capacitor electrode, the second insulation film and the wiring layers form capacitors. | 2008-10-23 |
20080258259 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor chip and a semiconductor device mounting the semiconductor chip capable of increasing a capacitance of a capacitor without reducing the number of signal bumps or power bumps of a package and the number of C | 2008-10-23 |
20080258260 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a capacitor formed over a semiconductor substrate and including a lower electrode, a dielectric film formed over the lower electrode and an upper electrode formed over the dielectric film, an insulation film formed over the semiconductor substrate and the capacitor, and an electrode pad formed over the insulation film and including an alloy film of aluminum and magnesium. | 2008-10-23 |
20080258261 | Split Chip - This Invention is a design method and a system for a miniaturized silicon circuit whereby the circuit is split into two pieces. This process is known to the Inventor as a bifurcated circuit or disintegrated circuit and is titled the “Split Chip” by the Inventor. The Split Chip contemplates an RFID enabled consumer oriented tracking system which protects consumer privacy. The goal of this Invention is accomplished by splitting the RFID transponder circuit into a retained piece and a detached piece. Each piece is contained on a separate wafer of silicon. The two pieces are electrically connected by a fine piece of conductive material. Each piece is dependent upon the other in order to disgorge data. The electrical connection between the two pieces can be severed by the consumer. This is accomplished by tearing the fine piece of conductive material at a designated spot on the substrate. The result of the tear is that the Split Chip is now moribund. Upon the circumstance of a return or refund consumer item the original data can be recovered through a laser guidance system which connects the retained piece and its alpha numeric identifier to a back end host computer administration network. | 2008-10-23 |
20080258262 | SEMICONDUCTOR DEVICE WITH IMPROVED PADS - A semiconductor device has: a circuit portion having semiconductor elements formed on a semiconductor substrate; insulating lamination formed above the semiconductor substrate and covering the circuit portion; a multilevel wiring structure formed in the insulating lamination and including wiring patterns and via conductors; and a pad electrode structure formed above the semiconductor substrate and connected to the multilevel wiring structure. The pad electrode structure includes pad wiring patterns and pad via conductors interconnecting the pad wiring patterns, the uppermost pad wiring pattern includes a pad pattern and a sealing pattern surrounding the pad pattern in a loop shape. Another pad wiring pattern has continuous extended pad pattern of a size overlapping the sealing pattern. The pad via conductors include a plurality of columnar via conductors disposed in register with the pad pattern and a loop-shaped wall portion disposed in register with the sealing pattern. | 2008-10-23 |
20080258263 | High Current Steering ESD Protection Zener Diode And Method - A method of fabricating a N+/P+ zener diode where the reverse breakdown occurs in a controlled, and uniform manner leading to improved speed of operation and increase in current handling capability. | 2008-10-23 |
20080258264 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a semiconductor device comprising a Ge semiconductor area, and an insulating film area, formed in direct contact with the Ge semiconductor area, containing metal, germanium, and oxygen. | 2008-10-23 |
20080258265 | METHODS FOR FORMING AN ASSEMBLY FOR TRANSFER OF A USEFUL LAYER - Methods for transferring of a useful layer from a support are described. In an embodiment, the method includes for facilitating transfer of a useful layer from a support by providing an interface in a first support to define a useful layer; and forming a peripheral recess on the first support below the interface so that the periphery of the interface is exposed to facilitate removal and transfer of the useful layer. An epitaxial layer can be formed on the useful layer after forming the recess, with the width and depth of the recess being sufficient to accommodate the volume of residual material resulting from formation of the epitaxial layer without covering the periphery of the interface. Alternatively, an epitaxial layer can be formed on the useful layer after forming the recess, wherein the peripheral recess is configured for receiving sufficient residual material from the epitaxial layer to prevent bonding between the residual material and the useful layer. | 2008-10-23 |
20080258266 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening. | 2008-10-23 |
20080258267 | Method of Producing Semiconductor Device and Semiconductor Device - A method of producing a semiconductor device which can reliably perform conductor filling to form a through hole electrode by a simple method is provided. A method of producing a semiconductor device of the present invention includes the steps of thinning a substrate from its back side in a state in which a first supporting body is attached to the front side of the substrate, removing the first supporting body from the substrate and attaching a second supporting body having an opening to the back side of the substrate, forming a through hole communicating with the opening of the second supporting body in the substrate before or after attaching the second supporting body, forming an insulating film within the through hole, and filling a conductor into the through hole of the substrate. | 2008-10-23 |
20080258268 | TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE - Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally, such that the deep trench of the deep trench capacitor has different shapes and sizes at different depths. By forming the deep trench with different shapes and sizes at different depths the capacitance of the capacitor can be selectively varied and the resistance of the buried conductive strap which connects the capacitor to a transistor in a memory device can be reduced. | 2008-10-23 |
20080258269 | SEMICONDUCTOR WAFER AND METHOD FOR CUTTING THE SAME - A semiconductor wafer and a method for cutting the same, enabling separation of the semiconductor wafer by natural cleavage planes, are disclosed. The cutting method according to an embodiment of the present invention comprises preparing a substrate including a semiconductor layer with at least one projection, formed on a predetermined area thereof; forming a post on an upper surface of the semiconductor layer at one or both sides of the projection to be placed on a cleaving line for cutting of the semiconductor layer; and cutting the substrate including the semiconductor layer along the cleaving line by performing a scribing process in a direction from the substrate and a breaking process in a direction from the semiconductor layer. | 2008-10-23 |
20080258270 | Mgo-Based Coating for Electrically Insulating Semiconductive Substrates and Production Method Thereof - The present invention relates to a magnesium oxide-based (MgO) inorganic coating intended to electrically insulate semiconductive substrates such as silicon carbide (SiC), and to a method for producing such an insulating coating. The method of the invention comprises the steps of preparing a treatment solution of at least one hydrolysable organomagnesium compound and/or of at least one hydrolysable magnesium salt, capable of forming a homogeneous polymer layer of magnesium oxyhydroxide by hydrolysis/condensation reaction with water; depositing the treatment solution of the hydrolysable organomagnesium compound or of the hydrolysable magnesium salt, onto a surface to form a magnesium oxide-based layer; and densifying the layer formed at a temperature of less than or equal to 1000° C. | 2008-10-23 |
20080258271 | Multi-dielectric films for semiconductor devices and methods of fabricating multi-dielectric films - A multi-dielectric film including at least one first dielectric film that is a composite film made of zirconium-hafnium-oxide and at least one second dielectric film that is a metal oxide film made of amorphous metal oxide. Adjacent ones of the dielectric films are made of different materials. | 2008-10-23 |
20080258272 | ETCHED LEADFRAME STRUCTURE - A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess. | 2008-10-23 |
20080258273 | Package Structure With Flat Bumps For Electronic Device and Method of Manufacture the Same - The invention discloses an ultra thin package structure of leadless electronic device and the packaging method, and includes lead support base adjacent to the chip support base; chip mounted on the chip support base; wires bonded between chip and lead support base; the molded body encapsulating the top surface and side surface of the chip support base, small protrusions of the chip support base and lead support base below the molded body; in the individual package, the number of the chip support base island can be one or more, the lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island. | 2008-10-23 |
20080258274 | Semiconductor Package and Method - A semiconductor package is disclosed. In one embodiment, the semiconductor package includes a leadframe including a chip position and a plurality of leadfingers. Each leadfinger includes a cutout in an inner edge providing a chip recess. The semiconductor package further includes a semiconductor chip located in the chip recess. The semiconductor chip has an active surface with a plurality of chip contact pads on each of which an electrically conductive bump is disposed. The inner portions of the leadfingers protrude into the chip position and are electrically connected to the chip contact pads by electrically conductive bumps. | 2008-10-23 |
20080258275 | CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES - Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. | 2008-10-23 |
20080258276 | Non-Leaded Semiconductor Package and a Method to Assemble the Same - A method to assemble a non-leaded semiconductor package ( | 2008-10-23 |
20080258277 | Semiconductor Device Comprising a Semiconductor Chip Stack and Method for Producing the Same - A semiconductor device includes a semiconductor chip stack having at least one lower semiconductor chip as a base of the semiconductor chip stack, and at least one upper semiconductor chip. An insulating intermediate plate is arranged between the semiconductor chips. Connecting elements wire the semiconductor chips, the intermediate plate and external terminals to one another. | 2008-10-23 |