43rd week of 2015 patent applcation highlights part 65 |
Patent application number | Title | Published |
20150303109 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate configured to include a circuit pattern at one surface, an insulation film formed over a back surface of the semiconductor substrate, a through silicon via (TSV) configured to pass through the semiconductor substrate and the insulation film, and an oxide film formed at a sidewall of the TSV and protruded from the back surface of the semiconductor substrate in a manner that the oxide film partially contacts the insulation film. | 2015-10-22 |
20150303110 | MICROFEATURE WORKPIECES HAVING INTERCONNECTS AND CONDUCTIVE BACKPLANES, AND ASSOCIATED SYSTEMS AND METHODS - Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals. The device further includes a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate. One or more of the interconnects are electrically coupled to the conductive layer at the back side of the semiconductor substrate. | 2015-10-22 |
20150303111 | DICING WAFERS HAVING SOLDER BUMPS ON WAFER BACKSIDE - Approaches for hybrid laser scribe and plasma etch dicing process for a wafer having backside solder bumps are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof and corresponding arrays of metal bumps on a backside thereof involves applying a dicing tape to the backside of the semiconductor wafer, the dicing tape covering the arrays of metal bumps. The method also involves, subsequently, forming a mask on the front side of the semiconductor wafer, the mask covering the integrated circuits. The method also involves forming scribe lines on the front side of the semiconductor wafer with a laser scribing process, the scribe lines formed in the mask and between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, the mask protecting the integrated circuits during the plasma etching. | 2015-10-22 |
20150303112 | METHOD FOR SINGULATING AN ASSEMBLAGE INTO SEMICONDUCTOR CHIPS, AND SEMICONDUCTOR CHIP - A method for singulating an assemblage ( | 2015-10-22 |
20150303113 | WAFER PROCESSING METHOD - A processing method for a wafer has a substrate and a laminated layer formed on the substrate. The laminated layer forms a plurality of crossing division lines and a plurality of devices formed in separate regions defined by the division lines. A groove is formed in the laminated layer along each division line by using a cutting blade. A modified layer is formed by applying a laser beam to the substrate along the division lines from the back side of the wafer in the condition where the focal point of the laser beam is set inside the substrate, thereby forming a modified layer inside the substrate along each division line. An external force is applied to the wafer, thereby dividing the wafer along each division line to obtain a plurality of individual chips. | 2015-10-22 |
20150303114 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE, OPTICAL APPARATUS INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A complementary metal oxide semiconductor (CMOS) device includes an n-type first transistor on a silicon substrate, the n-type first transistor including a Group III-V compound semiconductor substrate, and a p-type second transistor on the silicon substrate, the p-type second transistor including a germanium based substrate. | 2015-10-22 |
20150303115 | MODIFICATION OF A THRESHOLD VOLTAGE OF A TRANSISTOR BY OXYGEN TREATMENT - Methodologies and resulting devices are provided for modified FET threshold voltages. Embodiments include: providing an active region of a transistor on a semiconductor substrate; depositing a workfunction metal on the active region; and modifying a threshold voltage of the transistor by treating the workfunction metal with oxygen. Other embodiments include: providing first and second active regions in a semiconductor substrate for first and second transistors, respectively; forming a first workfunction metal on the first active region; forming a second workfunction metal on the second active region; and modifying a first threshold voltage level of the first transistor, a second threshold voltage level of the second transistor, or a combination thereof by treating the first workfunction metal, second workfunction metal, or a combination thereof with oxygen, wherein the second threshold voltage level is greater than the first threshold voltage level. | 2015-10-22 |
20150303116 | FinFETs with Different Fin Height and EPI Height Setting - An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip. | 2015-10-22 |
20150303117 | METHODS FOR FABRICATING INTEGRATED CIRCUTIS AND COMPONENTS THEREOF - Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for a fabricating a semiconductor device is provided. The method includes providing a partially fabricated semiconductor device and forming silicide regions outside of the first and second gates. The partially fabricated semiconductor device includes a semiconductor substrate, a first gate formed over the semiconductor substrate, and a second gate formed over the semiconductor substrate and spaced apart from the first gate. Silicide formation between the first gate and the second gate is inhibited. | 2015-10-22 |
20150303118 | Wrap-Around Contact - Fin structures are formed on a substrate. An isolation region is between the fin structures. The fin structures comprise epitaxial regions extending above the isolation region. Each of the epitaxial regions has a widest mid-region between an upper-surface and an under-surface. A dual-layer etch stop is formed over the fin structures and comprises a first sub-layer and a second sub-layer. The first sub-layer is along the upper- and under-surfaces and the isolation region. The second sub-layer is over the first sub-layer and along the upper-surfaces, and the second sub-layer merges together proximate the widest mid-regions of the epitaxial regions. Portions of the dual-layer etch stop are removed from the upper- and under-surfaces. A dielectric layer is formed on the upper- and under-surfaces. A metal layer is formed on the dielectric layer on the upper-surfaces. A barrier layer is formed on the metal layer and along the under-surfaces. | 2015-10-22 |
20150303119 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate having a main surface angled off in an off direction relative to a {0001} plane is prepared. A protruding first alignment mark is formed on the main surface of the silicon carbide substrate. A second alignment mark is formed on the first alignment mark by forming a silicon carbide epitaxial layer on the first alignment mark. The first alignment mark includes a first region and a second region, the second region being in contact with the first region and extending from the first region in the off direction. The second alignment mark includes a first portion formed on the first region and a second portion formed on the second region. An alignment step includes the step of capturing an image of the first portion while not including the second portion, and recognizing an edge of the first portion based on the image. | 2015-10-22 |
20150303120 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor package structure is disclosed. The method includes: providing a wafer having a front side and a backside; forming a plurality of through-silicon vias (TSVs) in the wafer and a plurality of metal interconnections on the TSVs, in which the metal interconnections are exposed from the front side of the wafer; performing a monitoring step to screen for TSV failures from the backside of the wafer; and bonding the wafer to a substrate. | 2015-10-22 |
20150303121 | HERMETIC PLASTIC MOLDED MEMS DEVICE PACKAGE AND METHOD OF FABRICATION - A hermetically packaged microelectromechanical system (MEMS) device has a substrate with an assembly pad ( | 2015-10-22 |
20150303122 | COMPOSITE COMPOSITIONS FOR ELECTRONICS APPLICATIONS - An electronics composition includes a curable matrix material and, optionally, a filler material disposed within the matrix material. The cured matrix material includes an oligomer or polymer material derived from a compound selected from a methylene malonate monomer, a multifunctional methylene monomer, a methylene beta ketoester monomer, a methylene beta diketone monomer, or a mixture thereof. | 2015-10-22 |
20150303123 | Array Substrate for Display Device and Manufacturing Method Thereof - The present disclosure provides an array substrate for a display device and a manufacturing method thereof. A transparent electrode pattern (ITO) may be formed between a source/drain metal pattern and a passivation layer located above the source/drain metal pattern, which are formed in a passivation hole area of a non-active area of the array substrate. Accordingly, it may be possible to prevent display failure caused by a delamination phenomenon or peel-off of a material of the passivation layer due to the lack of adhesion strength between a metal layer and the passivation layer in the passivation hole area. | 2015-10-22 |
20150303124 | NOVEL MULTI-FUNCTIONAL SEMICONDUCTOR REFRIGERATING AND WARMING DUAL-PURPOSE BOX AND MANUFACTURING METHOD - A multi-functional semiconductor refrigerating and warming dual-purpose box includes a box body, a refrigerating and heating unit, a composite condenser unit, and a liquid delivering pump. The box body includes two independent rooms, a bottom machine room, an upper working room, and a lower working room. The refrigerating and heating unit includes an upper room semiconductor refrigerating and heating unit and a lower room semiconductor refrigerating and heating unit, the upper room semiconductor refrigerating and heating unit comprising an external heat exchanger of the upper room, a first semiconductor chilling plate, and an internal heat exchanger of the upper room. The composite condenser unit and the liquid delivering pump are connected to the external heat exchanger of the upper room and the external heat exchanger of the lower room through pipes. A manufacturing method of a multi-functional semiconductor refrigerating and warming dual-purpose box is also provided. | 2015-10-22 |
20150303125 | SEMICONDUCTOR APPARATUS INCLUDING A HEAT DISSIPATING MEMBER - A semiconductor apparatus is provided. The semiconductor apparatus includes: a base having a main surface on which a terminal is disposed; a first semiconductor device retained on the main surface of the base and having a top surface on which an electrode is disposed and a bottom surface facing the main surface of the base; a connection member connecting the terminal and the electrode; an encapsulant disposed on the main surface of the base and covering the terminal, the first semiconductor device and the connection member; and a heat dissipating member disposed on the encapsulant and having a space that opens in a direction extending perpendicular to the main surface of the base. The encapsulant is disposed in the space and, in a side view of the base, a peak of the connection member is located inside the space. | 2015-10-22 |
20150303126 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate including a substrate, a metal pattern formed on an upper surface of the substrate, and a metal film formed on a lower surface of the substrate, a semiconductor element fixed on the metal pattern, a case surrounding the metal pattern and having a contact portion maintained in contact with the upper surface of the substrate, and an adhesive with which the case and a portion of the upper surface of the substrate outside a portion maintained in contact with the contact portion are bonded together, wherein a plurality of through holes are formed in a peripheral portion of the case, the through holes extending vertically through the case, and wherein the metal film exists in at least part of a place right below the contact portion. | 2015-10-22 |
20150303127 | Chip-Scale Packaging With Protective Heat Spreader - A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die. | 2015-10-22 |
20150303128 | Device Including Multiple Semiconductor Chips and Multiple Carriers - A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact. | 2015-10-22 |
20150303129 | THERMAL INTERFACE COMPOSITIONS AND METHODS FOR MAKING AND USING SAME - A thermal interface material includes a conformable component and a thermally conductive filler dispersed in the conformable component. The material is provided in at least two segments laterally spaced from one another to define one or more gaps, each of the segments having a length, a width, and a height. The average aspect ratio of length to height and/or width to height of the at least two segments is between 1:10 and 10:1. | 2015-10-22 |
20150303130 | Semiconductor Package and Method of Manufacturing the Same - Disclosed are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a flexible substrate provided with signal lines, a semiconductor device bonded on the flexible substrate and configured to be connected to the signal lines through at least one of gold bumps or solder bumps, and a heat dissipation layer formed on at least a portion of the flexible substrate and at least a portion of the semiconductor device. The heat dissipation layer is formed by coating a heat dissipation paint composition and curing the heat dissipation paint composition. The heat dissipation paint composition includes an epichlorohydrin bisphenol A resin, a modified epoxy resin, a curing agent, a curing accelerator and a heat dissipation filler. | 2015-10-22 |
20150303131 | Through-Polymer Via (TPV) and Method to Manufacture Such a Via - Vias for three dimensional (3D) stacking, packaging and heterogeneous integration of semi-conductor layers and wafers and a process for the manufacture of a via, to a via, to a 3D circuit and to a semiconductor device. Vias are interconnects used to vertically interconnect chips, devices, interconnection layers and wafers, i.e., in an out-of-plane direction. | 2015-10-22 |
20150303132 | POWER MANAGEMENT APPLICATIONS OF INTERCONNECT SUBSTRATES - Various applications of interconnect substrates in power management systems are described. | 2015-10-22 |
20150303133 | FLAT NO-LEAD PACKAGE AND THE MANUFACTURING METHOD THEREOF - A flat no-lead package includes an encapsulating material, and a die pad, a chip, a plurality of first contact pads and a plurality of second contact pads disposed in the encapsulating material. The encapsulating material has a package bottom surface. The die pad has a plurality of die pad extensions extending from the edges thereof. The chip is mounted on the die pad. The first contact pads are disposed near the edges of the encapsulating material and electrically coupled to the chip. The second contact pads are located between the die pad and the first contact pads and electrically coupled to the chip. Each of the second contact pads have a second contact pad extension corresponding to one of the die pad extensions respectively. The bottom surfaces of the first contact pads, the second contact pads and the second contact pad extensions arc exposed on the package bottom surface, | 2015-10-22 |
20150303134 | Universal Lead Frame for Flat No-Leads Packages - A universal lead frame for semiconductor packages includes a solid lead frame sheet comprising an electrically conductive material and a plurality of columns etched into the lead frame sheet and distributed with a predetermined lead pitch so that the universal lead frame has a solid first main side opposite the columns and a patterned second main side opposite the first main side. A method of manufacturing the universal lead frame includes providing a solid lead frame sheet of an electrically conductive material and etching a plurality of columns into the lead frame sheet so that the columns are distributed with a predetermined lead pitch and the universal lead frame has a solid first main side opposite the columns and a patterned second main side opposite the first main side. A method of manufacturing molded semiconductor packages using the universal lead frame is also provided. | 2015-10-22 |
20150303135 | Method for Fabricating a Semiconductor Package and Semiconductor Package - A method for fabricating semiconductor packages includes providing a first substrate having an aperture, providing a first semiconductor chip, connecting the first semiconductor chip to the first substrate, filling the aperture with a first insulating material and encapsulating the semiconductor chip with a second insulating material to create a first encapsulation body. | 2015-10-22 |
20150303136 | HIGH EFFICIENCY MODULE | 2015-10-22 |
20150303137 | MULTI-USE SUBSTRATE FOR INTEGRATED CIRCUIT - A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die. | 2015-10-22 |
20150303138 | SEMICONDUCTOR INTERPOSER AND PACKAGE STRUCTURE HAVING THE SAME - A semiconductor interposer is provided, which includes: a substrate body having a surface defined with an inner area and a peripheral area around the inner area; a plurality of conductive posts embedded in the substrate body and each having one end exposed from the surface of the substrate body; a passivation layer formed on the surface of the substrate body and having a peripheral portion formed in the peripheral area, a plurality of ring-shaped portions formed around peripheries of the exposed ends of the conductive posts in the inner area and a plurality of strip-shaped portions formed between the ring-shaped portions for connecting the ring-shaped portions; and a UBM layer formed on the exposed end of each of the conductive posts and extending on the ring-shaped portion around the periphery of the exposed end of the conductive post, thereby effectively reducing stresses to prevent warping of the semiconductor interposer. | 2015-10-22 |
20150303139 | SUBSTRATE HAVING ELECTRICAL INTERCONNECTION STRUCTURES AND FABRICATION METHOD THEREOF - A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer. | 2015-10-22 |
20150303140 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING THE SAME - One or more semiconductor arrangements are provided. A semiconductor arrangement includes a first dielectric layer defining a first recess, a first contact in the first dielectric layer, a first metal cap over at least part of the first contact and a second dielectric layer over the first dielectric layer within the first recess and defining an air gap proximate the first contact. One or more methods of forming a semiconductor arrangement are also provided. Such a method includes forming a first metal cap on a first exposed surface of a first contact, the first metal cap having an extension region that extends into a first recess defined in a first dielectric layer and forming a second dielectric layer over the first dielectric layer within the first recess such that an air gap is defined within the second dielectric layer proximate the first contact due to the extension region. | 2015-10-22 |
20150303141 | SEMICONDUCTOR DEVICE WITH INTEGRATED HOT PLATE AND RECESSED SUBSTRATE AND METHOD OF PRODUCTION - The semiconductor device comprises a substrate of semiconductor material, a dielectric layer on the substrate, an electrically conductive contact pad arranged in the dielectric layer, a hot plate arranged in the dielectric layer, a recess of the substrate at the location of the hot plate, and an integrated circuit, which operates the hot plate. An electrically conductive layer is arranged on a side of the substrate opposite the dielectric layer. The substrate is provided with a via hole above the contact pad, and an electrically conductive material connecting the electrically conductive layer with the contact pad is applied in the via hole. The recess and the via hole are formed in the same process step. | 2015-10-22 |
20150303142 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor substrate provided with an integrated circuit is polished by CMP or the like, and the semiconductor substrate is made into a thin film by forming an embrittlement layer in the semiconductor substrate and separating a part of the semiconductor substrate; thus, semiconductor chips such as IC chips and LSI chips which are thinner than ever are obtained. Moreover, such thinned LSI chips are stacked and electrically connected through wirings penetrating through the semiconductor substrate; thus, a three dimensional semiconductor integrated circuit with improved packing density is obtained. | 2015-10-22 |
20150303143 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device including an oscillator and a manufacturing method thereof, in which cost is low and design flexibility is high. The semiconductor device includes a wiring structure region and an oscillator region. The semiconductor device also includes, in the oscillator region, a metal resistive element as the same layer as a conducting film over uppermost metal wiring in the wiring structure region. | 2015-10-22 |
20150303144 | Semiconductor Device and A Method Increasing a Resistance Value of an Electric Fuse - A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers. | 2015-10-22 |
20150303145 | BACK END OF LINE (BEOL) LOCAL OPTIMIZATION TO IMPROVE PRODUCT PERFORMANCE - The disclosure relates to a locally optimized integrated circuit (IC) including a first portion employing one or more metal interconnects having a first metal width and/or one or more vias having a first via width, and a second portion employing one or more metal interconnects having a second metal width and/or one or more vias having a second via width, wherein the second portion comprises a critical area of the IC, and wherein the second metal width is greater than the first metal width and the second via width is greater than the first via width. A method of locally optimizing an IC includes forming the one or more metal interconnects and/or the one or more vias in the first portion of the IC, and forming the one or more metal interconnects and/or the one or the more vias in the second portion of the integrated circuit. | 2015-10-22 |
20150303146 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE - A semiconductor package includes a first substrate including a first surface layer where a first pad region and a second pad region are formed, the first pad region including a plurality of first pads for connection to a first IC, the second pad region including a plurality of second pads for connection to a second substrate, and a second surface layer where a third pad region including a plurality of third pads for connection to a second IC is formed, the second surface layer being formed on an opposite side of the first surface layer. The second pads surround the first pad region in at least three rows, and one or more pads included in the second pads and arranged in an inner portion are connected to one or more pads included in the first pads and to one or more pads included in the third pads. | 2015-10-22 |
20150303147 | Semiconductor Constructions, Methods of Forming Conductive Structures and Methods of Forming DRAM Cells - Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions. | 2015-10-22 |
20150303148 | DIE PACKAGE COMPRISING DIE-TO-WIRE CONNECTOR AND A WIRE-TO-DIE CONNECTOR CONFIGURED TO COUPLE TO A DIE PACKAGE - Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer. | 2015-10-22 |
20150303149 | EMI SHIELDED WAFER LEVEL FAN-OUT POP PACKAGE - In some embodiments, a semiconductor device package assembly may include a first substrate. The first substrate may include a first set of electrical conductors which electrically connect the assembly. In some embodiments, the assembly may include at least one electrical conductor coupled to the first substrate such that at least one of the electrical conductors exposes through a perimeter surface of the semiconductor device package assembly. In some embodiments, the assembly may include a first die electrically connected to a second surface of the first substrate using a second set of electrical conductors. The assembly may include an electronic memory module coupled to the first die. In some embodiments, the assembly may include a shield applied to an upper surface of the assembly and electrically coupled to at least one of the exposed electrical conductors. The shield may inhibit, during use, electromagnetic interference. | 2015-10-22 |
20150303150 | Array Substrate, Method of Manufacturing The Same and Display Device - An array substrate and manufacturing method thereof, and a display device are provided. The array substrate comprises a TFT, an isolating layer (M), a pixel electrode ( | 2015-10-22 |
20150303151 | RESIST FILM FORMING DEVICE AND METHOD, CONDUCTIVE FILM FORMING AND CIRCUIT FORMING DEVICE AND METHOD, ELECTROMAGNETIC WAVE SHIELD FORMING DEVICE AND METHOD, SHORTWAVE HIGH-TRANSMISSIBILITY INSULATION FILM FORMING DEVICE AND METHOD, FLUORESCENT LIGHT BODY FILM FORMING DEVICE AND METHOD, TRACE MATERIAL COMBINING DEVICE AND METHOD, RESIN MOLDING DEVICE, RESIN MOLDING METHOD, THIN FILM FORMING DEVICE, ORGANIC ELECTROLUMINESCENCE ELEMENT, BUMP FORMING DEVICE AND METHOD, WIRING FORMING DEVICE AND METHOD, AND WIRING STRUCTURE BODY - Provided is a resist film forming device which uses an electrostatic spray device which is capable of forming a thin film with a uniform thickness on a workpiece. A resist film forming device ( | 2015-10-22 |
20150303152 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR MODULE INCLUDING THE SAME - A semiconductor package includes the following elements. A high-output switch IC includes an IC top surface on which an electrode is disposed and an IC bottom surface on which no electrode is disposed. A connecting terminal is formed at a position outside a projection region toward a side portion of the semiconductor package. The projection region is a region projected in a thickness direction of the high-output switch IC. A wire electrically connects the electrode and the connecting terminal. A mold resin section covers the IC top surface and the wire and also covers a surface of the connecting terminal to which the wire is connected. A surface of the connecting terminal opposite to the surface to which the wire is connected is not covered with the mold resin section but is exposed. The IC bottom surface is not covered with a metal. | 2015-10-22 |
20150303153 | FUNCTIONAL ELEMENT, ELECTRONIC APPARATUS AND MOBILE ENTITY - According to an aspect of the invention, a functional element includes a substrate which is provided with a concave section; a stationary section connected to a wall section that defines the concave section of the substrate; an elastic section which extends from the stationary section and is capable of stretching and contracting in a first axis direction; a movable body connected to the elastic section; a movable electrode section which extends from the movable body. The concave section includes a cutout section which is provided on the wall section. The stationary section includes an overlap section which is spaced with the substrate, and overlaps the concave section when seen in a plan view. At least a portion of the overlap section overlaps the cutout section when seen in the plan view, and the elastic section extends from the overlap section. | 2015-10-22 |
20150303154 | X-RAY OBSCURATION FILM AND RELATED TECHNIQUES - An X-ray obscuration (XRO) film comprising one or more metallic wire mesh layers and an adjacent layer of indium foil having portions which extend into openings of the wire mesh and in contact with metallic portions thereof. The XRO film can be capable of absorbing at least a portion of X-ray energy thereby creating an interference pattern when the XRO film is coupled with an electronic circuit and placed between an X-ray source and an X-ray detector and subjected to radiographic inspection. The interference pattern can create sufficient visual static to effectively obscure circuit lines in the electronic circuit when subjected to radiographic inspection techniques. The XRO film can be substantially thinner than existing solutions for preventing X-ray inspection with an exemplary embodiment being no more than 5 mils thick. The metallic XRO film can also provide electromagnetic shielding and/or heat dissipation for electronic circuits. | 2015-10-22 |
20150303155 | METHOD OF PRODUCING SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE - In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole | 2015-10-22 |
20150303156 | SINGLE INLINE NO-LEAD SEMICONDUCTOR PACKAGE - Embodiments of a packaged semiconductor device with no leads are disclosed. One embodiment includes a semiconductor chip and a no leads package structure defining a boundary and having a bottom surface and includes three or more pads exposed at the bottom surface of the package structure. Each of the pads is located in a single inline row. | 2015-10-22 |
20150303157 | Bowl-shaped solder structure - An apparatus relating generally to a substrate is disclosed. In this apparatus, a first metal layer is on the substrate. The first metal layer has an opening. The opening of the first metal layer has a bottom and one or more sides extending from the bottom. A second metal layer is on the first metal layer. The first metal layer and the second metal layer provide a bowl-shaped structure. An inner surface of the bowl-shaped structure is defined responsive to the opening of the first metal layer and the second metal layer thereon. The opening of the bowl-shaped structure is configured to receive and at least partially retain a bonding material during a reflow process. | 2015-10-22 |
20150303158 | Warpage Reduction and Adhesion Improvement of Semiconductor Die Package - A method of forming a die package includes forming a conductive column over a first side of a carrier, attaching a semiconductor die to the first side of the carrier, and forming a molding compound over the first side of the carrier. The semiconductor die and the conductive column are embedded in the molding compound. A second side of the carrier opposite the first side is under a compressive stress. The method also includes forming a first compressive dielectric layer over the semiconductor die, the conductive column, and the molding compound, forming a first redistribution layer (RDL) over the first compressive dielectric layer, and forming a first passivation layer over the first RDL. | 2015-10-22 |
20150303159 | SEMICONDUCTOR DEVICE PACKAGE AND PACKAGING METHOD - A semiconductor device package and packaging method, the semiconductor device packaging method comprising: providing a chip with a bonding pad formed on the chip surface; forming a passivation layer and a bump on the chip surface, wherein the passivation layer has an opening exposing part of the pad, the bump is located in the opening and the size of the bump is less than the size of the opening; forming a solder ball covering the top surface and the side wall of the bump, and the bottom surface of the opening. The formed semiconductor device package is not easy to form a short circuit. The bonding strength between the solder ball and the bump is high and the performance of the semiconductor device is stable. | 2015-10-22 |
20150303160 | Connector Structures of Integrated Circuits - A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad. | 2015-10-22 |
20150303161 | Zero Stand-Off Bonding System and Method - A system and method for a zero stand-off configuration are provided. An embodiment comprises forming a seal layer over a conductive region that is part of a first substrate and breaching the seal with a conductive member of a second substrate in order to bond the first substrate to the second substrate. | 2015-10-22 |
20150303162 | INTEGRATED CIRCUIT CHIP AND DISPLAY APPARATUS - Provided are an IC chip and a display apparatus. The IC chip ( | 2015-10-22 |
20150303163 | UNDERFILL DISPENSING WITH CONTROLLED FILLET PROFILE - A method includes placing an underfill-shaping cover on a package component of a package, with a device die of the package extending into an opening of the underfill-shaping cover. An underfill is dispensed into the opening of the underfill-shaping cover. The underfill fills a gap between the device die and the package component through capillary. The method further includes, with the underfill-shaping cover on the package component, curing the underfill. After the curing the underfill, the underfill-shaping cover is removed from the package. | 2015-10-22 |
20150303164 | PACKAGE STRUCTURE - A package structure includes a first insulation layer, a first conductive layer, a direct bond copper substrate, and a first electronic component. A first conductive via is formed in the first insulation layer. The first conductive layer is disposed on a top surface of the first insulation layer and in contact with the first conductive via. The direct bond copper substrate includes a second conductive layer, a third conductive layer and a ceramic base. The ceramic base is disposed on a bottom surface of the first insulation layer and exposed to the first insulation layer by press-fit operation. The first electronic component is embedded within the first insulation layer and disposed on the second conductive layer. The first electronic component includes a first conducting terminal. The first conducting terminal is electrically connected with the second conductive layer and/or electrically connected with the first conductive layer through the first conductive via. | 2015-10-22 |
20150303165 | ALUMINUM ALLOY WIRE FOR BONDING APPLICATIONS - The invention is related to a bonding wire containing a core having a surface. The core contains aluminum as a main component and scandium in an amount between 0.05% and 1.0%. | 2015-10-22 |
20150303166 | SEMICONDUCTOR DEVICE - Provided is a wire bonding apparatus for electrically connecting an electrode and an aluminum alloy wire to each other by wire bonding. The apparatus includes a wire feeding device which feeds the wire. The wire has a diameter not less than 500 μm and not greater than 600 μm. The apparatus includes a heating device heats the wire to a temperature that is not lower than 50° C. and not higher than 100° C. The apparatus further includes a pressure device which presses the wire against the electrode. The apparatus further includes an ultrasonic wave generating device which generates an ultrasonic vibration that is applied to the wire that is pressed by the pressure device. | 2015-10-22 |
20150303167 | SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, AND ELECTRONIC APPARATUS - A semiconductor apparatus, including: a semiconductor component; a Cu stud bump that is formed on the semiconductor component; and a solder bump configured to electrically connect to the Cu stud bump. | 2015-10-22 |
20150303168 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME - Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit. | 2015-10-22 |
20150303169 | SYSTEMS AND METHODS FOR MULTIPLE BALL BOND STRUCTURES - A method for forming a semiconductor device includes forming a first ball bond on a first contact pad, in which the first ball bond has a first wire segment of a bonding wire extending from the ball bond; forming a mid-span ball in the first wire segment at a first distance from the ball bond; and after the forming the mid-span ball, attaching the mid-span ball to a second contact pad to form a second ball bond. | 2015-10-22 |
20150303170 | SINGULATED UNIT SUBSTRATE FOR A SEMICONDCUTOR DEVICE - A singulated substrate for a semiconductor device may include a singulated unit substrate comprising circuit patterns on a top surface and a bottom surface of the singulated unit substrate. A semiconductor die may be bonded to the top surface of the singulated unit substrate. An encapsulation layer may encapsulate the semiconductor die and cover the top surface of the singulated unit substrate. The side surfaces of the singulated unit substrate between the top surface and bottom surface of the singulated unit substrate may be coplanar with side surfaces of the encapsulation layer. The semiconductor die may be electrically coupled to the singulated unit substrate utilizing solder bumps. Solder balls may be formed on the circuit patterns on the bottom surface of the singulated unit substrate. An underfill material may be formed between the semiconductor die and the top surface of the singulated unit substrate. | 2015-10-22 |
20150303171 | SYSTEMS AND METHODS FOR CARRYING SINGULATED DEVICE PACKAGES - In accordance with embodiments of the present disclosure, a method may include providing a substrate adapted for use in wafer processing equipment, wherein the substrate includes an adhesive applied thereto. The method may also include reconstituting a plurality of device packages onto the substrate. In accordance with these and other embodiments of the present disclosure, an apparatus may include a substrate adapted for use in wafer processing equipment, an adhesive applied to the substrate, and a plurality of device packages reconstituted onto the substrate. | 2015-10-22 |
20150303172 | RECONSTITUTION TECHNIQUES FOR SEMICONDUCTOR PACKAGES - Reconstitution techniques for semiconductor packages are provided. One reconstitution technique is used to encapsulate a plurality of semiconductor packages into a single multi-chip module. Solder balls coupled to each package may be partially exposed after reconstitution, which enables the packages to be coupled to another device. Another reconstitution technique is used to couple a plurality of semiconductor packages into a package-on-package module using self-alignment feature(s). The self-alignment feature(s) are exposed solder ball(s) that are included in the bottom package of the package-on-package module. The exposed solder ball(s) serve as a frame of reference to other solder balls that are encapsulated by an encapsulation material. After the location of these other solders balls are determined, through-mold vias may be formed in the encapsulation material at locations corresponding to the other solder balls. The top package of the package-on-package module may then be coupled to the bottom package using these solder balls. | 2015-10-22 |
20150303173 | AN INTEGRATED ELECTRONIC DEVICE INCLUDING AN INTERPOSER STRUCTURE AND A METHOD FOR FABRICATING THE SAME - An integrated circuit device and a method of fabricating the same are presented. The integrated circuit device ( | 2015-10-22 |
20150303174 | Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same - An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs. | 2015-10-22 |
20150303175 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a package substrate on which a substrate pad is disposed, a structure disposed over the package substrate, a semiconductor chip disposed over the structure using an adhesive member having a magnetic material layer disposed therein, a chip pad disposed on a top surface of the semiconductor chip, and a bonding wire coupling the substrate pad and the chip pad. | 2015-10-22 |
20150303176 | MULTI-CHIP MODULES INCLUDING STACKED SEMICONDUCTOR DICE - An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first semiconductor device is disclosed. Spacers space the active surface of the first semiconductor device substantially a predetermined distance apart from the back side of the second semiconductor device. Discrete conductive elements are extended between the active surface of the first semiconductor device and the substrate prior to positioning of the second semiconductor device. Intermediate portions of the discrete conductive elements pass through an aperture formed between the active surface of the first semiconductor device, the back side of the second semiconductor device, and two of the spacers positioned therebetween. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed. | 2015-10-22 |
20150303177 | THREE-TERMINAL PRINTED DEVICES INTERCONNECTED AS CIRCUITS - A layer of microscopic, 3-terminal transistors is printed over a first conductor layer so that bottom electrodes of the transistors electrically contact the first conductor layer. A first dielectric layer overlies the first conductor layer, and a second conductor layer over the first dielectric layer contacts intermediate electrodes on the transistors between the bottom electrodes and top electrodes. A second dielectric layer overlies the second conductor layer, and a third conductor layer over the second dielectric layer contacts the top electrodes. The devices are thus electrically connected in parallel by a combination of the first conductor layer, the second conductor layer, and the third conductor layer. Separate groups of the devices may be interconnected to form more complex circuits. The resulting circuit may be a very thin flex-circuit. | 2015-10-22 |
20150303178 | CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A chip package includes a semiconductor chip, a first chip, a first connection portion, a molding layer, a metal redistribution layer and a packaging layer. The semiconductor chip includes a first conductive pad and a second conductive pad disposed on an upper surface of the semiconductor chip. The first chip is disposed on the upper surface, and the first chip has at least a first chip conductive pad. The first connection portion directly electrically connects the first chip conductive pad and the first conductive pad. The molding layer covers the upper surface, the first chip and the first connection portion, and the molding layer is formed with an opening exposing a second conductive pad. The metal redistribution layer is disposed in the opening, electrically connected to the second conductive pad and extending to the molding layer. The packaging layer covers the metal redistribution layer and the molding layer. | 2015-10-22 |
20150303179 | Light Emitting Diode Assembly With Integrated Circuit Element - An LED assembly with an ESD protection device integrated into the carrier substrate and a method for making the LED assembly is disclosed. In one embodiment, the LED assembly includes an LED in contact with a bonding layer in contact with a substrate. The substrate has a region containing a circuit element. The bonding layer forms an ohmic connection between the region containing the circuit element and the LED. In one embodiment, the region containing the circuit element is an ESD protection device, such as a Zener diode. | 2015-10-22 |
20150303180 | PHOTOCOUPLER - A photocoupler includes: a support substrate; a MOSFET; a light receiving element; a light emitting element; and a bonding layer. The support substrate includes an insulating layer, input and output terminals. The MOSFET is bonded to the support substrate. The MOSFET has a first surface having an operation region. The light receiving element includes p-n junction and is bonded to the MOSFET. The light receiving element has first and second surfaces. The first surface includes a light reception region, a first electrode, and a second electrode. The light emitting element is connected to the input terminal. The light emitting element has first and second surfaces. The first surface includes first and second electrodes. The second surface has a light emitting region. The bonding layer is configured to bond the light emitting element to the light reception region. | 2015-10-22 |
20150303181 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second semiconductor chip being adjacent to the first semiconductor chip, and a thermal expansion reinforcing pattern disposed over a second surface of the interposer. | 2015-10-22 |
20150303182 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes: a MOSFET having a gate electrode formed via a gate insulating film over a semiconductor layer and source and drain regions formed in the semiconductor layer on both sides of the gate electrode; and a diode. The diode has an n | 2015-10-22 |
20150303183 | METHOD OF MANUFACTURING FIN DIODE STRUCTURE - A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type. | 2015-10-22 |
20150303184 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device and a fabrication method for the semiconductor device are provided in which an increase of a forward loss is suppressed and a reverse recovery loss is reduced. | 2015-10-22 |
20150303185 | Low-Cost Complementary BiCMOS Integration Scheme - A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a first CMOS well in the CMOS region, an NPN bipolar device in a bipolar region, a second CMOS well in the bipolar region, the second CMOS well being a collector sinker and being electrically connected to a sub-collector of the NPN bipolar device, where the first CMOS well in the CMOS region and the second CMOS well in the bipolar region form a p-n junction to provide electrical isolation between the CMOS device and the NPN bipolar device. The BiCMOS device further includes a PNP bipolar device having a sub-collector, the sub-collector of the PNP bipolar device being electrically connected to a third CMOS well. | 2015-10-22 |
20150303186 | Efficient Fabrication of BiCMOS Devices - A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and a spacer clear region defined by an opening in a common spacer layer over the CMOS region and the bipolar region, wherein a sub-collector, a selectively implanted collector, and a base of the PNP bipolar device are formed in the spacer clear region. The PNP bipolar device further includes a collector sinker adjacent to the spacer clear region and electrically connected to the sub-collector of the PNP bipolar device. The BiCMOS device can further include an NPN bipolar device having a sub-collector, a selectively implanted collector and a base in another spacer clear region. | 2015-10-22 |
20150303187 | BiCMOS Integration Using a Shared SiGe Layer - A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and an NPN bipolar device in the bipolar region. The BiCMOS device includes also includes a silicon-germanium (SiGe) layer over a base of the PNP bipolar device and over a selectively implanted collector of the NPN bipolar device, wherein a first portion of the SiGe layer forms a base of the NPN bipolar device, and a second portion of the SiGe layer forms an emitter of the PNP bipolar device. | 2015-10-22 |
20150303188 | BiCMOS Integration with Reduced Masking Steps - A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and an NPN bipolar device in the bipolar region. The NPN bipolar device has an extrinsic base being self-aligned with an emitter of the NPN bipolar device. The extrinsic base of the NPN bipolar device and an emitter of the PNP bipolar device share a P type dopant. | 2015-10-22 |
20150303189 | SEMICONDUCTOR DEVICE - A semiconductor device which uses a fin-type semiconductor layer to form a bipolar transistor. The substrate of the device is a semiconductor substrate. A collector is a first-conductivity type impurity region which is formed in the semiconductor substrate. A base is a second-conductivity type impurity region which is formed in the surface layer of the collector. A first semiconductor layer is a fin-type semiconductor layer which lies over the base. An emitter is formed in the first semiconductor layer and its bottom is coupled to the base. A first contact is coupled to the collector, a second contact is coupled to the base, and a third contact is coupled to the emitter. | 2015-10-22 |
20150303190 | Semiconductor Device Having an Insulated Gate Bipolar Transistor Arrangement and a Method for Forming Such a Semiconductor Device - A semiconductor device includes an insulated gate bipolar transistor (IGBT) arrangement. The IGBT arrangement includes a carrier confinement reduction region laterally arranged between a cell region and a sensitive region. The IGBT arrangement is configured or formed so that the cell region has a first average density of free charge carriers in an on-state of the IGBT arrangement, the carrier confinement reduction region has a second average density of free charge carriers in the on-state of the IGBT arrangement and the sensitive region has a third average density of free charge carriers in the on-state of the IGBT arrangement. The first average density of free charge carriers is larger than the second average density of free charge carriers and the second average density of free charge carriers is larger than the third average density of free charge carriers. | 2015-10-22 |
20150303191 | PRECISION TRENCH CAPACITOR - A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection. | 2015-10-22 |
20150303192 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same, wherein an example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer to form an initial fin; performing anisotropic etching on the first semiconductor layer to form a Σ-shaped lateral recess therein; forming an isolation layer on the substrate to have a portion that fills the lateral recess, wherein the isolation layer, except the portion that fills the lateral recess, has a top surface located between a top surface and a bottom surface of the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer. | 2015-10-22 |
20150303193 | INTEGRATED CIRCUIT AND RELATED MANUFACTURING METHOD - A method for manufacturing an integrated circuit may include the following steps: forming a first transistor, which includes a first active region; forming a second transistor, which includes a second active region; forming a third transistor, which includes a gate electrode that overlaps each of the first active region and the second active region; and providing a predetermined voltage to the gate electrode for turning off the third transistor to isolate the first transistor from the second transistor. | 2015-10-22 |
20150303194 | FINFET SEMICONDUCTOR DEVICES INCLUDING DUMMY STRUCTURES - Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure. | 2015-10-22 |
20150303195 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device includes first and second fin-shaped semiconductor layers on a substrate, where the first and second fin-shaped semiconductor layers correspond to the dimension of a sidewall pattern around a dummy pattern. First and second pillar-shaped semiconductor layers reside on the first and second fin-shaped semiconductor layers, respectively. A gate insulating film and metal gate electrode are around underlying gate insulating layers on each fin-shaped semiconductor layer. A metal gate line is connected to the metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped semiconductor layers. Contacts reside on the upper portion of diffusion layers in upper portions of the first and second pillar-shaped semiconductor layers and are directly connected to the diffusion layers. | 2015-10-22 |
20150303196 | FINFET CELL ARCHITECTURE WITH POWER TRACES - A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions. | 2015-10-22 |
20150303197 | Semiconductor Device and Fabricating the Same - An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature. | 2015-10-22 |
20150303198 | METHOD AND STRUCTURE FOR FINFET DEVICE - The present disclosure provides a method for fabricating a fin-like field-effect transistor (FinFET). The method includes forming a first fin structures over a substrate, forming a patterned oxidation-hard-mask (OHM) over the substrate to expose the first fin structure in a first gate region of a n-type FET region, forming a semiconductor oxide feature in a middle portion of the first fin structure in the first gate region, forming a second fin structure in a PFET region, forming dummy gates, forming source/drain (S/D) features, replacing the dummy gates by a first high-k/metal gate (HK/MG) in the NFET region and a second HK/MG in the PFET region. | 2015-10-22 |
20150303199 | MEMORY STRUCTRUE AND OPERATION METHOD THEREOF - This invention provides a memory structure and an operation method thereof. The memory structure includes a triode for alternating current (TRIAC) and a memory cell. The memory cell is electrically connected to the TRIAC. | 2015-10-22 |
20150303200 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device comprising: a silicon substrate; an embedded gate electrode groove provided in the silicon substrate; a gate insulating film provided on the wall inside the embedded gate electrode groove; an embedded gate electrode provided on the gate insulating film so as to be installed inside the embedded gate electrode groove, the embedded gate electrode, having a first portion having a titanium nitride film and a first metal film thereon, and a second portion having a single-layer titanium nitride film; and a contact plug electrically connected to the first metal film constituting the first portion of the embedded gate electrode. | 2015-10-22 |
20150303201 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Semiconductor devices, and methods for forming the same, include forming a first wiring film and an etching buffer film in a cell array region and a peripheral circuit region of a substrate, and forming a contact hole by selectively etching the etching buffer film and the first wiring film so as to expose an active region of the cell array region and at least a part of a field isolation region adjacent thereto. A bit line contact is formed in the contact hole to be in contact with the active region, and a second wiring film is formed over the substrate. By patterning the second wiring film, the bit line contact, the etching buffer film, and the first wiring film, a bit line is formed in the cell array region and a peripheral gate is formed in the peripheral circuit region. | 2015-10-22 |
20150303202 | SEMICONDUCTOR DEVICES HAVING VERTICAL DEVICE AND NON-VERTICAL DEVICE AND METHODS OF FORMING THE SAME - A semiconductor device comprises a substrate extending in a horizontal direction and a vertical transistor on the substrate. The vertical transistor comprises: a first diffusion region on the substrate; a channel region on the first diffusion region and extending in a vertical direction relative to the horizontal direction of the extension of the substrate; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region. A portion of a gate electrode of the vertical transistor and a portion of the gate electrode of the horizontal transistor are at a same vertical position in the vertical direction relative to the substrate. | 2015-10-22 |
20150303203 | NONVOLATILE MEMORY DEVICE HAVING SINGLE-LAYER GATE, METHOD OF OPERATING THE SAME, AND MEMORY CELL ARRAY THEREOF - A nonvolatile memory device includes a single-layer gate, a first area, and a second area. The first area includes a first well region, a first contact region arranged in the first well region, and source and drain regions arranged at both sides of the single-layer gate in the first well region. The second area includes a second well region, a second contact region arranged to overlap a part of the single-layer gate in the second well region, and a third contact region arranged in the second well region. | 2015-10-22 |
20150303204 | NONVOLATILE MEMORY DEVICES HAVING CHARGE TRAPPING LAYERS AND METHODS OF FABRICATING THE SAME - A nonvolatile memory device includes a substrate having a first charge trap region, a second charge trap region, and a selection region between the first and second charge trap regions. A well region is disposed in the substrate. A source region and a drain region are disposed in the well region. A gate structure is disposed on a channel region between the source region and the drain region. The gate structure includes: a first tunneling layer, a first charge trap layer, a first blocking layer and a first conductive layer stacked in the first charge trap region; a second tunneling layer, a second charge trap layer, a second blocking layer and a second conductive layer stacked in the second charge trap region; and a first insulation layer, a second insulation layer, a third insulation layer and a third conductive layer stacked in the selection region. | 2015-10-22 |
20150303205 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device with a nonvolatile memory is provided which has improved electric performance. A memory gate electrode is formed over a semiconductor substrate via an insulating film. The insulating film is an insulating film having a charge storage portion therein, and includes a first silicon oxide film, a silicon nitride film over the first silicon oxide film, and a second silicon oxide film over the silicon nitride film. Metal elements exist between the silicon nitride film and the second silicon oxide film, or in the silicon nitride film at a surface density of 1×10 | 2015-10-22 |
20150303206 | Methods Of Forming Ferroelectric Capacitors - A method of forming a ferroelectric capacitor includes forming inner conductive capacitor electrode material over a substrate. After forming the inner electrode material, an outermost region of the inner electrode material is treated to increase carbon content in the outermost region from what it was prior to the treating. After the treating, ferroelectric capacitor dielectric material is formed over the treated outermost region of the inner electrode material. Outer conductive capacitor electrode material is formed over the ferroelectric capacitor dielectric material. | 2015-10-22 |
20150303207 | MANUFACTURING METHOD FOR SEMI-FLOATING GATE DEVICE - A manufacturing method for a semi-floating gate device, mainly comprising a manufacturing method for a floating gate and a floating gate opening area, and the specific process thereof is: reserving a hard mask layer after a U-shaped groove is formed, growing a gate dielectric layer on a surface of the formed U-shaped groove, depositing and etching back a first layer of polysilicon to protect the gate dielectric layer, etching away the exposed gate dielectric layer and hard mask layer, then covering a formed structure to deposit a second layer of polysilicon, then etching a formed polysilicon layer by a photoetching process and an etching process so as to form a floating gate, and forming a floating gate opening area in a self-aligning way. The manufacturing method can simplify the existing manufacturing process for a semi-floating gate device, reduce the difficulty in manufacturing the semi-floating gate device with a U-shaped channel, and improve the yield of the semi-floating-gate device. | 2015-10-22 |
20150303208 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a first active region and a second active region separated from each other; a floating gate crossing the first active region, and disposed such that an end thereof overlaps with the second active region; a selection gate crossing the first active region, and disposed side by side with and coupled to the floating gate; a dielectric layer disposed between the floating gate and the selection gate, wherein a stack of the dielectric layer, the floating gate and the selection gate forms a first capacitor in a horizontal structure; a well region disposed in the second active region and coupled to the floating gate, wherein a stack of the well region and the floating gate forms a second capacitor in a vertical structure; and a contact commonly coupled to the well region and the selection gate. | 2015-10-22 |