| 42nd week of 2021 patent applcation highlights part 60 |
| Patent application number | Title | Published |
|---|
| 20210327461 | MAGNETIC DISK DEVICE - According to one embodiment, a magnetic disk includes a disk, first and second heads which write data to the disk and read data from the disk, a first actuator includes the first head, a second actuator includes the second head, first and second controllers which control the first head, the second head, the first actuator and the second actuator, an auxiliary power supply which supplies power when power from a power supply is shut off, and a power supply detection unit which makes power supplied from the auxiliary power supply to the first controller higher than the power supplied from the auxiliary power supply to the second controller when shutoff of power from the power supply is detected. | 2021-10-21 |
| 20210327462 | DATA STORAGE DEVICES WITH INTEGRATED SLIDER VOLTAGE POTENTIAL CONTROL - Disclosed herein is a data storage device comprising a slider comprising an embedded contact sensor, an electronics module, and a plurality of lines disposed between and coupled to the slider and the electronics module, wherein at least one line of the plurality of lines is configured to both (a) couple a slider bias voltage to a body of the slider to control a potential of the slider, and (b) provide a signal to the embedded contact sensor. The slider may also include a shunt circuit for mitigating radio-frequency interference by shunting it to ground. The slider may include a write element, which may include a write-field enhancement structure. The slider may include a read element for reading from a recording media. | 2021-10-21 |
| 20210327463 | WAVEGUIDE WITH OPTICAL ISOLATOR FOR HEAT-ASSISTED MAGNETIC RECORDING - An apparatus includes a substrate. A laser is formed on a non-self supporting structure and bonded to the substrate. A waveguide having a gap portion is deposited proximate the laser. The waveguide is configured to communicate light from the laser to a near-field transducer (NFT) that directs energy resulting from plasmonic excitation to a recording medium. An optical isolator is disposed over the gap portion. | 2021-10-21 |
| 20210327464 | MAGNETIC-DISK SUBSTRATE AND MAGNETIC DISK - A magnetic-disk substrate has an average value of squares of inclinations that is 0.0025 or less, and a frequency at which squares of inclinations are 0.004 or more is 15% or less, in a case where samples of inclinations on a main surface are obtained at intervals of 10 nm. The main surface is configured to receive at least a magnetic recording layer thereon. The magnetic-disk substrate includes an outer circumferential end portion and an inner circumferential end portion, and the outer circumferential end portion and the inner circumferential end portion have chamfered portions. | 2021-10-21 |
| 20210327465 | OPTICAL DISK REPRODUCING DEVICE - An optical disk reproducing device includes a division element that divides a reflected light reflected and diffracted by an optical disk into a light flux in a central region and light fluxes in end regions; a photodetector that has a central light receiver that receives the light flux in the central region and at least two end light receivers that receive the light fluxes in the end regions, and outputs a light amount signal corresponding to a light amount of each of the received light fluxes; a non-linear processor that receives each of the light amount signals from the central light receiver and the end light receivers, and outputs linear signals and non-linear signals obtained by processing the light amount signals by linear and non-linear arithmetic operations; an equalization processor that receives the linear signals and the non-linear signals and outputs signals each amplified with a predetermined gain; an adder that adds the amplified signals and outputs an equalization signal; a reproduction signal processor that processes the equalization signal and outputs a reproduction signal and an equalization error signal; and a gain controller that receives the equalization error signal and controls an amplification gain of the non-linear signals. | 2021-10-21 |
| 20210327466 | OPTICAL DISK, METHOD OF MANUFACTURING SAME, OPTICAL INFORMATION DEVICE, AND INFORMATION PROCESSING METHOD - Provided is a method of manufacturing an optical disk having at least a cover layer, a first information recording surface, a first intermediate layer, a second information recording surface, a second intermediate layer, and a third information recording surface in order from a surface irradiated with a light beam on at least one side, wherein a numerical aperture of an objective lens that converges the light beam on any of the recording surface of the optical disk when information recording or information reproduction of the optical disk is performed is 0.91, standard value dk of each thickness from the surface to the first to third information recording surfaces is set on the premise of standard refractive index no, where k is 1, 2, 3, and a target value of each actual thickness from the surface to the first to third information recording surfaces is determined by a product of conversion coefficient g(n) depending on refractive index n from the first to third information recording surfaces, and standard value dk. | 2021-10-21 |
| 20210327467 | Management of Media Content Playback - Example techniques may involve managing playback of media content by a playback device. In an example implementation, a playback device receives, via the network interface from a control device of the media playback system, an instruction to queue a container of audio tracks into a queue for playback by the playback device, wherein the container of audio tracks and consists of: (a) an album, (b) a playlist, or (c) an internet radio station. While the playback device is playing back the queue and before each audio track of the playlist is played back, the playback device determines whether the respective audio track is associated with a negative preference. If the respective audio track is associated with the negative preference, the playback device advances playback over the respective audio track to the next audio track within the queue. | 2021-10-21 |
| 20210327468 | MAGNETIC DISK DEVICE, WRITING METHOD OF SERVO SECTOR, AND METHOD OF CORRECTING SERVO DEMODULATION POSITION - According to one embodiment, a magnetic disk device includes a disk including two first servo sectors and at least a second servo sector, a head, and a controller, wherein the first servo sector includes burst data and a first data pattern written before the circumferential direction of the burst data, the second servo sector includes the burst data, the first data pattern, and a second data pattern written after the circumferential direction of the burst data, a first frequency of the first data pattern is different from a second frequency of the second data pattern, and a first length of the first data pattern is different from a second length of the second data pattern. | 2021-10-21 |
| 20210327469 | MAGNETIC DISK DEVICE, WRITING METHOD OF SERVO SECTOR, AND METHOD OF CORRECTING SERVO DEMODULATION POSITION - According to one embodiment, a magnetic disk device includes a disk including two first servo sectors and at least a second servo sector, a head, and a controller, wherein the first servo sector includes burst data and a first data pattern written before the circumferential direction of the burst data, the second servo sector includes the burst data, the first data pattern, and a second data pattern written after the circumferential direction of the burst data, a first frequency of the first data pattern is different from a second frequency of the second data pattern, and a first length of the first data pattern is different from a second length of the second data pattern. | 2021-10-21 |
| 20210327470 | METHOD, APPARATUS AND COMPUTER PROGRAM - A method of providing edited media content is described. The method comprises: generating captured content and a representation of the captured content, the representation of the captured content having a smaller size than the captured content; providing the captured content over a first network path across a network and the representation of the captured content over a second network path across the network, the first network path having a higher latency than the second network path; generating an edited version of the received representation of the captured content; and providing an edited version of the captured content, the editing of the captured content being based on the editing of the representation of the captured content. | 2021-10-21 |
| 20210327471 | SYSTEM AND METHOD OF DYNAMIC RANDOM ACCESS RENDERING - A system is provided for dynamic random access rendering of media content. The system includes a rendering tool that loads a recipe having a reference to input essence and an instruction that collectively generates an output essence using the at least one input essence. The system further includes a render engine that execute the instruction and includes a file format parser configured to load the input essence from a file of media content. The render engine also includes plugin having a web server embedded therein that is communicatively coupled with a TCP port for receiving a request from a client device for the output essence. The render engine generates the output essence from the input essence in accordance with the instruction in the recipe and transmits the generated output essence to the client device for display thereon. | 2021-10-21 |
| 20210327472 | ELASTIC CLOUD VIDEO EDITING AND MULTIMEDIA SEARCH - Technologies for cloud-based media search and editing include a video editor configured to build a media query and associate the media query with a dynamic content slot of a media program. When generating video output based on the media program, the video editor transmits the media query to a cloud analytics server and receives search results identifying one or more media clips produced by a number of mobile computing devices. The video editor may display a list of clips for selection by the user or may automatically include one of the clips in the output. The cloud analytics server transmits an acceptance policy defining criteria for acceptable media, based on the media query, to the mobile computing devices. The mobile computing devices configure capture settings according to the acceptance policy and may display a user interface to assist the user in capturing acceptable media. Other embodiments are described and claimed. | 2021-10-21 |
| 20210327473 | TOP COVER SPRING DESIGNS - A hard disk drive includes a base, a cover coupled to the base to create an enclosure, and a voice coil motor assembly that is positioned within the enclosure. The cover includes a spring positioned adjacent to the voice coil motor assembly to dampen vibration of the voice coil motor assembly. | 2021-10-21 |
| 20210327474 | CIRCUITS AND METHODS FOR IN-MEMORY COMPUTING - In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as “C3SRAM”) is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments. With one analog-to-digital converter (ADC) per column, the macro cab realize fully parallel vector-matrix multiplication in a single cycle in accordance with some embodiments. | 2021-10-21 |
| 20210327475 | Configuring a Host Interface of a Memory Device Based on Mode of Operation - A memory device stores data for a host device. In one approach, a method includes: selecting, by the memory device, a first mode of operation for a host interface that implements a communication protocol for communications between the memory device and the host device. The host interface is configured to implement the communication protocol using a mode selected by the memory device from one of several available modes. In response to selecting the first mode, resources of the memory device are configured to customize the host interface for operation in the first mode. | 2021-10-21 |
| 20210327476 | MEMORY DEVICE, MEMORY SYSTEM, AND OPERATION METHOD OF MEMORY DEVICE - A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device. | 2021-10-21 |
| 20210327477 | LOW STANDBY POWER WITH FAST TURN ON METHOD FOR NON-VOLATILE MEMORY DEVICES - Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode. | 2021-10-21 |
| 20210327478 | SYSTEM FOR PERFORMING PHASE MATCHING OPERATION - A system for performing a phase matching operation includes a controller configured to output a clock, a command, and a strobe signal, and to input/output data. The system also includes a semiconductor device configured to generate an internal strobe signal by matching the phases of the command and the strobe signal according to the clock, and to input/output the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path to which the command is inputted and a delay amount of a second path to which the strobe signal is inputted. | 2021-10-21 |
| 20210327479 | SYSTEMS FOR PERFORMING A READ-MODIFY-WRITE OPERATION - A semiconductor memory device includes a read/write control circuit and an error correction circuit. The read/write control circuit generates an internal write signal after generating an internal read signal from one of a plurality of shifted signals which are generated by shifting a read-modify-write command according to a frequency of a clock signal. The error correction circuit corrects an error included in internal data by performing a logical operation of read data generated by the internal read signal and the internal data to generate write data. The internal read signal is enabled by a write set signal during the read-modify-write operation. | 2021-10-21 |
| 20210327480 | SEMICONDUCTOR DEVICE INCLUDING INPUT/OUTPUT PAD - A memory device includes a data pad disposed in a first pad area and configured to receive data, a data strobe pad disposed in the first pad area and configured to receive a data strobe signal, a clock pad disposed in a second pad area adjacent to the first pad area and configured to receive a clock signal, a data conversion circuit disposed in the first pad area and configured to convert the data inputted through the data pad into parallel data based on the data strobe signal, and a data driving circuit disposed in the first pad area and configured to transmit the parallel data through a global input and output line based on the clock signal. | 2021-10-21 |
| 20210327481 | SEMICONDUCTOR STORING APPARATUS AND READOUT METHOD - A semiconductor storing apparatus capable of performing continuous readout between multiple chips in high speed is provided. A NAND-type flash memory includes the stacked multiple chips. Each of the chips includes: a readout part performing the continuous readout; an output buffer part outputting data readout from the readout part to input/output bus synchronously with a clock signal; and a final page detecting part detecting if readout pages are the final pages of the chips. The output buffer part responds to a detecting result of the final pages under a condition of performing the continuous readout between the chips. After outputting the data of the final pages through a first output buffer with a large driving capability, outputs or holds the data of the final pages through a second output buffer with a little driving capability. | 2021-10-21 |
| 20210327482 | MEMORY DEVICE - A memory device includes a first substrate, a first memory array, a second substrate, and at least one first vertical transistor. The first memory array is disposed on the first substrate. The first memory array includes at least one first word line structure. The first memory array is disposed between the first substrate and the second substrate in a vertical direction. The first vertical transistor is electrically connected with the first word line structure. At least a part of the at least one first vertical transistor is disposed in the second substrate. | 2021-10-21 |
| 20210327483 | TUNNELING METAMAGNETIC RESISTANCE MEMORY DEVICE AND METHODS OF OPERATING THE SAME - A magnetoresistive memory device includes a first electrode, a second electrode, and a layer stack located between the first electrode and the second electrode. The layer stack may include a ferroelectric material layer and a metamagnetic tunnel junction containing a metamagnetic material layer, an insulating barrier layer, and a metallic material layer. Alternatively, the layer stack may include a multiferroic material layer, the metamagnetic material layer, the insulating barrier layer, and a reference magnetization layer. | 2021-10-21 |
| 20210327484 | TUNNELING METAMAGNETIC RESISTANCE MEMORY DEVICE AND METHODS OF OPERATING THE SAME - A magnetoresistive memory device includes a first electrode, a second electrode, and a layer stack located between the first electrode and the second electrode. The layer stack may include a ferroelectric material layer and a metamagnetic tunnel junction containing a metamagnetic material layer, an insulating barrier layer, and a metallic material layer. Alternatively, the layer stack may include a multiferroic material layer, the metamagnetic material layer, the insulating barrier layer, and a reference magnetization layer. | 2021-10-21 |
| 20210327485 | SPINTRONICS DEVICE, MAGNETIC MEMORY, AND ELECTRONIC APPARATUS - Provided are a spintronics device, a magnetic memory, and an electronics device capable of generating a large spin current without depending on a specific material. A spintronics device includes a first conductive layer, a second conductive layer having carrier mobility or electrical conductivity lower than that of the first conductive layer, and a boundary region between the conductive layers. The boundary region has a gradient of carrier mobility or electrical conductivity, and a spin current is generated by rotation of a velocity field of an electron caused by the gradient. | 2021-10-21 |
| 20210327486 | Multistate magnetic memory element using metamagnetic materials - A metamagnetic tunneling-based spin valve device for multistate magnetic memory comprising an electronic memory logic element with four stable resistance states. A metamagnetic tunneling-based spin valve device for multistate magnetic memory comprising a layer of a metamagnetic material, a layer of a nonmagnetic material on the layer of a metamagnetic material, and a layer of a ferromagnetic material on the layer of a nonmagnetic material. A method of making a metamagnetic tunneling-based spin valve device for multistate magnetic memory. | 2021-10-21 |
| 20210327487 | SENSING SCHEME FOR STT-MRAM USING LOW-BARRIER NANOMAGNETS - The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin. | 2021-10-21 |
| 20210327488 | TECHNIQUES FOR ADJUSTING CURRENT BASED ON OPERATING PARAMETERS - Methods, systems, and devices for techniques for adjusting current based on operating parameters are described. An apparatus may include an amplifier, a feedback component, and first and second current generators. The amplifier may include an input for receiving a first voltage and an output for outputting a second voltage. The first current generator may be coupled with the output of the amplifier and generate a first current based at least in part on the second voltage. The feedback component may be coupled with the first current generator to modify the first current based at least in part on an operating temperature associated with a memory device. The first current may be proportional to the operating temperature. The second current generator may be coupled with the first current generator to generate a second current based at least in part on the first current modified by the feedback component. | 2021-10-21 |
| 20210327489 | MEMORY MODULES AND STACKED MEMORY DEVICES - A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. Each semiconductor memory device includes a memory cell array to store data. The control device receives a command and an access address from an external device and provides the command and the access address to the semiconductor memory devices. Each semiconductor memory device performs an address swapping operation to randomly swap a portion of bits of the access address to generate a swapped address in response to a power-up signal or a reset signal, and enables a respective target word-line from among word-lines in the memory cell array such that two or more of the semiconductor memory devices enable different target word-lines in response to the access address. | 2021-10-21 |
| 20210327490 | APPARATUSES AND METHODS FOR PROVIDING MAIN WORD LINE SIGNAL WITH DYNAMIC WELL - A main word driver may be coupled to a subword driver to drive a main word line to select the subword driver. The main word driver may include a first transistor having a body and source/drain both coupled to a well. The main word driver may include a well control circuit configured to bias the well. In some examples, the well control circuit may provide a first low potential to the well followed by a second low potential lower than the first potential responsive to a precharge command. The main word driver may include a second transistor coupled to the well control circuit to receive the first and second low potentials and couple the first and second low potentials to the main word line. The body of the second transistor may be coupled to the well. Additional transistors in the main word driver may also be coupled to the well. | 2021-10-21 |
| 20210327491 | COLUMN SELECT SWIZZLE - A memory device includes a memory array having a plurality of memory cells and a column decoder circuit that is configured to provide at least one column select signal for selecting corresponding bit-lines for memory operations on the plurality of memory cells. The memory device also includes a column select section that is configured to route the at least one column select signal such that non-adjacent bit-lines are exclusively selected during a same column select access memory operation. | 2021-10-21 |
| 20210327492 | DATA EDGE JUMPING METHOD - The invention relates to a data edge jumping method, applied to a memory system, wherein the memory system comprises a processor and a memory driven by the processor, and a plurality of groups of data lines are connected between the processor and the memory. The data edge jumping method comprising: coding data output by the processor to enable total current produced by data transmission through each of the plurality of groups of data lines at the same time to be zero; transmitting the coded data through the plurality of groups of data cables, and decoding the data before reaching the memory; and inputting the decoded data into the memory, and enabling the total current produced in the data lines to be close to 0 A, so that electromagnetic interference is hardly produced by signals transmitted through the data lines, and allowance of signal radiation is large enough. | 2021-10-21 |
| 20210327493 | DEVICES FOR PERFORMING A REFRESH OPERATION BASED ON POWER CONTROL OPERATION - A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank. | 2021-10-21 |
| 20210327494 | HARDWARE-ASSISTED DYNAMIC RANDOM ACCESS MEMORY (DRAM) ROW MERGING - Hardware-assisted Dynamic Random Access Memory (DRAM) row merging, including: identifying, by a memory controller, in a DRAM module, a plurality of rows storing identical data; storing, in a mapping table, data mapping one or more rows of the plurality of rows to another row; and excluding the one or more rows from a refresh the DRAM module. | 2021-10-21 |
| 20210327495 | IN-MEMORY COMPUTING USING A STATIC RANDOM-ACCESS MEMORY (SRAM) - The present disclosure relates to in-memory computing using a static random access memory (SRAM). In particular, the present disclosure relates to a structure including a memory configured to store a first word and a second word, the memory further includes a configurable data path circuit, and the configured data path circuit is configured to perform an arithmetic logical operation based on the first word and the second word in parallel. | 2021-10-21 |
| 20210327496 | Adiabatic Flip-Flop and Memory Cell Design - In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time T | 2021-10-21 |
| 20210327497 | SRAM ARRAY - SRAM arrays are provided. Each SRAM cell is arranged in the same column of a cell array and includes a first transistor formed in a P-type well region of a substrate. The first transistor includes an active region formed by a Si-content fin. Each well strap cell is arranged on one of the columns in the cell array and includes a P-well strap structure formed on the P-type well region and configured to connect a VSS line to the P-type well region. The P-well strap structure includes an active region formed by a fin. In the P-type well region of two adjacent columns of the cell array, a first fin-to-fin distance between the fins of the P-well strap structures of two adjacent well strap cells is less than a second fin-to-fin distance between the Si-content fins of the first transistors of two adjacent SRAM cells. | 2021-10-21 |
| 20210327498 | DIFFERENTIAL WRITE OPERATION - Methods, systems, and devices for a differential write operation are described. The operations described herein may be used to alter a portion of a program file from a first state to a second state. For example, a file (e.g., a patch file) that is associated with a signature may be received at a memory device. Based on an authentication process, the file may be used to alter the program file to the second state. In some examples, the program file may be altered to the second state using a buffer of the memory device. A host system may transmit a file that includes the difference between the first state and the second state. A signature may be associated with the file and may be used to authenticate the file. | 2021-10-21 |
| 20210327499 | Word Line Pulse Width Control Circuit in Static Random Access Memory - Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. A control circuit includes a first transistor, an inverter coupled to the first transistor, and a second transistor comprising a gate, a first source/drain terminal and a second source/drain terminal. The second transistor is coupled to the inverter. The first source/drain terminal of the second transistor is coupled in series to the first transistor. The second source/drain terminal is coupled to a decoder driver circuit. The second transistor is configured to charge a load of a common decoder line so as to reduce an effective load of the decoder driver circuit. | 2021-10-21 |
| 20210327500 | TIME-INTERLEAVING SENSING SCHEME FOR PSEUDO DUAL-PORT MEMORY - The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal. | 2021-10-21 |
| 20210327501 | LOWER POWER MEMORY WRITE OPERATION - A static random access memory (SRAM) architecture includes a first column of SRAM cells coupled between a first bit line and a first complementary bit line, and first write circuit for the first column. The first write circuit includes a first latch receiving first input data and providing complementary outputs to the first bit line and the first complementary bit line. The first write circuit has a latchable output state driving the first bit line and first complementary bit line, and the latchable output state does not change between consecutive write operations if a state of the received first input data does not change between the consecutive write operations, but does change between the consecutive write operations if the state of the received first input data changes between the consecutive write operations. | 2021-10-21 |
| 20210327502 | ANALOG COMPUTING ARCHITECTURE FOR FOUR TERMINAL MEMORY DEVICES - A multiterminal non-volatile memory cross-bar array system includes a set of conductive row rails, a set of conductive column rails configured to form a plurality of crosspoints at intersections between the conductive rails and the conductive column rails and a resistive processing unit at each of the crosspoints each representing a neuron in a neural network. At least one given conductive row rail includes first and second row lines is in contact with a given resistive processing unit. At least one given conductive column rail including first and second column lines is in contact with the given resistive processing unit. | 2021-10-21 |
| 20210327503 | NON-VOLATILE MEMORY DEVICE WITH CONCURRENT BANK OPERATIONS - An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. | 2021-10-21 |
| 20210327504 | Multi-Level Cell Programming Using Optimized Multiphase Mapping with Balanced Gray Code - Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code. | 2021-10-21 |
| 20210327505 | COMPUTING ARRAY BASED ON 1T1R DEVICE, OPERATION CIRCUITS AND OPERATING METHODS THEREOF - The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes. | 2021-10-21 |
| 20210327506 | MECHANISM AND OPTICAL SYSTEM FOR OPTICAL-MEDIUM STORAGE - An optical mechanism and an optical system for optical-medium storage. The mechanism includes an optical-medium storage device, and an optical-medium transmission device. The optical-medium storage device is provided with an optical-medium storage module, configured to store an optical medium, and an optical-medium input-output end, configured to receive and transmit the optical medium to the optical-medium storage module and read data from the optical-medium storage module. The optical-medium receiving module is configured to receive the optical medium transmitted from outside and transmit the optical medium to the optical-medium storage module via the optical-medium input-output end, according to a receiving instruction. The optical-medium storing module is configured to form a storage path for the optical medium with the optical-medium storage module. The optical-medium reading module is configured to provide an interface for reading and read the optical medium stored in the optical-medium storage module, according to a reading instruction. | 2021-10-21 |
| 20210327507 | METHOD OF SEARCHING THROUGH TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) AND SYSTEM THEREOF - Present disclosure relates to a method and a system for searching through a Ternary Content Addressable Memory (TCAM). The system comprises a Digital Light Processing System (DLP) receiving an input query. The DLP comprises a 2-Dimensional array of digital micro mirrors configured for reflecting light from one or more input sources in the TCAM to a predefined position. The system further comprises a detection screen having a detection area. The detection area is configured for generating an image of a resultant pixel according to the reflection of the light, wherein the resultant pixel corresponds to a search result for an input query. | 2021-10-21 |
| 20210327508 | METHODS AND SYSTEMS FOR AN ANALOG CAM WITH FUZZY SEARCH - Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled. | 2021-10-21 |
| 20210327509 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device includes a cell string with a plurality of selection transistors, a plurality of dummy transistors and a plurality of memory cell transistors coupled in series therein and a pass transistor (TR) unit with a plurality of pass transistors that transmit a plurality of driving signals to the cell string. The pass TR unit includes a plurality of first pass transistors transmitting a first driving signal with a first level voltage, among the plurality of driving signals, to the plurality of selection transistors, respectively, and a plurality of second pass transistors transmitting a second driving signal with a second level voltage that is higher than the first level voltage, among the plurality of driving signals, to a plurality of dummy transistors, respectively. Each of the second pass transistors has a larger channel area than each of the first pass transistors. | 2021-10-21 |
| 20210327510 | THREE-DIMENSIONAL FLASH MEMORY INCLUDING MIDDLE METALLIZATION LAYER AND MANUFACTURING METHOD THEREOF - A three-dimensional flash memory including an intermediate wiring layer and a method of manufacturing the same are disclosed. According to an embodiment, a method of manufacturing a three-dimensional flash memory by using a back end process includes: forming a lower string in a first block, the first block including a sacrificial layer and an insulation layer which are formed to extend in a first direction and are alternately stacked; generating an inter-string insulation layer on the first block that has the lower string formed therein; etching at least a portion of the inter-string insulation layer to form at least one sacrificial film in a space where the at least a portion is etched; generating a second block on the inter-string insulation layer, where the at least one sacrificial film is formed, the second block including a sacrificial layer and an insulation layer which are formed to extend in the first direction and are alternately stacked; forming an upper string in the second block; etching the sacrificial layer included in the first block, the at least one sacrificial film, and the sacrificial layer included in the second block; and forming an electrode layer, which is to be used as at least one intermediate wiring layer, in a space where the at least one sacrificial film is etched, and an electrode layer, which is to be used as a word line, in a space where the sacrificial layer included in the first block is etched and a space where the sacrificial layer included in the second block is etched. | 2021-10-21 |
| 20210327511 | 3D NAND FLASH AND OPERATION METHOD THEREOF - A programming method of an increment step pulse program (ISPP) for a three-dimension (3D) NAND flash includes programming a select wordline of an unselect bit line of the 3D NAND flash; performing a first verification process with at least a verification voltage on the select wordline; determining whether a first verification voltage of the first verification process for the select wordline is higher than a default voltage or not; and removing a pre-pulse phase of the ISPP when the first verification voltage is higher than the default voltage; wherein the first verification voltage is a following verification voltage of the first verification process. | 2021-10-21 |
| 20210327512 | Non-volatile Memory System Using Strap Cells In Source Line Pull Down Circuits - The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells. | 2021-10-21 |
| 20210327513 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A memory device that controls a floating time point of word lines connected to a sub block adjacent to a sub block on which an erase operation is performed includes a plurality of memory blocks each including a plurality of sub blocks, a voltage generator configured to generate a plurality of voltages to perform an erase operation on any of the plurality of sub blocks, and control logic configured to divide a plurality of word lines connected to an adjacent sub block neighboring a sub block on which the erase operation is performed into a plurality of groups, and configured to control the voltage generator to differently set a floating time point of word lines included in each group for each of the plurality of groups, during the erase operation. | 2021-10-21 |
| 20210327514 | ERASE CYCLE HEALING USING A HIGH VOLTAGE PULSE - An indication to perform a write operation at a memory component can be received. A voltage pulse can be applied to a destination block of the memory component to store data of the write operation, the voltage pulse being at a first voltage level associated with a programmed state. An erase operation for the destination block can be performed to change the voltage state of the memory cell from the programmed state to a second voltage state associated with an erased state. A write operation can be performed to write the data to the destination block upon changing the voltage state of the memory cell to the second voltage state. | 2021-10-21 |
| 20210327515 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a controller which executes a read operation. In the read operation, the controller applies first and second read voltages to a word line, reads data at each of first and second times, applies the first voltage to a source line at each of the first and second times, applies a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and applies a third voltage to the source line during the application of the second read voltage to the word line and before the second time. | 2021-10-21 |
| 20210327516 | MEMORY DEVICE AND OPERATING METHOD THEREOF - A memory device includes: one or more planes each including a plurality of memory blocks; and a control circuit for selectively performing a dummy read operation before a valid read operation on the first memory block, according to whether a read command on the first memory block is firstly received from a host after a program operation is performed on a plane including the first memory block. | 2021-10-21 |
| 20210327517 | POWER-ON-RESET FOR MEMORY - A system can include a voltage generator configured to generate a reference voltage, a power-up voltage, and a replicated voltage based on a power supply voltage. The system can further include a logic sub-component coupled to the voltage generator and configured to output a reset signal based on a comparison of the reference voltage to the power-up voltage and an indication that the reference voltage that has entered a steady state and is reliable as a measurement with respect to a voltage level of the power supply voltage. The indication can be determined based on a comparison of the replicated voltage to a particular threshold voltage level. | 2021-10-21 |
| 20210327518 | NON-VOLATILE MEMORY WITH ERASE VERIFY SKIP - A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks of the block. Erase verify is performed between erase voltage pulses for NAND strings in the outer sub-blocks while skipping erase verify for NAND strings in the inner sub-blocks. Performing erase verify between erase voltage pulses for NAND strings in the inner sub-blocks is started at a predetermined number of erase voltage pulses after the NAND strings in the outer sub-blocks successfully erase verify. | 2021-10-21 |
| 20210327519 | METHODS AND APPARATUS FOR NAND FLASH MEMORY - Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a NAND flash memory. The method includes precharging selected bit lines of selected memory cells with a bias voltage level while unselected bit lines maintain the inhibit voltage, applying a verify voltage to a selected word line that is coupled to the selected memory cells, and discharging the selected bit lines that are coupled to on-cells over a first time interval. The method also includes sensing a sensed voltage level on a selected bit line, loading the selected bit line with the inhibit voltage level when the sensed voltage level is above a threshold level and a program voltage when the sensed voltage level is equal to or below the threshold level, and repeating the operations of sensing and loading for each of the selected bit lines. | 2021-10-21 |
| 20210327520 | ALL STRING VERIFY MODE FOR SINGLE-LEVEL CELL - A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty. | 2021-10-21 |
| 20210327521 | MEMORY CELL, MEMORY DEVICE, AND RELATED IDENTIFICATION TAG - A memory cell includes: a latch, powered by a first reference voltage and a second reference voltage different from the first reference voltage, and having a first connecting terminal and a second connecting terminal; a first programmable fuse, having a first terminal coupled to the first connecting terminal and a second terminal coupled to the second reference voltage; and a second programmable fuse, having a first terminal coupled to the second connecting terminal and a second terminal coupled to the second reference voltage. | 2021-10-21 |
| 20210327522 | LIQUID DISCHARGE HEAD AND METHOD OF MANUFACTURING THE SAME - A liquid discharge head having an element board including an element configured to discharge a liquid includes a first storage element and a second storage element. The first storage element is a fuse element or an anti-fuse element. The second storage element is a semiconductor memory capable of holding a larger capacity than the first storage element. The second storage element is provided on an area other than the element board. | 2021-10-21 |
| 20210327523 | METHOD AND DEVICE FOR SELF TRIMMING MEMORY DEVICES - The present disclosure relates to integrated memory device including:
| 2021-10-21 |
| 20210327524 | REFERENCE VOLTAGE ADJUSTMENT PER PATH FOR HIGH SPEED MEMORY SIGNALING - In a memory system, receiver reference voltage adjustment per path provides the capability to adjust receiver reference voltages on a per path basis. Adjustment of receiver reference voltages for the memory device to an optimal receiver reference voltage per path is accomplished with dedicated mode registers and a local receiver voltage reference adjuster circuit in the memory device for each data path. The optimal receiver reference voltage is determined during training based on selected feedback per path from the memory device. The dedicated mode registers contain adjustment values that were previously programmed during training, and include adjustments steps to add to or subtract from a global receiver reference voltage for all paths until reaching the optimal receiver reference voltage for a current path. | 2021-10-21 |
| 20210327525 | AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES - A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output. | 2021-10-21 |
| 20210327526 | MEMORY DEVICE WITH ANALOG MEASUREMENT MODE FEATURES - The present disclosure relates to apparatuses and methods for memory management and more particularly to a memory device structured with internal analogic measurement mode features. | 2021-10-21 |
| 20210327527 | TEST METHOD FOR MEMORY DEVICE - A test method for a memory device including the following steps is provided. A redundancy function of the memory device is disable and a first data is written to a first memory array. The redundancy function of the memory device is enabled and a second data is written to a second memory array. The first data and the second data are complementary. A redundancy information is read from a non-volatile memory block according to a margin condition and the second memory array is read based on the redundancy information to obtain a first readout data. A first test result is generated by comparing the second data and the first readout data. The second memory array includes a part of memory cells of the first memory array and at least one redundancy memory cell. | 2021-10-21 |
| 20210327528 | DATA VERIFYING METHOD, CHIP, AND VERIFYING APPARATUS - A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data. | 2021-10-21 |
| 20210327529 | DATA STORAGE DEVICE AND METHOD OF OPERATING THE SAME - A data storage device including a memory device and a memory controller is disclosed. The memory controller including a super block includes a parity controller in communication with a memory device including a plurality of pages and configured to generate a first parity using data to be written to a first group of pages among the plurality of pages, and generate a second parity using data to be written to a second group of pages among the plurality of pages, a write operation controller configured to control the memory device to store the first parity and the second parity, and an error correction circuitry coupled to apply the first parity and the second parity to correct at least one of the plurality of pages arranged to belong to the first group of pages and the second group of pages. | 2021-10-21 |
| 20210327530 | CONTROLLER AND OPERATING METHOD THEREOF - The controller that controls a memory device includes: a processor suitable for controlling the memory device to perform a first soft read operation by using first soft read voltages; and an error correction code (ECC) codec suitable for performing a first soft decision decoding operation based on first soft read data obtained through the first soft read operation, wherein the processor controls the memory device to perform a second soft read operation with an additional read voltage, of second soft read voltages, that is different than any of the first soft read voltages and which is determined based on the first soft read data, according to whether the first soft decision decoding operation failed, and wherein the ECC codec performs a second soft decision decoding operation based on the first soft read data and second soft read data obtained through the second soft read operation. | 2021-10-21 |
| 20210327531 | METHOD FOR READING AND WRITING AND MEMORY DEVICE - The embodiments provide a method for reading and writing and a memory device. The method for reading and writing includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and associating the address information pointed to by the read command with a spare memory cell if an error occurs in the data to be read out. The method for reading and writing provided by the present disclosure greatly improves reliability of the memory device and prolongs lifespan of the memory device. | 2021-10-21 |
| 20210327532 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE - The present technology relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block including memory cells, a peripheral circuit configured to program the memory cells in a set program state during a test operation and perform a test erase voltage application operation on the memory cells programmed in the set program state, and control logic configured to control the peripheral circuit to count abnormal memory cells of which a threshold voltage is less than a set threshold voltage among the memory cells. | 2021-10-21 |
| 20210327533 | METHODS FOR GENERATING BROADLY REACTIVE, PAN-EPITOPIC IMMUNOGENS, COMPOSITIONS AND METHODS OF USE THEREOF - Provided herein are methods for generating a non-naturally occurring, broadly reactive, pan-epitopic antigen derived from a pathogen, such as a virus, bacterium, and the like, that is immunogenic and is capable of eliciting a broadly reactive immune response, such as a broadly reactive neutralizing antibody response, against the pathogen following introduction into a subject. Also provided is a non-naturally occurring immunogen generated using the methods, and vaccines and compositions comprising the immunogen. Methods of generating an immune response in a subject by administering the immunogen, vaccine, or composition are provided. In particular, the immunogen comprises the hemagglutinin (HA) or neuraminidase (NA) protein of influenza virus strains. | 2021-10-21 |
| 20210327534 | CANCER CLASSIFICATION USING PATCH CONVOLUTIONAL NEURAL NETWORKS - Methods for determining a disease condition of a subject of a species are provided that comprises obtaining a dataset of fragment methylation patterns determined by methylation sequencing of nucleic acid from a biological sample of the subject. A fragment methylation pattern comprises the methylation state of each CpG site in the fragment. A patch including a channel comprising parameters for the methylation status of respective CpG sites in a set of CpG sites in a reference genome represented by the patch is constructed by populating, for each respective fragment in the plurality of fragments that aligns to the set of CpG sites, an instance of all or a portion of the plurality of parameters based on the methylation pattern of the respective fragment. Application of the patch to a patch convolutional neural network determines the disease condition of the subject. | 2021-10-21 |
| 20210327535 | SENSITIVELY DETECTING COPY NUMBER VARIATIONS (CNVS) FROM CIRCULATING CELL-FREE NUCLEIC ACID - The present disclosure provides methods and systems for detecting or inferring levels of Copy Number Variants (CNVs) in cell-free nucleic acid samples to detect or assess cancer and prenatal diseases. Cell-free nucleic acid methylation sequencing data may be utilized to distinguish tumor-derived or fetal-derived sequencing reads from normal cfDNA sequencing reads. Each cell-free nucleic acid sequencing read (e.g., containing tumor or fetal methylation markers) may be classified as corresponding to a tumor/fetal-derived or a normal-plasma cell-free nucleic acid, based on the methylation cfDNA sequencing data (e.g., obtained using Bisulfite sequencing or bisulfite-free sequencing methods) and tumor/fetal methylation markers. Next, a profile of the tumor/fetal-derived sequencing read counts may be constructed and then normalized. The CNV status (e.g., gain or loss) of each genomic region may be inferred, and a diagnosis or prognosis can be made based on a subjects inferred CNV profile. | 2021-10-21 |
| 20210327536 | Detection of Human Leukocyte Antigen Loss of Heterozygosity - Processes are provided for detecting loss of heterozygosity of Human Leukocyte Antigen (HLA) in a subject using analysis of next generation sequencing (NGS) data. The processes include aligning NGS data and identifying unmapped and mapped reads, updating reference data, and feeding one or more sequence reads to an HLA typing process for identifying candidate HLA alleles and feeding HLA type data to a loss of heterozygosity (LOH) modeling process for determining a LOH status for each HLA allele. A report may be generated of the LOH statuses for each of HLA allele. | 2021-10-21 |
| 20210327537 | VIRTUAL INFERENCE OF PROTEIN ACTIVITY BY REGULON ENRICHMENT ANALYSIS - Methods for determining regulon enrichment in gene expression signatures are disclosed herein. An example method can include obtaining a set of transcriptional targets of a regulon. The method can include obtaining a gene expression signature by comparing a gene expression profile of a test sample to gene expression profiles of a plurality of samples representing control phenotypes. The method can include calculating a regulon enrichment score for each regulon in the gene expression signature. The method can including determining whether a number of control samples in the control phenotypes is above a predetermined threshold to support evaluation of statistical significance using permutation analysis. The method can include, in response to determining that the number of control samples is above the predetermined threshold, calculating a significance value by comparing each regulon enrichment score to a null model. | 2021-10-21 |
| 20210327538 | METHODS AND SYSTEMS FOR CALLING PLOIDY STATES USING A NEURAL NETWORK - A method of calling a ploidy state using a neural network includes determining, for a training sample, genetic sequencing data or genetic array data for a plurality of genetic positions, determining respective true ploidy state values for a plurality of genetic segments, each genetic segment respectively comprising at least some of the plurality of genetic positions, based on the genetic sequencing data or genetic array data, and determining a neural network comprising one or more layers for calling respective ploidy state values, the neural network defined at least in part by a plurality of weights. The method further includes iteratively modifying the weights using specific processes. The method further includes calling, for a test sample, a ploidy state for a target genetic region by propagating genetic sequencing data for the test sample or genetic array data for the test sample through the modified neural network. | 2021-10-21 |
| 20210327539 | GENERATING SUBSEQUENCE CATALOGS FOR NUCLEIC ACID SYNTHESIS - Techniques for generating custom libraries for nucleic acid synthesis are disclosed. The techniques include: obtaining one or more nucleic acid sequences for which to generate a subsequence catalog; performing pattern recognition on the one or more nucleic acid sequences, to identify subsequences that are repeated in the one or more nucleic acid sequences; and generating the subsequence catalog, including the subsequences that are repeated in the one or more nucleic acid sequences. | 2021-10-21 |
| 20210327540 | USE OF MACHINE LEARNING MODELS FOR PREDICTION OF CLINICAL OUTCOMES - The present disclosure describes methods and systems for predicting if a subject has an increased risk of having or developing one or more clinical outcomes, including prior to the detection of symptoms thereof and/or prior to onset of any detectable symptoms thereof. The present disclosure also describes a method of generating a model for predicting one or more clinical outcomes. | 2021-10-21 |
| 20210327541 | DETECTION METHOD AND DETECTION APPARATUS FOR GENOMIC STRUCTURAL VARIATIONS BASED ON K-MER SET IN REFERENCE GENOME - Disclosed is a method of detecting a genomic structural variation based on k-mer set in a reference genome by means of a computer apparatus, the method including receiving sample sequence data, comparing the sample sequence data to k-mer set in reference genome data to determine at least one k-mer read that is not included in the reference genome data among reads of the sample sequence data, determining a breakpoint and a candidate region of a structural variation by mapping the at least one k-mer read to standard reference genome data, and predicting a structural variation type for the sample sequence data on the basis of a sequence mapping pattern and the breakpoint corresponding to the mapping result. | 2021-10-21 |
| 20210327542 | SYSTEMS AND METHODS FOR DETERMINING ANEUPLOIDY RISK USING SAMPLE FETAL FRACTION - Disclosed herein are system, method, and computer program product embodiments for determining aneuploidy risk in a target sample of maternal blood or plasma based on the amount of fetal DNA. An embodiment operates by receiving known genetic data from known prenatal testing samples and genetic data for the target sample. A fetal fraction distribution is determined for the known genetic data based on gestational age and the maternal weight associated with the target sample. A model is then generated based on a fixed ratio reduction of the determined fetal fraction distribution. A fetal fraction based data likelihood for the target sample is then determined for each of the plurality of ploidy states using the generated model. An aneuploidy risk score is then outputted based on applying a Bayesian probability determination that combines each fetal fraction based data likelihood with a previously determined risk score as a conditional value. | 2021-10-21 |
| 20210327543 | Artificial Intelligence Model for Predicting Actions of Test Substance in Humans - Actions, such as effects and adverse-events, of a test substance in humans are predicted by using an artificial intelligence model trained by a method for training an artificial intelligence model, the method including inputting into the artificial intelligence model a set of first training data and second training data or a set of the second training data to train the artificial intelligence model. | 2021-10-21 |
| 20210327544 | SYSTEMS AND METHODS FOR VISUALIZING ADAPTIVE IMMUNE CELL CLONOTYPING DATA - An interactive visualization system is disclosed herein. The system includes a data source, user input device, processor, and display. The data source obtains a B cell receptor and/or T cell receptor data source. The user input device receives a user selected parameter under which to analyze the data set. The processor identifies a clonotype group in the data set using the parameter, identifies subclonotypes within the clonotype group (wherein each identified subclonotype comprises cells having identical V(D)J transcripts), and processes the data to define a visualization model that can display a compressed view of the identified clonotype group. The display renders a visualization of said data set according to said visualization model. The visualization displays the clonotype group by identified subclonotype. | 2021-10-21 |
| 20210327545 | SYSTEM AND METHOD FOR BUILDING INTUITIVE CLINICAL TRIAL APPLICATIONS - The present invention allows clinical trial organizers to operate a platform for creating trial specific custom mobile applications at a price point that would not be possible if the application were created by programmers on a trial-by-trial basis. The invention shortens build time by creating a hierarchy of questions that changes the next question posed to the user based upon their answer to a previous question thereby reducing the number of questions the user must answer while providing the application creation platform with the detailed information relevant to a specific clinical trial. The platform uses a simulation builder that provides a test version of the application to the user mobile device during the application creation process thereby allowing the user to see the layout of the application as they progress through the building process. While building the application, the user can create a simulated version of the application in real time deliver the same to the mobile device of the user. The system creates a handshaking process that allows the user to create annotations and/or edits in the simulated application that are communicated back to the building platform. Changes made in the simulated application will affect the landing page the user sees when returning to the building platform. The system will collect usability data from a clinical trial application on a plurality of trial subject and trial organizer mobile devices. The system can measure variables such as time on page, misentries, and missed selections of icons to determine common trouble spots for users. That data may be used to redesign the interface or process flow of the application to optimize usability | 2021-10-21 |
| 20210327546 | Key Note - Methods, computer systems, and computer storage media are provided that enables clinicians to create and interact with snapshots of critical clinical/non-clinical information that is readily accessible in future visits. Initially, an indication to create a key note corresponding to a clinical note of a patient encounter for a patient is received. A selection of a key note section that will be associated with the key note is also received. Upon the clinical note being signed, the key note is created and saved. Upon receiving a request from a user, a key note window is provided in a user interface. The user interface enables the user to expand a header corresponding to a particular key note to display details associated with the corresponding encounter. A hyperlink to original summary notes from which the particular key note was created may be provided by the user interface. | 2021-10-21 |
| 20210327547 | SYSTEMS, METHODS, AND NON-TRANSITORY COMPUTER-READABLE MEDIA FOR SECURE BIOMETRICALLY-ENHANCED DATA EXCHANGES AND DATA STORAGE - A privacy-enhancing system, method, and non-transitory computer-readable medium for securely identifying or verifying an individual over time without retaining sensitive biometric data (e.g., biometric images or biometric templates) for the purpose of various data-related interactions. The data interactions including but not limited to: accessing, sharing, exchanging, controlling, or processing of personal data or any data related to an individual, entity, or thing. | 2021-10-21 |
| 20210327548 | STORING, AUTHENTICATING, AND TRANSMITTING HEALTH DATA - A computing device can authenticate a user account associated with a user. The computing device can scan an area to determine a scannable identifier associated with a vaccination dose. The computing device can determine a batch number and a lot number associated with the vaccination dose based on the scannable identifier. The computing device can determine a location associated with the at least one computing device. The computing device can receive a provider confirmation code corresponding to a provider. The computing device can perform a verification that the provider confirmation code matches an assigned provider confirmation code corresponding to the provider. The computing device can associate the vaccination dose with the user account in the data store as having been given to the user. | 2021-10-21 |
| 20210327549 | SYSTEMS AND METHODS FOR DATA PROCESSING AND PERFORMING STRUCTURED AND CONFIGURABLE DATA COMPRESSION - A wearable data storage and transmission device and related systems that collect and store sensor data from sensors worn by a user. The device components can include a processor, battery, data storage media, NFC components, Bluetooth components, Wi-Fi components, and wired communications components. The device can remain powered down, powering up periodically to collect sensor data using low energy methods and/or in response to receiving a signal (e.g., NFC, power, Bluetooth, etc.) from an external device that causes the device to power up its components and make sensor data available to the external device. The collected sensor data may be encoded, compressed, stored, and/or exchanged in one or more structured records using various methods to improve the information storage capabilities of the device, including using the disclosed QR coding methods. | 2021-10-21 |
| 20210327550 | SYSTEMS AND METHODS FOR PATIENT RECORD MATCHING - Methods for determining whether different first names are nicknames of each other and are to be used for matching different patient records with the same person are provided. At least one method includes obtaining the different first names and demographic information associated with each of the different first names, determining whether at least a threshold number of instances of the patient records include pairs of the different first names each associated with a household, measuring a likelihood of affinity between the different first names in each of the pairs based on the demographic information associated with each of the different first names, comparing the likelihood of affinity with an affinity threshold, identifying the different first names in at least one of the pairs as the nicknames of each other responsive to the likelihood of affinity exceeding the affinity threshold, and updating or creating a database storing associations between the nicknames. | 2021-10-21 |
| 20210327551 | BIOMETRICALLY-LINKED ELECTRONIC PROOF OF HEALTH STATUS OF INDIVIDUAL - Biometrically-linked electronic proof of health status of an individual. In one embodiment, an electronic device including a biometric capture circuitry, a memory, and an electronic processor. The biometric capture circuitry configured to capture one or more biometrics of the individual. The electronic processor is configured to receive the one or more biometrics of the individual that are captured by the biometric capture circuitry, generate a biometric token of the individual based on the one or more biometrics, receive information indicative of a health status of the individual, link the information indicative of the health status of the individual to the biometric token, and control the memory to store the biometric token and the information indicative of the health status of the individual that is linked to the biometric token. | 2021-10-21 |
| 20210327552 | MEDICAL WRISTBAND WITH INCREASED EASE OF MANUFACTURING - The present disclosure provides a new and innovative medical wristband that can be thermally printed with patient identification features and that also includes location-tracking features. The provided medical wristband includes a wristband component and a separate closure component. The wristband component may be thermally printed using conventional thermal printers because it is not physically attached to the location tracker that would otherwise make the medical wristband too thick for conventional thermal printers. The wristband component may be printed with patient identification information and/or a scannable code accessing patient identification information. The closure component has a location tracker coupled to it, such as a Bluetooth beacon. In one example, the location tracker is welded to the closure component. Accordingly, a patient may wear a single thermally printed wristband that provides medical professionals with both patient identification features and location tracking features. | 2021-10-21 |
| 20210327553 | PREDICTION OF ADVERSE DRUG REACTION BASED ON MACHINE-LEARNED MODELS USING PROTEIN FUNCTION SCORES AND CLINICAL FACTORS - The present disclosure predicts adverse reaction to drugs based on individual genetic and clinical information. The system receives as an input to the system gene sequence information and clinical information for a subject, and determines one or more scores (e.g., protein function score, clinical factor score, drug safety score) based on that information, where the scores can indicate subject's risk of having the adverse drug reaction. The system provides a representation of the prediction and/or information about the associated phenotype for display on a user interface in a client device (e.g., a physician's device). | 2021-10-21 |
| 20210327554 | AUTOMATED PILL DISPENSER - Disclosed is a cloud-based resource and information tracking system for medical patients and healthcare providers. The cloud-based software system integrates all or many sources of patient medical and health information, updates the information in near real-time, and makes the data available to member(s) of the patient's healthcare team securely. | 2021-10-21 |
| 20210327555 | RETROSPECTIVE HORIZON BASED INSULIN DOSE PREDICTION - The invention relates to a novel system to provide data quality control of a subject dataset, useful for treating patients with diabetes mellitus. The data quality control system, via a trained regression model, analyzes blood glucose measurements and provides a predicted insulin injection amount to the subject. The predicted insulin injection amount may be used to improve the accuracy of insulin dose titration programs, providing the subject with confidence that a titrated insulin dose is appropriate and is providing optimal treatment for the diabetes condition. Thus, the data quality control system provides for improved patient outcomes. | 2021-10-21 |
| 20210327556 | Energy Expenditure - Aspects relate to calculating energy expenditure values from an apparatus configured to be worn on an appendage of a user. Steps counts may be quantified, such as by detecting arm swings peaks and bounce peaks in motion data. A search range of acceleration frequencies related to an expected activity may be established. Frequencies of acceleration data within a search range may be analyzed to identify one or more peaks, such as a bounce peak and an arm swing peak. Novel systems and methods may determine whether to utilize the arm swing data, bounce data, and/or other data or portions of data to quantify steps. The number of peaks (and types of peaks) may be used to choose a step frequency and step magnitude. At least a portion of the motion data may be classified into an activity category based upon the quantification of steps. | 2021-10-21 |
| 20210327557 | Collection and Display of Athletic Information - Systems and techniques for the collection and display of athletic information. Athletic data relating to a single person or group of people is collected at a central location, and subsequently displayed at a desired remote location so that the person or people can review and critique their performance. In addition, athletic data for multiple persons can be collected at a central location, and subsequently displayed to a user at a desired remote location, so that the user can compare his or her athletic activities to others. | 2021-10-21 |
| 20210327558 | NAVIGABLE PRESENTATION OF A VARIETY OF SOLUTIONS FOR THERAPY PLANS - The present invention includes a method for representing a plurality of pre-calculated solutions in radiation therapy that are stored in a database and displayed in a manner controllable by a user. Arrays of DVH curves provide the user with essential information on the ‘quality of a plan’. A DVH diagram is displayed as a main diagram, wherein only one of the solutions is visually represented at a time. By selecting a first starting point on a selected DVH curve as the main diagram, a first straight axis extending through the first starting point is placed. A first region, located around the first starting point and on the first straight axis, is highlighted as a first control region for controllable visualization of the plurality of currently non-displayed solutions stored in the database, the DVH curves of which correspond to the selected DVH curve and intersect the first straight axis. | 2021-10-21 |
| 20210327559 | System for Optimizing Behavioral Changes of a User to Improve the User's Wellbeing - A method for optimizing a user's behavioral changes uses an artificial intelligence system to present actions to the user for achieving a behavioral change goal. The goal is first set at a time instant t. A user characteristics vector and current state vector are generated using static and dynamic user characteristics describing the user's current state. The vectors are used to generate a behavioral change tool vector for the time instant t. The behavioral change tool vector is presented to the user to select a suggested action for achieving the goal. The user characteristics, current state, and behavioral change tool vectors for the time instant t are mapped to a next current state vector for a next time instant t+1. The system repeats generating the behavioral change tool vector using vectors updated for the next time instant t+1 until the mapping indicates that the behavioral change goal has been achieved. | 2021-10-21 |
| 20210327560 | SYSTEMS AND METHODS FOR FUNCTIONAL IMAGING - A system includes a structural imaging acquisition unit, a functional imaging acquisition unit, and one or more processors. The structural imaging acquisition unit is configured to perform a structural scan to acquire structural imaging information of a patient. The functional imaging acquisition unit is configured to perform a functional scan to acquire functional imaging information of a patient. The one or more processors are configured to generate a tissue-specific anatomical probability map using the structural imaging information; generate a tissue-non-specific anatomical probability map using the structural imaging information; generate local combined anatomical probability weights using the tissue-specific anatomical probability map, the tissue-non-specific anatomical probability map, and the functional image data; re-distribute the functional image data using the local combined anatomical probability weights to provide re-distributed functional volumetric data; and generate an image using the re-distributed functional volumetric data. | 2021-10-21 |
