42nd week of 2011 patent applcation highlights part 16 |
Patent application number | Title | Published |
20110254037 | Light-Emitting Device and Electronic Device - A low-power light-emitting device which can be manufactured in simple steps and is suitable for increasing definition and the size of a substrate is provided. The light-emitting device includes a layer for blocking visible light; a conductive layer that partly overlaps with the layer for blocking visible light; a color filter layer that includes an opening over the layer for blocking visible light; a first electrode layer for transmitting visible light that is connected to the conductive layer through the opening, over the color filter layer; an insulating partition over the first electrode layer overlapping with the opening; a layer containing an organic compound over the first electrode layer and the partition; and a second electrode layer over the layer containing an organic compound. The layer containing an organic compound includes a layer containing a donor substance and an acceptor substance and a layer containing a light-emitting organic compound. | 2011-10-20 |
20110254038 | LED HOUSING WITH FLUOROPOLYMER SURFACE COATING LAYER AND LED STRUCTURE HAVING THE SAME - A housing for supporting a light-emitting diode chip is disclosed. The housing includes a housing body made of non-fluoro-containing polymer and a surface coating layer covering at least a portion of the housing body. The surface coating layer is made of fluoropolymer dispersion and provided for reflecting light emitted from a light-emitting diode chip disposed on the housing body. A structure of light-emitting diode including the housing and a light-emitting diode chip is also disclosed. | 2011-10-20 |
20110254039 | LIGHT EMITTING DIODE PACKAGE, LIGHTING APPARATUS HAVING THE SAME, AND METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE - A light emitting diode (LED) package, a lighting apparatus including the same, and a method for manufacturing an LED package are disclosed. The LED package includes: a package substrate; an LED chip mounted on the package substrate; and a wavelength conversion layer formed to cover at least a portion of an upper surface of the LED chip when a surface formed by the LED chip when viewed from above is defined as the upper surface of the LED chip, wherein the wavelength conversion layer is formed so as not to exceed the area of the upper surface of the LED chip and includes a flat surface parallel to the upper surface of the LED chip and curved surfaces connecting the corners of the upper surface of the LED chip. | 2011-10-20 |
20110254040 | LIGHT-EMITTING DEVICE - A light-emitting device includes a base and a light-emitting element that is disposed on the base. The light-emitting element is made up of a plurality of semiconductor layers including a light-emitting layer, and at the same time, is covered with a wavelength converting portion that includes a wavelength converting material. The light-emitting layer emits primary light, and the wavelength converting material absorbs part of the primary light and emits secondary light. The luminance of the primary light emitted from the edge portion of the light extraction surface of the light-emitting device is higher than the luminance of the primary light emitted from the inner region located inside the edge portion, and the ratio of the primary light and the secondary light that are emitted from a light extraction surface of the wavelength converting portion is substantially uniform across the light extraction surface of the wavelength converting portion. Thereby, a light color difference across the light extraction surface of the wavelength converting portion that covers the light-emitting element can be reduced further, and it is possible to irradiate an irradiation surface with light of uniform color. | 2011-10-20 |
20110254041 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor light emitting device and a method of fabricating the same. The semiconductor light emitting device includes: a light emitting structure comprising a first conductive type semiconductor layer, an active layer under the first conductive type semiconductor layer, and a second conductive type semiconductor layer under the active layer; a reflective electrode layer under the light emitting structure, and an outer protection layer at an outer circumference of the reflective electrode layer. | 2011-10-20 |
20110254042 | ELONGATED LENSES FOR USE IN LIGHT EMITTING APPARATUSES - A light emitting apparatus includes one or more light emitting semiconductors, and an elongated lens encapsulating the one or more light emitting semiconductors. The elongated lens comprises an exterior surface having a photoluminescent material thereon. | 2011-10-20 |
20110254043 | ROD-LIKE LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING ROD-LIKE LIGHT-EMITTING DEVICE, BACKLIGHT, ILLUMINATING DEVICE, AND DISPLAY DEVICE - To facilitate electrode connections and achieve a high light emitting efficiency, a rod-like light-emitting device includes a semiconductor core of a first conductivity type having a rod shape, and a semiconductor layer of a second conductivity type formed to cover the semiconductor core. The outer peripheral surface of part of the semiconductor core is exposed. | 2011-10-20 |
20110254044 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING A LIGHT EMITTING DEVICE - A light emitting device and a method of fabricating a light emitting device are provided. The light emitting device includes a carrier substrate, at least one epitaxy structure, a high resistant ring wall, a first electrode, and a second electrode. The epitaxy structure is disposed on the carrier substrate and includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence. The first semiconductor layer is relatively away from the carrier substrate and the second semiconductor layer is relatively close to the carrier substrate. The high resistant ring wall surrounds the epitaxy structure and a width of the high resistant ring wall is greater than 5 μm. The first electrode is disposed between the carrier substrate and the epitaxy structure. The second electrode is disposed at a side of the epitaxy structure away from the carrier substrate. | 2011-10-20 |
20110254045 | LIGHT EMITTING DIODE PACKAGE AND LIGHT EMITTING DIODE SYSTEM HAVING AT LEAST TWO HEAT SINKS - There is provided a light emitting diode package having at least two heat sinks. The light emitting diode package includes a main body, at least two lead terminals fixed to the main body, and at least two heat sinks of electrically and thermally conductive materials, the heat sinks being fixed to the main body. The at least two heat sinks are separated from each other. Thus, high luminous power can be obtained mounting a plurality of light emitting diode dies in one LED package. Further, it is possible to embody polychromatic lights mounting LED dies emitting different wavelengths of light each other in the LED package. | 2011-10-20 |
20110254046 | LIGHT-EMITTING DEVICE - The present invention is related to a light-emitting device. The present invention illustrates a vertical light-emitting device in one embodiment, comprising the following elements: a conductive substrate includes a through-hole, a patterned semiconductor structure disposed on a first surface of the substrate, a first bonding pad and a second bonding pad disposed on a second surface of the substrate, a conductive line passing through the through-hole connecting electrically the semiconductor structure layer, and an insulation layer on at least one sidewall of the through-hole insulates the conductive line form the substrate. The present invention illustrates a horizontal light-emitting device in another embodiment, comprising the following elements: a substrate includes a first tilted sidewall, a patterned semiconductor structure disposed on a first surface of the substrate, a first conductive line is disposed on at least the first tilted sidewall of the substrate and connecting electrically the patterned semiconductor structure. | 2011-10-20 |
20110254047 | Curable Organopolysiloxane Composition, Optical Semiconductor Element Sealant, And Optical Semiconductor Device - A hydrosilylation reaction-curable organopolysiloxane composition comprising (A) a methylpheny-lalkenylpolysiloxane that has at least two alkenyl groups wherein diphenylsiloxane units are no more than 5 mole % and at least 20 mole % is comprised of phenyl groups, (B) a methylphenylhydrogenpolysiloxane that has at least two Si-bonded hydrogen atoms wherein diphenylsiloxane units are no more than 5 mole % and at least 20 mole 1% is comprised of phenyl groups, and (C) a hydrosilylation reaction catalyst. An optical semiconductor element sealant comprising this composition. An optical semiconductor device sealed with this optical semiconductor element sealant. | 2011-10-20 |
20110254048 | GROUP III NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE - An object of the present invention is to provide a Group III nitride semiconductor epitaxial substrate, i.e., an Al | 2011-10-20 |
20110254049 | SEMICONDUCTOR DEVICE - A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns. | 2011-10-20 |
20110254050 | REVERSE CONDUCTING IGBT - An insulated gate bipolar transistor (IGBT) is provided comprising a semiconductor substrate having the following regions in sequence: (i) a first region of a first conductive type having opposing surfaces, a column region of a second conductive type within the first region extending from a first of said opposing surfaces; (ii) a drift region of the second conductive type; (iii) a second region of the first conductive type, and (iv) a third region of the second conductive type. There is provided a gate electrode disposed to form a channel between the third region and the drift region, a first electrode operatively connected to the second region and the third region, a second electrode operatively connected to the first region and the column region. The arrangement of the IGBT is such that the column region is spaced from a second surface of the opposing surfaces of the first region, whereby a forward conduction path extends sequentially through the third region, the second region, the drift region, and the first region, and whereby a reverse conduction path extends sequentially through the second region, the drift region, the first region and the column region. Reverse conduction of the IGBT occurs through a thyristor structure which is embedded in the IGBT. Such an IGBT structure is advantageous over a reverse conducting IGBT structure in which an anti-parallel diode is integrated or embedded because it provides improved reverse conduction and snapback performance. | 2011-10-20 |
20110254051 | SEMICONDUCTOR DEVICE - A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained. | 2011-10-20 |
20110254052 | Hybrid Group IV/III-V Semiconductor Structures - Described herein are semiconductor structures comprising (i) a Si substrate; (ii) a buffer region formed directly over the Si substrate, wherein the buffer region comprises (a) a Ge layer having a threading dislocation density below about 10 | 2011-10-20 |
20110254053 | SUPERCONDUCTOR TRANSISTOR AND METHOD FOR MANUFACTURING SUCH TRANSISTOR - This field-effect superconductor transistor ( | 2011-10-20 |
20110254054 | SEMICONDUCTOR DEVICE - A semiconductor device has at least an n-type MIS transistor, which includes a first gate insulating film formed on a first semiconductor region in a semiconductor substrate, a first gate electrode formed on the first gate insulating film, first sidewalls formed on the side surfaces of the first gate electrode, and carbon-containing silicon regions formed laterally outside the first sidewalls. The top surfaces of the carbon-containing silicon regions are at a level higher than the top surface of a region in the first semiconductor region lying under the first gate insulating film. | 2011-10-20 |
20110254055 | FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A field effect transistor includes a channel layer of group-III nitride-based compound semiconductor; an interface layer formed on the channel layer and of Al | 2011-10-20 |
20110254056 | SEMICONDUCTOR DEVICE HAVING TRANSISTOR AND RECTIFIER - A semiconductor device having a transistor and a rectifier includes: a current path; a first main electrode having a rectifying function and arranged on one end of the current path; a second main electrode arranged on the other end of the current path; an auxiliary electrode arranged in a region of the current path between the first main electrode and the second main electrode; a third main electrode arranged on the one end of the current path apart from the first main electrode along a direction intersecting the current path; and a control electrode arranged in a region of the current path between the second main electrode and the third main electrode. The transistor includes the current path, the second main electrode, the third main electrode, and the control electrode. The rectifier includes the current path, the first main electrode, the second main electrode, and the auxiliary electrode. | 2011-10-20 |
20110254057 | NITRIDE BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING OF THE SAME - Disclosed herein is a nitride based semiconductor device. The nitride based semiconductor device includes: a base substrate; an epitaxial growth layer disposed on the base substrate and having a defect generated due to lattice disparity with the base substrate; a leakage current barrier covering the epitaxial growth layer while filling the defect; and an electrode part disposed on the epitaxial growth layer. | 2011-10-20 |
20110254058 | Gate-All-Around CMOSFET devices - A GAA (Gate-All-Around) CMOSFET device includes a semiconductor substrate, a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The surfaces of the first channel and the second channel are substantially surrounded by the gate region. A buried insulation layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the semiconductor substrate to isolate them from one another. The structure is simple, compact and highly integrated, has high carrier mobility, and avoids polysilicon gate depletion and short channel effect. | 2011-10-20 |
20110254059 | STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES - A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures. | 2011-10-20 |
20110254060 | Metal Gate Structure and Fabricating Method thereof - A method of fabricating a metal gate structure is provided. Firstly, a high-K gate dielectric layer is formed on a semiconductor substrate. Then, a first metal-containing layer having a surface away from the gate dielectric layer is formed on the gate dielectric layer. After that, the surface of the first metal-containing layer is treated to improve the nitrogen content thereof of the surface. Subsequently, a silicon layer is formed on the first metal-containing layer. Because the silicon layer is formed on the surface having high nitrogen content, the catalyzing effect to the silicon layer resulted from the metal material in the first metal-containing layer can be prevented. As a result, the process yield is improved. | 2011-10-20 |
20110254061 | TRANSISTOR AND METHOD OF FABRICATING THE SAME - A transistor including a gate, an active stacked structure, a dielectric layer, a source and a drain. The gate is located over a first surface of the dielectric layer. The active stacked structure, including a first active layer and a second active layer, is located over a second surface of the dielectric layer. The source and the drain are located over the second surface of the dielectric layer and at two sides of the active stacked structure and extend between the first active layer and the second active layer of the active stacked structure. | 2011-10-20 |
20110254062 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A field effect transistor which can operate at a low threshold value includes: an n-type semiconductor region; a source region and a drain region separately formed in the n-type semiconductor region; a first insulating film formed in the semiconductor region between the source region and the drain region and containing silicon and oxygen; a second insulating film formed on the first insulating film and containing at least one material selected from Hf, Zr, and Ti and oxygen; and a gate electrode formed on the second insulating film. Ge is doped in an interface region including an interface between the first insulating film and the second insulating film, and an area density of the Ge has a peak on a first insulating film side in the interface region. | 2011-10-20 |
20110254063 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a MOS device, which comprises: a substrate; an interface layer thin film formed on the substrate; a high k gate dielectric layer formed on the interface layer thin film; and a metal gate formed on the high k gate dielectric layer. The metal gate comprises, upwardly in order, a metal gate work function layer, an oxygen absorption element barrier layer, a metal gate oxygen absorbing layer, a metal gate barrier layer and a polysilicon layer. A metal gate oxygen absorbing layer is introduced into the metal gate for the purpose of preventing the outside oxygen from coming into the interface layer and absorbing the oxygen in the interface layer during a annealing process, such that the interface layer is reduced to be thinner and the EOT of MOS devices are effectively reduced; meanwhile, by adding an oxygen absorption element barrier layer, the “oxygen absorption element” is prevented from diffusing into the high k gate dielectric layer and giving rise to unfavorable impact thereon; in this way, the high k/metal gate system can be more easily integrated, and the performance of the device can be further improved accordingly. | 2011-10-20 |
20110254064 | SEMICONDUCTOR DEVICE WITH CARBON ATOMS IMPLANTED UNDER GATE STRUCTURE - An exemplary semiconductor device includes a substrate, a spacer, a metal silicide layer and carbon atoms. The substrate has a gate structure formed thereon. The spacer is formed on the sidewall of the gate structure. The spacer has a first side adjacent to the gate structure and a second side away from the gate structure. The metal silicide layer is formed on the substrate and adjacent to the second side of the spacer but away from the first side of the spacer. The carbon atoms are formed into the substrate and adjacent to the first side of the spacer but away from the second side of the spacer. | 2011-10-20 |
20110254065 | PHOTOELECTRIC CONVERSION DEVICE, METHOD FOR MANUFACTURING THE SAME AND IMAGE PICKUP SYSTEM - An object of the present invention is to provide a photoelectric conversion device, wherein improvement of charge transfer properties when charge is output from a charge storage region and suppression of dark current generation during charge storage are compatible with each other. This object is achieved by forming a depletion voltage of a charge storage region in the range from zero to one half of a power source voltage (V), forming a gate voltage of a transfer MOS transistor during a charge transfer period in the range from one half of the power source voltage to the power source voltage (V) and forming a gate voltage of the transfer MOS transistor during a charge storage period in the range from minus one half of the power source voltage to zero (V). | 2011-10-20 |
20110254066 | SEMICONDUCTOR DEVICE - A semiconductor device includes, a semiconductor substrate, a first transistor of a first conductivity type, a second transistor of a second conductivity type, a first capacitor, and a first wiring. The semiconductor substrate includes first, second, and third regions. The third region is sandwiched between the first and second regions. The first transistor of the first conductivity type is disposed in the first region. The second transistor of the second conductivity type is disposed in the second region. The first capacitor is disposed in the third region. The first wiring electrically couples one of main electrodes of the first transistor and one of main electrodes of the second transistor. The first wiring passes above the first capacitor. | 2011-10-20 |
20110254067 | DRAM Layout with Vertical FETS and Method of Formation - DRAM cell arrays having a cell area of about 4F | 2011-10-20 |
20110254068 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode. | 2011-10-20 |
20110254069 | FLOATING GATE TYPE NONVOLATILE MEMORY DEVICE AND RELATED METHODS OF MANUFACTURE AND OPERATION - A floating gate type nonvolatile memory device comprises a semiconductor layer, wordlines crossing over the semiconductor layer, and a memory element disposed between the wordlines and facing the semiconductor layer. | 2011-10-20 |
20110254070 | TRENCH MOSFET WITH TRENCHED FLOATING GATES IN TERMINATION - A trench MOSFET comprising a plurality of transistor cells, multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in active area. In some preferred embodiments, the trench MOSFET further comprises a gate metal runner surrounding outside the source metal and extending to the gate metal pad. Furthermore, the termination area further comprises an EPR surrounding outside the trenched floating gates. | 2011-10-20 |
20110254071 | SHIELDED TRENCH MOSFET WITH MULTIPLE TRENCHED FLOATING GATES AS TERMINATION - A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure. | 2011-10-20 |
20110254072 | CHARGE STORAGE STRUCTURES AND METHODS - Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor. | 2011-10-20 |
20110254073 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Nonvolatile semiconductor memory device includes; a first element isolation insulation layer within a first dummy cell region; a second element isolation insulation layer within a second dummy cell region; and a third element isolation insulation layer at boundary between the first and second dummy cell regions. Top surface of the first element isolation insulation layer is located lower than that of first floating electrode layers. Top surface of the second element isolation insulation layer is located at the same height as that of second floating electrode layers. The third element isolation insulation layer has a top surface. The end portion of the top surface adjoining the first floating electrode layer is located at a height lower than the top surface of the first floating electrode layer. The top surface of the third element isolation insulation layer has gradient ascending from the side surface of the first floating electrode layer toward that of the second floating electrode layer. | 2011-10-20 |
20110254074 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor integrated circuit device includes defining a first area by forming a separating area on a substrate, and forming a tunnel film in the first area, a floating gate on the tunnel film, a first electrode in the separating area, a first film on the floating gate, a second film on the first electrode, a control gate on the first film, a second electrode on the second film, and source and drain areas in the first area. The method includes forming a first interlayer film to cover the control gate and the second electrode, forming, in the first interlayer film, a conductive via plug reaching the second electrode, and forming, on the first interlayer film, a second wiring electrically coupled to the second electrode via the conductive via plug, and a first wiring that is capacitively-coupled to the second wiring and to the second electrode. | 2011-10-20 |
20110254075 | USE OF DILUTE STEAM AMBIENT FOR IMPROVEMENT OF FLASH DEVICES - A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized. | 2011-10-20 |
20110254076 | HIGH DENSITY FLASH MEMORY CELL DEVICE, CELL STRING AND FABRICATION METHOD THEREFOR - Provided is an ultra highly-integrated flash memory cell device. The cell device includes a semiconductor substrate, a first doping semiconductor area formed on the semiconductor substrate, a second doping semiconductor area formed on the first doping semiconductor area, and a tunneling insulating layer, a charge storage node, a control insulating layer, and a control electrode which are sequentially formed on the second doping semiconductor area. The first and second doping semiconductor areas are doped with impurities of the different semiconductor types According to the present invention, it is possible to greatly improve miniaturization characteristics and performance of the cell devices in conventional NOR or NAND flash memories. Unlike conventional transistor type cell devices, the cell device according to the present invention does not have a channel and a source/drain. Therefore, in comparison with the conventional memories, the fabricating process can be simplified, and the problem such as cross-talk or read disturb can be greatly reduced. | 2011-10-20 |
20110254077 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a plurality of gate structures disposed on a substrate. Respective gate structures may include a lower control gate layer and an upper control gate layer. The upper control gate layer may be disposed on the lower control gate layer and may include a different material from the lower control gate layer. The semiconductor device may further include insulation patterned layers disposed in gap regions defined between the gate structures adjacent to each other. Upper surfaces of the insulation patterned layers may be lower than an upper surface of the lower control gate layer. | 2011-10-20 |
20110254078 | METHOD FOR DEPOSITING SILICON NITRIDE FILM, COMPUTER-READABLE STORAGE MEDIUM, AND PLASMA CVD DEVICE - Provided is a method for depositing a silicon nitride film in a plasma CVD device which introduces microwaves into a process chamber by a planar antenna having a plurality of apertures, and the method including setting the pressure in the process chamber within a range from 10 Pa to 133.3 Pa and performing plasma CVD by using film formation gas including a silicon containing compound gas and a nitrogen gas while applying an RF bias to the wafer by supplying high-frequency power with an output density within a range from 0.009 W/cm | 2011-10-20 |
20110254079 | NON-VOLATILE MEMORY DEVICES - A non-volatile memory device can include a plurality of parallel active regions that are defined by a plurality of device isolation layers formed on a semiconductor substrate, where each of the plurality of parallel active regions extends in a first direction and has a top surface and sidewalls. A plurality of parallel word lines can extend in a second direction and cross over the plurality of parallel active regions at intersecting locations. A plurality of charge storage layers can be disposed at the intersecting locations between the plurality of parallel active regions and the plurality of parallel word lines. Each of the plurality of charge storage layers at the intersecting locations can have a first side and a second side that is parallel to the second direction and can have a first length, a third side and a fourth side that are parallel to the first direction and can have a second length, where the first length is less than the second length. | 2011-10-20 |
20110254080 | TUNNEL FIELD EFFECT TRANSISTOR - A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack. | 2011-10-20 |
20110254081 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed. | 2011-10-20 |
20110254082 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a conductive pattern formed on the substrate; an interlayer dielectric layer formed on the conductive pattern; a contact plug connected to the conductive pattern extending through the interlayer dielectric layer; a semiconductor layer and an insulating layer sequentially formed on the interlayer dielectric layer; an electrode pattern formed on the insulating layer; and a capping insulating layer pattern covering upper portions of neighboring electrode patterns with the contact plug. An additional process is not needed to define an active region. An active region apart from the gate patter is not needed. A storage electrode contact line does not need to be formed. A height of a landing plug is reduced to reduce the landing plug resistance. A junction region does not need to be formed. | 2011-10-20 |
20110254083 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device including a buried gate and a method for forming the same are disclosed. The semiconductor device includes a buffer layer formed on a surface of a trench in a semiconductor substrate, and a gate electrode configured to partially bury the trench and formed of the same material as in the buffer layer. | 2011-10-20 |
20110254084 | STRUCTURES AND METHODS OF FABRICATING DUAL GATE DEVICES - First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed. | 2011-10-20 |
20110254085 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING REDUCED UNIT CELL AREA AND METHOD FOR MANUFACTURING THE SAME - A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate and arranged to intersect the word lines, thereby delimiting a plurality of crossing regions and a plurality of unit memory cells; a plurality of gate electrodes formed to control respective pairs of unit memory cells adjacent to each other with the word lines interposed therebetween and to contact corresponding word lines on one sides of the crossing regions; storage node contacts respectively formed in spaces of the unit memory cells; and a plurality of bit line contacts formed to contact the respective bit lines on one sides of the crossing regions. | 2011-10-20 |
20110254086 | SHIELDED TRENCH MOSFET WITH MULTIPLE TRENCHED FLOATING GATES AS TERMINATION - A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure. | 2011-10-20 |
20110254087 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n | 2011-10-20 |
20110254088 | Power MOSFET With Embedded Recessed Field Plate and Methods of Fabrication - Semiconductor power devices, and related methods, wherein a recessed contact makes lateral ohmic contact to the source diffusion, but is insulated from the underlying recessed field plate (RFP). Such an insulated RFP is here referred to as an embedded recessed field plate (ERFP). | 2011-10-20 |
20110254089 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF FABRICATING SAME - A semiconductor integrated circuit comprising thin-film transistors in each of which the second wiring is prevented from breaking at steps. A silicon nitride film is formed on gate electrodes and on gate wiring extending from the gate electrodes. Substantially triangular regions are formed out of an insulator over side surfaces of the gate electrodes and of the gate wiring. The presence of these substantially triangular side walls make milder the steps at which the second wiring goes over the gate wiring. This suppresses breakage of the second wiring. | 2011-10-20 |
20110254090 | RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER - A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion. | 2011-10-20 |
20110254091 | ESD Protection Structures on SOI Substrates - An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region. | 2011-10-20 |
20110254092 | ETSOI CMOS ARCHITECTURE WITH DUAL BACKSIDE STRESSORS - A semiconductor is formed on an ETSOI layer, the thin Si layer of an ETSOI substrate, with enhanced channel stress. Embodiments include semiconductor devices having dual stress liners on the back surface of the ETSOI layer. An embodiment includes forming an ETSOI substrate comprising an extra thin layer of Si on a backside substrate with an insulating layer, e.g., a BOX, there between, forming a semiconductor device on the Si surface, removing the backside substrate, as by CMP and the insulting layer, as by wet etching, and forming a stress liner on the backside of the remaining Si layer opposite the semiconductor device. The use of stress liners on the backside of the ETSOI layer enhances channel stress without modifying ETSOI semiconductor process flow. | 2011-10-20 |
20110254093 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. A multi-component high-k interface layer containing elements of the substrate is formed from a ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment. Thus, the present invention may also avoid the growth of the interface layers and the degradation of carrier mobility. Furthermore, the present invention may further alleviate the problem of high interface state and interface roughness caused by direct contact of the high-k gate dielectric layer with high dielectric constant and the substrate, and thus the overall performance of the device is effectively enhanced. | 2011-10-20 |
20110254094 | Semiconductor device - A semiconductor device | 2011-10-20 |
20110254095 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to reduce the number of manufacturing steps of a semiconductor device, to improve yield of a semiconductor device, or to reduce manufacturing cost of a semiconductor device. One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes, over a substrate, a first transistor having a single crystal semiconductor layer in a channel formation region, a second transistor that is isolated from the first transistor with an insulating layer positioned therebetween and has an oxide semiconductor layer in a channel formation region, and a diode having a single crystal semiconductor layer and a oxide semiconductor layer. | 2011-10-20 |
20110254096 | SEMICONDUCTOR DEVICE HAVING NON-SILICIDE REGION IN WHICH NO SILICIDE IS FORMED ON DIFFUSION LAYER - A semiconductor device includes first and second MOSFETs corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein. The first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region. | 2011-10-20 |
20110254097 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH TWIN-WELL - A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well. | 2011-10-20 |
20110254098 | INTEGRATED CIRCUIT WITH REPLACEMENT METAL GATES AND DUAL DIELECTRICS - A replacement gate structure and method of fabrication are disclosed. The method provides for fabrication of both high performance FET and low leakage FET devices within the same integrated circuit. Low leakage FET devices are fabricated with a hybrid gate dielectric comprised of a low-K dielectric layer and a high-K dielectric layer. High performance FET devices are fabricated with a low-K gate dielectric. | 2011-10-20 |
20110254099 | Hybrid material accumulation mode GAA CMOSFET - A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device. | 2011-10-20 |
20110254100 | HYBRID MATERIAL ACCUMULATION MODE GAA CMOSFET - A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device has high carrier mobility, high device drive current, and maintains the electrical integrity of the device. Meanwhile, polysilicon gate depletion and short channel effects are prevented. | 2011-10-20 |
20110254101 | HYBRID MATERIAL INVERSION MODE GAA CMOSFET - A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device. | 2011-10-20 |
20110254102 | HYBRID ORIENTATION INVERSION MODE GAA CMOSFET - A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Si (110) and p-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have different orientation channels, the GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, and prevent polysilicon gate depletion and short channel effects. | 2011-10-20 |
20110254103 | Semiconductor Memory Devices Having Strain Layers Therein That Increase Device Performance And Methods of Forming Same - Integrated circuit memory devices include a semiconductor word line having an electrically insulating strain layer directly contacting an upper surface thereof. The strain layer, which has a contact opening therein, has a sufficiently high degree of internal compressive strain therein to thereby impart a net tensile stress within at least a first portion of the semiconductor word line. A P-N junction diode is also provided on the semiconductor word line. The diode includes a first terminal (e.g., cathode, anode) electrically coupled through the opening in the strain layer to the surface of the semiconductor word line. A data storage element (e.g., MRAM, FRAM, PRAM, RRAM, etc.) may also be provided, which has a current carrying terminal electrically coupled to a second terminal of the p-n junction diode. | 2011-10-20 |
20110254104 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET. | 2011-10-20 |
20110254105 | Strained Semiconductor Device with Recessed Channel - A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes. | 2011-10-20 |
20110254106 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes a gate insulation film formed over a semiconductor substrate; a cap film formed over the gate insulation film; a silicon oxide film formed over the cap film; a metal gate electrode formed over the silicon oxide film; and source/drain diffused layers formed in the semiconductor substrate on both sides of the metal gate electrode. | 2011-10-20 |
20110254107 | METHOD AND APPARATUS FOR FORMING MEMS DEVICE - The disclosure is generally directed to fabrication steps, and operation principles for microelectromechanical (MEMS) transducers. In one embodiment, the disclosure relates to a texture morphing device. The texture morphing device includes: a plurality of supports arranged on a substrate to support a deformable mirror; an ITO layer; and a Distributed Bragg Reflector (DBR) layer. A pair of adjacent supports form a cavity with the ITO layer and the deformable mirror. When the height of the cavity changes responsive to an external pressure, the internal reflection within the cavity is changed. The change in the height of the cavity causes the exterior texture to morph. Similar principles are disclosed for constructing sensor and actuators. | 2011-10-20 |
20110254108 | FINGER SENSOR INCLUDING CAPACITIVE LENS AND ASSOCIATED METHODS - A finger sensing device may include a mounting substrate, an integrated circuit (IC) die carried by the mounting substrate and having an array of electric field-based finger sensing elements, and first electrical connections coupling the mounting substrate and the IC die. In addition, the finger sensing device may include a protective plate attached over the array of electric field-based finger sensing elements and having a dielectric constant greater than 5 in all directions and a thickness greater than 40 microns to define a capacitive lens for the array of electric field-based finger sensing elements. The finger sensing device may also include an encapsulating material adjacent the mounting substrate and the IC die and around at least the first electrical connections. | 2011-10-20 |
20110254109 | INTEGRATED CIRCUIT WITH SPURRIOUS ACOUSTIC MODE SUPPRESSION AND METHOD OF MANUFACTURE THEREOF - An integrated circuit (IC) apparatus includes a substrate having opposed first and second major sides and one or more edges defining an outer periphery of the substrate. The substrate may be a semiconductor material. The IC apparatus may further include one or more transducers situated on the first major side of the substrate; and an attenuation pattern formed in at least one of the second major side and one or more of the edges of the substrate. | 2011-10-20 |
20110254110 | MEMS DEVICE HAVING A MOVABLE ELECTRODE - A microelectromechanical system (MEMS) device includes a semiconductor substrate, a MEMS including a fixed electrode and a movable electrode formed on the semiconductor substrate through an insulating layer, and a well formed in the semiconductor substrate below the fixed electrode. The well is one of an n-type well and a p-type well. The p-type well applies a positive voltage to the fixed electrode while the n-type well applies a negative voltage to the fixed electrode. | 2011-10-20 |
20110254111 | PACKAGED ACOUSTIC TRANSDUCER DEVICE WITH SHIELDING FROM ELECTROMAGNETIC INTERFERENCE - A device includes: a housing structure; lid configured together with the housing structure to define a cavity therein; and at least one acoustic transducer disposed within the cavity, wherein the lid shields the at least one acoustic transducer from exposure to electromagnetic interference from electromagnetic radiation originating outside the device. In some embodiments, the housing structure includes some electrically conductive leads, including a ground lead, and the lid is directly connected to the ground lead. | 2011-10-20 |
20110254112 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a semiconductor substrate, and plural switching transistors provided on the semiconductor substrate. A contact plug is embedded between the adjacent two switching transistors described above, is insulated from gates of the adjacent two switching transistors, and is electrically connected to diffusion layers of the adjacent two switching transistors. An upper connector is formed on the contact plug, and an upper surface is at a position higher than upper surfaces of the switching transistors. A memory element is provided on the upper surface of the upper connector, and stores data. A wiring is provided on the memory element. | 2011-10-20 |
20110254113 | ST-RAM MAGNETIC ELEMENT CONFIGURATIONS TO REDUCE SWITCHING CURRENT - In order to increase an efficiency of spin transfer and thereby reduce the required switching current, a current perpendicular to plane (CPP) magnetic element for a memory device includes either one or both of a free magnetic layer, which has an electronically reflective surface, and a permanent magnet layer, which has perpendicular anisotropy to bias the free magnetic layer. | 2011-10-20 |
20110254114 | MAGNETORESISTIVE EFFECT ELEMENT - A magnetoresistive effect element includes a first ferromagnetic layer formed above a substrate, a second ferromagnetic layer formed above the first ferromagnetic layer, an insulating layer interposed between the first ferromagnetic layer and the second ferromagnetic layer and formed of a metal oxide, and a first nonmagnetic metal layer interposed between the insulating layer and the second ferromagnetic layer and in contact with a surface of the insulating layer on the side of the second ferromagnetic layer, the first nonmagnetic metal layer containing the same metal element as the metal oxide. | 2011-10-20 |
20110254115 | INSERTED REFLECTIVE SHIELD TO IMPROVE QUANTUM EFFICIENCY OF IMAGE SENSORS - The structures of reflective shields and methods of making such structures described enable reflection of light that has not be absorbed by photodiodes in image sensor devices and increase quantum efficiency of the photodiodes. Such structures can be applied (or used) for any image sensors to improve image quality. Such structures are particular useful for image sensors with smaller pixel sizes and for long-wavelength light (or rays), whose absorption length (or depth) could be insufficient, especially for backside illumination (BSI) devices. The reflective shields could double, or more than double, the absorption depth for light passing through the image sensors and getting reflected back to the photodiodes. Concave-shaped reflective shields have the additional advantage of directing reflected light toward the image sensors. | 2011-10-20 |
20110254116 | Photoelectric Conversion Module - A photoelectric conversion module X | 2011-10-20 |
20110254117 | Electrical Devices Including Dendritic Metal Electrodes - The present invention relates generally to electrical devices. The present invention relates more particularly to electrical devices including dendritic metal electrodes. One aspect of the present invention is an electrical device comprising a first electrode comprising at least one dendritic metal structure; a second electrode; and an electrically active structure disposed between the dendritic metal structure and the second electrode. | 2011-10-20 |
20110254118 | Schottky Diode with Control Gate for Optimization of the On State Resistance, the Reverse Leakage, and the Reverse Breakdown - A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode. | 2011-10-20 |
20110254119 | Semiconductor Device and Method of Manufacturing the Same - A method of manufacturing semiconductor devices includes forming a tunnel insulating layer, a conductive layer for a floating gate, and a hard mask layer on a semiconductor substrate, forming a first trench in the semiconductor substrate by partially etching the hard mask layer, the conductive layer for the floating gate, the tunnel insulating layer, and the semiconductor substrate, forming a first ion implantation region having a first impurity concentration into the semiconductor substrate of inner walls of the first trench by performing a first ion implantation process, forming a second trench extending from the first trench by etching the semiconductor substrate of a bottom of the first trench, and forming a second ion implantation region having a second impurity concentration lower than the first impurity concentration into the semiconductor substrate of inner walls of the second trench by performing a second ion implantation process, wherein a depth of the first trench is shallower than that of a junction region. | 2011-10-20 |
20110254120 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a substrate of a first conductivity type; a first diffusion layer of a second conductivity type formed on the substrate; a second diffusion layer of the first conductivity type formed in an upper part of the first diffusion layer; a third diffusion layer of the second conductivity type formed in an upper part of the second diffusion layer; a fourth diffusion layer of the second conductivity type formed in the upper part of the first diffusion layer; and a fifth diffusion layer of the first conductivity type formed below the third diffusion layer. A sum of a shortest distance from the third diffusion layer to the fifth diffusion layer and a shortest distance from the fifth diffusion layer or the lower end of the first diffusion layer to the fourth diffusion layer is smaller than a shortest distance from the third diffusion layer to the fourth diffusion layer. | 2011-10-20 |
20110254121 | PROGRAMMABLE ANTI-FUSE STRUCTURES WITH CONDUCTIVE MATERIAL ISLANDS - Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features. | 2011-10-20 |
20110254122 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object of one embodiment of the present invention is to provide an antifuse which has low writing voltage. The antifuse is used for a memory element for a read only memory device. The antifuse includes a first conductive layer, an insulating layer, a semiconductor layer, and a second conductive layer. The insulating layer included in the antifuse is a silicon oxynitride layer formed by adding ammonia to a source gas. When hydrogen is contained in the layer at greater than or equal to 1.2×10 | 2011-10-20 |
20110254123 | ULTRA HIGH SPEED SIGNAL TRANSMISSION/RECEPTION - There is provided, in combination, an integrated circuit chip, a device, and a multilayered structure mounted between the integrated circuit chip and the device. The multilayered structure has signal pathways that transfer signals between the integrated circuit chip and the device, and at least one signal pathway with a first wireless coupling element in the multilayered structure that is in communication with a second wireless coupling element in one of the integrated circuit chip, the device, and the multilayered structure. | 2011-10-20 |
20110254124 | FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material. | 2011-10-20 |
20110254125 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to the present invention is equipped with a plurality of analog macros having comb capacitors ( | 2011-10-20 |
20110254126 | MEMORY CELL WITH CARBON SWITCHING MATERIAL HAVING A REDUCED CROSS-SECTIONAL AREA AND METHODS FOR FORMING THE SAME - In a first aspect, a method of forming a metal-insulator-metal (“MIM”) stack is provided, the method including: (1) forming a dielectric material having an opening and a first conductive carbon layer within the opening; (2) forming a spacer in the opening; (3) forming a carbon-based switching material on a sidewall of the spacer; and (4) forming a second conductive carbon layer above the carbon-based switching material. A ratio of a cross sectional area of the opening in the dielectric material to a cross sectional area of the carbon-based switching material on the sidewall of the spacer is at least 5. Numerous other aspects are provided. | 2011-10-20 |
20110254127 | METHOD AND DEVICE FOR A DRAM CAPACITOR HAVING LOW DEPLETION RATIO - A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided. | 2011-10-20 |
20110254128 | ELECTRODE FOR ENERGY STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - An electrode for an energy storage device with less deterioration due to charge and discharge, and a method for manufacturing thereof are provided. Further, an energy storage device having large capacity and high endurance can be provided. In an electrode of an energy storage device in which an active material is formed over a current collector, the surface of the active material is formed of a crystalline semiconductor film having a { | 2011-10-20 |
20110254129 | ELECTRICAL COMPONENTS FOR MICROELECTRONIC DEVICES AND METHODS OF FORMING THE SAME - Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process. | 2011-10-20 |
20110254130 | SEMICONDUCTOR DEVICE INCLUDING METAL-INSULATOR-METAL CAPACITOR ARRANGEMENT - A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor. | 2011-10-20 |
20110254131 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device including a digital circuit region in which a digital circuit is formed, and an analog circuit region in which an analog circuit is formed, the analog circuit region is separated into an active element region in which an active element of the analog circuit is formed, and a resistive and capacitive element region in which a resistor or a capacitor of the analog circuit is formed, the resistive and capacitive element region is arranged in a region adjacent to the digital circuit region, and the active element region is arranged in a region separated from the digital circuit region. | 2011-10-20 |
20110254132 | VERTICAL INTERDIGITATED SEMICONDUCTOR CAPACITOR - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate that spans in an X-direction and a Y-direction that is orthogonal to the X-direction. The semiconductor device includes an interconnect structure formed over the substrate in a Z-direction that is orthogonal to both the X-direction and the Y-direction. The interconnect structure includes a plurality of metal lines interconnected together in the Z-direction by a plurality of vias. The interconnect structure contains a capacitor that includes an anode component and a cathode component. The anode component includes an array of elongate anode stack elements extending in the Z-direction. The cathode component includes an array of elongate cathode stack elements extending in the Z-direction. The array of anode stack elements are interdigitated with the array of cathode stack elements in both the X direction and the Y direction. | 2011-10-20 |
20110254133 | PHOTORESISTS AND METHODS FOR USE THEREOF - New photoresist are provided that comprises an Si-containing component and that are particularly useful for ion implant lithography applications. Photoresists of the invention can exhibit good adhesion to underlying inorganic surfaces such as SiON, silicon oxide, silicon nitride and other inorganic surfaces. | 2011-10-20 |
20110254134 | Method of Group III Metal - Nitride Material Growth Using Metal Organic Vapor Phase Epitaxy - The non-polar or semi-polar Nitride film is grown using Metal Organic Vapor Phase Epitaxy over a substrate. The in-situ grown seed layer comprising Magnesium and Nitrogen is deposited prior to the Nitride film growth. The said seed layer enhances the crystal growth of the Nitride material and makes it suitable for electronics and optoelectronics applications. The use of non-polar and/or semi-polar epitaxial films of the Nitride materials allows avoiding the unwanted effects related to polarization fields and associated interface and surface charges, thus significantly improving the semiconductor device performance and efficiency. In addition, the said seed layer is also easily destroyable by physical or chemical stress, including the ability to dissolve in water or acid, which makes the substrate removal process available and easy. The substrate removal provides the possibility to achieve exceptional thermal conductivity and application flexibility, such as additional contact formation, electromagnetic radiation extraction, packaging or other purposes suggested or discovered by the skilled artisan. | 2011-10-20 |
20110254135 | III-NITRIDE SEMICONDUCTOR GROWTH SUBSTRATE, III-NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE, III-NITRIDE SEMICONDUCTOR ELEMENT, III-NITRIDE SEMICONDUCTOR FREESTANDING SUBSTRATE, AND METHOD FOR FABRICATING THESE - An object of the present invention is to address the problems described herein and to provide a III-nitride semiconductor epitaxial substrate, a III-nitride semiconductor element, and a III-nitride semiconductor freestanding substrate, which have good crystallinity, not only with AlGaN, GaN, or GaInN, the growth temperature of which is at or below 1050° C., but also with Al | 2011-10-20 |
20110254136 | SEMICONDUCTOR DEVICE - A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening. | 2011-10-20 |