42nd week of 2017 patent applcation highlights part 66 |
Patent application number | Title | Published |
20170302235 | AMPLIFIER - An amplification circuit has a field effect transistor, an input side matching circuit, an output side matching circuit, a capacitor, and a resistor. The input side matching circuit is connected between an input port and the source terminal of the field effect transistor and outputs an input signal that changes with a bias voltage as a center value. The output side matching circuit is connected between an output port and the drain terminal of the field effect transistor. The capacitor is connected between the gate terminal of the field effect transistor and a first reference voltage source. The resistor is connected between the gate terminal of the field effect transistor and the first reference voltage source. | 2017-10-19 |
20170302236 | AMPLIFICATION CIRCUIT - An amplification circuit includes a first switching circuit that includes input terminals and first and second output terminals and that puts the second output terminal into an open state with respect to the input terminals while selectively putting the first output terminal into a state of being connected to any of the input terminals or selectively puts the second output terminal into a state of being connected to any of input terminals while putting the first output terminal into a state of being open with respect to the input terminals; a matching network that is connected to the first output terminal; an amplifier that is connected to an output side of the matching network; a second switching circuit that is connected to an output side of the amplifier; and a bypass path that electrically connects the second output terminal and an output terminal of the second switching circuit. The amplifier is a variable-gain amplifier. | 2017-10-19 |
20170302237 | LINEARIZED DYNAMIC AMPLIFIER - A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC). | 2017-10-19 |
20170302238 | DC OFFSET CANCELLATION CIRCUIT - Disclosed herein is a DC offset cancellation circuit. The DC offset cancellation circuit includes a DC feedback unit configured to vary a DC feedback (DCFB) bandwidth to add at least one mid-bandwidth to the DCFB bandwidth and to provide a delay time in each case in order to reduce the DC droop error that occurs in switching from the high bandwidth (BW) to the mid-BW or from the mid-BW mode to the low BW mode, such that stable settling is ensured. | 2017-10-19 |
20170302239 | FEEDBACK CIRCUIT FOR POWER AMPLIFIER - Feedback circuit for power amplifier. In some embodiments, a radio-frequency amplifier can include a bipolar junction transistor configured to amplify a signal, and having an input and an output. The radio-frequency amplifier can further include a feedback circuit implemented between the output and input of the bipolar junction transistor. The feedback circuit can include a parallel assembly of a field-effect transistor and a resistive element such that the resistive element is bypassed when the field-effect transistor is ON and an overall resistance of the feedback circuit includes the resistive element when the field-effect transistor is OFF. Such a feedback circuit can be configured to be capable of providing a plurality of resistance values between the output and input of the bipolar junction transistor to facilitate different gains of the bipolar junction transistor. | 2017-10-19 |
20170302240 | LOUDNESS LEVEL CONTROL FOR AUDIO RECEPTION AND DECODING EQUIPMENT - The application discusses a computer implemented method and apparatus for performing audio equalisation in an audio receiver device, such as an integrated receiver/decoder or set top box, or integrated TV, connected to one or more audio playback devices, such as a television unit, computer screen and speakers, amplifier or home theatre equipment. The method and apparatus use an equalisation process which compares audio signals received in different audio formats (e.g. MPEG-1 Layer II, AC-3 2.0, AC-3 5.1 and HE-AAC) with one another, allowing a correction gain factor to be determined for equalising the perceived loudness of the signals when played-back at a connected playback device. The correction gain factor is then applied in the audio receiver device before output. | 2017-10-19 |
20170302241 | MANAGEMENT OF BROADCAST AUDIO LOUDNESS - To control loudness during a junction between different types of broadcast content, such as a junction between programme and commercial or promotional content, representative loudness values for content respectively before (P) and after (C) the junction are received from a playout automation system. A time-varying gain control is applied before and after the junction in order to smooth loudness around the junction. The audio gain is smoothly increased prior to the junction to a gain (P+C)/ | 2017-10-19 |
20170302242 | PIEZOELECTRIC VIBRATION MEMBER AND METHOD OF MANUFACTURING THE SAME - A piezoelectric vibration member that includes a substrate having a main surface on or in which a piezoelectric vibration member is mounted, a lid having a recess that is open so as to face the main surface and which includes a flange portion that projects outward from an opening edge of the recess, and a bonding layer that bonds the substrate and the lid together so as to hermetically seal the piezoelectric vibrator in a space between the recess and the main surface. The surface roughness of a side surface of the flange portion is greater than the surface roughness of the surface of the recess, and the bonding layer extends from the main surface of the substrate to the side surface of the flange portion. | 2017-10-19 |
20170302243 | FILTER CIRCUIT, RF FRONT END CIRCUIT, AND COMMUNICATION APPARATUS - A filter circuit is provided which allows the pass band to be tuned to a desired communication signal while achieving increased attenuation in a given frequency band that lies outside the pass band. A filter circuit includes a fixed filter and a tunable filter. The fixed filter has a pass band wider than a frequency band corresponding to a predetermined communication signal and overlapping with the frequency band corresponding to the communication signal. The tunable filter has a stop band narrower than the pass band of the fixed filter and having tunable frequency. The fixed filter and the tunable filter are connected in series. | 2017-10-19 |
20170302244 | POWER CONVERSION SYSTEM - For power conversion, a power conversion system includes a plurality of power converters and a phase shifting transformer. The phase shifting transformer includes | 2017-10-19 |
20170302245 | ULTRA-BROAD BANDWIDTH MATCHING TECHNIQUE - A multicomponent network may be added to a transmission line in a high-frequency circuit to transform a first impedance of a downstream circuit element to second impedance that better matches the impedance of an upstream circuit element. The multicomponent network may be added at a distance more than one-quarter wavelength from the downstream circuit element, and can tighten a frequency response of the impedance-transforming circuit to maintain low Q values and low VSWR values over a broad range of frequencies. | 2017-10-19 |
20170302246 | ANTENNA MATCHING CIRCUIT, ANTENNA DEVICE, AND COMMUNICATION TERMINAL APPARATUS - An antenna device includes an impedance converter circuit connected to a feeder circuit, an impedance-conversion-ratio adjustment circuit, and an antenna. The impedance converter circuit includes a first inductance element and a second inductance element, which are coupled to each other through magnetic fields, so as to provide an autotransformer circuit. The impedance-conversion-ratio adjustment circuit includes a third inductance element which is series-connected between the impedance converter circuit and an antenna port, and a capacitance element which is shunt-connected between the antenna port and ground. The impedance-conversion-ratio adjustment circuit corrects an impedance conversion ratio of the impedance converter circuit in accordance with a frequency band. | 2017-10-19 |
20170302247 | METHOD AND APPARATUS FOR DETECTING RF FIELD STRENGTH - A method and apparatus for detecting RF field strength. A field strength reference generator develops a field strength reference current as a function of a field strength of a received RF signal; and a field strength quantizer develops a digital field-strength value indicative of the field strength reference current. In one embodiment, detected field strength is used to dynamically vary the impedance of a tank circuit whereby, over time, induced current is maximized. | 2017-10-19 |
20170302248 | POSITIONING METHOD AND APPARATUS - A positioning method includes: emitting an interrogator signal from an electronic device; detecting, by the electronic device, a response signal that is generated and emitted by a sensor among a plurality of sensors, in response to the interrogator signal; and acquire location information about the sensor by identifying the sensor based on the detected response signal. The response signal is generated based on transduction of the interrogator signal. | 2017-10-19 |
20170302249 | CRYSTAL RESONATOR - A crystal resonator includes a crystal element and excitation electrodes. The crystal element has a pair of principal surfaces parallel to an X′-axis and a Z′-axis. The X′-axis is an axis of rotating an X-axis as a crystallographic axis of a crystal in a range of 15 degrees to 25 degrees around a Z-axis as a crystallographic axis of the crystal. The Z′-axis is an axis of rotating the Z-axis in a range of 33 degrees to 35 degrees around the X′-axis. The excitation electrodes are formed on the respective principal surfaces of the crystal element. Elliptical mesa portions or elliptical inverted mesa portions are formed on the respective principal surfaces. The mesa portions project from outer peripheries of the principal surfaces. The inverted mesa portions are depressed from the outer peripheries of the principal surfaces. | 2017-10-19 |
20170302250 | RADIO FREQUENCY TRANSMIT FILTER WITH INTEGRATED IMPEDANCE MATCHING NETWORK - A transmit filter for a communications device includes a surface acoustic wave (SAW) band-pass filter configured to pass a transmit frequency band and a tunable transmitter impedance matching network in series. The tunable transmitter impedance matching network matches an input impedance of the SAW band-pass filter to the output impedance of a power amplifier over a portion of the transmit frequency band in response to a tuning input. | 2017-10-19 |
20170302251 | ACOUSTIC FILTERS INTEGRATED INTO SINGLE DIE - A multiplexer device includes a single die, at least three acoustic filters and at least one antenna port arranged on the single die, and a shunt inductance connected between each of the at least one antenna port and ground. Each acoustic filter includes one of a transmit or receive filter corresponding to a predetermined radio frequency band. The at least one antenna port is connected to at least one antenna, respectively, where each of the at least one antenna port is further connected to at least one acoustic filter arranged on the single die, and is configured to pass RF signals corresponding to the predetermined RF band of the connected at least one acoustic filter. The shunt inductance provides impedance matching between each of the at least one antenna port and each of the at least one acoustic filter connect to the at least one antenna port. | 2017-10-19 |
20170302252 | DUAL PASSBAND RADIO FREQUENCY FILTER AND COMMUNICATIONS DEVICE - Multi-band filters and communications devices are disclosed. A multi-band filter has a lower pass-band and an upper pass-band separated by an intervening stop-band. The multi-band filter includes a first ladder network and a second ladder network coupled in series. The first ladder network is configured to provide transmission zeros at frequencies below a lower edge of the lower pass-band and transmission zeros at frequencies above an upper edge of the upper pass-band. The second ladder network is configured to provide transmission zeros at frequencies within the intervening stop-band. | 2017-10-19 |
20170302253 | State Change Stabilization in a Phase Shifter/Attenuator Circuit - An electronic system that includes a digitally selectable phase shifter circuit and an insertion loss fine adjustment circuit such that the system as a whole exhibits little or no change in insertion loss when changing phase state, and/or a digitally selectable attenuator circuit and a phase fine adjustment circuit such that the system as a whole exhibits little or no effect on phase when changing attenuation state. Included are methods for selecting adjustment control words for such circuits. | 2017-10-19 |
20170302254 | VOLTAGE CONTROLLED EQUALIZER NETWORK - An apparatus includes a radio frequency (RF) input port, an RF output port, a variable attenuation network, a first filter network, a second filter network, and a third filter network. The variable attenuation network may be coupled between the RF input port and the RF output port. Attenuation of the variable attenuation network is controlled by a first control signal and a second control signal. The first filter network may be connected between the RF input port and the RF output port. The second filter network may be connected between the variable attenuation network and a ground potential. The third filter network may be connected between the variable attenuation network and the ground potential. The first, the second, and the third filter networks modify performance of the variable attenuation network to produce a particular tilt of a radio frequency signal passing through the apparatus between the RF input port and the RF output port. The particular tilt is selectable by adjustment of at least one of the first and the second control signals. | 2017-10-19 |
20170302255 | SOLID STATE RELAY - The disclosure relates to solid state relay circuit for switching an electrical load. The solid state relay circuit may include a relay transistor; and a driver circuit comprising a constant current source. The driver circuit is configured and arranged to switchably operate the relay transistor, and the relay transistor is configured and arranged to switchably operate the electrical load. | 2017-10-19 |
20170302256 | SYSTEM AND METHOD FOR DUTY CYCLE CORRECTION - Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives an input clock signal and a control signal and produces an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit that divides a frequency of the input clock signal by a positive even integer and generates an intermediate clock signal, and a phase detector that generates the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal. | 2017-10-19 |
20170302257 | COMPARATOR CIRCUIT WITH INPUT ATTENUATOR - A comparator circuit's signal range can be enhanced using an input signal attenuation circuit. In an example, a comparator circuit receives an input signal and a reference signal. The input signal can be conditioned by one or both of the attenuation circuit and a conditioning circuit, and a resulting conditioned signal can be presented to a compare element. Under first operating conditions where the input signal is approximately equal to the reference signal, the attenuation circuit can be substantially bypassed and a first resulting conditioned signal can be presented to the compare element. Under second operating conditions where the input signal is substantially greater than the reference signal, the attenuation circuit receives a portion of the input signal and a different second resulting conditioned signal can be presented to the compare element. | 2017-10-19 |
20170302258 | COMPARATOR - A comparator is disclosed, for comparing a first input voltage (e+) with a second input voltage (e−) and generating a corresponding output voltage (out). The comparator comprises: a first input terminal (e+) for receiving the first input voltage: a second input terminal (e−) for receiving the second input voltage; an output terminal (out) for outputting the output voltage; a first supply rail (VCC) for providing a first supply voltage; and a second supply rail (VDD) for providing a second supply voltage. The comparator further comprises: a follower stage comprising a first follower stage supply terminal coupled to the first supply rail, a second follower stage supply terminal coupled to the second supply rail, a follower stage input terminal coupled to the second input terminal, and a follower stage output terminal for providing a follower stage output voltage; and an inverter stage comprising a first inverter stage supply terminal coupled to the first supply rail, a second inverter stage supply terminal coupled to the follower stage output terminal, an inverter stage input terminal coupled to the first input terminal, and an inverter stage output terminal for providing an inverter stage output voltage and coupled to the output terminal. | 2017-10-19 |
20170302259 | RADIO FREQUENCY SWITCHING CIRCUITRY WITH IMPROVED SWITCHING SPEED - RF switching circuitry includes one or more RF switching elements, a control signal input node, a common resistor, and common resistor bypass circuitry. The one or more RF switching elements are coupled in series between a switch input node and a switch output node. A state of each one of the one or more switching elements is determined based on a control signal. The control signal input node is configured to receive the control signal. The common resistor is coupled between the control signal input node and the one or more RF switching elements. The common resistor bypass circuitry is configured to receive the switching control signal and bypass the common resistor for a predetermined time period following one or more of a leading edge of the switching control signal and a falling edge of the switching control signal. | 2017-10-19 |
20170302260 | DRIVING DEVICE AND INDUCTIVE LOAD DRIVING DEVICE - To provide an inductive load driving device which can control a clamp voltage using a ground voltage as a reference, with a simple structure. An inductive load driving device includes: an inductive load whose one end is connected to a power source and whose other end is connected to a ground: an output stage semiconductor switch element connected in series with the inductive load; a clamping circuit connected between a high-voltage side electrode and a control electrode of the output stage semiconductor switch element; and a resistance value control unit connected between the control electrode of the output stage semiconductor switch element and the ground. | 2017-10-19 |
20170302261 | PROTECTION CIRCUIT - A protection circuit includes a periodicity determination device, an off circuit and a control device. The periodicity determination device directly or indirectly detects a noise superimposed on a first transistor including a control terminal and determines periodicity of the noise. The off circuit is connected to the control terminal of the first transistor and is configured to perform an off-operation of the first transistor. The control device enables the off-operation of the first transistor, performed by the off circuit, when the periodicity determination device determines that the noise has periodicity. The control device disables the off-operation of the first transistor, performed by the off circuit, when the periodicity determination device determines that the noise does not have periodicity. Accordingly, the protection circuit withdraws an ESD energy while stabilizing a circuit operation. | 2017-10-19 |
20170302262 | SEMICONDUCTOR SWITCHING ELEMENT DRIVER CIRCUIT WITH OPERATION BASED ON TEMPERATURE - A driver circuit ( | 2017-10-19 |
20170302263 | IGBT Gate Drive During Turnoff To Reduce Switching Loss - A vehicle powertrain includes an IGBT and a gate driver. The IGBT is configured to energize an electric machine. The gate driver is configured to apply an off voltage less than a threshold voltage onto a gate of the IGBT while the IGBT is operating in a saturation mode, and in response to expiration of a delay from a transition from saturation to linear mode, apply a voltage pulse above the off voltage to reduce flyback from the electric machine. The gate driver may be configured to, in response to expiration of a delay from a transition from saturation to linear mode, apply a voltage pulse above the off voltage and below the threshold to reduce flyback from the electric machine. | 2017-10-19 |
20170302264 | THIN FILM TRANSISTOR GATE VOLTAGE SUPPLY CIRCUIT - The present invention provides a thin film transistor gate voltage supply circuit, and the thin film transistor gate voltage supply circuit is employed to supply a gate voltage for a thin film transistor, and the thin film transistor gate voltage supply circuit comprises a voltage generation circuit and a temperature compensation circuit, and the voltage generation circuit is employed to generate an original voltage, and the temperature compensation circuit is electrically coupled to the voltage generation circuit, and the temperature compensation circuit is employed to detect an ambient temperature, and as the ambient temperature is smaller than a preset temperature, the temperature compensation circuit compensates the original voltage according to a difference value of the ambient temperature and the preset temperature to obtain a first voltage, and supplies the first voltage to a gate of the thin film transistor to drive the thin film transistor normally work. | 2017-10-19 |
20170302265 | METHOD FOR ELECTRICALLY AGING A PMOS THIN FILM TRANSISTOR - The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A-40) to (A-8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A-80) to (A-16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd−Vs<0. In this way, reduction of a leakage current of the PMOS thin film transistor is achieved without changing a structural design of the thin film transistor. | 2017-10-19 |
20170302266 | RADIO-FREQUENCY DEVICES WITH FREQUENCY-TUNED BODY BIAS - Radio-frequency (RF) devices are disclosed providing improved switching performance. An RF switch device includes one or more field-effect transistors (FETs) disposed between a first node and a second node. Each FET has a respective source, drain, gate, and body. A resonance circuit connects the body of each of the one or more FETs to a reference node. The resonance circuit may be configured to behave as an approximately closed circuit at low frequencies below a selected value. The resonance circuit may also be configured to behave as an approximately open circuit at an operating frequency. The approximately closed circuit allows removal of surface charge from the body to the reference node. | 2017-10-19 |
20170302267 | LINE DRIVER APPARATUS WITH COMBINED FEED-THROUGH CAPACITANCE AND FEED-FORWARD EQUALIZATION - Example embodiments of the present disclosure relate to a line driver apparatus. In some example embodiments, an apparatus is provided. The apparatus includes a capacitive feed-through module and a driving module. The capacitive feed-through module includes a first pre-driver operable to receive input differential signals and delayed signals of the input differential signals, generate first drive signals from the input differential signals and the delayed signals, and equalize the first drive signals. The capacitive feed-through module also includes a capacitance reducing module arranged between the first pre-driver and transmission lines and operable to reduce parasitic capacitance at the transmission lines in response to the first drive signals. The driving module is coupled to the transmission lines and operable to generate output differential signals from the input differential signals for transmission on the transmission lines. | 2017-10-19 |
20170302268 | SEMICONDUCTOR CIRCUIT, VOLTAGE DETECTION CIRCUIT, AND VOLTAGE DETERMINATION CIRCUIT - A semiconductor circuit including a PMOS transistor that includes a first source connected to a power supply, a first drain, and a first gate to which a fixed potential is supplied; an output circuit that outputs a first output signal, which is a reset signal or a power-on signal, and that outputs a second output signal according to a potential of the first drain; a constant current source connected to the first drain; and an NMOS transistor that includes a second source to which a fixed potential is supplied, a second drain connected to the first drain, and a second gate to which the second output signal from the output circuit is applied. | 2017-10-19 |
20170302269 | Electronically switchable diplexer - An electronically switchable diplexer ( | 2017-10-19 |
20170302270 | METHOD AND APPARATUS FOR CURRENT/POWER BALANCING - Aspects of the disclosure provide a system having a power circuit. The power circuit includes a first switch circuit having at least a first transistor and a second switch circuit having at least a second transistor. Further, the power circuit includes first interconnections configured to couple the first switch circuit to driving nodes, a source node and a drain node of the power circuit, and second interconnection configured to couple the second switch circuit in parallel to the first switch circuit to the driving nodes, the source node and the drain node of the power circuit. A polarity of unbalance in the first interconnections and the second interconnections dominates a polarity of current unbalance in the first switch circuit and the second switch circuit. | 2017-10-19 |
20170302271 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SEMICONDUCTOR DEVICE - A potential is held stably. A negative potential is generated with high accuracy. A semiconductor device with a high output voltage is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, and a comparator. The comparator includes a non-inverting input terminal, an inverting input terminal, and an output terminal. A gate and one of a source and a drain of the first transistor are electrically connected to each other. One of a source and a drain of the second transistor is electrically connected to the non-inverting input terminal of the comparator, one electrode of the capacitor, and a gate of the second transistor. The other of the source and the drain of the second transistor is electrically connected to the one of the source and the drain of the first transistor. The first transistor and the second transistor each contain an oxide semiconductor. | 2017-10-19 |
20170302272 | Optimized RF Switching Device Architecture for Impedance Control Applications - A switch architecture having open reflective unselected ports. Signals can be selectively coupled between a common port and at least one selectable port through series connected switches. When one or more port is selected, the remaining ports are opened. In addition, associated “shuntable” switches from each of the selectable ports to ground are always open, regardless of the ON or OFF state of the series switches; thus, there is no normally active connection of the selectable ports to ground, but the presence of the shuntable switches provides electrostatic discharge protection for all ports. Embodiments of the invention allow configurability between a traditional architecture and an open reflective unselected port architecture, and include integrated circuit and field effect transistor embodiments. | 2017-10-19 |
20170302273 | SENSOR ELEMENT OF AN INDUCTIVE PROXIMITY OR DISTANCE SENSOR AND METHOD FOR OPERATING THE SENSOR ELEMENT - A sensor element of an inductive proximity sensor or distance sensor contains a coil arrangement with at least one excitation coil and at least one receiving coil and includes an electrically conductive shielding which contains a shielding cup that surrounds the coil arrangement laterally and on the rear face. A method operates the sensor element. The shielding of the sensor element further contains a flange which is provided on the front face of the sensor element, is connected to the shielding cup in an electrically conductive manner, and completely surrounds the coil arrangement. | 2017-10-19 |
20170302274 | OPERATION SWITCH, DRESSING TABLE AND MIRROR USING CAPACITANCE SENSOR - An operation switch includes: a capacitance sensor that generates three or more detection signals in response to approach or contact of an object to respective three or more electrodes; a determination circuit that determines whether or not the object is a living body based on one or more detection signals selected from the three or more detection signals, the one or more detection signals excluding a detection signal having a maximum intensity among the three or more detection signals; and a controller that, when the object is determined to be a living body, generates an operation signal for operating a predetermined device. | 2017-10-19 |
20170302275 | ELECTRONIC SWITCH WITH FORCE FEEDBACK FUNCTION - An electronic switch with force feedback function includes a base, an actuating component and a. The actuating component is movably connected to the base, and includes a. The magnetic field generating module is disposed on the base, and provides a magnetic repulsive force to the magnetic unit for force feedback while the actuating component moves close to the base. | 2017-10-19 |
20170302276 | IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - An impedance calibration circuit includes a first reference resistor electrically coupled to a calibration pad, a second reference resistor which is coupled to the first reference resistor in parallel and a resistance value of the second reference resistor is varied according to an operation voltage mode, and a calibration circuit electrically coupled to the calibration pad and configured to generate a calibration code according to a resistance value formed by the first reference resistor and the second reference resistor and calibrate an impedance value in the calibration pad according to the calibration code. | 2017-10-19 |
20170302277 | INTEGRATED CIRCUIT WITH MULTI-BIT CLOCK GATING CELLS - A multi-bit clock gating cell is used in an integrated circuit (IC) in place of single bit clock gating cells to reduce power consumption. A physical design method is used to form a clock tree of the IC. Initial positions of clock gating cells are defined with respective initial clock input paths. Selected clock gating cells are moved to modified positions in which they may be adjoining. Adjoining cells are merged by substituting a multi-bit clock gating cell having multiple gating signal inputs, corresponding gated clock outputs, and a common clock input path. A net reduction is obtained for the overall capacitance of the clock path due to reduction of the upstream capacitance of the clock path and of the resulting multi-bit clock gating cell itself, compared with the aggregate capacitance of the clock paths of the corresponding clock gating cells before moving and merging. | 2017-10-19 |
20170302278 | LOW CORE POWER LEAKAGE STRUCTURE IN IO RECEIVER DURING IO POWER DOWN - A receiver includes a first transfer gate, a first inverter, a second inverter, a second transfer gate, a third inverter, and a fourth inverter connected in series, a first power supply supplying power to the first and second inverters, a second power supply supplying power to the third and fourth inverters, a third power supply supplying power to the second transfer gate, first and second signals having opposite logic levels for controlling the first transfer gate. The third power supply is significantly lower than the first or second power supply. The leakage current of the receiver is significantly reduced in the core when the second power supply remains on but the first power supply is turned off while the performance of the receiver remains the same. | 2017-10-19 |
20170302279 | SEMICONDUCTOR CIRCUITS - A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level. | 2017-10-19 |
20170302280 | SPIN TORQUE MAJORITY GATE DEVICE - The disclosed technology generally relates to magnetic devices and more particularly to spin torque majority gate devices, and to methods of operating such devices. In one aspect, a majority gate device comprises a free ferromagnetic layer comprising 3N input zones and an output zone. The output zone has a polygon shape having 3N sides, where each input zone adjoins the output zone. The input zones are arranged around the output zone according to a 3N-fold rotational symmetry, where N is a positive integer greater than 0. The input zones are spaced apart from one another by the output zone. The majority gate device additionally comprises a plurality of input controls, where each of the input zones is magnetically coupled to a corresponding one of the plurality of input controls, where each of the input controls is configured to control the magnetization state of the corresponding input zone. The majority gate device further comprises an output sensor magnetically coupled to the output zone, where the output sensor is adapted for sensing the magnetization state of the output zone. Each input zones adjoins the output zone at one of the 3N sides. | 2017-10-19 |
20170302281 | CLOCK SYNCHRONIZATION BETWEEN TIME CALIBRATION BOARDS - Methods, devices and computer-readable mediums for clock synchronization are provided. The methods include receiving a synchronizing clock in a unit clock cycle of a measuring clock, calibrating position information of a rising edge of the synchronizing clock in the unit clock cycle, determining a phase difference between the measuring clock and the synchronizing clock in the unit clock cycle based on the calibrated position information, and compensating a photon time in the unit clock cycle with the determined phase difference as a time compensation value. | 2017-10-19 |
20170302282 | RADAR TARGET DETECTION SYSTEM FOR AUTONOMOUS VEHICLES WITH ULTRA-LOW PHASE NOISE FREQUENCY SYNTHESIZER - An object detection system for autonomous vehicle, comprising a radar unit and at least one ultra-low phase noise frequency synthesizer, is provided. The radar unit configured for detecting the presence and characteristics of one or more objects in various directions. The radar unit may include a transmitter for transmitting at least one radio signal; and a receiver for receiving the at least one radio signal returned from the one or more objects. The ultra-low phase noise frequency synthesizer may utilize Clocking device, Sampling Reference PLL, at least one fixed frequency divider, DDS and main PLL to reduce phase noise from the returned radio signal. This proposed system overcomes deficiencies of current generation state of the art Radar Systems by providing much lower level of phase noise which would result in improved performance of the radar system in terms of target detection, characterization etc. Further, a method or autonomous vehicle is also disclosed. | 2017-10-19 |
20170302283 | PHASE DETECTION METHOD BASED ON A PLURALITY OF CONSECUTIVE VALUES OF A RECEIVING SIGNAL - The invention relates to a phase detection method ( | 2017-10-19 |
20170302284 | PLL SYSTEM AND METHOD OF OPERATING SAME - The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase detector, the phase detector generating a primary control signal to adjust the variable frequency oscillator; and a secondary control subsystem having an analog-to-digital converter and a digital-to-analog converter connected in series to receive the primary control signal and generate a secondary control signal also connected to independently adjust the variable frequency oscillator. | 2017-10-19 |
20170302285 | CLOCK GENERATING DEVICE, ELECTRONIC CIRCUIT, INTEGRATED CIRCUIT AND ELECTRICAL MACHINERY - The present invention is related to a clock generating device for generating an internal clock signal having a frequency correlated with a clock frequency of an external oscillator when the clock frequency of the external oscillator is not specified in advance. A clock generating device | 2017-10-19 |
20170302286 | FREQUENCY DIVIDER CIRCUIT AND A FREQUENCY SYNTHESIZER CIRCUIT - A frequency divider circuit and a frequency synthesizer circuit are presented, comprising: | 2017-10-19 |
20170302287 | PATTERN BASED ESTIMATION OF ERRORS IN ADC - The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal. | 2017-10-19 |
20170302288 | Calibration Circuit and Calibration Method for DAC - A calibration method for a digital-to-analog converter (DAC) is disclosed. The DAC is applied to a successive approximation analog-to-digital converter (SA ADC) and includes a first capacitor, multiple second capacitors and a bridge capacitor. The method includes the steps of: (a) controlling voltages at two input terminals of a comparator of the SA ADC to be equal; (b) changing a voltage at a first terminal of the first capacitor; (b) obtaining a first output of the SA ADC; (d) after obtaining the first output, controlling voltages at the two input terminals of the comparator to be equal; (e) changing voltages at multiple first terminals of the second capacitors; (f) obtaining a second output of the SA ADC; and (g) calibrating the DAC according to the first output and the second output. | 2017-10-19 |
20170302289 | HYBRID ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter (ADC) circuit is configured to receive an analog input signal and convert the analog input signal to a digital output signal. The ADC circuit includes a first circuit that is configured to convert the analog input signal into a first digital signal that includes a first subset of bits of the digital output signal and further provide a residue signal based on the first digital signal; and a second circuit, coupled to the first circuit, and is configured to determine a discharging time duration by simultaneously amplifying and discharging the residue signal. | 2017-10-19 |
20170302290 | ANALOG TO DIGITAL CONVERTER - The present embodiments provide an analog to digital converter, including a beam splitter, M photodetectors, M amplifier modules, and an encoder. Each output end of the beam splitter is corresponding to an input end of a photodetector, an output end of each photodetector is connected to an input end of an amplifier module, and an output end of each amplifier module is connected to an input end of the encoder. The beam splitter splits an inputted analog optical signal into M optical signals, outputs each optical signal to a corresponding photodetector to convert each optical signal into a current signal, inputs each current signal to a corresponding amplifier module to generate an output voltage, and outputs the output voltage to a corresponding input end of the encoder. | 2017-10-19 |
20170302291 | LINEARIZED OPTICAL DIGITAL-TO-ANALOG MODULATOR - A system for converting digital data into a modulated optical signal, comprises an electrically controllable device having M actuating electrodes. The device provides an optical signal that is modulated in response to binary voltages applied to the actuating electrodes. The system also comprises a digital-to-digital converter that provides a mapping of input data words to binary actuation vectors of M bits and supplies the binary actuation vectors as M bits of binary actuation voltages to the M actuating electrodes, where M is larger than the number of bits in each input data word. The digital-to-digital converter is enabled to map each digital input data word to a binary actuation vector by selecting a binary actuation vector from a subset of binary actuation vectors available to represent each of the input data words. | 2017-10-19 |
20170302292 | COMPUTER-READABLE RECORDING MEDIUM, ENCODING DEVICE, AND ENCODING METHOD - The encoding device | 2017-10-19 |
20170302293 | FAST UPDATE OF DATA PACKET CHECKSUMS - A device includes a processor and a checksum module, wherein the checksum module calculates, for first data, an updated checksum that complies with Internet Engineering Task Force Request For Comments Number 1624 using twos-complement arithmetic. The processor replaces the original checksum with the updated checksum to update a data packet. | 2017-10-19 |
20170302294 | DATA PROCESSING METHOD AND SYSTEM BASED ON QUASI-CYCLIC LDPC - A data processing method based on a quasi-cyclic LDPC includes: when a size of service data is less than a magnitude of information bit of the quasi-cyclic LDPC, calculating a difference value between the magnitude of the information bit of the quasi-cyclic LDPC and the size of the service data, and filling the service data with the same amount of known data as the difference value (S | 2017-10-19 |
20170302295 | LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 7/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME - A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). | 2017-10-19 |
20170302296 | ENCODER, DECODER, TRANSMISSION DEVICE, AND RECEPTION DEVICE - A transmission device and reception device for digital data that have excellent resistance to noise are provided. An encoder ( | 2017-10-19 |
20170302297 | LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME - A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). | 2017-10-19 |
20170302298 | LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME - A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). | 2017-10-19 |
20170302299 | DATA PROCESSING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT - A data processing method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first write data; performing a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data and generating first transition data; performing a second stage encoding operation of the LDPC code on the first transition data and generating a first error correcting code (ECC); receiving second write data; and performing the first stage encoding operation of the LDPC code on the second write data during a time period of performing the second stage encoding operation of the LDPC code on the first transition data. Accordingly, the data processing efficiency corresponding to the LDPC code can be improved. | 2017-10-19 |
20170302300 | COMMUNICATION UNIT - A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal. | 2017-10-19 |
20170302301 | COMMUNICATION UNIT - A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal. | 2017-10-19 |
20170302302 | LOW-NOISE BLOCK DOWNCONVERTER AND METHOD FOR THE SAME - An LNB downconverter comprising: two LNBs configured to receive their respective satellite signals: the first and second LNB being configured to output, four IF signals of different polarization and frequency range to a respective first and second Cross-bar Switch (CBS); wherein the first and second CBS, are configured to accept four RF inputs, and routing them, to any of four outputs, as configured by a Controller: wherein outputs of CBSs are connected to respective Satellite Channel Routers (SCRs) configured by the Controller to shift the frequency of their input signals to fixed intermediate frequencies; wherein outputs of SCRs are connected to respective Band Pass Filters (BPFs) whereas the fixed intermediate frequencies of SCRs are different and wherein the band passed by each BPF is non-overlapping; an Adder adding the signals on different frequencies, output by each BPF, to form a single output signal comprising data from both satellite signals. | 2017-10-19 |
20170302303 | DEVICE, SYSTEM AND METHOD OF CONFIGURING A RADIO TRANSCEIVER - A device, system and method of configuring a radio transceiver are described. In particular, there is described an RF front-end for transmitting wireless communication signals, the RF front-end comprising a plurality of elements, and wherein the RF front-end is configured to obtain an RF protection class signal and to selectively apply one or more of the plurality of elements to a transmitted signal based on the obtained RF protection class signal. | 2017-10-19 |
20170302304 | AMPLIFIER DEVICE FOR HIGH FREQUENCY SIGNALS - An amplifier device for high frequency signals, in particular a linear high frequency amplifier device, which comprises at least one input, an incoming line, a pre-distortion unit, in particular an adaptive pre-distortion unit, an amplifier unit, in particular a non-linear power amplifier unit, a transmission line, a feedback unit, and an output. The output is connected to the amplifier unit via the transmission line. In addition, the at least one input is connected to the pre-distortion unit such that two incoming branch lines are provided which are interconnected by a switching unit. A first incoming branch line of the incoming branch lines comprises a down-converter being arranged between the at least one input and the pre-distortion unit. | 2017-10-19 |
20170302305 | ELECTRONIC DEVICE - This electronic device includes a wearing detector, provided at a position that comes close to or in contact with a human body when the electronic device is worn by a user, that detects wearing of the electronic device by the user, an antenna that transmits radio waves, and a controller that restricts transmission of radio waves from the antenna when wearing is detected by the wearing detector. | 2017-10-19 |
20170302306 | Electronic Device With Millimeter Wave Antennas - An electronic device may be provided with wireless circuitry. The wireless circuitry may include one or more antennas. The antennas may include phased antenna arrays each of which includes multiple antenna elements. Phased antenna arrays may be mounted along edges of a housing for the electronic device, behind a dielectric window such as a dielectric logo window in the housing, in alignment with dielectric housing portions at corners of the housing, or elsewhere in the electronic device. A phased antenna array may include arrays of patch antenna elements on dielectric layers separated by a ground layer. A baseband processor may distribute wireless signals to the phased antenna arrays at intermediate frequencies over intermediate frequency signal paths. Transceiver circuits at the phased antenna arrays may include upconverters and downconverters coupled to the intermediate frequency signal paths. | 2017-10-19 |
20170302307 | SEMICONDUCTOR DEVICE AND RADIO COMMUNICATION DEVICE - A semiconductor device ( | 2017-10-19 |
20170302308 | TRANSMITTER HARMONICS CALIBRATION TO IMPROVE TRANSMIT LINEARITY - An apparatus comprises: radio frequency (RF) transceiver circuitry for electrical coupling to an antenna and including: a local oscillator (LO) circuit configured to generate a LO signal, and a mixer circuit configured to mix a CW tone signal with the LO signal; a measurement receiver path configured to measure an antenna signal, wherein the antenna signal includes the CW tone signal mixed with the LO signal; and baseband processing circuitry electrically coupled to the measurement receiver path and configured to adjust a clock duty ratio of the LO signal to reduce one or more counter intermodulation (CIM) signals in the antenna signal. | 2017-10-19 |
20170302309 | DATA TRANSMISSION TERMINAL, DATA TRANSMISSION/RECEPTION SYSTEM AND DATA TRANSMISSION METHOD - A data transmission terminal according to the present invention comprises: a communication unit which performs communication with a server; a noise collection unit which collects a peripheral noise; a data transmission unit which transmits data to a data reception terminal through an audible frequency band; and a control unit which analyzes the collected noise to generate a noise analysis result and controls the communication unit to transmit the noise analysis result to the server. | 2017-10-19 |
20170302310 | SELECTIVELY ACTIVATING OSCILLATION MODULES BASED ON SIGNAL STRENGTHS - At least some embodiments are directed to a receiver system that comprises a first oscillation module configured to provide oscillating signals of differing frequencies and a second oscillation module configured to provide other oscillating signals of the differing frequencies. The second oscillation module is configured to produce less noise than the first oscillation module. A controller is coupled to the first and second oscillation modules and configured to selectively activate and deactivate each of the first and second oscillation modules based on signal strengths of primary signals received via a wireless medium and based on signal strengths of interference signals received via the wireless medium. | 2017-10-19 |
20170302311 | FM RECEPTION DEVICE, FM RECEPTION METHOD FOR RECEIVING FM SIGNALS - A first local oscillator generates a modulation signal of a predetermined frequency. A second local oscillator outputs a local oscillation signal frequency-modulated by using the modulation signal from the first local oscillator. A quadrature detection unit subjects an FM signal to quadrature detection by using the local oscillation signal output from the second local oscillator and outputs a base band signal. A first reduction unit and a second reduction unit reduce a direct current component contained in the base band signal. A correction unit restores the direct current component by correcting the base band signal such that the base band signal is centered around an origin of a polar coordinate system on an IQ plane. An FM detection unit subjects the corrected base band signal to FM detection and generates a detection signal. | 2017-10-19 |
20170302312 | Method for Transmitting Reference Signal in Cell that Uses Unlicensed Frequency Band and Device - A system and method for transmitting a reference signal in a cell that uses an unlicensed frequency band. The method includes determining a candidate resource set that is used when a first reference signal is transmitted in the cell that uses the unlicensed frequency band, where the candidate resource set includes a preset resource and at least one flexible candidate resource, determining a first candidate resource that is used when the first reference signal is transmitted in the cell that uses the unlicensed frequency band, where a channel on the unlicensed frequency band corresponding to the first candidate resource is in an idle state, and the first candidate resource is the preset resource or a flexible candidate resource in the candidate resource set, and sending the first reference signal on the first candidate resource. | 2017-10-19 |
20170302313 | METHOD AND SECURITY MODULE FOR ADAPTATION OF A REFERENCE VALUE FOR GENERATION OF A BIT STREAM - A method and a circuit are arranged for adapting a first reference value for generating a first bit stream from an input signal by a first amplitude adapting unit. The input signal comprises a first and a second signal. The first signal and the second signal form a baseband sum signal. A first non-linear component demodulates the input signal and outputs a demodulated input signal. The amplitude adapting unit outputs the first bit stream from the demodulated input signal on the basis of a first reference value. A reference-value adapting unit comprises a detection unit which detects the first and the second signal. Upon discontinuation of the first and second signals, an adjusting unit adjusts the first reference value to a basic reference value. | 2017-10-19 |
20170302314 | Adaptive Data Recovery from Distorted Signals - This application presents an adaptive data recovery from distorted signals (ADRDS) of original data symbols from intervals or parameters of tone signals derived from a received OFDM signal, including responding to dynamic distortions introduced to the received OFDM signal by an OFDM transmission channel. Such ADRDS is implemented by converting back the derived intervals or parameters into original data symbols corresponding to distinctive sets of the intervals or parameters which the derived intervals or parameters belong to. | 2017-10-19 |
20170302315 | SCHEDULING METHOD AND APPARATUS IN WIRELESS COMMUNICATION SYSTEM - The present disclosure relates to a 5G or pre-5G communication system to be provided for supporting a higher data transfer rate beyond a 4G communication system such as LTE. The present invention relates to a NOMA system based FQAM connection method and an apparatus therefor. The present invention can increase the user transfer rate at a cell boundary. The scheduling method in a wireless communication system, according to an embodiment of the present invention, comprises a step of receiving a signal-to-interference-noise ratio (SINR) value and an alpha value from a terminal; a step of determining, on the basis of the SINR value and the alpha value, a Gaussian SINR value; a step of pairing users on the basis of the Gaussian SINR value; and a step of re-computing MCS on the basis of a re-computed alpha value. | 2017-10-19 |
20170302316 | Ultra-Low-Power RF Receiver Frontend With Tunable Matching Networks - A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array. | 2017-10-19 |
20170302317 | HIGH FREQUENCY FRONT-END CIRCUIT AND COMMUNICATION DEVICE - A front-end circuit includes an antenna terminal, front-end terminals (Pfe | 2017-10-19 |
20170302318 | FM RECEPTION DEVICE, FM RECEPTION METHOD FOR RECEIVING FM SIGNALS - A quadrature detection unit subjects an FM signal to quadrature detection using a local oscillation signal and outputs a base band signal. A first correction unit and a second correction unit correct the base band signal using a DC offset correction value. A DC offset detection unit subjects the corrected base band signal to rectangular to polar conversion and derives the DC offset correction value such that amplitudes in a plurality of phase domains defined in an IQ plane approximate each other. An FM detection unit subjects the corrected base band signal to FM detection and generates a detection signal. An addition unit adds an offset to the detection signal. An AFC unit generates a control signal for controlling a frequency of a local oscillation signal based on the detection signal to which the offset is added. | 2017-10-19 |
20170302319 | WEARABLE DEVICES AND METHODS FOR DATA TRANSMISSION AND RECEPTION THEREWITH - In a wearable device provided, the TCP/IP protocol and wireless communications protocol are separated from a primary MCU of the wearable device and are integrated into a secondary MCU integrated with a communication unit and coupled to an RF unit, the secondary MCU together with the communication unit and the RF unit acting as a communication module. The communication module is configured to perform data transmission with an external terminal or server using the wireless communications protocol and TCP/IP protocol. A method for data transmission or reception is also provided. | 2017-10-19 |
20170302320 | WRISTBAND-TYPE HANDSET AND WRISTBAND-TYPE ALERTING DEVICE - Proposed is a bracelet-type transmission/reception device comprising: a cartilage conduction vibration source provided in a portion to be attached to a wrist; a speaker; a variable directional microphone; and a control unit which sets the directivity of the variable directional microphone to the back side of a hand when the speaker is used and sets the directivity of the variable directional microphone to the palm side of the hand when the cartilage conduction vibration source is used. The bracelet-type transmission/reception device is provided together with a display means for information relating to a transmission/reception method or a handling explanation medium or advertising medium having the information relating to the transmission/reception method. An example of a method for use thereof is to conduct the vibration of the cartilage conduction vibration source to a thumb and to bring the thumb into contact with a tragus in a state where the back of the hand faces forward. The cartilage conduction vibration source is also used as a vibration source of an incoming vibrator, and when the cartilage conduction vibration source vibrates for cartilage conduction, a vibrational component in a low-frequency range that induces a sense of vibration is cut. The cartilage conduction vibration source vibrates for notification by announcement voice data in a storage unit. | 2017-10-19 |
20170302321 | PORTABLE ELECTRONIC DEVICE HOLDER FOR USE IN A VEHICLE - A portable electronic device holder of a vehicle is provided herein. A housing defines a space therein and has an open end. A first and second number of retention members are coupled to opposing side walls of the housing and are disposed to extend into the space. The first and second number of retention members cooperate to hold a portable electronic device inserted into the space through the open end. | 2017-10-19 |
20170302322 | UNIVERSAL ROTATING AND LOCKING TABLET CASE - A rotatable case for holding an electronic device during video conferencing or gaming. The case includes a device-surrounding frame, a main body component with a lower planar surface, a rotatable bottom, an upper surface, one or connecting sidewalls and a groove in which an axially tilting rod can be locked in place. That rod includes spaced fingers for holding the framed device and preventing it from being accidentally pulled down, knocked over or removed from its locking fingers. The case also includes means for securing the main body component to a planar surface. | 2017-10-19 |
20170302323 | BIODEGRADABLE PROTECTIVE DEVICE - A biodegradable protective device adapted for a mobile device includes a main body and a protective portion. The main body is made of biodegradable plastic. The protective portion is made of biodegradable material, and the protective portion is connected to the main body and used to protect the mobile device from damage. | 2017-10-19 |
20170302324 | COMBINATION MOBILE PHONE CASE AND ELECTRONIC CIGARETTE - A mobile phone case comprising a protective case element designed for coupling to a mobile phone with a first rechargeable battery, a wireless charging system embedded in the case element, a terminal conductively coupled with the wireless charging system, the terminal configured for conductively coupling with a power port in the mobile phone, an electronic cigarette element removably coupled to the case element, wherein when the terminal is conductively coupled with the power port in the mobile phone, and the case element is placed in proximity to a charging station, the wireless charging system charges the first rechargeable battery of the mobile phone and the second rechargeable battery of the electronic cigarette element. | 2017-10-19 |
20170302325 | RADIO FREQUENCY SYSTEM-IN-PACKAGE INCLUDING A STACKED SYSTEM-ON-CHIP - A packaged module for use in a wireless communication device has a substrate supporting a crystal and a first die that includes at least a microprocessor and one or more of radio frequency transmitter circuitry and radio frequency receiver circuitry. The crystal is disposed between the first die and the substrate. An overmold encloses the crystal and the first die. The substrate also supports a second die that includes at least a power amplifier for amplifying a radio frequency input signal where the second die is disposed on an opposite side of the substrate from the first die and the crystal. | 2017-10-19 |
20170302326 | Electronic Device Having Antenna Tuning Integrated Circuits With Sensors - An electronic device may be provided with wireless circuitry. The wireless circuitry may include one or more antennas. An antenna may have an antenna feed that is coupled to a radio-frequency transceiver with a transmission line. An impedance matching circuit may be coupled to the antenna feed to match the impedance of the transmission line and the antenna. The impedance matching circuit and tunable circuitry in the antenna may be formed using integrated circuits. Each integrated circuit may include switching circuitry that is used in switching components such as inductors and capacitors into use. Sensors such as temperature sensors, current and voltage sensors, power sensors, and impedance sensors may be integrated into the integrated circuits. Each integrated circuit may store settings for the switching circuitry and may include communications and control circuitry for communicating with external circuits and processing sensor data. | 2017-10-19 |
20170302327 | TRANSMIT LEAKAGE CANCELLATION IN A WIDE BANDWIDTH DISTRIBUTED ANTENNA SYSTEM - A system and methods for cancelling transmission leakage signals in a wide bandwidth Distributed Antenna System (“DAS”) having remote units is disclosed. An internal cancellation circuit within the remote unit is employed to reduce the transmitted leakage signals by generating a cancellation signal. This cancellation signal is added to the received signal to cancel the transmission leakage signal in the receiving signal path. A pilot signal generation circuit is employed to optimize the cancellation circuit operating parameters. The frequency of the pilot signal is swept over a range to determine the pilot frequency having the highest electromagnetic coupling. The amplitude and phase of the cancellation signal is then optimized to minimize the level of transmission leakage in the receiving transmission path. | 2017-10-19 |
20170302328 | HIGH-FREQUENCY POWER AMPLIFYING MODULE AND COMMUNICATION APPARATUS - A high-frequency power amplifying module is provided for a communication device that simultaneously uses at least a radio wave in a first band and a radio wave in a second band, and a first high-frequency power amplifier for the first band and a second high-frequency power amplifier for the second band are mounted. The first band and the second band are frequency bands that produce intermodulation distortion of a frequency included in the receive frequency band of the second band, due to a transmit frequency of the first band received by the first high-frequency power amplifier and a transmit frequency of the second band received h the second high-frequency power amplifier. The second high-frequency power amplifier includes a filter that blocks a signal at the transmit frequency of the first band. | 2017-10-19 |
20170302329 | METHOD, SYSTEM, AND APPARATUS FOR SPECTRUM SENSING OF RADAR - An improved technique for detecting the presence or absence of one or more predetermined signals in a shared spectrum. In accordance with the disclosed embodiments, a received RF signal may be down-converted to a baseband signal, which is subsequently processed by a spectrum sensor to detect the presence or absence of a predetermined signal, such as a predetermined radar signal. The spectrum sensor may transform the baseband signal to the frequency domain, for example using a fast Fourier transform, to generate a corresponding set of frequency components. The spectrum sensor multiplies the frequency components of the baseband signal with the frequency response of a matched filter having a set of coefficients corresponding to the predetermined signal. The spectrum sensor may convert the matched-filter output signal to the time domain, for example using an inverse fast Fourier transform, and then may determine a value indicative of the signal power that it compares with a known threshold value. The spectrum sensor may determine the presence or absence of the predetermined signal in the received RF signal based on the result of the comparison, and may use the results of its determination to cause the reconfiguration of a transmitter that may be used to transmit RF signals in the same shared spectrum as the received RF signal. | 2017-10-19 |
20170302330 | MULTI-CHANNEL SPREAD SPECTRUM RETURN CHANNEL FOR ULTRA SMALL APERTURE TERMINALS (USATS) - A return channel system for ultra-small aperture terminals has a spreader that receives an input signal and outputs a spread spectrum signal having multiple replicated signals with a lower power than the input signal. A de-spreader includes a de-multiplexer that receives the spread spectrum signal via satellite. The de-multiplexer separates the spread spectrum signal into a first channel having a first signal and a second channel having a second signal. The de-spreader also has an offset compensation circuit having a phase estimator configured to estimate a phase offset between a phase of the first signal and a phase of the second signal. And a phase adjustor that receives the second signal and adjusts the phase of the second signal to align with the phase of the first signal to provide a phase-adjusted second signal. A summer combines the first signal with the phase-adjusted second signal to provide a composite signal. | 2017-10-19 |
20170302331 | GENERATION METHOD FOR DISTRIBUTED CHANNEL HOPPING SYSTEM IN COGNITIVE RADIO NETWORKS - A method for generating a distributed channel hopping system in cognitive radio networks. The method includes: 1) providing a symmetric asynchronous CH system comprising n periodic CH sequences such that each period of a CH sequence comprises exactly L frames and each frame comprises n timeslots; 2) labelling the n periodic CH sequences in the constructed CH system; 3) hopping, by the CH sequence i, to the channel (lM+j mod N) in each timeslot t | 2017-10-19 |
20170302332 | METHOD AND APPARATUS FOR MITIGATING SIGNAL INTERFERENCE IN A FEEDBACK SYSTEM - A system that incorporates the subject disclosure may include, for example, a process that includes adjusting a filter in electrical communication between an input terminal and a demodulator. The filter is applied to an information bearing signal, e.g., to mitigate interference, received at the input terminal, resulting in a filtered signal. An error signal is received, indicative of errors detected within information obtained by demodulation of a modulated carrier of the filtered signal. A modified filter state is determined in response to the error signal and the filter is adjusted according to the modified filter state, e.g., to improve mitigation of the interference. Other embodiments are disclosed. | 2017-10-19 |
20170302333 | METHOD AND APPARATUS FOR COMMUNICATING NETWORK MANAGEMENT TRAFFIC OVER A NETWORK - Aspects of the subject disclosure may include, for example, determining whether communications are encrypted, determining a communication type for the communications according to sensitivity criteria, encrypting the communications according to the communication type to generate encrypted communications, and transmitting to a second network device the encrypted communications. Other embodiments are disclosed. | 2017-10-19 |
20170302334 | ELECTRICAL DEVICE FOR MULTIPLE-SIGNAL INJECTION ONTO MULTIPLE-CONDUCTOR COMMUNICATIONS MEDIUM - An electrical device includes signal ports, transformers, and a differential mode device. The transformers are in communication with the signal ports, respectively. The transformers are configured to receive input signals, respectively, from the signal ports. Each transformer is configured to inject the respective input signal onto a pair of output lines of the transformer. The differential mode device is connected to a first output line of the pair of output lines of a first transformer exclusive of connection to a second output line of the first transformer. The differential mode device is configured to inject a signal from the first output line onto the pair of output lines of a second transformer. Signals from the pair of output lines of the second transformer are injected onto a pair of conductors, respectively, of a communications medium. | 2017-10-19 |