42nd week of 2017 patent applcation highlights part 60 |
Patent application number | Title | Published |
20170301635 | ELECTRONIC CHIP - An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth. | 2017-10-19 |
20170301636 | ELECTROSTATIC DISCHARGE PROTECTION FOR ANTENNA USING VIAS - An integrated circuit device is formed to include a plurality of vias that connect an antenna to a ground reference. This configuration of the integrated circuit device provides an electrical path from the antenna to ground, thereby preventing the buildup of charge at the antenna. The vias thereby reduce the likelihood of a potential difference between components of the integrated circuit device and the antenna, in turn reducing the likelihood of electrostatic discharge at the integrated circuit device. | 2017-10-19 |
20170301637 | Contact Pad For Semiconductor Device - A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound. | 2017-10-19 |
20170301638 | INTERCONNECT ETCH WITH POLYMER LAYER EDGE PROTECTION - Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask. | 2017-10-19 |
20170301639 | MICROELECTRONIC DEVICES AND METHODS FOR FILLING VIAS IN MICROELECTRONIC DEVICES - Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece. | 2017-10-19 |
20170301640 | SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR CHIP CONNECTED IN A FLIP CHIP MANNER - A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode. | 2017-10-19 |
20170301641 | Three-Dimensional Chip Stack and Method of Forming the Same - A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region. | 2017-10-19 |
20170301642 | PRINTED WIRING BOARD - A printed wiring board according to an embodiment includes a metal plate and a wiring member. The meal plate includes a current path part, which is a main current path of an electronic part mounted on or above a front surface of the metal plate, and a heat radiation part, which radiates heat generated from the electronic part. The wiring member is arranged on or above a back surface of the metal plate. The current path part and the heat radiation part are in the same layer to be integrally formed with the wiring member. | 2017-10-19 |
20170301643 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted. | 2017-10-19 |
20170301644 | CLAMPING SYSTEM, WIRE BONDING MACHINE, AND METHOD FOR BONDING WIRES - A clamping system, a wire bonding machine and a method for bonding wires are provided. An exemplary clamping system includes a clamping device. The clamping device includes: at least one linear guide rail; a first clamping rod arranged perpendicular to the linear guide rail; and a second clamping rod arranged perpendicular to the linear guide rail and parallel to the first clamping rod. | 2017-10-19 |
20170301645 | Method and Apparatus for Connecting Packages onto Printed Circuit Boards - Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer flux may be provided in the process to mount an IC package to a PCB. The polymer flux may be provided on connectors of the IC package, or provided on PCB contact pad and/or pre-solder of the PCB. When the IC package is mounted onto the PCB, the polymer flux may cover a part of the connector, and may extend to cover a surface of the molding compound on the IC package. The polymer flux may completely cover the connector as well. The polymer flux delivers a fluxing component that facilitates smooth solder joint formation as well as a polymer component that offers added device protection by encapsulating individual connectors. The polymer component may be an epoxy. | 2017-10-19 |
20170301646 | METHOD OF BONDING SEMICONDUCTOR SUBSTRATES - The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art. | 2017-10-19 |
20170301647 | RADIO FREQUENCY TRANSMISSION LINE WITH FINISH PLATING ON CONDUCTIVE LAYER - This disclosure relates to a radio frequency (RF) transmission line for high performance RF applications. The RF transmission line includes a conductive layer and finish plating on the conductive layer. The finish plating includes a gold layer, a palladium layer proximate the gold layer, and a nickel layer proximate the palladium layer. The nickel layer has a thickness that allows a radio frequency signal received at the gold layer to penetrate the nickel layer and propagate in the conductive layer. | 2017-10-19 |
20170301648 | Methods and Structures for Packaging Semiconductor Dies - A method of packaging a semiconductor device, comprising: attaching a plurality of dies to a carrier wafer, wherein each of the dies includes a top surface; forming a molding compound layer over the dies, wherein the top surface of the dies are covered by the molding compound layer; removing a first portion of the molding compound layer; removing a second portion of the molding compound layer such that the top surface of the dies is not covered by the molding compound layer; forming a redistribution layer (RDL) over the top surface of the dies; forming a plurality of solder balls over at least a portion of the RDL; and singulating the dies. | 2017-10-19 |
20170301649 | Chip Packages and Methods of Manufacture Thereof - Chip packages and method of manufacturing the same are disclosed. In an embodiment, a chip package may include: a redistribution layer (RDL); a first chip including a plurality of first contact pads, the plurality of first contact pads facing the RDL; a second chip disposed between the first chip and the redistribution layer (RDL) wherein a portion of the first chip is disposed outside a lateral extent of the second chip; and a conductive via laterally separated from the second chip, the conductive via extending between the RDL and a first contact pad of the plurality of first contact pads, the first contact pad located in the portion of the first chip disposed outside the lateral extent of the second chip. | 2017-10-19 |
20170301650 | 3DIC Formation with Dies Bonded to Formed RDLs - A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer. | 2017-10-19 |
20170301651 | WAFER LEVEL SYSTEM IN PACKAGE (SIP) USING A RECONSTITUTED WAFER AND METHOD OF MAKING - A package such as a system in package (SiP) includes a first die disposed in a first mold layer and coupled to a first dielectric layer disposed above the first mold and a second die disposed in a second mold layer and coupled to a second dielectric layer disposed above the second die. A pillar is disposed through the second mold layer and is coupled to a first metal layer disposed above the first dielectric layer. The first metal layer is coupled to the first die, and the pillar is coupled to a second metal layer disposed above the second dielectric layer. | 2017-10-19 |
20170301652 | METHOD OF FABRICATING PACKAGE SUBSTRATES - This disclosure provides a package substrate fabrication method including: forming a first conductive wire and a first connecting unit on a first carrier substrate; forming a first dielectric layer on the first carrier substrate while enabling an end face of the first connecting unit to be exposed; bonding a second carrier substrate to the first dielectric layer and removing the first carrier substrate; disposing a first circuit chip and a second connecting unit on the first conductive wire; forming a second dielectric layer on the second carrier substrate while enabling the first circuit chip and the second connecting unit to be surrounded by the second dielectric layer and an end face of the second connecting unit to be exposed; forming a second conductive wire on the second dielectric layer; disposing a second circuit chip on the second conductive wire; and forming a third dielectric layer on the second carrier substrate. | 2017-10-19 |
20170301653 | RADIO FREQUENCY SYSTEM-IN-PACKAGE WITH STACKED CLOCKING CRYSTAL - A packaged module for use in a wireless communication device has a substrate supporting a crystal and a first die that includes at least a microprocessor and one or more of radio frequency transmitter circuitry and radio frequency receiver circuitry. The first die is disposed between the crystal and the substrate. An overmold encloses the first die and the crystal. The substrate also supports a second die that includes at least a power amplifier for amplifying a radio frequency input signal, where the second die is disposed on an opposite side of the substrate from the first die and the crystal. | 2017-10-19 |
20170301654 | SYSTEM IN PACKAGE WITH VERTICALLY ARRANGED RADIO FREQUENCY COMPONENTRY - A packaged module for use in a wireless communication device has a substrate supporting a first integrated circuit die that implements at least a portion of a radio frequency baseband subsystem and a second integrated circuit die that implements at least a portion of a radio frequency front end including a radio frequency power amplifier. The substrate is disposed between the first integrated circuit die and the second integrated circuit die. An overmold encloses one of the first integrated circuit die and the second integrated circuit die. | 2017-10-19 |
20170301655 | REDUCED FORM FACTOR RADIO FREQUENCY SYSTEM-IN-PACKAGE - A packaged module for a radio frequency wireless device has a substrate supporting a first wireless device component and a second wireless device component where the first wireless device component is between the second wireless device component and a first surface of the substrate. At least a first overhanging portion of the second wireless device component extends beyond at least a portion of the periphery of the first wireless device component. | 2017-10-19 |
20170301656 | HETEROGENEOUS ANNEALING METHOD AND DEVICE - A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts. | 2017-10-19 |
20170301657 | THREE DIMENSIONAL INTEGRATED CIRCUIT - A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric structures and the conductive structures to define a cleave plane in the first substrate. The first substrate is cleaved at the cleave plane to obtain a cleaved layer having the dielectric structure and the conductive structures. The cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers. | 2017-10-19 |
20170301658 | FABRICATION METHOD OF PACKAGE STRUCTURE - A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process. | 2017-10-19 |
20170301659 | DEVICE ARRANGEMENT STRUCTURE ASSEMBLY AND TEST METHOD - An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer. | 2017-10-19 |
20170301660 | METHOD OF FORMING AN ARRAY OF A MULTI-DEVICE UNIT CELL - Backplane-side bonding structures including a common metal are formed on a backplane. Multiple source coupons are provided such that each source coupon includes a transfer substrate and an array of devices to be transferred. Each array of devices are arranged such that each array includes a unit cell structure including multiple devices of the same type and different types of bonding structures including different metals that provide different eutectic temperatures with the common metal. Different types of devices can be sequentially transferred to the backplane by sequentially applying the supply coupons and selecting devices providing progressively higher eutectic temperatures between respective bonding pads and the backplane-side bonding structures. Previously transferred devices stay on the backplane during subsequent transfer processes, enabling formation of arrays of different devices on the backplane. | 2017-10-19 |
20170301661 | OPTICAL APPARATUS - An optical apparatus includes a substrate | 2017-10-19 |
20170301662 | POWER CONVERSION APPARATUS - A power conversion apparatus performs power conversion. The power conversion apparatus includes a semiconductor module and a cooler. The semiconductor module includes an insulated-gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor, and a lead frame. The insulated-gate bipolar transistor and the metal-oxide-semiconductor field-effect transistor are connected in parallel to each other and provided on the same lead frame. The cooler has a coolant flow passage. The coolant flow passage extends such that the coolant flow passage and the lead frame of the semiconductor module are opposed to each other. The semiconductor module is configured such that the metal-oxide-semiconductor field-effect transistor is not disposed further downstream than the insulated-gate bipolar transistor in a flow direction of a coolant in the coolant flow passage of the cooler. | 2017-10-19 |
20170301663 | MECHANISMS FOR FORMING PACKAGE STRUCTURE - A package structure is provided. The package structure includes a semiconductor die and a protection layer surrounding sidewalls of the semiconductor die. The package structure also includes a conductive structure penetrating through the protection layer. The package structure further includes an interfacial layer between the protection layer and the conductive structure. The interfacial layer is made of an insulating material, and the interfacial layer is in direct contact with the protection layer. The interfacial layer extends across a back side of the semiconductor die. | 2017-10-19 |
20170301664 | SEMICONDUCTOR DEVICE - Based on a basic idea to effectively utilize a space created in a third wiring layer (M | 2017-10-19 |
20170301665 | SEMICONDUCTOR DEVICE AND DESIGN METHOD OF SAME - A semiconductor device includes a semiconductor substrate having a predetermined region in which a standard cell is disposed, and also includes: a first circuit connected to a first ground power line; a second circuit that is connected to a second ground power line and formed from the standard cells; and a protection circuit interposed and connected between the first circuit and the second circuit. The protection circuit includes: a resistor connected in series between the first circuit and the second circuit; and a protector that is interposed and connected between a node of the resistor on the second circuit side and the second ground power line and clamps a potential difference between the node and the second ground power line to a predetermined voltage or lower. The protection circuit is formed in a protection cell disposed in the predetermined region. | 2017-10-19 |
20170301666 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE INTEGRATED WITH VERTICAL FIELD EFFECT TRANSISTOR - An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel. | 2017-10-19 |
20170301667 | 3D SEMICONDUCTOR STRUCTURE AND DEVICE - A 3D structure, the structure including: a first stratum overlaid by a second stratum, the second stratum is less than two microns thick, where the first stratum includes an array of memory cells including at least four rows of memory cells, each of the rows is controlled by a bit-line, where the array of memory cells includes a plurality of columns of memory cells, each of the columns is controlled by a word-line, and where the second stratum includes memory control circuits directly connected to the bit-lines and the word-lines. | 2017-10-19 |
20170301668 | INTEGRATED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate. | 2017-10-19 |
20170301669 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having an element isolation structure formed in the main surface of semiconductor substrate, having a space in a trench, and prevented from having deteriorated performance due to an increase in the height of the top portion of the space. A trench portion is formed in the main surface of a semiconductor substrate by using a hard-mask insulating film. A first insulating film that covers the upper surface of the hard-mask insulating film and the surface of the trench portion is formed, followed by etch-back of the first insulating film to expose the upper surface of the hard-mask insulating film. Then, second and third insulating films that cover the upper surface of the hard-mask insulating film and the surface of the trench portion are formed to form a space in the trench portion. | 2017-10-19 |
20170301670 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate. | 2017-10-19 |
20170301671 | FIN PITCH SCALING FOR HIGH VOLTAGE DEVICES AND LOW VOLTAGE DEVICES ON THE SAME WAFER - A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor. | 2017-10-19 |
20170301672 | SUB 59 MV / DECADE SI CMOS COMPATIBLE TUNNEL FET AS FOOTER TRANSISTOR FOR POWER GATING - An integrated circuit (IC) including a circuit block including a plurality of complementary metal oxide semiconductor field-effect transistors (CMOSFETs), and a tunnel field-effect transistor (TFET) between the circuit block and ground for power gating the circuit block. | 2017-10-19 |
20170301673 | HIGH VOLTAGE CMOS WITH TRIPLE GATE OXIDE - An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors. | 2017-10-19 |
20170301674 | Three-Dimensional Vertical One-Time-Programmable Memory - The present invention discloses a three-dimensional vertical read-only memory (3D-OTP | 2017-10-19 |
20170301675 | ULTRA HIGH DENSITY INTEGRATED COMPOSITE CAPACITOR - Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS) capacitor formed from a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal. The drain terminal and the source terminal are not electrically connected to any other node, and the gate terminal and the body terminal form respective first and second terminals of the MOS capacitor. The IC chip also includes an electrical conductor coupled to one of the gate terminal or the body terminal of the MOS transistor and configured to deliver a voltage to operate the MOS capacitor in an accumulation mode. | 2017-10-19 |
20170301676 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND APPARATUS USED IN FABRICATION THEREOF - A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided. | 2017-10-19 |
20170301677 | NANO-IMPRINTED SELF-ALIGNED MULTI-LEVEL PROCESSING METHOD - The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4 F | 2017-10-19 |
20170301678 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof. | 2017-10-19 |
20170301679 | METHOD FOR PRODUCING AN SGT-INCLUDING SEMICONDUCTOR DEVICE - A method for producing an SGT-including semiconductor device includes forming a gate insulating layer on an outer periphery of a Si pillar, forming a gate conductor layer on the gate insulating layer, and forming an oxide layer on the gate conductor layer. Then a hydrogen fluoride ion diffusion layer containing hydrogen fluoride ions is formed so as to make contact with the oxide layer and lie at an intermediate position of the Si pillar. A part of the oxide film in contact with the hydrogen fluoride ion diffusion layer is etched and an opening is thereby formed on the outer periphery of the Si pillar. | 2017-10-19 |
20170301680 | METAL FINFET ANTI-FUSE - Semiconductor structures containing FinFET anti-fuses with reduced breakdown voltage are provided which can be readily integrated with high performance FinFETs. The anti-fuse includes at least one metal structure having a faceted sidewall. The sharp corner of the faceted sidewall of the at least one metal structure causes an electric field concentration, thus reducing the breakdown voltage of the anti-fuse. | 2017-10-19 |
20170301681 | CONFIGURABLE ROM - A configurable read only memory (ROM) including a number of memory cells. The memory cells include first-type memory cells that are electrically-programmable antifuses and second-type memory cells that are antifuses programmed by masking. | 2017-10-19 |
20170301682 | ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY - An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line. | 2017-10-19 |
20170301683 | SEMICONDUCTOR DEVICE WITH SPLIT GATE FLASH MEMORY CELL STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device with split gate flash memory cell structure includes a substrate having a first area and a second area, at least a first cell formed in the first area and at least a second cell formed in the second area. The first cell includes a first dielectric layer formed on the substrate, a floating gate (FG), a word line and an erase gate (EG) formed on the first dielectric layer, an interlayer dielectric (ILD) layer, an inter-gate dielectric layer and a control gate (CG). The FG is positioned between the word line and the EG, and the ILD layer is formed on the word line and the EG, wherein the ILD layer has a trench exposing the FG. The inter-gate dielectric layer is formed in the trench as a liner, and the CG formed in the trench is surrounded by the inter-gate dielectric layer. | 2017-10-19 |
20170301684 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor memory device includes: a substrate including a cell region and a connection region; a first word line stack comprising a plurality of first word lines that extend to the connection region and are stacked on the cell region; a second word line stack comprising a plurality of second word lines that extend to the connection region and are stacked on the cell region, the second word line being adjacent to the first word line stack; vertical channels in the cell region of the substrate, the vertical channels being connected to the substrate and coupled with the plurality of first and second word lines; a bridge region that connects the first word lines of the first word line stack with the second word lines of the second word line stack; and a local planarized region under the bridge region. | 2017-10-19 |
20170301685 | Integrated Structures Including Material Containing Silicon, Nitrogen, and at Least One of Carbon, Oxygen, Boron and Phosphorus - Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. | 2017-10-19 |
20170301686 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The electrode layers have a plurality of terrace portions arranged in a stairstep configuration with a difference in levels. The insulating layer is provided above the terrace portions. The columnar portions extend in a stacking direction of the stacked body through the insulating layer and through the stacked body under the insulating layer. The columnar portions are insulative. The contact portions are provided at side surfaces of the columnar portions on the terrace portions. The contact portions are connected to the terrace portions. | 2017-10-19 |
20170301687 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, columnar portions extend through an insulating layer and through a stacked body under the insulating layer. The columnar portions are of an insulating material different from the insulating layer. Contact portions include a first contact portion disposed inside a first terrace portion and a second contact portion disposed inside a second terrace portion. The columnar portions including a first columnar portion disposed inside the first terrace portion and a second columnar portion disposed inside the second terrace portion. A shortest distance between the first contact portion and the first columnar portion, and a shortest distance between the second contact portion and the second columnar portion are substantially equal to each other. | 2017-10-19 |
20170301688 | NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING SAME - A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate. | 2017-10-19 |
20170301689 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure. | 2017-10-19 |
20170301690 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes. | 2017-10-19 |
20170301691 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes. | 2017-10-19 |
20170301692 | TRANSISTOR WITH CONTROLLED OVERLAP OF ACCESS REGIONS - A method for producing a microelectronic device with one or more transistor(s) including forming a first gate on a region of a semiconductor layer, forming a first cavity in the semiconductor layer, the first cavity having a wall contiguous with the given region, filling the first cavity in such a way as to form a first semiconductor block wherein a source or drain region of the first transistor is capable of being produced, by epitaxial growth of a first semiconductor material in the first cavity, the growth being carried out such that a first zone of predetermined thickness of the layer of first semiconductor material lines the wall contiguous with the given region, epitaxial growth of a second zone made of a second semiconductor material on the first zone. | 2017-10-19 |
20170301693 | RF ELECTRONIC CIRCUIT COMPRISING CAVITIES BURIED UNDER RF ELECTRONIC COMPONENTS OF THE CIRCUIT - RF electronic circuit comprising at least:
| 2017-10-19 |
20170301694 | SEMICONDUCTOR DEVICE WITH SILICON LAYER CONTAINING CARBON - A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced. | 2017-10-19 |
20170301695 | DISPLAY PANEL AND A METHOD OF MANUFACTURING THE SAME - A display panel includes a substrate including a display area, a peripheral area and a buffer area disposed between the display area and the peripheral area. The display panel further includes a switching element disposed in the display area. The switching element includes an active pattern, a gate electrode overlapping the active pattern, a source electrode connecting with the active pattern, and a drain electrode spaced apart from the source electrode. The display panel further includes a power supply line disposed in the peripheral area and disposed on a same layer as the source electrode and the drain electrode. The display panel additionally includes a power connecting line disposed in the buffer area and connecting the switching element to the power supply line. The display panel further includes a dummy active pattern disposed in the buffer area and overlapping the power connecting line. | 2017-10-19 |
20170301696 | Array Substrate, Display Panel and Display Apparatus - The present disclosure provides an array substrate, a display panel and a display apparatus. The array substrate includes gate lines and data lines defining a sub-pixel array, which contains sub-pixels of three different colors and includes repeating units, each of which includes twelve sub-pixels arranged in a matrix of four rows and three columns; in each repeating unit, three sub-pixels in a same row or column, among nine sub-pixels in three consecutive rows, have colors different from each other, three sub-pixels in the other row than the three consecutive rows of the repeating unit are arranged in the same order as three sub-pixels in a middle row among the three consecutive rows; each gate line is connected to a corresponding row of sub-pixels in the sub-pixel array; and each data line is connected to sub-pixels of a same color in corresponding three consecutive columns of sub-pixels in the sub-pixel array. | 2017-10-19 |
20170301697 | SILICON GERMANIUM FINS ON INSULATOR FORMED BY LATERAL RECRYSTALLIZATION - Relaxed silicon germanium fins are formed on a bulk silicon substrate through the lateral recrystallization of molten silicon germanium having high germanium content. Following formation of the silicon germanium fins, the silicon is selectively recessed. | 2017-10-19 |
20170301698 | METHOD OF PROVIDING AN IMAGING SYSTEM AND IMAGING SYSTEM THEREOF - Some embodiments include a method. The method can include providing a scintillator structure. Providing the scintillator structure can include providing a scintillator support layer, providing a scintillator layer, and coupling the scintillator layer to the scintillator support layer. Meanwhile, the scintillator support layer has a substantially non-planar surface, the scintillator layer having a first surface and a second surface opposite the first surface and being configured to scintillate, and the first surface of the scintillator layer is coupled to the substantially non-planar surface of the scintillator support layer such that the second surface of the scintillator layer has a contour of the substantially non-planar surface of the scintillator support layer. Other embodiments of related methods and systems are also disclosed. | 2017-10-19 |
20170301699 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE - To improve field-effect mobility and reliability of a transistor including an oxide semiconductor film. A semiconductor device includes an oxide semiconductor film, a gate electrode, an insulating film over the gate electrode, the oxide semiconductor film over the insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film and a second oxide semiconductor film over the first oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film, include the same element. The first oxide semiconductor film includes a region having lower crystallinity than the second oxide semiconductor film. | 2017-10-19 |
20170301700 | METHOD FOR PRODUCING TFT ARRAY SUBSTRATE, TFT ARRAY SUBSTRATE, AND DISPLAY APPARATUS - The present disclosure provides a method for producing a TFT array substrate, a TFT array substrate, and a display apparatus, and relates to a technical field of display. It can solve a problem of no signal transmission caused by fracture of a source signal line, without increasing a coupling capacitance of the TFT array substrate. The method for producing a TFT array substrate includes: forming a transparent conductive layer and a source-drain metal layer in sequence onto a base substrate; and patterning the source-drain metal layer and the transparent conductive layer in one patterning process to form a source signal line and a pixel electrode line overlapping with each other. | 2017-10-19 |
20170301701 | ACTIVE DEVICE - An active device includes a poly-silicon semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer, a first through hole, an oxide semiconductor layer, a first electrode and a second electrode. The poly-silicon semiconductor layer includes a first doped region, a channel region and a second doped region. The gate electrode is disposed on the first insulating layer covering the poly-silicon semiconductor layer, and corresponds to the channel region. The gate electrode is covered by the second insulating layer, where the first and second insulating layers have a first through hole. The oxide semiconductor layer is disposed on the second insulating layer and corresponds to the gate electrode. The first and second electrodes are oppositely disposed on the oxide semiconductor layer. The oxide semiconductor layer is electrically connected to the second electrode, and to the second doped region via the first through hole. | 2017-10-19 |
20170301702 | DISPLAY DEVICE - Deterioration of image quality in a display device due to kickback voltages may be reduced or prevented by varying parasite capacitance, the size of the semiconductor layer, and/or storage capacitance in each of thin film transistors for the pixels in the display. Various embodiments of display devices capable of reducing or preventing kickback voltages are disclosed. | 2017-10-19 |
20170301703 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - An array substrate, a manufacturing method therefor, and a display device are provided. The array substrate comprises multiple pixel units, where at least one of the pixel units comprises a first subpixel electrode and a second subpixel electrode, the first subpixel electrode is electrically connected to a first charging thin-film transistor, and the second subpixel electrode is electrically connected to a second charging thin-film transistor. In same one pixel unit, the charging capacity of the second charging thin-film transistor is greater than the charging capacity of the first charging thin-film transistor. | 2017-10-19 |
20170301704 | THIN-FILM TRANSISTOR DEVICE - A thin-film transistor (TFT) device may include a data line and a gate line formed on a base substrate, a TFT connected to the data line and the gate line, and a magnetic field antenna spaced apart from the data line and the gate line on the base substrate. The magnetic field antenna may be connected to the TFT and configured to transmit and receive a signal to and from the TFT or to control a driving of the TFT. | 2017-10-19 |
20170301705 | LTPS PIXEL UNIT AND MANUFACTURING METHOD FOR THE SAME - An LTPS pixel unit and a manufacturing method. The method includes following steps: forming a buffering layer on the substrate; forming a semiconductor pattern and a common electrode pattern which are disposed with an interval on the buffering layer; sequentially forming a first insulation layer, a gate electrode pattern and a second insulation layer on the semiconductor pattern; forming a source electrode pattern and a drain electrode pattern on the second insulation layer, wherein, the source electrode pattern and the drain electrode pattern electrically contact with the semiconductor pattern through a first contact hole at the first insulation layer and the second insulation layer; and forming a pixel electrode pattern on the second insulation layer, wherein, the pixel electrode pattern electrically contacts with the source electrode pattern or the drain electrode pattern. Accordingly, the present invention can save the cost and increase process yield. | 2017-10-19 |
20170301706 | METHOD OF MANUFACTURING DISPLAY PANEL SUBSTRATE - A method of manufacturing a display panel substrate having a semiconductor element includes a film forming step of forming a thin film, a resist film forming step of forming a positive resist film on the thin film, a first exposure step of selectively exposing a resist film via a photomask including a pattern of the semiconductor element, a second exposure step of selectively exposing the resist film by scanning and irradiating the resist film with light along an outline shape of the display panel substrate, a developing step of developing the resist film to remove the resist film exposed in the first and second exposure steps and form a resist pattern on the thin film, an etching step of etching the thin film using the resist pattern as a mask, and forming a thin-film pattern by selectively removing the thin film, and a peeling step of peeling the resist pattern. | 2017-10-19 |
20170301707 | DISPLAY SUBSTRATE ASSEMBLY AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS - The present disclosure provides a display substrate assembly including a first substrate and a second substrate opposite to each other, the first substrate including a first region and a second region, and, a total thickness of functional layers within the first region being less than a total thickness of functional layers within the second region, of the first substrate. A thickness compensation layer is provided on at least one of the first substrate and the second substrate, a position of the thickness compensation layer corresponds to a position of the first region, and, a sum of thickness of a thickness of the thickness compensation layer and the total thickness of the functional layers within the first region equals to the total thickness of the functional layers within the second region. | 2017-10-19 |
20170301708 | MAJORITY CURRENT ASSISTED RADIATION DETECTOR DEVICE - The invention relates to a majority current assisted detector device, comprising a semiconductor layer of a first conductivity type epitaxially grown on a semiconductor substrate, at least two control regions of the first conductivity type, at least two detection regions of a second conductivity type opposite to the first conductivity type, and a source for generating a majority carrier current in the semiconductor layer between the two control regions, the majority current being associated with an electrical field. The detection regions surround the control regions, thereby forming at least two taps. The device is configured for backside illumination and further comprises a well of the first conductivity type between the two detection regions for insulating the detection regions. The well comprises pixel circuitry elements. | 2017-10-19 |
20170301709 | DEEP TRENCH ISOLATION FABRICATION FOR BSI IMAGE SENSOR - The present disclosure relates to an integrated circuit, and an associated method of formation. In some embodiments, the integrated circuit comprises a deep trench grid disposed at a back side of a substrate. A passivation layer lines the deep trench grid within the substrate. The passivation layer includes a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer. A first dielectric layer is disposed over the passivation layer, lining the deep trench grid and extending over an upper surface of the substrate. A second dielectric layer is disposed over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid. The air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate. | 2017-10-19 |
20170301710 | IMAGE SENSORS HAVING CURVED UPPER SURFACES AND IMAGE SENSOR MODULES INCLUDING THE SAME - Provided is an image sensor. The image sensor may include a circuit board, a supporting board provided under the circuit board, and an image sensor chip provided over the circuit board. The circuit board, the supporting board, and the image sensor chip respectively have concavely curved upper surfaces. The supporting board comprises a central area and a peripheral area. The central area is thinner than the peripheral area. | 2017-10-19 |
20170301711 | IMAGING APPARATUS - An imaging apparatus includes a substrate including an imaging element, one or two attachment portions that attach the substrate by screwing and are capable of inclining a board surface of the substrate, by screwing in a screw, relative to a plane perpendicular to an optical axis of an optical system that forms an optical image on the imaging element; and one or more supports configured to abut the substrate from an opposite direction to a screwing direction of the attachment portion at any position, on the substrate, that rotates in the screwing direction of the attachment portion when the board surface is inclined by screwing. As a result, an imaging apparatus that allows an imaging element to be installed at a desired position and orientation while reducing the size of the substrate is provided. | 2017-10-19 |
20170301712 | IMAGE SENSOR INCLUDING PLANAR BOUNDARY BETWEEN OPTICAL BLACK AND ACTIVE PIXEL SENSOR AREAS - An image sensor includes a substrate including a sensor array area, a pad area, and a circuit area, a wiring layer on the pad area, and a light-shielding pattern on the sensor array area. The sensor array area includes a first area including active pixels and a second area including optical back pixels. The wiring layer is apart from the substrate by a first distance on the pad area. The light-shielding pattern includes a first portion spaced apart from the substrate by a second distance less than the first distance, a second portion disposed between the first portion and the wiring layer and extending on the same level as the wiring layer, and a third portion disposed between the first portion and the second portion and integrally formed with the first portion and the second portion. | 2017-10-19 |
20170301713 | SOLID STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREFOR - A solid state imaging device for a wafer-level pinhole camera module is provided by using a mask transfer technique to form, with a high degree of precision, pinhole openings in a light-shielding material formed upon cover glass covering the surfaces of imaging elements for wafer-level camera modules, and then dicing. Also provided is a manufacturing method therefor. Further provided is a compound-eye camera system in which a plurality of pinhole openings are formed. It is also possible to impart an apodization effect by changing the cross-sectional shape of the opening in the light-shielding material to a tapered shape to thereby change the transmission characteristics thereof. | 2017-10-19 |
20170301714 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME, AND IMAGING APPARATUS - A solid-state imaging device includes: a semiconductor substrate provided with an effective pixel region including a light receiving section that photoelectrically converts incident light; an interconnection layer that is provided at a plane side opposite to the light receiving plane of the semiconductor substrate; a first groove portion that is provided between adjacent light receiving sections and is formed at a predetermined depth from the light receiving plane side of the semiconductor substrate; and an insulating material that is embedded in at least a part of the first groove portion. | 2017-10-19 |
20170301715 | PAD STRUCTURE FOR BACKSIDE ILLUMINATED (BSI) IMAGE SENSORS - A pad structure with a contact via array for high bond structure is provided. In some embodiments, a semiconductor substrate comprises a pad opening. An interconnect structure is under the semiconductor substrate, and comprises an interlayer dielectric (ILD) layer, a wiring layer, and the contact via array. The wiring layer and the contact via array are in the ILD layer. Further, the contact via array borders the wiring layer and is between the wiring layer and the semiconductor substrate. A pad covers the contact via array in the pad opening, and protrudes into the ILD layer to contact the wiring layer on opposite sides of the contact via array. A method for manufacturing the pad structure, as well as an image sensor with the pad structure, are also provided. | 2017-10-19 |
20170301716 | ACTIVE AREA SELECTION FOR LIDAR RECEIVERS - Techniques provided herein are directed toward providing an optical sensor that reduces noise from sources of light other than the LIDAR transmitter by changing the active area of the sensor of a LIDAR receiver. The optical sensor may include a two dimensional array of single photon avalanche devices (SPADs) with row-select and column-select transistors, where rows and columns are selected based on a predicted spot size and angle of reflected laser light detected at the LIDAR receiver. Among other things, this can eliminate or reduce the need for moving parts within the LIDAR receiver. | 2017-10-19 |
20170301717 | SEMICONDUCTOR INTEGRATED CIRCUIT, ELECTRONIC DEVICE, SOLID-STATE IMAGING APPARATUS, AND IMAGING APPARATUS - A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate. | 2017-10-19 |
20170301718 | FULL-PDAF (PHASE DETECTION AUTOFOCUS) CMOS IMAGE SENSOR STRUCTURES - The present disclosure relates to an image sensor having autofocus function and associated methods. In some embodiments, the image sensor has first and second image sensing pixels arranged one next to another in a row. Each of the first and second image sensing pixels respectively have a left PD (phase detection) pixel including a left photodiode operably coupled to a left transfer gate, and a right PD pixel including a right photodiode operably coupled to a right transfer gate. The right transfer gate of the second image sensing pixel is a mirror image of the left transfer gate of the first image sensing pixel along a boundary line between the first and second image sensing pixels. The left transfer gate of the second image sensing pixel is a mirror image of the right transfer gate of the first image sensing pixel along the boundary line. | 2017-10-19 |
20170301719 | IMAGING DEVICE AND METHOD OF MANUFACTURING IMAGING DEVICE - An imaging device includes a plurality of pixels. Each of the pixels includes a photoelectric conversion unit provided in a first semiconductor region of a first conductivity type, a transfer transistor including a second semiconductor region of a second conductivity type to which charge generated in the photoelectric conversion unit is transferred, a third semiconductor region of the first conductivity type provided in a portion deeper than the second semiconductor region and having a higher impurity concentration than the first semiconductor region, and a counter doped region provided around the second semiconductor region. A part of the third semiconductor region and a part the counter doped region are overlapped with a gate electrode of the transfer transistor in a plan view. An overlap of the counter doped region with respect to the gate electrode is larger than an overlap of the third semiconductor region with respect to the gate electrode. | 2017-10-19 |
20170301720 | CMOS IMAGE SENSOR STRUCTURE WITH IR/NIR INTEGRATION - A semiconductor device includes a substrate, light sensing devices, at least one infrared radiation sensing device, a transparent insulating layer, an infrared radiation cut layer, a color filter layer and an infrared radiation color filter layer. The light sensing devices and the at least one infrared radiation sensing device are disposed in the substrate and are adjacent to each other. The transparent insulating layer is disposed on the substrate overlying the light sensing devices and the at least one infrared radiation sensing device. The infrared radiation cut layer is disposed on the transparent insulating layer overlying the light sensing devices for filtering out infrared radiation and/or near infrared radiation. The color filter layer is disposed on the infrared radiation cut layer. The infrared radiation color filter layer is disposed on the transparent insulating layer overlying the at least one infrared radiation sensing device. | 2017-10-19 |
20170301721 | METHOD OF MANUFACTURING AN IMAGER AND IMAGER DEVICE - Embodiments related to a method of manufacturing of an imager and an imager device are shown and depicted. | 2017-10-19 |
20170301722 | BACKSIDE INCIDENCE TYPE SOLID-STATE IMAGE PICKUP DEVICE - A back-illuminated solid-state imaging device includes a semiconductor substrate, a shift register, and a light-shielding film. The semiconductor substrate includes a light incident surface on the back side and a light receiving portion generating a charge in accordance with light incidence. The shift register is disposed on the side of a light-detective surface opposite to the light incident surface of the semiconductor substrate. The light-shielding film is disposed on the side of the light-detective surface of the semiconductor substrate. The light-shielding film includes an uneven surface opposing the light-detective surface. | 2017-10-19 |
20170301723 | MANUFACTURING OF AN IMAGER DEVICE AND IMAGER DEVICE - Embodiments related to the manufacturing of an imager device and an imager device are disclosed. Embodiments associated with methods of an imager device are also disclosed. | 2017-10-19 |
20170301724 | DISPLAY APPARATUS - A display apparatus includes at least one substrate with several penetration holes, several displaying units and several switch devices disposed at different sides of the at least one substrate, and at least one bonding material filling up the penetration holes, wherein the displaying units and the switch devices are connected to each other through the at least one bonding material. | 2017-10-19 |
20170301725 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes first and second light emitting bodies, a first electrode, a second electrode and a first interconnection. The first and second light emitting bodies are disposed on a conductive substrate, and each includes first and second semiconductor layers and a light emitting layer therebetween. The first electrode is provided between the first light emitting body and the conductive substrate, and electrically connected to a first semiconductor layer and the conductive substrate. The second electrode is provided between the second light emitting body and the conductive substrate, and electrically connected to a first semiconductor layer. The first interconnection electrically connects the second semiconductor layer of the first light emitting body and the second electrode. The first interconnection includes a first portion extending over the first and second light emitting bodies and a second portion extending into the second light emitting body. | 2017-10-19 |
20170301726 | HALL SENSOR WITH BURIED HALL PLATE - A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit. | 2017-10-19 |
20170301727 | SPIN-ORBIT TORQUE MAGNETIC RANDOM ACCESS MEMORY - A spin-orbit torque magnetic random access memory includes a substrate, and an SOT memory cell disposed on the substrate and including a magnetic free layer including a ferromagnetic first metal layer, an anti-ferromagnetic second metal layer, and a third metal layer for generating spin-Hall effect. The first metal layer has a thickness ranging from 0.5 nm to 1.5 nm and exhibits perpendicular magnetic anisotropy (PMA). The second metal layer has a thickness greater than 6 nm for providing an exchange bias field. The second metal layer is an IrMn layer not undergone out-of-plane magnetic annealing or coating and exhibiting no PMA. The magnetic free layer has a coercive magnetic field (H | 2017-10-19 |
20170301728 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a bottom electrode via (BEVA), a recap layer on the BEVA, and a magnetic tunneling junction (MTJ) layer over the recap layer. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA, and electroplated copper over the lining layer, filling the trench of the BEVA. The recap layer overlaps a top surface of the lining layer and a top surface of the electroplated copper. | 2017-10-19 |
20170301729 | NANO-IMPRINTED SELF-ALIGNED MULTI-LEVEL PROCESSING METHOD - The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4F | 2017-10-19 |
20170301730 | MEMORY CELL STRUCTURES - A memory cell includes a first diode, a second diode, and a random access memory cell element. The first diode and the random access memory cell element are series connected between a bit line and a word line. The second diode and the random access memory cell element are series connected between the word line and a reset line. A set path is formed through the first diode and the random access memory cell element, and a reset path is formed through the random access memory cell element and the second diode. The first diode is configured to performed a read operation and a set operation. The second diode is configured to perform a reset operation. The memory cell has higher forward current, lower leakage current and smaller size comparing with conventional memory cells. | 2017-10-19 |
20170301731 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a memory device and semiconductor device includes forming pillar-shaped phase change layers and lower electrodes in two or more rows and two or more columns on a semiconductor substrate. A reset gate insulating film is formed that surrounds the pillar-shaped phase change layers and the lower electrodes, and a reset gate is formed that surrounds the pillar-shaped phase change layers that function as memory devices arranged in two or more rows and two or more columns. | 2017-10-19 |
20170301732 | DUAL OTS MEMORY CELL SELECTION MEANS AND METHOD - A 3D cross-point memory array includes a bitline and a word line. Both the bitline and the word line have multiple selector switches. Each switch of a corresponding bitline or word line is connected to a horizontal conductor or a vertical conductor so that a given bitline or word line has two switches, a horizontal conductor and a vertical conductor. By activating a particular horizontal conductor and vertical conductor, a specific bitline or word line is selected. | 2017-10-19 |
20170301733 | Memory Arrays - Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F | 2017-10-19 |
20170301734 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR ELEMENT AND MANUFACTURE METHOD THEREOF - Disclosed is a CMOS element. The CMOS element comprises a substrate, a first metal layer, an insulation layer and a first type metal oxide semiconductor layer; and the element further comprises a first, a second and a third metal parts which are located on the insulation layer, and the first and the second metal parts are located at two sides of the first type metal oxide semiconductor layer and both contacts therewith; a second type organic semiconductor layer, located in a gap between the second, and the third metal parts and on the second, the third metal parts where are adjacent to the gap; a passivation layer, located on the first, the second and the third metal parts, the first type metal oxide semiconductor layer and the second type organic semiconductor layer; a third metal layer located on the passivation layer corresponding to the second type organic semiconductor layer. | 2017-10-19 |