42nd week of 2012 patent applcation highlights part 56 |
Patent application number | Title | Published |
20120265896 | MEDIA PLAYER WITH INTEGRATED PARALLEL SOURCE DOWNLOAD TECHNOLOGY - A media player implements an integrated parallel source download technology to receive a media file from streamed and segmented media file sources. A first source streams delivery of streamed media packets of the media file in sequential packet number order to the media player, while a second source provides segmented delivery of segmented media packets of the media file in random order to the media player. The media player combines the streamed media packets and the segmented media packets to produce the media file. | 2012-10-18 |
20120265897 | METHODS AND APPARATUS FOR ENHANCING DEVICE PERFORMANCE THROUGH FLOW CONTROL - A method and apparatus for enhancing device performance through transport flow control is provided. The method may include determining that a level of user interest is indicated in at least one application of one or more applications, and modifying a transport flow associated with at least one of the one or more applications. | 2012-10-18 |
20120265898 | ADJUSTING THE QUALITY OF SERVICE BASED ON NETWORK ADDRESSES ASSOCIATED WITH A MOBILE DEVICE - Implementations and techniques for adjusting the quality of service on an application-by-application basis based at least in part on a plurality of network addresses associated with a given mobile device are generally discussed. | 2012-10-18 |
20120265899 | FAST CONTENT-BASED ROUTING - Systems and methods for fast, efficient content-based routing that allow a router to perform true content-based routing without having to de-serialize the data and apply a full content-based filter by determining the exact set of consumers to forward the data onto based on packet headers. A system for fast content-based routing may receive a subscription from a receiver machine and may assign a unique ID associated with the subscription in a router table. The system may then place a ID associated with a particular subscription in a message header if the message corresponds to the subscription. The system may then analyze the router table to determine one or more receiver machines associated with the ID in the header of the message. The system may then send, from a sender machine to one or more receiver machines, one or more messages containing the ID in the header of the message. | 2012-10-18 |
20120265900 | UPDATING ROUTING INFORMATION BASED ON CLIENT LOCATION - A system, method, and computer-readable medium for updating request routing information associated with client location information are provided. A content delivery network service provider receives a DNS query from a client computing device. The DNS query corresponds to a resource identifier for requested content from the client computing device. The content delivery network service provider obtains a query IP address corresponding to the client computing device. Based on routing information associated with the query IP address, the content delivery network service provider routes the DNS query. The process further includes monitoring performance data associated with the transmission of the requested resource and updating routing information associated with the query IP address based on the performance data for use in processing subsequent requests form the client computing device. | 2012-10-18 |
20120265901 | Real-Time Video Optimizer - A video optimizer receives a request to optimize a video, wherein the request includes optimization parameters and a uniform resource locator (URL) of the video. The video optimizer retrieves the video from an origin server and transcodes the video based on optimization parameters. The video optimizer load balances several transcoding sessions over one or more servers and tracks each session based on session identifications (IDs). Additionally, the video optimizer tracks each session to determine when a server is at or near capacity to prevent an overflow situation. The video optimizer is also enabled to stitch together two or more transcoding sessions in the event of a seek operation by a user during video playback. The video optimizer streams the video to the client device, enabling the client device to stream videos in substantially real-time after requesting the video. | 2012-10-18 |
20120265902 | METHOD AND SYSTEM FOR PROVIDING PREVALIDATED SECURE PRODUCT MAINTENANCE, REPAIR AND TRAINING INFORMATION TO A FIELD TECHNICIAN - The present invention relates providing maintenance, repair, and training to a remote field technician and ability to sign off on work or training without the ability to edit or otherwise change information in a secure and updatable manner utilizing a secured handheld display device for displaying text, video, graphs, figures, and the like. | 2012-10-18 |
20120265903 | EFFICIENT CONNECTION MANAGEMENT IN A SAS TARGET - A method includes pre-configuring a hardware-implemented front-end of a storage device with multiple contexts of respective connections conducted between one or more hosts and the storage device. Storage commands, which are received in the storage device and are associated with the connections having the pre-configured contexts, are executed in a memory of the storage device using the hardware-implemented front-end. Upon identifying a storage command associated with a context that is not pre-configured in the hardware-implemented front-end, software of the storage device is triggered to configure the context in the hardware-implemented front-end, and the storage command is then executed using the hardware-implemented front-end in accordance with the context configured by the software. | 2012-10-18 |
20120265904 | PROCESSOR SYSTEM - Disclosed herein is a processor system including a specific code area setting register holding a first set value corresponding to an address range of a specific code area in which a specific program is stored; a peripheral device having a specific data storage area for storing specific data to be used by the specific program; a processor element outputting an access request to the peripheral device upon executing programs including the specific program, and determining whether the program executed by reference to the first set value is the specific program, and a safety guard controlling access to the specific data storage area depending on whether the access request results from the execution of the specific program. | 2012-10-18 |
20120265905 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface. | 2012-10-18 |
20120265906 | DEMAND-BASED DMA ISSUANCE FOR EXECUTION OVERLAP - A method, apparatus, and program product retrieve data for a task utilizing demand-based direct memory access (“DMA”) requests. The method comprises, prior to the execution thereof, analyzing a first portion of a task to determine whether data required for execution thereby is stored in a local memory, and, in response to determining that the data required for execution by the first portion of the task is not stored in the local memory, proactively issuing a first DMA request for the data required for execution by the first portion of the task. The method further comprises, in response to determining that the first DMA request is not complete, determining whether to proactively analyze a second portion of the task prior to the execution thereof for a determination whether data required for execution thereby is stored in the local memory. | 2012-10-18 |
20120265907 | ACCESS METHOD, COMPUTER AND RECORDING MEDIUM - An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations. | 2012-10-18 |
20120265908 | SERVER AND METHOD FOR BUFFERING MONITORED DATA - A method for buffering monitored data received from a monitoring device. The received monitored data is buffered into a buffer area and all of the monitored data from the buffer area is stored to a database server when a current count of data in the buffer area equals a recycling predetermined count N. An address of the received monitored data is recorded in a data list. When a monitoring server receives request for monitored data from a client server, the required one or more items of monitored data is read from the buffer area and sent to the client server. | 2012-10-18 |
20120265909 | COMMUNICATION OF COMMANDS IN A HOME AUTOMATION NETWORK AND BETWEEN HOME AUTOMATION NETWORKS - Method of communication in a home automation network allowing communication between parties consisting of command transmitters and/or communication receivers associated with equipment in a building by means of frames. | 2012-10-18 |
20120265910 | Server Input/Output Failover Device Serving Highly Available Virtual Devices - A failover input/output device and corresponding method are provided to manage failover events of input/output controller devices that operate in accordance with a computer expansion card standard, such as the Peripheral Component Interconnect Express (PCIe) standard. The failover input/output device connects to redundant first and second virtualized input/output controller devices each comprising multiple virtual network interfaces that are in an active or standby state at any given time, and to a computing device that hosts one or more processes. The failover input/output device broadcasts transactions in accordance with the computer expansion card standard initiated from the computing device to the first and second virtualized input/output controller devices. The failover input/output device receives signals associated with upstream transaction completions in accordance with the computer expansion card standard for both active and standby virtual network interfaces on the first and second virtualized input/output controller devices. The failover input/output device forwards signals associated with upstream transaction completions for active virtual network interfaces on the first and second virtualized input/output controller devices to the computing device. | 2012-10-18 |
20120265911 | MOBILE DEVICE AUTO DETECTION APPARATUS AND METHOD - This application discusses, among other things, multiple interface detection circuits configured to connect with a mobile electronic device connector. In an example, a multiple interface detection circuit can include a first comparator to compare a bus voltage of the mobile electronic device connector with a first threshold and to provide a first control signal, a second comparator to compare the bus voltage of the mobile electronic device connector with the first threshold and to provide a second control signal, a third comparator to compare the bus voltage of the mobile electronic device connector with a second threshold and to provide a third control signal, and a switch control configured to switch one or more signals of the connector. | 2012-10-18 |
20120265912 | OUT OF BAND LOCATION INFORMATION RETRIEVAL - A data processing system boots at least one service processor controlling at least one PCIe card in an I/O unit. The data processing system boots a second service processor located in a processor unit, wherein the processor unit and I/O unit are interconnected using functional path conductors, wherein functional path conductors are according to PCIe standard. The data processing system reads location information from the first at least one service processor, wherein the location information is reported for each PCIe card prior to initializing a functional path to the PCIe card. The data processing system sends location information from the second at least one service processor to a system controller. The data processing system initializes the PCIe card and a hub card of the processor unit in order to initialize a functional path and configures the I/O unit by communicating configuration commands over the functional path. | 2012-10-18 |
20120265913 | METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR CREATING A WIRELESS DOCKING GROUP - Method, apparatus, and computer program product embodiments are disclosed to enable simplified configuring of a wireless docking group for wireless devices by allowing a wireless device to communicate its capabilities and characteristics of one or more wireless devices within a wireless docking group, using a new Wireless Docking Protocol, to a wireless docking station that will use that information and the Wireless Docking Protocol to define an optimal set of connections for wireless devices in the wireless docking group. | 2012-10-18 |
20120265914 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. | 2012-10-18 |
20120265915 | DISTRIBUTED COMPUTING SYSTEM ARCHITECTURE - A computing system architecture is based upon a peer-to-peer, asynchronous model. The architecture specifies a set of infrastructure facilities that comprise an inter-prise operating system. The inter-prise operating system provides all the facilities that make application coding as easy in the peer-to-peer asynchronous model as it is in a hierarchical, synchronous model. Services, which reside in containers, are linked asynchronously by an inter-prise bus and use data from a virtual data store. | 2012-10-18 |
20120265916 | DYNAMIC ALLOCATION OF A DIRECT MEMORY ADDRESS WINDOW - A computer-implemented method may include determining that a slot coupled to a peripheral component interconnect host bridge is occupied by an input/output adapter. The computer-implemented method may include determining one or more characteristics of the input/output adapter and determining whether the input/output adapter is capable of using additional memory based on the one or more characteristics of the input/output adapter. The computer-implemented method may also include allocating the additional memory for the input/output adapter in response to determining that the input/output adapter is capable of using the additional memory. | 2012-10-18 |
20120265917 | DATA TRANSFERRING DEVICE - A data transfer device for transferring data on a platform, in particular for transferring simultaneous data between different components of the platform, is disclosed. In one aspect, the data transfer device is adapted for simultaneous transfer of data between at least 3 ports of which at least one is an input port and at least one is an output port. The data transfer device has at least two controllers for executing instructions that transfer data between an input port and an output port. The controllers are adapted for receiving a synchronization instruction for synchronizing between the controllers and/or a synchronization instruction for synchronizing input ports and output ports. | 2012-10-18 |
20120265918 | INTERFACE DEVICE AND WIRING BOARD - In the case of mounting two serial communication interfaces such as PCI-e and USB 3.0 with standards different from each other, it is allowed to flexibly address a design change and the like, and reduce a board area. An interface device includes a PCI-e I/F, a USB 3.0 I/F with characteristic impedance and an electric characteristic which are equivalent to those of the PCI-e I/F, and a controller provided with the PCI-e I/F and the USB 3.0 I/F. The interface device is provided with a PHY bus switch for selectively switching between the PCI-e I/F and the USB 3.0 I/F, and in which wiring for connecting the PCI-e I/F and the PHY bus switch and wiring for connecting the USB 3.0 I/F and the PHY bus switch are shared therebetween. | 2012-10-18 |
20120265919 | INTERFACE DEVICE AND WIRING BOARD - In the case of mounting two serial communication interfaces such as PCI-e and USB 3.0 with standards different from each other, it is allowed to flexibly address a design change and the like, and reduce a board area. An interface device is provided with a PCI-e PHY I/F, a USB 3.0 PHY I/F with equivalent specifications of a PIPE I/F to that of the PCI-e PHY I/F, and a system controller for controlling the PCI-e PHY I/F and the USB 3.0 PHY I/F. The interface device includes a PIPE I/F bridge in which the PCI-e PHY I/F and the USB 3.0 PHY I/F are provided, and the PIPE I/F bridge selectively switches connection of the PCI-e PHY I/F or the USB 3.0 PHY I/F with the system controller. | 2012-10-18 |
20120265920 | STORAGE BLOCK DEALLOCATION IN VIRTUAL ENVIRONMENTS - A system and method deallocates data blocks in virtual environments with high efficiency. A computer system hosting a virtual machine includes an I/O device driver in the guest operating system of the virtual machine. The I/O device driver intercepts an operation performed by the guest operating system that causes a data block to be deallocated in the virtual machine. The I/O device driver informs a hypervisor of the computer system that the data block is to be deallocated. The hypervisor then instructs the data storage to deallocate the data block for reuse. | 2012-10-18 |
20120265921 | BOOT DATA STORAGE SCHEMES FOR ELECTRONIC DEVICES - Systems and methods are provided for storing and retrieving boot data (e.g., a first stage bootloader) in and from a non-volatile memory (“NVM”), such as a NAND flash memory. To increase storage reliability, the boot data may be stored in a subset of the pages in a boot data storage area, such as in only lower pages. The subset may be selected based on the specific operating specifications and characteristics of the NVM. To prevent a boot ROM from having to maintain a NVM-specific map of which pages are used to store boot data, the map may be maintained in the NVM itself. For example, the map may be in the form of a linked list, where each page storing boot data can include a pointer that points to the next page that stores boot data. | 2012-10-18 |
20120265922 | STOCHASTIC BLOCK ALLOCATION FOR IMPROVED WEAR LEVELING - Systems and methods are disclosed for stochastic block allocation for improved wear leveling for a system having non-volatile memory (“NVM”). The system can probabilistically allocate a block or super block for wear leveling based on statistics associated with the block or super block. In some embodiments, the system can select a set of blocks or super blocks based on a pre-determined threshold of a number of cycles (e.g., erase cycles and/or write cycles). The block or super block can then be selected from the set of super blocks. In other embodiments, the system can use a fully stochastic approach by selecting a block or super block based on a biased random variable. The biased random variable may be generated based in part on the number of cycles associated with each block or super block of the NVM. | 2012-10-18 |
20120265923 | Program Method, Data Recovery Method, and Flash Memory Using the Same - A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed. | 2012-10-18 |
20120265924 | ELASTIC DATA TECHNIQUES FOR MANAGING CACHE STORAGE USING RAM AND FLASH-BASED MEMORY - A set of data caching techniques are described which are used to seamlessly store data across both RAM and flash based memory. The techniques utilize a memory manager that includes a RAM journal and a flash journal to efficiently store the data and to make the management of the data across both mediums transparent to the user. The flash based journal works in conjunction with the RAM journal and takes the overflow of data from the RAM journal when certain capacity limits are reached. The resource manager uses journaling techniques to write data to the cache and manages the garbage collection created by the data journaling. | 2012-10-18 |
20120265925 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING NON-VOLATILE MEMORY DEVICE - A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state. | 2012-10-18 |
20120265926 | MANAGING A SOLID-STATE STORAGE DEVICE - A method, comprising: during a normal operating mode of a first solid-state storage device, reserving a portion of an available physical storage space of the first solid-state storage device, giving rise to a reserved portion and a user data portion; setting a user data capacity of the first solid-state storage device according to a size of the user data portion; using substantially the entire available physical storage space for storing user data within the first solid-state storage device; and upon receiving at the first solid-state storage device an instruction to switch to a data protection mode, switching the first solid-state storage device to the data protection mode and allocating part of the reserved portion to the user data portion, giving rise to an extended user data portion, and using the added user data capacity for backing up data that is or was stored on the second solid-state storage device. | 2012-10-18 |
20120265927 | METHOD OF OPERATING MEMORY CONTROLLER, MEMORY CONTROLLER, MEMORY DEVICE AND MEMORY SYSTEM - A method of operating a memory controller, a memory controller, a memory device and a memory system are provided. The method includes reading first data from a nonvolatile memory device using a first read voltage, the first data includes a uncorrectable error bit, reading second data from a nonvolatile memory device using a second read voltage different from the first read voltage, the second data includes an correctable error bit, and reprogramming the nonvolatile memory device according to the comparison result of the first read voltage and the second read voltage. | 2012-10-18 |
20120265928 | NON-VOLATILE MEMORY DEVICES, METHODS OF OPERATING NON-VOLATILE MEMORY DEVICES, AND SYSTEMS INCLUDING THE SAME - Random sequence data is sequentially generated based on a seed assigned to a selected memory space, and one of access-requested segments of the selected memory space is logically combined with the sequentially generated random sequence data to transfer the access-requested segment. The sequentially generating and the logically combining are iteratively performed until remaining access-requested segments all transferred. | 2012-10-18 |
20120265929 | INTEGRATED CIRCUITS TO CONTROL ACCESS TO MULTIPLE LAYERS OF MEMORY IN A SOLID STATE DRIVE - Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. | 2012-10-18 |
20120265930 | CONTROLLING ON-DIE TERMINATION IN A DYNAMIC RANDOM ACCESS MEMORY DEVICE - An integrated circuit device transmits, to a dynamic random access memory device (DRAM), a write command indicating that write data is to be sampled by a data interface of the DRAM, and a plurality of commands that specify programming a plurality of control values into a plurality of corresponding registers in the DRAM. The plurality of control values include first and second control values that indicate respective first and second terminations that the DRAM is to apply to the data interface during a time interval that begins a predetermined amount of time after the DRAM receives the write command, the first termination to be applied during a first portion of the time interval while the data interface is sampling the write data and the second termination to be applied during a second portion of the time interval after the write data is sampled. | 2012-10-18 |
20120265931 | HIERARCHICAL IMMUTABLE CONTENT-ADDRESSABLE MEMORY PROCESSOR - Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write. | 2012-10-18 |
20120265932 | METHOD TO INCREASE THE FLEXIBILITY OF CONFIGURATION AND/OR I/O PERFORMANCE ON A DRIVE ARRAY BY CREATION OF RAID VOLUME IN A HETEROGENEOUS MODE - An apparatus comprising a controller and a plurality of storage drives. The controller may be configured to generate a control signal in response to one or more input/output requests. The plurality of storage drives may be arranged as one or more volumes. Each of the volumes may comprise a plurality of drive groups. Each of the drive groups may comprise a particular type of storage drive. The controller may be configured to form the volume across drives from two or more of the groups. | 2012-10-18 |
20120265933 | STRIDE BASED FREE SPACE MANAGEMENT ON COMPRESSED VOLUMES - Compressed data is maintained in a plurality of strides of a redundant array of independent disks, wherein a stride is configurable to store a plurality of tracks. A request is received to write one or more tracks, and a determination is made as to whether all of the one or more tracks can be stored in one selected stride of the plurality of strides. In response to determining that all of the one or more tracks can be stored in the one selected stride, the one or more tracks are written in the one selected stride of the plurality of strides. | 2012-10-18 |
20120265934 | WRITING ADJACENT TRACKS TO A STRIDE, BASED ON A COMPARISON OF A DESTAGING OF TRACKS TO A DEFRAGMENTATION OF THE STRIDE - Compressed data is maintained in a plurality of strides of a redundant array of independent disks, wherein a stride is configurable to store a plurality of tracks. A request is received to write one or more tracks. The one or more tracks are written to a selected stride of the plurality of strides, based on comparing the number of operations required to destage selected tracks from the selected stride to the number of operations required to defragment the compressed data in the selected stride. | 2012-10-18 |
20120265935 | METHOD FOR IMPLEMENTING DISK ARRAY, AND METHOD AND APPARATUS FOR READING OR WRITING DATA - A method for implementing a disk array, and a method and apparatus for reading or writing data are provided in embodiments of the present invention. The method includes: creating logical partition regions, where each logical partition region corresponds to one controller in one controller group; recording a mapping relationship between the logical partition regions and the controllers in a controller mapping table; and allocating, chunklets for the logical partition regions from a physical disk that is managed by a controller in a controller group that is corresponding to each logical partition region, and recording a mapping relationship between the logical partition regions and the chunklets in a chunklet mapping table. In the present invention, a chunklet in a physical disk that is managed by a controller in the same controller group is set to corresponding to each logical partition region, so that an expansion operation is completed easily. | 2012-10-18 |
20120265936 | SYSTEM AND METHOD FOR IMPROVED MEDIA IDENTIFICATION IN A STORAGE DEVICE - Systems and methods are provided for improved identification of removable storage media. A scanner may be used to read an identifier, such as a barcode, on a removable storage media. In the event that the scanner reads the identifier incorrectly due to a defect in the barcode, such as a damaged label, misaligned identifier, or because the scanner is incapable of reading the identifier type or the scanner's field of view is incorrect, a media management component receives the scanned identifier data and matches it to a known set of media identifiers to create a subset of matching identifier data. A closest matching media identifier may be identified from the subset of matching identifier data. An index may be updated with information indicating the closest matching media identifier and a location of the removable storage media. | 2012-10-18 |
20120265937 | DISTRIBUTED STORAGE NETWORK INCLUDING MEMORY DIVERSITY - A dispersed storage (DS) unit a processing module and a plurality of hard drives. The processing module is operable to maintain states for at least some of the plurality of hard drives. The processing module is further operable to receive a memory access request regarding an encoded data slice and identify a hard drive of the plurality of hard drives based on the memory access request. The processing module is further operable to determine a state of the hard drive. When the hard drive is in a read state and the memory access request is a write request, the processing module is operable to queue the write request, change from the read state to a write state in accordance with a state transition process, and, when in the write state, perform the write request to store the encoded data slice in the hard drive. | 2012-10-18 |
20120265938 | PERFORMING A PARTIAL CACHE LINE STORAGE-MODIFYING OPERATION BASED UPON A HINT - Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored. Generating the post-processed code includes marking the storage-modifying instruction with a partial cache line hint indicating that said storage-modifying instruction targets less than a full cache line of data within a memory hierarchy if the analyzing indicates only one granule of the target cache line will be accessed while the cache line is held in the cache memory and otherwise refraining from marking the storage-modifying instruction with the partial cache line hint. | 2012-10-18 |
20120265939 | Cache memory structure and method - The invention relates to a cache memory and method for controlling access to data. According to the invention, a control area which is advantageously formed separate from a data area is provided for controlling the access to data stored in the cache and to be read by applicative processes. The control area includes at least one release area with offsets and data version definition sections. | 2012-10-18 |
20120265940 | TRANSACTIONAL PROCESSING FOR CLUSTERED FILE SYSTEMS - Systems and methods for transactional processing within a clustered file system wherein user defined transactions operate on data segments of the file system data. The users are provided within an interface for using a transactional mechanism, namely services for opening, writing and rolling-back transactions. A distributed shared memory technology is utilized to facilitate efficient and coherent cache management within the clustered file system based on the granularity of data segments (rather than files). | 2012-10-18 |
20120265941 | Prefetching Irregular Data References for Software Controlled Caches - Prefetching irregular memory references into a software controlled cache is provided. A compiler analyzes source code to identify at least one of a plurality of loops that contain an irregular memory reference. The compiler determines if the irregular memory reference within the at least one loop is a candidate for optimization. Responsive to an indication that the irregular memory reference may be optimized, the compiler determines if the irregular memory reference is valid for prefetching. Responsive to an indication that the irregular memory reference is valid for prefetching, a store statement for an address of the irregular memory reference is inserted into the at least one loop. A runtime library call is inserted into a prefetch runtime library for the irregular memory reference. Data associated with the irregular memory reference is prefetched into the software controlled cache when the runtime library call is invoked. | 2012-10-18 |
20120265942 | PREDICTIVE OWNERSHIP CONTROL OF SHARED MEMORY COMPUTING SYSTEM DATA - A method, circuit arrangement, and design structure utilize a lock prediction data structure to control ownership of a cache line in a shared memory computing system. In a first node among the plurality of nodes, lock prediction data in a hardware-based lock prediction data structure for a cache line associated with a first memory request is updated in response to that first memory request, wherein at least a portion of the lock prediction data is predictive of whether the cache line is associated with a release operation. The lock prediction data is then accessed in response to a second memory request associated with the cache line and issued by a second node and a determination is made as to whether to transfer ownership of the cache line from the first node to the second node based at least in part on the accessed lock prediction data. | 2012-10-18 |
20120265943 | Configurable Cache and Method to Configure Same - A method includes receiving an address at a tag state array of a cache. The cache is configurable to have a first size or a second size that is larger than the first size. The method includes identifying a first portion of the address as a set index and using the set index to locate at least one tag field of the tag state array. The method also includes identifying a second portion of the address to compare to a value stored at the at least one tag field and locating at least one state field of the tag state array associated with a particular tag field that matches the second portion. The method further includes identifying a cache line based on a comparison of a third portion of the address to at least two status bits of the at least one state field and retrieving the cache line. | 2012-10-18 |
20120265944 | Assigning Memory to On-Chip Coherence Domains - A mechanism for assigning memory to on-chip cache coherence domains assigns caches within a processing unit to coherence domains. The mechanism assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller. | 2012-10-18 |
20120265945 | Recording Device, Recording Device Control Method, and Storage Medium - Managing commands in a buffer is simplified while continuing to enable immediately executing real-time commands. A control unit of a printer sequentially writes commands received from a host computer to a first buffer and sequentially reads the commands. If the read command is a real-time command, the control unit executes the command. If the read command is a normal command, the control unit writes the command to a second buffer without executing the command from the first buffer. The control unit sequentially reads and executes normal commands written to the second buffer. | 2012-10-18 |
20120265946 | BYPASSING USER MODE REDIRECTION - In one embodiment, a non-transitory processor-readable medium stores code associated with a function module included in a resource library. The code can represent instructions that when executed cause a processor to define, in response to a function hook associated with the function module, a copy of the resource library, the copy of the resource library including an unhooked copy of the function module. The code can further represent instructions that when executed cause the processor to execute the unhooked copy of the function module based on at least one policy from a plurality of policies. | 2012-10-18 |
20120265947 | LIGHTWEIGHT RANDOM MEMORY ALLOCATION - In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread. | 2012-10-18 |
20120265948 | EMULATING A SKIP READ COMMAND - In an embodiment, a skip read command is received that requests transfer of a requested block from a storage device and that requests non-transfer of a skipped block from the storage device. The skip read command specifies a skip mask that comprises an identification of a location of the requested block relative to a location of the skipped block at the storage device. In response to the skip read command, the requested block and the skipped block are transferred from the storage device by creating a read command that requests transfer of the requested block and the skipped block and sending the read command to the storage device. In various embodiments, the skipped block is transferred to a temporary buffer and not transferred to a destination buffer, or the skipped block is transferred to the destination buffer, but overwritten by a transfer of the requested block to the destination buffer. | 2012-10-18 |
20120265949 | SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, a semiconductor memory system includes semiconductor memories, and a memory controller configured to control the semiconductor memories. Each of the semiconductor memories is configured to execute an internal sequence including operations and have a wait period after an end of each of the operations, to notify, during the wait period, a status signal, which notifies in advance a start of a next operation, to the memory controller, and to start the next operation upon receiving a restart instruction of the internal sequence from the memory controller. | 2012-10-18 |
20120265950 | Storage Card Socket, Mobile Terminal and Method for Protecting the Storage Card - A storage card socket, mobile terminal and method for protecting the storage card, the storage card socket comprising: a first contact point on the base of the storage card socket; a second contact point on the base of the storage card socket, the second contact point electrically connected to the first contact point after the upper lid of the storage card socket is closed; and a guide slot on the base of the storage card socket, the guide slot being positioned at a side of a connecting part connecting the base and the upper lid, the connecting part being positioned in the guide slot so that the upper lid is slidable along the guide slot. | 2012-10-18 |
20120265951 | WIDE BANDWIDTH READ AND WRITE MEMORY SYSTEM AND METHOD - A memory device includes a first memory array, a first read port, a second read port, and a control input port. The first memory array contains a plurality of memory cells arranged in an array configuration. The first read port is configured to read first data from a single memory cell during a single read cycle, and the second read port is configured to read second data from a group of memory cells controlled by a common word line. Further, the control input is configured to receive a mode signal indicating a functional mode for the memory device including a first read mode and a second read mode. When the mode signal indicates the first read mode, the first read port is used to read the first data. When the mode signal indicates the second read mode, the first read port is used to read out the first data and the second read port is used to read the second data. | 2012-10-18 |
20120265952 | DATA COMMUNICATING APPARATUS AND METHOD FOR MANAGING MEMORY OF DATA COMMUNICATING APPARATUS - An IC card has a mechanism to securely manage information for each of a plurality of service providers in a memory area of the IC card. The IC card is shared by the plurality of service providers. | 2012-10-18 |
20120265953 | MEMORY MANAGEMENT DEVICE, MEMORY MANAGEMENT METHOD, AND CONTROL PROGRAM - When a page on a random access memory (RAM) having a value matching a page on a read only memory (ROM) is detected, a memory management section of a memory manager updates a conversion table so that the page on the ROM having the matching value is referred to, and discards the detected page on the RAM. The present technology is applicable to, for example, a built-in device. | 2012-10-18 |
20120265954 | SYSTEM AND METHOD FOR OPTIMIZED RECLAMATION PROCESSING IN A VIRTUAL TAPE LIBRARY SYSTEM - A storage management application determines that a source virtual tape requires reclamation, identifies all block addresses for active data of a source virtual tape and sorts the block addresses in an ascending order, identifies a target virtual tape which has sufficient free capacity to store the active data of said source virtual tape and the last written block address on said target virtual tape, and sends a command to the VTL-system instructing it to perform reclamation including information about said source and said target virtual tape, the sorted list of block addresses denoting active data on the source virtual tape and the starting block address on the target virtual tape. The reclamation logic references the active data host blocks of said source volume to said target virtual tape starting at said starting block address by just updating the host block to disk block mapping table. | 2012-10-18 |
20120265955 | STORAGE CONTROL APPARATUS FOR COPYING DATA BETWEEN LOGICAL VOLUMES, STORAGE SYSTEM COMPRISING THIS STORAGE CONTROL APPARATUS, AND STORAGE CONTROL METHOD - A storage control apparatus comprises a virtualization control part in addition to a copy control part determining whether or not a PVOL (a copy-source VOL) attribute set and a SVOL (a copy-destination VOL) attribute set are the same and carrying out a data copy between VOLs in a case where the result of this determination is affirmative. The virtualization control part creates either a virtual PVOL which is a VOL obtained by virtualizing the PVOL and which comprises the SVOL attribute set, or a virtual SVOL which is a VOL obtained by virtualizing the SVOL and which comprises the PVOL attribute set. As a result, either the VOL attribute set of the virtual PVOL and the SVOL attribute set become the same, or the PVOL attribute set and the VOL attribute set of the virtual SVOL become the same, and the copy control part can thereby carry out a copy between VOLs. | 2012-10-18 |
20120265956 | STORAGE SUBSYSTEM, DATA MIGRATION METHOD AND COMPUTER SYSTEM - It is provided a storage subsystem, comprising: a storage device which provides a volume for storing data; a processor which executes a program for controlling the storage subsystem; a memory which stores data used by the processor; and a port which is coupled to another storage subsystem. The memory stores interface management information, which holds a use of the port in migration, and port management information, which holds a use of a port of the another storage subsystem in migration. The processor refers to the interface management information and the port management information to identify a port of the another storage subsystem which is permitted to communicate with the port of the storage subsystem, in order to determine a communication zone of the port coupled to the another storage subsystem for migration. | 2012-10-18 |
20120265957 | MEMORY MEDIA AND METHOD FOR DATA BACKUP AND RECOVERY - A method is applied for data backup and recovery between an external memory device and an internal memory. A first determination signal is output according to a resistance of the external memory device. The external memory device is switched to electrically connect to the internal memory from a previous state according to the first determination signal. If an operation signal is received, a second determination signal is output. If no operation signal is received, a delay signal is output. Whether the operation signal is a saving operation signal or a recovering operation signal is determined according to the second determination signal. A control signal is output to the internal memory in response to the first determination signal and the operation signal, to control the internal memory reading or writing data to and from the external memory device. | 2012-10-18 |
20120265958 | METHOD AND SYSTEM FOR CASCADED FLASHCOPY ZONING AND ALGORITHM AND/OR COMPUTER PROGRAM CODE AND METHOD IMPLEMENTING THE SAME - A method of performing cascaded flashcopy (FC) including starting a flashcopy map when a target disk is already a source of an active FC map. A computer storage system includes a configuration that allows a flashcopy (FC) map to be started when a target disk is already the source of an active FC map. | 2012-10-18 |
20120265959 | SYSTEM AND METHOD FOR CONVERTING A PHYSICAL DISK TO A VIRTUAL DISK - A method for converting a disk of a physical computer into a virtual disk for use by a virtual machine is described. Contents of the disk of the physical computer are copied into an image file, wherein the image file has a different sector-by-sector organization of the contents than the disk but a logically equivalent file system organization. Hardware configuration information from the image file is then extracted, wherein the hardware configuration information relates to hardware of the physical computer and, based on a comparison of the extracted hardware configuration information and a virtual hardware configuration of the virtual machine, hardware-dependent files in the image file are replaced with substitute files that are compatible with the virtual hardware configuration of the virtual machine. | 2012-10-18 |
20120265960 | ELECTRONIC DEVICE, ELECTRONIC TIMEPIECE, AND PROGRAM - A CPU measures time. A memory unit stores the values of the times measured by the CPU as data groups for each measuring of time, and stores the data groups in association with protection information showing whether the data groups are in a protection state or an unprotected state. An input switch receives an instruction as an input. The CPU sets protection information stored in the memory unit on the basis of the instruction received by the input switch. Further, the CPU deletes the data of data groups in an unprotected state from the memory unit, on the basis of the protection information stored in the memory unit, when there is no capacity for storing the measured time values in the memory unit. | 2012-10-18 |
20120265961 | STORAGE SYSTEM AND UTILIZATION MANAGEMENT METHOD FOR STORAGE SYSTEM - A storage system | 2012-10-18 |
20120265962 | HIGH-PERFORMANCE SAS TARGET - A method for data storage includes, in a storage device that communicates with a host over a storage interface for executing a storage command in a memory of the storage device, estimating an expected data under-run between fetching data for the storage command from the memory and sending the data over the storage interface. A data size to be prefetched from the memory, in order to complete uninterrupted execution of the storage command, is calculated in the storage device based on the estimated data under-run. The storage command is executed in the memory while prefetching from the memory data of at least the calculated data size. | 2012-10-18 |
20120265963 | LARGE-PAGE OPTIMIZATION IN VIRTUAL MEMORY PAGING SYSTEMS - A computer system that is programmed with virtual memory accesses to physical memory employs multi-bit counters associated with its page table entries. When a page walker visits a page table entry, the multi-bit counter associated with that page table entry is incremented by one. The computer operating system uses the counts in the multi-bit counters of different page table entries to determine where large pages can be deployed effectively. In a virtualized computer system having a nested paging system, multi-bit counters associated with both its primary page table entries and its nested page table entries are used. These multi-bit counters are incremented during nested page walks. Subsequently, the guest operating systems and the virtual machine monitors use the counts in the appropriate multi-bit counters to determine where large pages can be deployed effectively. | 2012-10-18 |
20120265964 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD THEREOF - Disclosed is a data processing device capable of efficiently performing an arithmetic process on variable-length data and an arithmetic process on fixed-length data. The data processing device includes first PEs of SIMD type, SRAMs provided respectively for the first PEs, and second PEs. The first PEs each perform an arithmetic operation on data stored in a corresponding one of the SRAMs. The second PEs each perform an arithmetic operation on data stored in corresponding ones of the SRAMs. Therefore, the SRAMs can be shared so as to efficiently perform the arithmetic process on variable-length data and the arithmetic process on fixed-length data. | 2012-10-18 |
20120265965 | PROCESSING BYPASS DIRECTORY TRACKING SYSTEM AND METHOD - A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at. | 2012-10-18 |
20120265966 | PROCESSOR WITH INCREASED EFFICIENCY VIA EARLY INSTRUCTION COMPLETION - Methods and apparatuses are provided for increased efficiency in a processor via early instruction completion. An apparatus is provided for increased efficiency in a processor via early instruction completion. The apparatus comprises an execution unit for processing instructions and determining whether a later issued instruction is ready for completion or an earlier issued instruction is ready for completion and a retire unit for retiring the later issued instruction when the later instruction is ready for completion or to retire the earlier instruction when later instruction is not ready for completion and the earlier issued instruction has a known good completion status. A method is provided for increased efficiency in a processor via early instruction completion. The method comprises completing an earlier issued instruction having a known good completion status ahead of a later issued instruction when the later issued instruction is not ready for completion. | 2012-10-18 |
20120265967 | IMPLEMENTING INSTRUCTION SET ARCHITECTURES WITH NON-CONTIGUOUS REGISTER FILE SPECIFIERS - There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing an instruction of an instruction set using a non-contiguous register specifier of a non-contiguous register specification. The instruction includes the non-contiguous register specifier. | 2012-10-18 |
20120265968 | Locating Bottleneck Threads in Multi-Thread Applications - A method for identifying a consumer-producer pattern in a multi-threaded application includes obtaining synchronization event data of the multi-threaded application, and identifying the consumer-producer communication pattern from the synchronization event data. | 2012-10-18 |
20120265969 | ALLOCATION OF COUNTERS FROM A POOL OF COUNTERS TO TRACK MAPPINGS OF LOGICAL REGISTERS TO PHYSICAL REGISTERS FOR MAPPER BASED INSTRUCTION EXECUTIONS - A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an execution of an instruction by a mapper unit mapping at least one logical register from among the plurality of logical registers to the particular physical register, wherein the number of the plurality of counters is less than a number of the plurality of physical registers. The computer system, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool. | 2012-10-18 |
20120265970 | SYSTEM AND METHOD OF INDIRECT REGISTER ACCESS - Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect registers may be accessed through the direct registers, and the direct registers may provide various features to provide faster access to the indirect registers. One of the direct registers may indicate access modes for accessing the indirect registers. The access modes may include auto-increment, auto-decrement, auto-reset, and no change modes. Based on the access mode, the currently accessed address may be automatically modified after accessing the indirect register at the address. | 2012-10-18 |
20120265971 | ALLOCATION OF COUNTERS FROM A POOL OF COUNTERS TO TRACK MAPPINGS OF LOGICAL REGISTERS TO PHYSICAL REGISTERS FOR MAPPER BASED INSTRUCTION EXECUTIONS - A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from among multiple physical registers, responsive to an execution of an instruction by the mapper unit mapping at least one logical register to the particular physical register. The number of counters is less than the number of physical registers. The mapper unit, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool. | 2012-10-18 |
20120265972 | METHOD AND APPARATUS AND RECORD CARRIER - Method of generating respective instruction compaction schemes for subsets of instructions to be processed by a programmable processor, comprising the steps of a) receiving at least one input code sample representative for software to be executed on the programmable processor, the input code comprising a plurality of instructions defining a first set of instructions (S | 2012-10-18 |
20120265973 | High Reliability Processor System - A method of testing the integrity of microprogramming within a computer processor employs a test calculation designed to exercise instructions and to reveal errors in those instructions. The problem of testing instructions using the very instructions which may possibly be corrupt is addressed by developing a signature passed from instruction to instruction providing a low likelihood of a false positive outcome. A time-out system is used in the evaluation of the test calculation to capture a wide variety of other pathological operating conditions. | 2012-10-18 |
20120265974 | Method and Device for Resetting Intelligent Terminal - The disclosure discloses a method for resetting an intelligent terminal, including: receiving a reset instruction input by a user after a receiving state of reset instructions is started; determining whether the reset instruction is valid, determining a current running state of the intelligent terminal when the received reset instruction is valid, and triggering a reset of the intelligent terminal when the intelligent terminal is in a dead halt state or an abnormal instruction state. The disclosure further discloses a device for resetting an intelligent terminal. The disclosure can perform a soft reset of the intelligent terminal quickly, conveniently and securely, thereby greatly avoiding the instable work state caused by disassembling battery and avoiding the reset misoperation caused by the resetting of the existing single function key. | 2012-10-18 |
20120265975 | Microcontroller with Embedded Secure Feature - A secure environment is established within a system on a chip (SoC) without the use of a memory management unit. A set of security parameters is produced by a configuration program executed by a processor within the SoC that is read from a first non-volatile memory within the SoC. A set of stored parameters is created in a committable non-volatile memory within the SoC by writing the set of security parameters into the committable non-volatile memory. The committable non-volatile memory is sealed so that that it cannot be read or written by the processor after being sealed. The stored parameters can then be accessed only by control circuitry. Security circuitry within the SoC is configured using the stored parameters each time the SoC is initialized and thereby enforces the secure environment within the SoC. | 2012-10-18 |
20120265976 | Secure Network Cloud Architecture - Apparatuses, computer readable media, methods, and systems are described for requesting creation of virtual machine (VM) in a cloud environment comprising a virtual private cloud. Through various communications between a cloud DMZ, cloud provider, and/or company's network, a VM instance may be securely created, initialized, booted, unlocked, and/or monitored through a series of interactions building, in some examples, upon a root of trust. | 2012-10-18 |
20120265977 | MOBILE COMMUNICATOR DEVICE INCLUDING USER ATTENTIVENESS DETECTOR - Disclosed herein is a mobile communicator that includes a speed detection system for determining whether the mobile communicator is moving faster than a threshold speed. The mobile communicator further includes a user attentiveness detector configured determine whether a user is inattentive. The mobile communicator includes a circuit configured to ensure that a functionality of the mobile communicator is in a turned off state when the speed detection system determines that the mobile communicator is moving faster than the threshold speed and the user attentiveness detector determines that the user is inattentive. | 2012-10-18 |
20120265978 | System and Method for Context Aware Dynamic Ribbon - Predicting user actions and preemptively modifying a device in such a way as to make performing those actions easier. More specifically, a dynamic ribbon (DR) which comprises a ribbon whose contents and attributes can be changed dynamically based on anticipated user actions. The anticipated user action is facilitated by modifying the DR according to a preference to make some information available and/or make some action easier to perform. | 2012-10-18 |
20120265979 | MACHINE-TO-MACHINE NODE ERASE PROCEDURE - A method for erasing bootstrapping, at a device or a gateway in a Machine-to-Machine (M2M) service is provided. The method includes receiving an erase request containing a first M2M-Erase-Token from an M2M Authentication Server (MAS) or an M2M Service Bootstrapping Function (MSBF), processing the erase request based on the first M2M-Erase-Token or a local policy of the device or the gateway, and sending an erase response containing a second M2M-Erase-Token to the MAS or the MSBF. | 2012-10-18 |
20120265980 | APPARATUS AND METHOD FOR SECURING USER INPUT DATA - An apparatus and method for securing user input data in an electronic device including an input interface. A touch panel senses touch events in an input interface, a touch integrated circuit receives coordinate data associated with the touch events and encrypts the coordinate data using a secure key. The touch integrated circuit blocks a main processor of the electronic device from being aware that a touch event has been sensed and may directly transmit the coordinate data to a server without the intervention of the main processor. | 2012-10-18 |
20120265981 | ELECTRONIC DEVICE AND METHOD FOR SECURING USER INPUT DATA - An apparatus to secure input data includes a main processor to enter into a secure mode, a touch panel to detect an input, and a touch integrated circuit (IC) to obtain coordinate data of the input, and to encrypt data related to the input using a secure key, in which the data related to the input is encrypted in the secure mode, and the touch IC transmits the encrypted data to the main processor. A method for securing input data in an electronic device includes entering into a secure mode, receiving an input using a touch panel, obtaining coordinate data of the input using a touch integrated circuit (IC), and encrypting data related to the input using a secure key, in which the data related to the input is encrypted in the secure mode, and the touch IC transmits the encrypted data to the main processor. | 2012-10-18 |
20120265982 | METHOD, AUTHENTICATION SERVER, TERMINAL AND SYSTEM FOR IMPLEMENTING KEY MAPPING - The disclosure discloses a method for implementing key mapping applied to a Next Generation Network (NGN), which mainly includes: when a handoff of a terminal from an original network to a destination network is performed, an authentication server receiving a key material mapping request from the terminal, mapping an original key material in the original network to obtain a destination key material in the destination network, and setting up communication security between the terminal and the destination network. In addition, the disclosure further discloses an authentication server, a terminal and a system for implementing key mapping. By applying the solution of the disclosure, when the handoff of the terminal between different NGNs is performed, it is possible to improve the efficiency of session key generation and to reduce the time delay of the handoff of the terminal between the networks, and it is advantageous to reduce authentication signaling interaction and the load of the authentication server. | 2012-10-18 |
20120265983 | METHOD AND APPARATUS FOR PROVIDING MACHINE-TO-MACHINE SERVICE - A method and an apparatus for providing Machine-to-Machine (M2M) service are provided. A method of providing service by an M2M device includes transmitting a request for service to a Network Security Capability (NSEC), the request for service comprising a identifier of a Device Servie Capability Layer (DSCL) of the M2M device, performing an Extensible Authentication Protocol (EAP) authentication with an M2M Authentication Server (MAS) via the NSEC, and generating, if the EAP authentication is successful, a service key using a Master Session Key (MSK), a first constant string, and the identifier of the DSCL. | 2012-10-18 |
20120265984 | NETWORK WITH PROTOCOL, PRIVACY PRESERVING SOURCE ATTRIBUTION AND ADMISSION CONTROL AND METHOD - A device implemented, carrier independent packet delivery universal addressing networking protocol for communication over a network between network nodes utilizing a packet. The protocol has an IP stack having layers. At least some of the layers have privacy preserving source node attribution and network admission control. The packet is admitted to the network only if a source node of the network nodes admits the packet. | 2012-10-18 |
20120265985 | APPLICATION EXECUTING DEVICE, MANAGING METHOD, AND PROGRAM - A playback device reads an application and a digital stream from a recording medium to execute the application with playback of the digital stream. The playback device includes a management unit operable to verify authenticity of the application by judging whether a disc root certificate is identical to a first root certificate, and an execution unit operable to execute the application if authenticity of the application is verified by the management unit. The playback device also includes a storage unit having a storage area that is specified by a file path that uses the provider ID and a hash value of a second root certificate, and a playback unit operable to play back the digital stream in accordance with the playlist information. | 2012-10-18 |
20120265986 | METHOD AND SYSTEM FOR ENCRYPTING DATA DELIVERED OVER A NETWORK - Systems and methods are provided for delivering e-mail, typically with time relevant content, to users, whose e-mail addresses are encrypted. Specifically, the e-mails are administered by a host or home server that is transparent to the e-mail addresses of the computers and e-mail clients, that electronic communications are being sent to and received from. | 2012-10-18 |
20120265987 | COMMUNICATION BETWEEN KEY MANAGER AND STORAGE SUBSYSTEM KERNEL VIA MANAGEMENT CONSOLE - System, computer program product, and method embodiments for communication between a kernel operational on a storage subsystem and a key manager (KM) through a hardware management console (HMC) to provide encryption support are provided. In one embodiment, an event request is initiated by the kernel to the KM to execute an event flow. Pursuant to a communication request by the kernel to the HMC, a socket of the HMC is opened along a communication path between the KM and the kernel according to an event flow type selected by the KM for the event flow. Pursuant to a data request by the kernel to the KM, data including a data payload is sent by the KM to the kernel, the data payload corresponding to the selected event flow type. | 2012-10-18 |
20120265988 | DUAL INTERFACE DEVICE FOR ACCESS CONTROL AND A METHOD THEREFOR - The invention provides a low-cost access control device for identification and authentication in both the “digital” and “physical” worlds by contact-bound respectively contact-less interfaces and where individual users of the device can securely update access control credentials and cryptographic keys from a remote system without the need for any additional hardware or specialized software. The access control credentials and the at least one cryptographic key shall be readable by an access control system via the contact-less interface of the device, thereby enabling or denying the holder of the device access. | 2012-10-18 |
20120265989 | SECURE LOGIN METHOD - The present invention provides a secure login method, including connecting a user end to a server end via internet and accessing user end information by the server end; generating or selecting an algorithm corresponding to the user end information by the user end according to a predetermined rule; and providing a website page to the user end by the server end, and encrypting information entered into the website page by the algorithm provided via the website page and to storing the encrypted information in the user end. While the user end is re-connected to the server end and logins the server end, the website provided to the user end uses the algorithm to decrypt the encrypted information stored in the user end, and the decrypted information is entered into the website page. Accordingly, the present invention prevents hackers from stealing others' cookies, so as to secure the user's information. | 2012-10-18 |
20120265990 | AUTHENTICATION SYSTEM, METHOD AND DEVICE - An authentication system, method and device are provided in the present application. The authentication system includes an Application Server (AS) for providing non Internet protocol Multimedia Subsystem (IMS) service, an authentication gateway and an IMS terminal. The AS forwards a connection request message sent by the IMS terminal to said authentication gateway, the authentication gateway sends a obtained first random number to said IMS terminal through the AS, the IMS terminal generates a first Response (RES) value according to the first random number and sends the generated first RES value to the authentication gateway through the AS, and if the received first response value and an obtained Expected Response (XRES) value is found coincident after being compared by the authentication gateway, the authentication gateway determines that the authentication to the IMS terminal is passed, and indicates the AS to provide non IMS service for the IMS terminal. By using the technical solutions of the present application, solved is the problem existed in prior art that non IMS AS needs to authenticate each of IMS terminals respectively for obtaining non IMS service and thus reducing the service processing efficiency of the AS. | 2012-10-18 |
20120265991 | SYSTEMS AND METHODS FOR OPTIMIZING SSL HANDSHAKE PROCESSING - A method for enabling efficient SSL handshakes through pre-computing of handshake messages, the method includes: receiving, by an appliance, a server certificate identifying a server; generating, by the appliance, at least one of: (i) an SSL server certificate message comprising the received server certificate, (ii) an SSL client certificate request message, and (iii) an SSL hello done message; storing, by the appliance, the generated messages; receiving, by the appliance from a client, an SSL client hello message identifying the server; and transmitting, by the appliance to the client, an SSL server hello message and at least one of the stored messages. Corresponding systems are also described. | 2012-10-18 |
20120265992 | METHOD FOR PROCESSING A SOAP MESSAGE WITHIN A NETWORK AND A NETWORK - For allowing a one-pass streaming processing of XML (Extended Markup Language) based SOAP (Simple Object Access Protocol) messages with signed and/or encrypted MTOM attachments in a simple way, a method for processing a SOAP message within a network is provided. The SOAP message includes a fragment with binary content that will be moved into an MTOM (Message Transmission Optimization Mechanism) attachment of the SOAP message with a remaining reference to the binary content within the SOAP message and wherein the attachment will be signed and/or encrypted by a signing and encryption process, respectively. During signing process in addition to the hash of the signed fragment itself the same fragment excluding the binary content will be hashed and/or during encryption process in addition to the encryption of the fragment itself the fragment including only the reference to the binary content instead of the binary content will be encrypted. | 2012-10-18 |
20120265993 | ADVANCED WATERMARKING SYSTEM AND METHOD - A method, computer program product, and computing device for obtaining an uncompressed digital media data file. One or more default watermarks is inserted into the uncompressed digital media data file to form a watermarked uncompressed digital media data file. The watermarked uncompressed digital media data file is compressed to form a first watermarked compressed digital media data file. The first watermarked compressed media data file is stored on a storage device. The first watermarked compressed media data file is retrieved from the storage device. The first watermarked compressed digital media data file is modified to associate the first watermarked compressed digital media data file with a transaction identifier to form a second watermarked compressed digital media data file. | 2012-10-18 |
20120265994 | SYSTEM AND METHOD TO ESTABLISH AND/OR MANAGE A TRUSTED RELATIONSHIP BETWEEN A HOST TO STORAGE ARRAY CONTROLLER AND/OR A STORAGE ARRAY TO STORAGE ARRAY CONTROLLER - A method for establishing a secure connection between a first computer and a second computer, comprising the steps of (A) generating a signature authentication pair on the first computer, (B) receiving a plurality of authentication pairs that may or may not include the signature authentication pair, (C) detecting whether the signature authentication pair is received in the authentication pairs and (D) if the signature authentication pair is detected, creating a secure connection between the first computer and the second computer. | 2012-10-18 |
20120265995 | Exploiting Application Characteristics for Multiple-Authenticator Broadcast Authentication Schemes - A method for securing communications in a vehicle-to-vehicle (V2V) system including an on-board computer of a broadcasting vehicle predicting a value for a vehicle parameter, generating a heavyweight signature corresponding to the predicted value, and obtaining an actual value for the vehicle parameter. The method also includes the computer comparing the predicted value to the actual value to determine if the predicted value bears a first relationship to the actual value. If the computer determines that the predicted value bears the relationship to the actual value, the on-board computer generates a lightweight authenticating signature to correspond to the predicted value and broadcasts a data message having the predicted value with the corresponding heavyweight authenticating signature and the corresponding lightweight authenticating signature. | 2012-10-18 |