42nd week of 2008 patent applcation highlights part 58 |
Patent application number | Title | Published |
20080256246 | Method and apparatus for file sharing between a group of user devices with crucial portions sent via satellite and non-crucial portions sent using a peer-to-peer network - A communication system | 2008-10-16 |
20080256247 | PROTECTION OF DATA TRANSMISSION NETWORK SYSTEMS AGAINST BUFFER OVERSIZING - A method of managing the allocation to TCP connections of memory blocks of a TCP re-assembly buffer in a TCP network device including a TCP Processing unit, comprises computing a function r(t) on a per connection basis, that measures the occupancy rate of the re-assembly buffer for the relevant TCP connection, and that is updated upon reception of any packet belonging to said TCP connection; and allowing the TCP connection to be closed and the corresponding memory blocks to be released based on a decision scheme that includes at least a first trigger set on the corresponding function r(t), which defines two different states for said function r(t). | 2008-10-16 |
20080256248 | SINGLE SERVER ACCESS IN A MULTIPLE TCP/IP INSTANCE ENVIRONMENT - Methods, systems and computer program products are provided that access a single server application executing on a processing system having multiple TCP/IP instances. The single server application may be accessed by establishing a registration repository containing information sufficient to identify to both the single server application and a client application seeking to access the single server application, one of the multiple TCP/IP instances through which the single server application may be accessed by client applications. In such a case, the registration repository is accessible by the multiple TCP/IP instances and the single server application. | 2008-10-16 |
20080256249 | CLIENT AGENTS FOR OBTAINING ATTRIBUTES FROM UNAVAILABLE CLIENTS - A computer system and methods for creating an agency relationship among clients of a computer system with respect to personal privileged, or otherwise sensitive permissions and/or attributes, is described. The system and methods allow a querying client to obtain permission and/or attributes from a queried client, even if the queried client is unavailable. | 2008-10-16 |
20080256250 | Sub-tree access control in network architectures - A logical network directory database compliant with the X.500 standard for a directory data system is disclosed. The network directory database provides a source of subscriber and service data accessible by various control and management processes that require subscriber information. The network directory database may be extensible across various communications service providers and IT domain. Further, the disclosed network directory database may be applied to new and existing services, such as, IP Multimedia Subsystem, Unlicensed Mobile Access (UMA) and other IP services. | 2008-10-16 |
20080256251 | Mechanism for executing server discovery - A mechanism to ensure that the same server/proxy is selected by different server/proxy discovery mechanisms executed in a network control element and a terminal equipment, respectively. A first selection of a server/proxy is executed by a network control element on the basis of a first discovery procedure. Then, a second selection of a server/proxy is started by a terminal equipment on the basis of a second discovery procedure. A relay agent element is used for responding to the request on behalf of a configuration server or for modifying a configuration server response so that the same server/proxy is selected by the network control element and the terminal equipment. | 2008-10-16 |
20080256252 | SERVER APPARATUS, CONTENT PROCESSING METHOD THEREFOR, CONTENT PROCESSING PROGRAM THEREFOR, SERVER SYSTEM AND RECORDING MEDIUM - The present invention relates to a server apparatus that provides content to Web sites, and is directed to dynamically disperse accesses. A server apparatus that receives accesses from a plurality of client apparatuses and responds to the accesses, configured to include a processing unit that monitors accesses of the client apparatuses and, when accesses concentrate, creates second content correlated with first content on which the accesses concentrate for the first content, and to disperse accesses that concentrate on the first content to the second content. | 2008-10-16 |
20080256253 | Method and Apparatus for Cooperative Data Stream Processing - A cooperative data stream processing system is provided that utilizes a plurality of independent, autonomous and possibly heterogeneous sites in a cooperative arrangement to process user-defined job requests over dynamic, continuous streams of data. The sites negotiate peering relationships to share data and processing resources to handle the submitted job requests. These peering relationships can be cooperative or federated and can be expressed using common interest policies. Each site within the system runs an instance of a system architecture for processing job requests and is therefore a self-contained, fully functional instance of the cooperative data stream processing system. | 2008-10-16 |
20080256254 | COMMUNICATION METHOD AND APPARATUS USING HYPERTEXT TRANSFER PROTOCOL - A communication method for implementing a real-time streaming using hypertext transfer protocol (HTTP) in a network is provided. Chunked encoding of HTTP is applied so that information can be exchanged between a server and a client while an HTTP request is being progressed. Therefore, bidirectional communication between the client and the server using HTTP is possible without modifying an existing HTTP protocol, and real-time transmission can be implemented. | 2008-10-16 |
20080256255 | PROCESS FOR STREAMING MEDIA DATA IN A PEER-TO-PEER NETWORK - The process for streaming media data in a peer-to-peer (P2P) network includes the step of submitting a request through the P2P network to play a time segment of a media file. A local computer is connected through the P2P network to a streaming computer having the desired time segment. Thereafter, an initial data byte is located in the time segment via a conversion table associated with the media file. The time segment is streamed from the streaming computer to the local computer starting with the initial data byte. The time segment is stored on the local computer for playback through a corresponding media player. | 2008-10-16 |
20080256256 | Method and Apparatus for Autonomically Regulating Ratio of Stateful to Stateless Transaction Processing for Increasing Scalability in a Network of SIP Servers - Systems and methods are provided for maximizing call throughput in a server network by optimizing the balance of stateful to stateless handling or transactions at each server within the network. The identification of transaction messages to be handled statelessly or statefully is made at each proxy server within the network in order to maximize the total throughput at that proxy server within prescribed processor utilization limits. In general, each transaction is handled statefully by at least one server within the network. Reports on the stateful handling of messages and the resource consumption at various proxies are communicated throughout the network to be used in identifying the ratio of messages to be forwarded statefully to messages to be forwarded statelessly at any given proxy. | 2008-10-16 |
20080256257 | SYSTEMS AND METHODS FOR REFLECTING MESSAGES ASSOCIATED WITH A TARGET PROTOCOL WITHIN A NETWORK - A protocol management system is capable of detecting certain message protocols and applying policy rules to the detected message protocols that prevent intrusion, or abuse, of a network's resources. In one aspect, a protocol message gateway is configured to apply policy rules to high level message protocols, such as those that reside at layer 7 of the ISO protocol stack. | 2008-10-16 |
20080256258 | Business-to-Business Internet Infrastructure - A system and method is disclosed for integrating a trading partner into an XML based Internet. The system is operable to access the Internet to register a business name with one or more XML naming systems and register a business name with one or more XML naming systems. The system is further operable to receive an XML based address from the one or more XML naming systems. The system is still further operable to assign the XML based address to an authoritative XML naming system and map the XML based address to the Internet. | 2008-10-16 |
20080256259 | TECHNIQUES FOR PROVIDING A VIRTUAL WORKSPACE COMPRISED OF A MULTIPLICITY OF ELECTRONIC DEVICES - A virtual workspace is provided for a user with a number of electronic devices, in which information can be exchanged among the electronic devices through a number of connections between the electronic devices. The virtual workspace is provided by determining where services are located and the type of the services, determining one or more data formats associated with data accessible by one or more of the electronic devices. A portion of the data has a given one of one or more data formats. An electronic device is selected based at least in part on predetermined criteria and the given data format. A route through the connections to the selected electronic device is determined, where the route may comprise a given one or more of the connections. At least the portion of the data associated with the given data format is routed to the selected electronic device. The portion of the data is utilizable for presentation by the selected electronic device when received by the selected electronic device. | 2008-10-16 |
20080256260 | Lightweight Mrrm with Radio Agnostic Access Selection in the Core Network - A method and arrangement for making a handover decision in a multi-access communication network is disclosed. A first set of criteria is determined for when a handover between at least two access paths should be performed and a report is sent when at least one criterion of a first set of criteria is fulfilled. A second set of criteria is determined for when a handover between said at least two access paths should be performed and a report is sent when at least one criterion of said second set of criteria is fulfilled. One or more data sessions of at least one user terminal network are determined to be handed over based on the sent reports and a core network anchor and a terminal anchor are directed to execute a handover by re-routing said determined data sessions from one access path to an alternative access path. | 2008-10-16 |
20080256261 | Proximity Detection Method - The invention relates to a method of determining a proximity between a root node ( | 2008-10-16 |
20080256262 | Clock Signal Synchronization Among Computers In A Network - Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer. | 2008-10-16 |
20080256263 | Incorporating a Mobile Device Into a Peer-to-Peer Network - A system and a method enabling a mobile user-terminal ( | 2008-10-16 |
20080256264 | DATA PROCESSING SYSTEM, DATA PROCESSING METHOD AND PROGRAM - In the host, an IP issues CCW, and a CH encodes the CCW and a CCW chain by the encode program to create a code including the description of controlling a conditional branch with the DKC and transmits the code to a PORT in the DKC. In the DKC, the PORT decodes the code by the decode program, and a CP sequentially processes each command obtained by the decoding and returns a return code representing the end state of the processing. The host receives the return code to recognize the end state of the processing. | 2008-10-16 |
20080256265 | Display hard disk drive status on external display - A system with a visual display that provides an indication of a reliability of a hard disk drive of the system. The visual display may display the number of sector reallocations that have been performed by the disk drive. The display is coupled to a system housing so that a user can readily determine the reliability of the disk drive. | 2008-10-16 |
20080256266 | Computer system using remote I/O and I/O data transfer method - To improve throughput in data transfer in a remote I/O system, this invention provides a computer system including: a host computer; a device which communicates with the host computer; and a network which connects the host computer and the device, in which the device is coupled to the network via a device bridge including a bridge memory, and the host computer includes a host memory and a device driver. The device driver writes, when at least one of data and an address is written in the host memory, in the bridge memory the at least one of the data and address stored through the writing in the host memory; and sends a data transfer request to the device bridge, and the device bridge reads, upon reception of the data transfer request, an address from a predetermined area; and reads data from an area that is indicated by the read address. | 2008-10-16 |
20080256267 | High-speed data readable information processing device - A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory. | 2008-10-16 |
20080256268 | SYSTEM AND METHOD FOR TESTING AND CALIBRATING A CONTROL UNIT USING AN ADAPTATION UNIT - A system and method for testing and calibrating a control unit including a microcontroller includes an influencing device and an adaptation unit. The adaptation unit includes a memory that can store at least part of a data of a data communication between the influencing device and the control unit. The memory can be read from and/or written to by the microcontroller of the control unit when the control unit is in an on state. | 2008-10-16 |
20080256269 | Path Assignment Method in Consideration of I/O Characteristics - A computer system includes a plurality of host computers, at least one storage system coupled to the plurality of host computers through a plurality of paths, and a management computer, in which each of the plurality of host computers executes at least one application program which issues an I/O to the storage system, and the management computer obtains a characteristic of the application program and a characteristic of the path from the plurality of host computers and calculates a rate of assignment of data processed by the application program to each of the plurality of host computers based on the obtained characteristics of the application program and the path. | 2008-10-16 |
20080256270 | Quality of service based preemptive routing - Disclosed is a method of controlling communication between a plurality of devices having a plurality of routing paths between the plurality of devices. The method comprises measuring quality of communication between each of the plurality of devices and recording communication values representing the quality of communication with an associated repeating time value. The method further comprises selecting a current time value corresponding to a desired time period according to a selection criteria and selecting a routing path having an optimized communication value corresponding to the current time value. The communication values may be determined by utilizing a plurality of quality of service indicators including quality of service amplitude, quality of service signal quality and quality of service reported. The communication values may be used to distribute functions from the master device to a designated slave device in response to a triggering event. | 2008-10-16 |
20080256271 | Methods and apparatus for reducing storage usage in devices - Transmission buffer apparatus and methods configured to minimize the storage requirements for transmission/retransmission of data by allocating retransmission data to two or more types of storage. In one embodiment, RAM usage in a RAM-limited embedded device is minimized by storing only a reference or pointer to ROM- or Flash-sourced within the retransmission buffer (e.g., RAM), thereby reducing the storage burden on the buffer. For example, web pages having largely non-volatile components can be stored in ROM or Flash, while only the dynamic or volatile portions are stored in RAM. Apparatus and methods for implementing an exemplary serial-to-Ethernet interface are disclosed, as well as use of Flash or ROM to store configuration data in the form of e.g., a web page image. A circular buffer approach implementing the aforementioned methodologies is also described. | 2008-10-16 |
20080256272 | Packet Scheduling for Data Stream Transmission - The invention relates to transmitting data elements of a data stream based on a priority and target buffer fill levels at a receiving device. A transmitter controller transmits data elements of a data element class with a highest priority first, for reaching an associated buffer fill level and then turns to data elements of successively lower priorities, until the available bandwidth is exhausted. | 2008-10-16 |
20080256273 | SERIAL COMMUNICATION METHOD AND SERIAL COMMUNICATION SYSTEM - A host device continuously transmits a same command or a same piece of data to a remote device in serial format. The remote device receives the command or the data, and then determines whether the command or the data has an error. When the command or the data has no error, the remote device transmits a response to the host device. Upon reception of the response, the host device stops the continuous transmission of the command or the data. | 2008-10-16 |
20080256274 | Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit - An electronic device includes a scan-based circuit that includes a combinational decompressor, a combinational compressor, scan chains, and logic which typically includes a number of storage elements. Cycle time normally needed to shift data into or out of a scan cell to/from an external interface of the electronic device is reduced by use of one or more additional storage element(s) located between the external interface and one of the combinational elements (decompressor/compressor). The one or more additional storage element(s) form a pipeline that shifts compressed data in stages, across small portions of an otherwise long path between the external interface and one of the combinational elements. Staged shifting causes the limit on cycle time to drop to the longest time required to traverse a stage of the pipeline. The reduced cycle time in turn enables a corresponding increase in shift frequency. | 2008-10-16 |
20080256275 | Multi-Chip Module With Third Dimension Interconnect - A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. | 2008-10-16 |
20080256276 | ADDRESS TRANSLATION DEVICE - An apparatus, system and method to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The apparatus includes a detection module to detect an incoming address on the I2C bus, a translation module to translate the incoming address to an outgoing address, and a communication module to communicate data between the host device and the slave device where the outgoing address matches the physical address of the slave device. In this manner, the present invention avoids address conflicts between commonly addressed slave devices while reducing costs, components, and complexities traditionally associated with dynamic addressing techniques and other prior art solutions to address conflicts. | 2008-10-16 |
20080256277 | Processing apparatus and processing module - A processing apparatus has a master processing module and a plurality of slave processing modules. The master processing module has a master recording unit and a slave recording unit recording part of the data recorded in the master recording unit. The slave processing modules access the master processing module when it is necessary to access the data recorded in the master recording unit. When the data to be accessed from one slave processing module is recorded in the slave recording unit, the master processing module transmits the data to be accessed, from the slave recording unit to the one slave processing module. In the processing apparatus such as a base transceiver station communicating with transceivers such as mobile telephones, a reduction in the overall cost of the apparatus and an efficient internal communication are realized, and the overall processing time is reduced. | 2008-10-16 |
20080256278 | Method and System for Bus Arbitration - A method and system for bus arbitration to be used in a system having a plurality of data handling units ( | 2008-10-16 |
20080256279 | RESOURCE ARBITER - An aspect of the present invention provides an arbiter which grants a request (to access a resource) in the same clock cycle as in which the requests from requesters is received. In one embodiment, such a feature may be provided in case of arbitration policies requiring state information from previous grants. In another embodiment, such a feature may be provided when the arbitration policy is programmable such that the same arbiter can be used for different arbitration policies. | 2008-10-16 |
20080256280 | Splitting One Hardware Interrupt To Multiple Handlers - A method and apparatus are provided for reducing latency associated with processing events of a hardware interrupt. Send and receive events share the same hardware interrupt. A receive handler and a separate send handler are provided to simultaneously process completion of a send event and a receive event. In addition, separate queues are provided to communicate receipt of an event to the respective interrupt handler. | 2008-10-16 |
20080256281 | SYSTEM AND METHOD FOR PROVIDING AN ADAPTER FOR RE-USE OF LEGACY DIMMS IN A FULLY BUFFERED MEMORY ENVIRONMENT - A system and method for providing an adapter for re-use of legacy DIMMS in a fully buffered memory environment. The system includes a memory adapter card having two rows of contacts along a leading edge of a length of the card. The rows of contacts are adapted to be inserted into a socket that is connected to a daisy chain high-speed memory bus via a packetized multi-transfer interface. The memory adapter card also includes a socket installed on the trailing edge of the card. In addition, the memory adapter card includes a hub device for converting the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. In addition, the hub device converts the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. The hub device also converts the parallel interface into the packetized multi-transfer interface. | 2008-10-16 |
20080256282 | Calibration of Read/Write Memory Access via Advanced Memory Buffer - Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB). | 2008-10-16 |
20080256283 | Multimedia expansion module and computer device using the same - A multimedia expansion module suitable to be assembled in a computer device is provided. The multimedia expansion module includes a first group of pins, a second group of pins, a third group of pins, a first pin area and a second pin area. The first group of pins supports the transmission of universal serial bus (USB) signals. The second group of pins supports the transmission of serial disk drive interface signals. The third group of pins supports the transmission of peripheral component interconnect (PCI) express interface signal whose rate is at least 2.5 G bps. The third group of pins includes a first part of pins and a second part of pins. The first group of pins and the first part of pins are provided at the first pin area, and the second group of pins and the second part of pins are provided at the second pin area. | 2008-10-16 |
20080256284 | Simulation Circuit of Pci Express Endpoint and Downstream Port for a Pci Express Switch - Single hardware subsystems that present two software views that appear to be two separate hardware subsystems attached in a hierarchy are implemented with PCI-type arrangements. According to an example embodiment of the present invention, a hardware arrangement is adapted to emulate two virtually separate hierarchical subsystems in a single hardware block. This emulation facilitates the coupling of devices to PCI Express-type communications links while addressing PCI-Express-type linking requirements for such devices. | 2008-10-16 |
20080256285 | Image processing controller and image processing device - A first interface receives image information and an output destination address from a first external device. A second interface transmits image information to a second external device at a lower communication speed than the first interface. A communication path connects the first interface and the second interface to exchange data, on which a first-in first-out memory is provided. Upon the first interface receiving the address, when the second interface is specified as a transmission destination based on the address, a transmitting unit transmits the image information to the second interface through the communication path and the first-in first-out memory. | 2008-10-16 |
20080256286 | VERIFICATION OF NON VOLATILE STORAGE STORING PRESERVED UNNEEDED DATA - Non volatile storage may be employed to temporarily store data which is destaged to data storage drives. The non volatile storage is configured to preserve the data through a power outage. Some data may be preserved, but is not needed, such as the result of a failover to another non volatile storage. This unneeded data is tested to verify the non volatile storage by indicating whether the data survived the power cycle from full power to self refresh mode battery power to full power, without risking the loss of data that is needed. | 2008-10-16 |
20080256287 | Methods and systems of managing memory addresses in a large capacity multi-level cell (MLC) based flash memory device - Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM. | 2008-10-16 |
20080256288 | MICROCOMPUTER, ELECTRONIC INSTRUMENT, AND FLASH MEMORY PROTECTION METHOD - A microcomputer includes a flash memory and a flash controller that controls access to the flash memory, the flash memory including a protection information storage section that stores protection information, the protection information indicating whether or not access to a given area of the flash memory is available; the flash controller including a flash protection section that performs a protection process relating to access to a given area of the flash memory based on the protection information; and the flash protection section performing the protection process relating to access to the flash memory when an access target is data. | 2008-10-16 |
20080256289 | MEMORY APPARATUS TO WRITE AND READ DATA, AND METHOD THEREOF - An apparatus and method of reading and writing data from and on a storage medium include receiving at least one of file information and file data from a host, generating a logical block address corresponding to the one of the file information and the file data, and writing the one of the file information and the file data at the generated logical block address | 2008-10-16 |
20080256290 | METHOD AND SYSTEM OF RANDOMIZING MEMORY LOCATIONS - A memory system that disperses memory addresses of stings of data throughout a memory is provided. The memory system includes a memory, a central processing unit (CPU) and an address randomizer. The memory is configured to store stings of data. The CPU is configured to direct the storing and retrieving of the strings of data from the memory at select memory addresses. The address randomizer is coupled between the CPU and the memory. Moreover, the address randomizer is configured to disburse the strings of data throughout locations of the memory by changing the select memory addresses directed by the CPU. | 2008-10-16 |
20080256291 | Disk array synchronization using power distribution - Disk drives are synchronized by a timing signal generated in a master disk drive. The timing signal is transmitted over a power distribution network common to the disk drives. A slave drive receives the timing signal and synchronizes at least one disk based on the timing signal. | 2008-10-16 |
20080256292 | APPARATUS, SYSTEM, AND METHOD FOR A SHARED, FRONT-END, DISTRIBUTED RAID - An apparatus, system, and method are disclosed for a shared, front-end, distributed redundant array of independent drives (“RAID”). A multiple storage request receiver module receives at least two storage requests from at least two clients to store file or object data in one or more storage devices of a storage device set. The storage requests are concurrent and have at least a portion of the data in common. The storage device set includes autonomous storage devices forming a RAID group. Each storage device is capable of independently receiving storage requests from a client over a network. A striping module calculates a stripe pattern and writes N data segments per stripe to N storage devices. A parity-mirror module writes a set of N data segments to parity-mirror storage devices. A sequencer module ensures completion of a first storage request prior to executing a second storage request. | 2008-10-16 |
20080256293 | CARRIER FOR MANUFACTURING A MEMORY DEVICE, METHOD USING THE SAME, MEMORY DEVICE USING THE SAME AND MANUFACTURING METHOD OF A MEMORY DEVICE USING THE SAME - A carrier including a bottom plate, an intermediate cover, and a top cover for manufacturing a memory device is introduced herein. A printed circuit board is disposed on the bottom plate, and memory elements are arranged and disposed on the PCB. The intermediate cover is used to press peripheral regions of the printed circuit board, and to expose the regions where the memory elements are formed on the printed circuit board. The printed circuit board is closely attached to a surface of the bottom plate by fixing the intermediate cover. The top cover is used to cover the memory elements formed on the printed circuit board after some manufacturing processes, and by exerting an external force, the formed memory elements are clamped down, so as to protect the memory elements from being affected by the printed circuit board in the following thermal process due to the thermal stress deformation. | 2008-10-16 |
20080256294 | SYSTEMS AND METHODS FOR MULTI-LEVEL EXCLUSIVE CACHING USING HINTS - Systems and methods for multi-level exclusive caching using hints. Exemplary embodiments include a method for multi-level exclusive caching, the method including identifying a cache management protocol within a multi-level cache hierarchy having a plurality of caches, defining a hint protocol within the multi-level cache hierarchy, identifying deciding caches and non-deciding caches within the multi-level cache hierarchy and implementing the hint protocol in conjunction with the cache management protocol to decide which pages within the multi-level cache to retain and where to store the pages. | 2008-10-16 |
20080256295 | Method of Increasing Boot-Up Speed - There is provided a method of increasing boot-up speed in a computer system ( | 2008-10-16 |
20080256296 | INFORMATION PROCESSING APPARATUS AND METHOD FOR CACHING DATA - A processor is provided with a register and operates to: determine whether a first tag address match with a second tag address, the first tag address being derived from a target main memory address that is to be accessed for obtaining target data subjected to a computation, the second tag address being one of the tag addresses stored in the local memory; start copying data stored in at least one of the cache lines assigned with a line number that matches with a target line number that is derived from the target main memory address into the register before completing the determination of match between the first tag address and the second tag address; and access the register to obtain the data copied from the local memory when determined that the first tag address match with the second tag address. | 2008-10-16 |
20080256297 | Multi-Port High-Level Cache Unit an a Method For Retrieving Information From a Multi-Port High-Level Cache Unit - A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs. | 2008-10-16 |
20080256298 | Intelligent caching of user data for real time communications - Apparatus and methods for storing user data for use in real-time communications (e.g., IM or VoIP) are provided. The apparatus comprises at least a first cache device (e.g., a cache server) and a second cache device for storing user data, wherein the user data stored with the first cache device is mirrored with the second cache device. The apparatus further comprising a server having logic for causing access to the user data (e.g., to respond to or process messages) from the first cache device, if accessible, and from the second cache device if the user data is not accessible form the first cache device. The apparatus may further include logic for causing user data to be restored to the first cache device from the second cache device if the first cache device loses user data (e.g., if the first cache device goes down). | 2008-10-16 |
20080256299 | System and Method for Achieving Different Levels of Data Consistency - A system and method for maintaining consistency in a system where multiple copies of an object may exist is provided for maintaining consistent copies. Consistency is maintained using a plurality of consistency policies in which at least one consistency policy results in different performance than a second consistency policy. A consistency policy is selected from the plurality consistency policies for each object to improve system performance. | 2008-10-16 |
20080256300 | System and method for dynamically reconfiguring a vertex cache - A system to process a plurality of vertices to model an object. An embodiment of the system includes a processor, a front end unit coupled to the processor, and cache configuration logic coupled to the front end unit and the processor. The processor is configured to process the plurality of vertices. The front end unit is configured to communicate vertex data to the processor. The cache configuration logic is configured to establish a cache line size of a vertex cache based on a vertex size of a drawing command. | 2008-10-16 |
20080256301 | PROTECTION OF THE EXECUTION OF A PROGRAM - A method for controlling the execution of at least one program in an electronic circuit and a processor for executing a program, in which at least one volatile memory area of the circuit is, prior to the execution of the program to be controlled, filled with first instructions resulting in an exception processing; the program contains instructions for replacing all or part of the first instructions with second valid instructions; and the area is called for execution of all or part of the instruction that it contains at the end of the execution of the instruction program. | 2008-10-16 |
20080256302 | Programmable Data Prefetching - A method, computer program product, and system are provided for prefetching data into a cache memory. As a program is executed an object identifier is obtained of a first object of the program. A lookup operation is performed on a data structure to determine if the object identifier is present in the data structure. Responsive to the object identifier being present in the data structure, a referenced object identifier is retrieved that is referenced by the object identifier. Then, the data associated with the referenced object identifier is prefetched from main memory into the cache memory. | 2008-10-16 |
20080256303 | Cache memory - An apparatus for processing data comprises a cache memory having a plurality of cache rows each operable to store a cache line of data values, a memory management unit responsive to a page table entry to control access to a corresponding group of memory addresses forming a memory page, and a cache controller coupled to said cache memory and responsive to a cache miss to trigger a line fill operation to store data values into a cache row. The cache controller is responsive to a cache line size specifier associated with at least one page table entry to vary the number of data values within a cache line fetched in a line fill operation in dependence upon said cache line size specifier. Accordingly, by associating cache line size specifiers with page table entries, the number of data values to be stored in a line fill operation can be controlled on a memory page basis, which is advantageous because data values within the same page of memory are likely to be subject to similar types of access behaviour in the cache. Additionally, controlling cache line size on a page basis is more efficient, in terms of computation and storage, than controlling cache line size on a cache row or virtual address basis. | 2008-10-16 |
20080256304 | Storage system and control method thereof - The plurality of host systems or the plurality of applications include an insertion unit for sending the identifier. The storage controller includes an analysis unit for identifying a host system or an application based on the identifier contained in the access information and analyzing an access pattern of access information sent from the identified host system or application, a management unit for managing the identifier, the analysis result of the access pattern analyzed with the analysis unit, and a control method for controlling the processing of data to be sent from a host system based on the analysis result or data to be stored in a logical volume, and a data processing controller for controlling the processing of data to be sent from a host system or data to be stored in a logical volume according to the control method managed by the management unit. | 2008-10-16 |
20080256305 | MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE - A multipath accessible semiconductor memory device provides an interfacing function between multiple processors which indirectly controls a flash memory. The multipath accessible semiconductor memory device comprises a shared memory area, an internal register and a control unit. The shared memory area is accessed by first and second processors through different ports and is allocated to a portion of a memory cell array. The internal register is located outside the memory cell array and is accessed by the first and second processors. The control unit provides storage of address map data associated with the flash memory outside the shared memory area so that the first processor indirectly accesses the flash memory by using the shared memory area and the internal register even when only the second processor is coupled to the flash memory. The control unit also controls a connection path between the shared memory area and one of the first and second processors. The processors share the flash memory and a multiprocessor system is provided that has a compact size, thereby substantially reducing the cost of memory utilized within the multiprocessor system. | 2008-10-16 |
20080256306 | NON-INCLUSIVE CACHE SYSTEMS AND METHODS - Non-inclusive cache systems and methods are provided. In one embodiment a non-inclusive cache system is provided comprising a non-inclusive cache and a cache agent that receives a request for access to the non-inclusive cache and denies the request for access to the non-inclusive cache if the non-inclusive cache system exceeds a predetermined level of activity. | 2008-10-16 |
20080256307 | STORAGE SUBSYSTEM, STORAGE SYSTEM, AND METHOD OF CONTROLLING POWER SUPPLY TO THE STORAGE SUBSYSTEM - Provided is storage subsystem including: a storage unit containing multiple disk groups; and a control device for controlling the storage unit. The storage unit includes at least one redundant disk group composed of at least a first disk group and a second disk group for redundancy. The control device is configured to: put the first disk group into a power-on state; put the second disk group into a power-off state; read/write data stored in the first disk group; turns on power of the second disk group at a predetermined timing; write, in the second disk group, data that has been written in the first disk group while the second disk group has been in the power-off state; and put one of the first and second disk group into the power-on state and the other one of the first and second disk group into the power-off state after the writing. | 2008-10-16 |
20080256308 | Storage system, method for managing the same, and storage controller - A storage system includes one or more host computers; and a storage controller that provides each of the one or more host computers with a plurality of logical volumes, each including a storage area for reading/writing data from/to, and also being either allocated or not allocated to one or more of the host computers, the storage controller including: an identification unit that identifies function information relating to a logical volume from among the plurality of logical volumes included in information relating to the plurality of logical volumes based on a command from a host computer from among the one or more host computers; and an execution unit that executes processing on the logical volume in accordance with an identification result of the identification unit. | 2008-10-16 |
20080256309 | MAINTAIN OWNING APPLICATION INFORMATION OF DATA FOR A DATA STORAGE SYSTEM - A data storage system writes data supplied from a host to data storage in accordance with write I/O of an owning application. A workload manager directs the processing of the supplied data in accordance with the write I/O of the owning application, provides service workload identification describing the write I/O, a storage subsystem control adds the service workload identification to record set information for the data, and a journal management system stores the record set information in a journal. The journaled information, for example, may be employed for performing forensic analysis of data corruption events or to perform security audits, etc. | 2008-10-16 |
20080256310 | MAINTAIN OWNING APPLICATION INFORMATION OF DATA FOR A DATA STORAGE SYSTEM - A data storage system writes data supplied from a host to data storage in accordance with write I/O of an owning application. A workload manager directs the processing of the supplied data in accordance with the write I/O of the owning application, provides service workload identification describing the write I/O, a storage subsystem control adds the service workload identification to record set information for the data, and a journal management system stores the record set information in a journal. The journaled information, for example, may be employed for performing forensic analysis of data corruption events or to perform security audits, etc. | 2008-10-16 |
20080256311 | SNAPSHOT PRESERVED DATA CLONING - A method and device for cloning snapshots is provided. A new snapshot can be created by cloning an existing snapshot. The clone snapshot may use the preserved data of the existing snapshot, thereby obviating the need to copy the preserved data. Additionally, the clone snapshot may be created with a data structure for storing write data. Since the clone snapshot initially has no write data to store, the creation of the entire clone snapshot can be accomplished without copying any preserved data or write data from the existing snapshot, thereby increasing the efficiency with which a clone snapshot can be created. | 2008-10-16 |
20080256312 | APPARATUS AND METHOD TO DETECT AND REPAIR A BROKEN DATASET - A method is disclosed to detect and repair a broken dataset. The method creates and maintains a backup log and an update log for a dataset. If the method finds a dataset structural error, then the method deletes the corrupted dataset, obtains the most current backup copy of the dataset, obtains all dataset updates made after the most current backup copy of the dataset was saved, and generates a recovered dataset using the most current backup and the dataset updates. | 2008-10-16 |
20080256313 | System, Method And Computer Program Product For Remote Mirroring - A method for remote mirroring, the method includes: (a) establishing a remote mirroring relationship between a primary site and a secondary site; (b) copying data from the primary site to the secondary site; and (c) writing status information by a primary site controller to a first memory space at the secondary site, the first memory space is allocated for storing status information representative of a relationship between (i) data stored in the primary site but destined to be copied to the secondary site and (ii) data copied from the primary site to the secondary site. | 2008-10-16 |
20080256314 | CONTROLLED ANTICIPATION IN CREATING A SHADOW COPY - Controlling data retention of a collection of data in a data store. An instruction is received to store a shadow collection of data to the data store. The data store has a previous version of the shadow collection of data. An available amount of data storage space on the data store is identified. An amount of data storage space needed is estimated for storing the shadow collection of data to the data store based on the received instruction. It is determined whether the identified available amount of data storage space is sufficient for storing the estimated amount of data storage space. The shadow collection of data is stored to the data store when said determine indicates that the identified available amount of data storage space is sufficient and the previous version is permitted to be deleted or to be overwritten. | 2008-10-16 |
20080256315 | BACKUP SYSTEM, BACKUP DEVICE, BACKUP REQUEST DEVICE, BACKUP METHOD, BACKUP REQUEST METHOD, BACKUP PROGRAM AND BACKUP REQUEST PROGRAM - In a backup system, a backup request device includes: a storage section that stores a piece of content data; and a transmission section that regards the piece of content data as a piece of backup target data and transmits, along with a piece of device identification information, a piece of backup information including a piece of data quality information and a piece of content identification information, while a backup device includes: a storage section that stores a piece of backup data that is the same content as the piece of backup target data and whose data quality is higher than or equal to the piece of backup target data such that it is associated with the piece of content identification information; and a control section that stores the received piece of backup information in the storage section such that it is associated with the received piece of device identification information. | 2008-10-16 |
20080256316 | Mirroring System Memory In Non-Volatile Random Access Memory (NVRAM) For Fast Power On/Off Cycling - A computer comprising a processor, a volatile main store, a non-volatile random access memory (NVRAM) mirror store, and optionally a cache for the non-volatile mirror store. While programs of the computer are operational, the contents of the volatile main store are mirrored in the non-volatile mirror store such that when a startup signal is received, the contents of the volatile main store are quickly restored from the contents of the non-volatile mirror store. | 2008-10-16 |
20080256317 | Storage system and computer system - A storage system that is capable of communicating with one or more host devices that issue a host input/output request, including two or more physical devices, one or more logical devices provided in the two or more physical devices, said logical devices each representing a logical volume provided in the two or more physical devices, one or more memories that store security information that is information corresponding with each of the one or more logical devices that serves to control access based on a host input/output request for the logical device, and a control device that controls access of a host input/output, said security information being used to permit or deny a read/write request requesting access to the first logical device, said read/write request including a logical unit number (LUN) related to the first logical. | 2008-10-16 |
20080256318 | Copy Engine and a Method for Data Movement - A copy engine ( | 2008-10-16 |
20080256319 | Memory controller - A memory controller includes a page configure module that communicates with a memory array comprising B memory blocks each including P pages. The page configure module selectively configures memory cells in the P pages of each of the B memory blocks to store from 1 to T bits per cell. The page configure module also generates a memory map based on the configuration. B, P, and T are integers greater than 1. At least one of a write module selectively writes data to the memory array based on the memory map or a read module selectively reads data from the memory array based on the memory map. | 2008-10-16 |
20080256320 | Method For Storing Messages in a Message Memory and Message Memory - In a method for storing messages in a communications module, the messages to be stored contain first data having a first data volume and second data having a second data volume, and it is possible for the second data volume to be different per message. A message memory contains a header segment, in which the first data of the message are stored in a respective header area per message, and the message memory also contains a data segment, in which the second data of the message are stored in a respective data area per message The message memory is configured such that a division between the header segment and the data segment is variable, depending on the number of messages and the second data volume. | 2008-10-16 |
20080256321 | System and Method for Tracking the Memory State of a Migrating Logical Partition - An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the logical partition for transferring. The state may include a value or other data used to track changes affecting the page or the relative ease and/or appropriateness of migrating the page. A page manager table with entries corresponding to the state of each page of the logical partition may be used to track the state while the logical partition continues to run during a migration. | 2008-10-16 |
20080256322 | Secure storage apparatus and method for controlling the same - The present invention discloses a storage apparatus in communication with one or more external systems, including at least one storage region, at least one logical partition formed by using a first part of the storage region for storing data, and a logic controller, provided with an authentication module for setting one access mode for controlling access to the logical partition according to the access mode when a vendor command from the external system requesting access to the logical partition is received. | 2008-10-16 |
20080256323 | Reconfiguring a Storage Area Network - The invention relates to a method and apparatus for reconfiguring a portion of a storage area network by establishing one or more auxiliary data paths, configuring the storage area network to re-route communications from the portion of the storage area network to be reconfigured to the one or more auxiliary data paths and reconfiguring the portion of the storage area network while the communications are being re-routed. | 2008-10-16 |
20080256324 | IMPLEMENTING A FAST FILE SYNCHRONIZATION IN A DATA PROCESSING SYSTEM - A system and method for implementing a fast file synchronization in a data processing system. A memory management unit divides a file stored in system memory into a collection of data block groups. In response to a master (e.g., processing unit, peripheral, etc.) modifying a first data block group among the collection of data block groups, the memory management unit writes a first block group number associated with the first data block group to system memory. In response to a master modifying a second data block group, the memory management unit writes the first data block group to a hard disk drive and writes a second data block group number associated with the second data block group to system memory. In response to a request to update modified data block groups of the file stored in the system memory to the hard disk drive, the memory management unit writes the second data block to the hard disk drive. | 2008-10-16 |
20080256325 | Memory Device and Device for Reading Out - A device includes an input for an N-bit data word. A circuit is adapted to map the N-bit data word to a physical M-bit memory data word by means of a mapping rule. The mapping rule includes a quantity of values of possible physical M-bit memory data words the mean number of first physical bit values of which is smaller than N/2. The circuit also includes output for the physical M-bit memory data word. Memory cells are couplable to the output. | 2008-10-16 |
20080256326 | Subsegmenting for efficient storage, resemblance determination, and transmission - Transmitting or storing subsegments is disclosed. A data stream or a data block is received and broken into a plurality of segments. For at least one segment, the segment is broken into a plurality of subsegments. A previously stored or transmitted segment similar to the at least one segment is identified. A fingerprint is computed for at least one subsegment. And, using the fingerprint for the at least one subsegment, determining whether the at least one subsegment is identical to a subsegment of the previously stored or transmitted segment without directly comparing the content of the at leas one subsegment with the content of the subsegment of the previously stored or transmitted segment. | 2008-10-16 |
20080256327 | System and Method for Maintaining Page Tables Used During a Logical Partition Migration - An apparatus, program product and method maintains data integrity for a logical partition by enabling nonintrusive switching of page tables used during a migration of the logical partition from a source computer system to a target computer system. A first page table may be configured to store a plurality of page entries made within a logically partitioned environment. A second page table may be used during migration to store one or more page entries generated during the migration. After migration, the processor page table pointer may be transparently switched to point to the first page table. A page entry in the second page table corresponding to a page entry made to the first page table by the logical partition may be invalidated in response to a page table hypervisor call made by the logical partition. In parallel, a plurality of entries generated during the migration of the logical partition in the second page table may be read through and invalidated. This reading through of the entries may be accomplished concurrently with the invalidation of the corresponding page entry in the second page table in response to a page table call made by the logical partition. Moreover, the reading of the entries may be accomplished in intervals and with portions of the plurality of entries. | 2008-10-16 |
20080256328 | Customizable memory indexing functions - Methods and apparatus related to memory indexing. Receiving indications of an indexing function for use with a memory. Performing indexing functions with a processor before addressing a memory location. Referencing a customizable lookup table to determine a memory location. Translating a computer program to control a computer system to use a desired indexing function. Determining desired indexing functions based on performance of a computer system. | 2008-10-16 |
20080256329 | Multi-Magnitudinal Vectors with Resolution Based on Source Vector Features - Methods, systems and computer program products for resolving multiple magnitudes assigned to a target vector are disclosed. A target vector that includes one or more target vector dimensions is received. One of the target vector dimensions is processed to determine a total number of magnitudes assigned to the processed target vector dimension. Also, a source vector that includes one or more source vector dimensions is received. The received source vector is processed to determine a total number of features associated with the source vector. When it is detected that the total number of magnitudes assigned to the processed target vector dimension exceeds one, one of the assigned magnitudes is selected based on one of the determined features associated with the source vector. | 2008-10-16 |
20080256330 | Programming environment for heterogeneous processor resource integration - Compiling a source code program for a heterogeneous multi-core processor having a first instruction sequencer, having a first instruction set architecture, an accelerator to the first instruction sequencer, wherein the accelerator comprises a heterogeneous resource with respect to the first instruction sequencer having a second instruction set architecture, the source code program having specified therein a region of source code for the first instruction set architecture of the processor and a region of source code for the second instruction set architecture of the processor. | 2008-10-16 |
20080256331 | ARITHMETIC DEVICE CAPABLE OF OBTAINING HIGH-ACCURACY CALCULATION RESULTS - A plurality of general-purpose registers each has a first bit width. A computing unit has a first and a second input end, at least the first input end having a second bit width wider than the first bit width, and performs an arithmetical operation on data supplied from the general-purpose registers to the first and second input ends. An overflow register having a bit width narrower than the first bit width holds data on figures overflowed as a result of calculation by the computing unit as overflow data and supplies the held overflow data as higher-order bits to at least one input end of the computing unit. | 2008-10-16 |
20080256332 | Processes and devices for compression and decompression of executable code by a microprocessor with a RISC architecture - The invention relates to a process for compression of executable code ( | 2008-10-16 |
20080256333 | SYSTEM AND METHOD FOR IGNORING FETCH PROTECTION - A system, method, and program product is provided that receives an instruction to fetch data from a data page. The data page is associated with a storage key and a fetch protection bit, and the instruction is pointed to by the program status word (PSW) that includes a PSW key and an ignore fetch protection bit. The data is fetched from the data page when the PSW key is a non-zero value, the PSW key is different than the storage key, and both the fetch protection bit and the ignore fetch protection bit are set ON. However, the data is not fetched from the data page when the PSW key is a non-zero value, the PSW key is different than the storage key, the fetch protection bit is ON, and the ignore fetch protection bit is OFF. | 2008-10-16 |
20080256334 | Processing System and Method for Executing Instructions - A processing system for executing instructions comprises a first part ( | 2008-10-16 |
20080256335 | MICROPROCESSOR, MICROCOMPUTER, AND ELECTRONIC INSTRUMENT - A microprocessor includes a pipeline control section which controls a pipeline process. The pipeline control section decodes an instruction code of an interrupt instruction and causes an immediate generation section to generate a vector address used for referring to information relating to a branch destination address corresponding to the interrupt instruction stored in a vector table based on a decoding result in a first instruction execution stage of the interrupt instruction. The pipeline control section controls the pipeline process so that the vector address is set in a pipeline register | 2008-10-16 |
20080256336 | MICROPROCESSOR WITH PRIVATE MICROCODE RAM - A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macroarchitecture, thereby enabling it to provide significantly more storage for microcode. The microinstruction set includes a microinstruction for loading data from the PRAM into the user-accessible registers, and a microinstruction for storing data from user-accessible registers to the PRAM. The microcode may also use the two microinstructions to load/store between the PRAM and non-user-accessible registers of the microarchitecture. Examples of PRAM uses include: computational temporary storage area; storage of x86 VMX VMCS in response to VMREAD and VMWRITE macroinstructions; instantiation of non-user-accessible storage, such as the x86 SMBASE register; and instantiation of x86 MSRs that tolerate the additional access latency of the PRAM, such as the IA32_SYSENTER_CS MSR. | 2008-10-16 |
20080256337 | Method of Decoding A Bit Sequence, Network Element Apparatus And PDU Specification Tool Kit - In the field of data communications, it is desirable to track bits of a bit sequence remaining to be decoded by a decoder. A method of decoding the bit sequence that corresponds to a PDU comprises reading-in a bit sequence and processing the bit sequence. In order to maintain a record of the bits reaming to be processed, a data stack is used during decoding of the bit sequence. | 2008-10-16 |
20080256338 | Techniques for Storing Instructions and Related Information in a Memory Hierarchy - A memory subsystem includes a first memory, a second memory, a first compressor, and a first decompressor. The first memory is configured to store instruction bytes of a fetch window and to store first predecode information and first branch information that characterizes the instruction bytes of the fetch window. The second memory is configured to store the instruction bytes of the fetch window upon eviction of the instruction bytes from the first memory and to store combined predecode/branch information that also characterizes the instruction bytes of the fetch window. The first compressor is configured to compress the first predecode information and the first branch information into the combined predecode/branch information. The first decompressor is configured to decode at least some of the instruction bytes stored in the second memory to convert the combined predecode/branch information into second predecode information, which corresponds to an uncompressed version of the first predecode information, for storage in the third memory. | 2008-10-16 |
20080256339 | Techniques for Tracing Processes in a Multi-Threaded Processor - A technique for tracing processes executing in a multi-threaded processor includes forming a trace message that includes a virtual core identification (VCID) that identifies an associated thread. The trace message, including the VCID, is then transmitted to a debug tool. | 2008-10-16 |
20080256340 | Distributed File Fuzzing - Embodiments provide a distributed file fuzzing environment. In an embodiment, a number of computing devices can be used as part of a distributing fuzzing system. Fuzzing operations can be distributed to the number of computing devices and processed accordingly. A group or team can be defined to process particular fuzzing operations that may be best suited to the group. The time required to perform a fuzzing operation can be reduced by distributing the fuzzing work to the number of computing devices. A client can be associated with each computing device and used in conjunction with fuzzing operations. | 2008-10-16 |
20080256341 | Data Processing Pipeline Selection - Strategies for automatically selecting the most appropriate processing pipeline (or runtime) for a particular data item are described. In one embodiment, a media playing application automatically selects the most appropriate media processing pipeline for a media data item from multiple available processing pipelines, or candidates. In this regard, the application makes this selection by utilizing heuristic techniques to identify which available pipeline provides the most enhanced playback experience to a user with respect to certain attributes such as supported playback features and security. These heuristic techniques can take one or more criteria into account and can be implemented in any suitable way. By way of example and not limitation, in one embodiment, a selection process is used wherein potential pipeline candidates are ordered and sequentially evaluated. | 2008-10-16 |
20080256342 | SCALABLE AND CONFIGURABLE EXECUTION PIPELINE - Optimizing pipeline handler execution. A method may be practiced in a computing environment including an execution pipeline. The method includes acts to optimize execution of handlers in the pipeline. The method includes receiving a payload object. Policy information about the payload object is referenced. The policy information includes at least one property value. Based on the policy information about the payload object, handlers are selected from among the pipeline to execute on the payload object. The policy information may be referenced by strategies. Handlers may be registered with the strategies to facilitate the strategies being used to select handlers. | 2008-10-16 |
20080256343 | Convergence determination and scaling factor estimation based on sensed switching activity or measured power consumption - A method and system for determining convergence of iterative processes and estimating a scaling factor in decoding processes based on switching activity of the logic circuitry are provided. During execution of an iterative process using logic circuitry comprising logic gates switching activity of a plurality of the logic gates is sensed to determine switching data indicative of a total switching activity of the plurality of the logic gates. The iterative process is iterated using the logic circuitry until convergence is indicated by the switching data. Similarly, a scaling factor for use in decoding processes is determined based on the switching data. | 2008-10-16 |
20080256344 | Scan Configuration of Field Programmable Gate Arrays - Embodiments herein include a method, service, apparatus, etc., that sets at least one integrated circuit board (that has programmable elements) to a programming state. When such programmable elements are set to the programming state, they are capable of being changed. Once the programmable elements are set to be changed, at least one printed sheet is scanned. The scanning can be preformed using any scanner that is operatively connected to the integrated circuit board through, for example, a processor. Again, the printed data (e.g., the barcodes or glyphs or other computer-only readable markings) on the printed sheet comprises the reprogramming data. The processor reads the barcodes or glyphs from the bitmap generated by the scanner, and executes the reprogramming data to change the logical instructions and data maintained within the programmable elements. | 2008-10-16 |
20080256345 | Method and Apparatus for Conserving Power by Throttling Instruction Fetching When a Processor Encounters Low Confidence Branches in an Information Handling System - An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions. | 2008-10-16 |