42nd week of 2008 patent applcation highlights part 27 |
Patent application number | Title | Published |
20080253142 | VEHICLE LIGHTING UNIT - A vehicle lighting unit is provided with: a projection lens arranged on a lens center axis extending in a longitudinal direction of a vehicle; a light source arranged on a rear side of a rear focal point of the projection lens; a reflector for reflecting forward a light from the light source toward the lens center axis; and a shade. An upper end edge of the shade passes in a vicinity of the rear focal point of the projection lens to shield a part of a reflected light from the reflector. An optical axis of the reflector is shifted from the lens center axis that is set to pass through an upper end edge of the shade so that the optical axis of the reflector is apart from the upper end edge. | 2008-10-16 |
20080253143 | COMPACT LIGHTING DEVICE FULFILLING A BENDING LIGHT FUNCTION - A lighting device for a motor vehicle producing a global light beam, the lighting device comprising a first fixed optical module comprising at least one first light source for producing a first light beam of the type consisting of a light beam with a substantially flat and horizontal cutoff. The lighting device also comprises a second movable optical module comprising at least one first light source for producing a second light beam of the type consisting of a light beam with non-flat cutoff able to be moved with respect to the first light beam. | 2008-10-16 |
20080253144 | Semiconductor light engine using polymer light pipes and lighting systems constructed with the light engine - A light engine for use in systems such as automotive lighting systems employs two or more semiconductor light sources, such as LEDs. Light emitted from the light sources is captured by light pipes which are mounted such that the light capturing surface of the light pipes are properly positioned, with respect to the semiconductor light sources, substantially independent of changes in the dimensions of the light pipes which may result from thermal expansion or contraction of the light pipes. The light pipes transfer substantially all of the light captured from the semiconductor light sources to light emitting surfaces of the light pipes which can be appropriately located adjacent the output optics of the lighting system. The light engine can be easily assembled as the light pipes are retained in slots on a positioning member which is mounted at a known position with respect to the semiconductor light sources. | 2008-10-16 |
20080253145 | EQUIPPED FLEXIBLE ELECTRONIC SUPPORT, SUPPORTING AT LEAST ONE LIGHT EMITTING DIODE, AND THE ASSOCIATED MANUFACTURING METHOD - A motor vehicle light comprising an equipped flexible electronic support that comprises: a flat flexible insulating support equipped on a first face with a plurality of flat conductive tracks; at least one light source of the light emitting diode type disposed on the first face of the flexible insulating support; wherein a second face of the flexible insulating support is covered with a layer of thermally conductive material for dissipating the heat produced by the light emitting diodes, the layer comprising an area of contact with the diode and an extended area extending out of this contact area, the dissipation of the heat taking place essentially at this extended area. | 2008-10-16 |
20080253146 | LIGHT UNIFORMING ELEMENT AND ILLUMINATION SYSTEM - A light uniforming element adapted to an illumination system with multiple lamps is provided. The light uniforming element includes a hollow rod and a plurality of solid rods. The hollow rod has a first light input end and a first light output end opposite to the first light input end. Each of the solid rods has a second light input end and a second light output end opposite to the second light input end. The second light output ends are inserted into the first light input end of the hollow rod. The light outputting efficiency of the light uniforming element is relatively high to improve an image quality of a projection apparatus. | 2008-10-16 |
20080253147 | BACKLIGHT UNIT HAVING IMPROVED CHROMATIC DISPERSION - Provided is a backlight device that includes: a light guide panel having a diffraction pattern for emitting light through an emission surface of the light guide panel by diffracting light entering the light guide panel; and a chromatic dispersion compensation member that is an optical transmitting member located on a light emission side of the light guide panel and has a lattice pattern having a depth in a direction vertical to the emission surface of the light guide panel. | 2008-10-16 |
20080253148 | Polymerizable Composition Comprising Low Molecular Weight Organic Component - Polymerizable compositions comprising particularly useful for brightness enhancing films. | 2008-10-16 |
20080253149 | COMPOSITE TRANSFORMER AND INSULATED SWITCHING POWER SOURCE DEVICE - An E-shaped transformer core has a middle leg and one pair of outer legs and on opposite sides with respect to the middle leg. A first pair of coils including at least two coils are wound around the middle leg so that a power transmission transformer unit is formed. The outer leg is divided into two outer leg portions and with a space therebetween allowing coil wiring therebetween, and a second pair of coils including two coils are respectively wound around the respective two outer leg portions and so as to have mutually opposite winding directions, so that a signal transmission transformer unit is formed. | 2008-10-16 |
20080253150 | Flyback converter providing simplified control of rectifier MOSFETS when utilizing both stacked secondary windings and synchronous rectification - The present invention provides methods and systems for a flyback converter arranged with synchronous rectifier MOSFETS in such a manner that they operate with a common source potential while still providing for the use of a stacked output winding. With a common source potential, a single rectifier control voltage can be used to operate the rectifiers for multiple outputs greatly simplifying the control circuit. Advantageously, the present invention maintains the inherent simplicity of the flyback design while enabling designs with well-regulated multiple voltage outputs and the efficiency benefits of synchronous rectification. | 2008-10-16 |
20080253151 | METHOD AND APPARATUS TO REDUCE DYNAMIC Rdson IN A POWER SWITCHING CIRCUIT HAVING A III-NITRIDE DEVICE - A method of preventing the Rdson of a III-V Nitride power switching circuit from varying over time. The method includes biasing the switch to a pre-bias voltage level just below turn ON when the switch is OFF, wherein traps are discharged when the switch is biased to the pre-bias voltage level just below turn ON and the varying of the Rdson over time due to traps is reduced. The method can be employed in DC-DC converter circuits having III-V Nitride control and synchronous switches connected at a switching node. | 2008-10-16 |
20080253152 | Method for Reducing Body Diode Conduction in NMOS Synchronous Rectifiers - A switching regulator that practices the current invention includes a high-side switch M1 connected between an input voltage and a node L | 2008-10-16 |
20080253153 | Active Power Conditioner - An active power conditioner includes a first power electronic switch set, a second power electronic switch set, a third power electronic switch set, an input filter and an output filter. The active power conditioner can supply a stable AC voltage to a load when a voltage variation is occurred at an AC power source by controlling either the second power electronic switch set or the third power electronic switch set via high-frequency switching, and the other power electronic switch sets that are not switched in high frequency are controlled to switch in low-frequency switching. | 2008-10-16 |
20080253154 | Inrush Current Limiter Device and Power Factor Control (Pfc) Circuit Having an Improved Inrush Current Limiter Device - The present invention relates to an inrush current limiter device ( | 2008-10-16 |
20080253155 | Power Supply with Current Limiting Circuits - A power supply ( | 2008-10-16 |
20080253156 | DC/DC POWER CONVERSION DEVICE - A DC/DC power conversion device with smoothing capacitors including three column circuits share the smoothing capacitors to be connected in parallel, each column circuit have a plurality of circuits connected in series where two MOSFETs are connected in series between both ends of respective smoothing capacitors and LC serial bodies of capacitors and inductors with the same resonant cycle are disposed between the circuits at two middle terminals. Driving signals for the respective column circuits have the same driving cycle identical with the resonant cycle of the LC serial bodies, and are out of phase with each other by 2π/3(rad), and thus charge-discharge currents towards the smoothing capacitors are circulated among the column circuits and ripple currents flowing through the smoothing capacitors are reduced. | 2008-10-16 |
20080253157 | Method for Switching Low-Power Using Ac and System for Performing the Same and Power Supply for Using the System - A power control method using AC power, the method being capable of performing: low power control that passes only two portions of positive direction waves of each one-cycle sine wave of the AC power and only two portions of negative direction waves of each one-cycle sine wave of the AC power, which have voltage levels lower than a set reference voltage level, through a system; and high power control that does not pass only two portions of positive direction waves of each one-cycle sine wave of the AC power and only two portions of negative direction waves of each one-cycle sine wave of the AC power, which have voltage levels lower than a set reference voltage level, through the system. | 2008-10-16 |
20080253158 | Power Converter - There are provided: sets of pairs of main circuit switching elements ( | 2008-10-16 |
20080253159 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises word lines, global bit lines intersecting with the word lines; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; global sense amplifiers for amplifying the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line and for selectively coupling the signal to an external data line. | 2008-10-16 |
20080253160 | INTEGRATED CIRCUIT HAVING A MEMORY CELL ARRAY AND METHOD OF FORMING AN INTEGRATED CIRCUIT - An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75. | 2008-10-16 |
20080253161 | SEQUENCE OF CURRENT PULSES FOR DEPINNING MAGNETIC DOMAIN WALLS - A method and structure for depinning a domain wall that is in spatial confinement by a pinning potential to within a local region of a magnetic device. At least one current pulse applied to the domain has a pulse length sufficiently close to a precession period of the domain wall motion and the current pulses are separated by a pulse interval sufficiently close to the precession period such that: the at least one current pulse causes a depinning of the domain wall such that the domain wall escapes the spatial confinement; and each current pulse has an amplitude less than the minimum amplitude of a direct current that would cause the depinning if the direct current were applied to the domain wall instead of the at least one current pulse. The pulse length and pulse interval may be in a range of 25% to 75% of the precession period. | 2008-10-16 |
20080253162 | MULTIBIT ROM MEMORY - The invention concerns a ROM comprising a set of memory points arranged in rows and columns, each memory point capable of storing two bits of data and comprising a single switch controllable to connect together first and second terminals of said switch, each of said first and second terminals being connected to one of first, second and third conductive lines, wherein said switch is connected via said first and second terminals between said first and second lines to encode a first data value, between said first and third lines to encode a second data value, between said second and third lines to encode a third data value, and both of said first and second terminals being connected to the same one of said first, second and third lines to encode a fourth data value. | 2008-10-16 |
20080253163 | FERROELECTRIC RANDOM ACCESS MEMORY CIRCUITS FOR GUARDING AGAINST OPERATION WITH OUT-OF-RANGE VOLTAGES AND METHODS OF OPERATING SAME - A semiconductor device can include a first ferroelectric random access memory to which a first voltage is applied and a second ferroelectric random access memory to which a second voltage is applied, where the second voltage is lower than the first voltage. A data protection circuit can determine whether test data is normally read from the second ferroelectric random access memory or whether a write-back operation is normally performed on the second ferroelectric random access memory on the basis of the second voltage. The data protection circuit can also generate a read prevention control signal to control whether a read operation is to be performed on the first ferroelectric random access memory based on the determined result. | 2008-10-16 |
20080253164 | Integrated Circuit, Resistivity Changing Memory Device, Memory Module and Method of Fabricating an Integrated Circuit - According to one embodiment of the present invention, an integrated circuit includes a plurality of resistivity changing memory cells, and a plurality of conductive elements being electrically connected to the resistivity changing memory cells, at least some of the conductive elements comprising copper. | 2008-10-16 |
20080253165 | Method of Manufacturing a Memory Device, Memory Device, Cell, Integrated Circuit, Memory Module, and Computing System - In one embodiment of the present invention, a method of fabricating a memory device includes: providing a composite structure including a resistivity changing layer and a first conductive layer disposed on or above the resistivity changing layer, forming a second conductive layer on or above the first conductive layer, and patterning the second conductive layer such that at least a part of the patterned second conductive layer is usable as a via for contacting the first conductive layer. | 2008-10-16 |
20080253166 | Integrated Circuit, Method for Manufacturing an Integrated Circuit, Memory Cell Array, Memory Module, and Device - According to one embodiment of the present invention, a memory cell array comprises a plurality of voids, the spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids. | 2008-10-16 |
20080253167 | Integrated Circuit, Method of Operating an Integrated Circuit, Method of Manufacturing an Integrated Circuit, Active Element, Memory Module, and Computing System - According to one embodiment of the present invention, an active element includes a reactive electrode, an inert electrode and a solid electrolyte disposed between the reactive electrode and the inert electrode. The solid electrolyte has a negative differential resistance. | 2008-10-16 |
20080253168 | Integrated circuit, resistivity changing memory device, memory module, and method of fabricating an integrated circuit - According to one embodiment of the present invention, a memory device includes a composite structure including a resistivity changing layer and an electrode layer being arranged on or above the resistivity changing layer. The resistivity changing memory device further includes a protection layer being arranged on or above the composite structure, the protection layer protecting the electrode layer against electromagnetic waves. | 2008-10-16 |
20080253169 | Semiconductor memory device and writing method thereof - A semiconductor memory device includes a phase-change memory and has high compatibility with DRAM interface. The memory cell array comprises a memory cell that includes a phase-change element provided at the intersection of a bit line and word line. A write address and data accompanying a write request are temporarily held in a write address register and a data register respectively, and a write operation is not performed on the memory cell array in this cycle of write request. And when a next write request occurs, the held data is written to the memory cell array. At this time, two write cycles—RESET cycle and SET cycle—are provided. Then the written contents of the memory cell and the rewrite data are compared, and after only SET cells are temporarily RESET (amorphization, increasing the resistance), it is operated so as to write only SET data (crystallization, lowering the resistance). | 2008-10-16 |
20080253170 | SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device A semiconductor device may include a SRAM cell having a first inverter, a second inverter, a first transfer transistor and a second transistor, the first inverter having a first load transistor and a first driver transistor connected to the first load transistor, the second inverter having a second load transistor and a second driver transistor connected to the second load transistor, a voltage supplying circuit configured to supply a voltage to one of the terminals of the first driver transistor and one of the terminals of the second driver transistor, the voltage which is one of more than a GND voltage and less than a GND voltage. | 2008-10-16 |
20080253171 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor. | 2008-10-16 |
20080253172 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of memory cells arranged in a matrix, a plurality of word lines corresponding to respective rows of the plurality of memory cells, a plurality of word line drivers for driving the plurality of word lines, respectively, and a plurality of pull-down circuits connected to the plurality of word lines, respectively, for causing voltages of the respective connected word lines to be lower than or equal to a power supply voltage when the respective word lines are in an active state. The word line drivers each have a transistor for causing the corresponding word line to go into the active state. The pull-down circuits each have a pull-down transistor for pulling down the corresponding word line, the pull-down transistor being a transistor having the same conductivity type as that of the transistor included the word line driver for driving the corresponding word line. | 2008-10-16 |
20080253173 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory according to an example of the invention comprises a first reference bit line shared by first reference cells, a second reference bit line shared by second reference cells, a first driver-sinker to feed a first writing current, a second driver-sinker to feed a second writing current, and a control circuit which checks data stored in the first and second reference cells line by line, and executes writing simultaneously to all of the first and second reference cells by a uniaxial writing when the data is broken. | 2008-10-16 |
20080253174 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETORESISTIVE RANDOM ACCESS MEMORY USING THE SAME - A magnetoresistive effect element includes a first magnetic layer, a second magnetic layer, and a first spacer layer. The first magnetic layer has an invariable magnetization direction. The second magnetic layer has a variable magnetization direction, and contains at least one element selected from Fe, Co, and Ni, at least one element selected from Ru, Rh, Pd, Ag, Re, Os, Ir, Pt, and Au, and at least one element selected from V, Cr, and Mn. The spacer layer is formed between the first magnetic layer and the second magnetic layer, and made of a nonmagnetic material. A bidirectional electric current flowing through the first magnetic layer, the spacer layer, and the second magnetic layer makes the magnetization direction of the second magnetic layer variable. | 2008-10-16 |
20080253175 | NONVOLATILE MAGNETIC MEMORY DEVICE AND PHOTOMASK - A nonvolatile magnetic memory device including a magntoresistance device having a recording layer formed of a ferromagnetic material for storing information by use of variation in resistance depending on the magnetization inversion state. The plan-view shape of the recording layer includes a pseudo-rhombic shape having four sides, at least two of the four sides each include a smooth curve having a central portion curved toward the center of the pseudo-rhombic shape. The easy axis of magnetization of the recording layer is substantially parallel to the longer axis of the pseudo-rhombic shape. The hard axis of magnetization of the recording layer is substantially parallel to the shorter axis of the pseudo-rhombic shape. The sides constituting the plan-view shape of the recording layer are smoothly connected to each other. | 2008-10-16 |
20080253176 | NONVOLATILE MAGNETIC MEMORY DEVICE AND PHOTOMASK - A nonvolatile magnetic memory device including a magntoresistance device having a recording layer formed of a ferromagnetic material for storing information by use of variation in resistance depending on the magnetization inversion state. The plan-view shape of the recording layer includes a pseudo-rhombic shape having four sides, at least two of the four sides each include a smooth curve having a central portion curved toward the center of the pseudo-rhombic shape. The easy axis of magnetization of the recording layer is substantially parallel to the longer axis of the pseudo-rhombic shape. The hard axis of magnetization of the recording layer is substantially parallel to the shorter axis of the pseudo-rhombic shape. The sides constituting the plan-view shape of the recording layer are smoothly connected to each other. | 2008-10-16 |
20080253177 | Write Operations for Phase-Change-Material Memory - Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed. | 2008-10-16 |
20080253178 | MRAM with enhanced programming margin - An MRAM that is not subject to accidental writing of half-selected memory elements is described, together with a method for its manufacture. The key features of this MRAM are a C-shaped memory element used in conjunction with a segmented bit line architecture. | 2008-10-16 |
20080253179 | SEMICONDUCTOR DEVICE, AN ELECTRONIC DEVICE AND A METHOD FOR OPERATING THE SAME - A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a non-addressed state. | 2008-10-16 |
20080253180 | Hardened Memory Cell - The memory cell comprises first and second inverter circuits, connected in a loop. First and second decoupling transistors, normally turned off outside the write phases, are respectively connected between an output of the second inverter circuit and first and second inputs of the first inverter circuit. The memory cell is thereby protected against transient disturbances due to ionizing particles. The gates of the decoupling transistors are preferably respectively connected to a supply voltage for the P-type decoupling transistors and grounded for the N-type decoupling transistors. | 2008-10-16 |
20080253181 | METHOD FOR PROGRAMMING A SEMICONDUCTOR MEMORY DEVICE - A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels. | 2008-10-16 |
20080253182 | NAND FLASH MEMORY DEVICE AND PROGRAMMING METHOD - A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating a program voltage to be supplied to the memory cell; and a program voltage controller controlling a start level of the program voltage. The device supplies an LSB start voltage to a selected word line during an LSB program, and an MSB start voltage higher than the LSB start voltage to the selected word line during an MSB program. | 2008-10-16 |
20080253183 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films. | 2008-10-16 |
20080253184 | NON VOLATILE MEMORY - An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation. | 2008-10-16 |
20080253185 | Non-Volatile Memory and Method with Control Gate Compensation for Source Line Bias Errors - Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor. | 2008-10-16 |
20080253186 | Bit line structure for a multilevel, dual-sided nonvolatile memory cell array - A nonvolatile memory array includes a plurality of dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells. Each NAND series string has a top select transistor and a bottom select transistor. Pairs of braided bit lines are connected in a braided columnar bit line structure such that each column of the dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells is connected to an associated pair of braided bit lines. | 2008-10-16 |
20080253187 | MULTIPLE SELECT GATE ARCHITECTURE - Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells. By utilizing multiple series-coupled select gates, each gate can be made using smaller features sizes while achieving the same level of protection against GIDL and other forms of current leakage. By reducing the feature size of the select gates, the footprint of the strings of memory cells can be reduced, thereby facilitating smaller memory device sizing. Further reductions in device sizing may be achieved utilizing a staggered self-aligned bit line contact configuration. | 2008-10-16 |
20080253188 | PROGRAMMING METHOD TO REDUCE GATE COUPLING INTERFERENCE FOR NON-VOLATILE MEMORY - A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory cells, so that the coupling effect results in the desired target threshold voltages for the cells. In one embodiment of the present invention, memory cell coupling is compensated for by adjusting programming level of one or more memory cells of a first page a memory array to a higher or lower threshold verify target voltage given the data/programming level to be written to directly adjacent memory cells of a second page, so that coupling between the directly adjacent memory cells of the first and second pages brings the memory cells of first page to their final target programming level. | 2008-10-16 |
20080253189 | MEMORY UNIT - A memory unit is provided herein. The present invention utilizes two non-volatile devices having a split gate structure to save a logic state of the memory unit. Thus, even when a power supply for the memory unit is shut down, the non-volatile devices can still save the logic state. The memory unit not only has the advantage of high speed operation of a static random access memory, but also functions as a non-volatile memory for saving data. | 2008-10-16 |
20080253190 | Non-volatile memory device and method of operating the same - The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled. | 2008-10-16 |
20080253191 | FLASH MEMORY DEVICE AND SET-UP DATA INITIALIZATION METHOD - A flash memory device includes a memory cell array having a set-up data region configured to store set-up data, wherein the set-up data includes first data and second data. The second data is stored in an empty cell area of the set-up data region. The flash memory also includes a page buffer and decoder configured to read the set-up data from the set-up data region, and a status detector receiving the set-up data from the page buffer and decoder and configured to discriminate the first data from the second data and generate a Pass/Fail status signal. | 2008-10-16 |
20080253192 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a memory cell array having a plurality of blocks, a storage unit, a block replacement information register group, and a bad block flag register group. The storage unit includes a block replacement information registration area with which it is possible to register block replacement information, and a bad block information registration area with which it is possible to register bad block information. The block replacement information register group is set in accordance with the block replacement information read out of the storage unit during a boot sequence, and the bad block flag register group is set in accordance with both of the block replacement information and the bad block information read out of the storage unit during the boot sequence. | 2008-10-16 |
20080253193 | Non-Volatile Memory with Predictive Programming - In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to program a given memory cell to a given target threshold voltage level. In this way, no verify operation needs to be performed, thereby greatly improving the performance of the programming operation. In a preferred embodiment, the predetermined function is linear and is calibrated for each memory cell under programming by one or more checkpoints. A checkpoint is a set of coordinates on the predetermined function determined by a conventional programming mode employing alternating program and verify operations. | 2008-10-16 |
20080253194 | FLASH MEMORY DEVICE AND PROGRAM METHOD THEREOF - A method of programming a plurality of memory cells in a flash memory device from a first state to a second state includes verifying the plurality of memory cells using a verify voltage having a level increased according to an increase in a program loop number; and programming the plurality of memory cells using a program voltage having an increment decreased according to an increase in the program loop number, wherein the verifying and programming steps constitute a program loop, the program loop being terminated at a point in time when a level of the verify voltage reaches to a voltage range of the second state. | 2008-10-16 |
20080253195 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MOS TRANSISTOR HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND DATA READOUT METHOD THEREOF - A semiconductor memory device includes first and second memory cells and a sense amplifier. The first memory cell includes a MOS transistor and is capable of retaining n-bit (n is a natural number more than one) first data. The MOS transistor includes a charge accumulation layer and a control gate. The second memory cell retains second data. The second data is a criterion for the first data. The sense amplifier determines the first data read out from the first memory cell and amplifies the first data using a first reference level and a second reference level. The first reference level is obtained based on the second data read out from the second memory cell. The second reference level is generated inside based on the first reference level. | 2008-10-16 |
20080253196 | METHOD AND APPARATUS FOR CHARGING LARGE CAPACITANCES - A method and apparatus for charging large capacitances of a circuit, such as an integrated circuit, without imparting noise on an operating voltage. A comparator compares a reference voltage to a voltage representing the voltage on the capacitance and a multiplexer routes one of an external voltage or an operating voltage derived from said external voltage to charge the capacitance depending on the output of the comparator. | 2008-10-16 |
20080253197 | Predictive Programming in Non-Volatile Memory - In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to program a given memory cell to a given target threshold voltage level. In this way, no verify operation needs to be performed, thereby greatly improving the performance of the programming operation. In a preferred embodiment, the predetermined function is linear and is calibrated for each memory cell under programming by one or more checkpoints. The checkpoint is an actual programming voltage that programs the memory cell in question to a verified designated threshold voltage level. | 2008-10-16 |
20080253198 | SEMICONDUCTOR MEMORY DEVICE WITH A NOISE FILTER AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a memory cell array, an output buffer circuit and an input buffer circuit. The memory cell array includes a plurality of memory cells holding data. The output buffer circuit outputs data read from the memory cells. The input buffer circuit receives an address signal for the memory cells and includes a noise filter to remove noise. The filter length of the noise filter is variable according to the output capability of the data in the output buffer circuit. | 2008-10-16 |
20080253199 | PARALLEL DATA STORAGE SYSTEM - A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A switch is used to selectively connect the interface and the data storage devices to the buffer to facilitate the transfer of data into and out of the buffer. The data sectors are transferred by segmenting each sector into multiple smaller data cells and distributing these data cells among the data storage devices using an arbitrated distribution method. | 2008-10-16 |
20080253200 | Reading of the State of a Non-Volatile Storage Element - A method for reading of the state of a non-volatile memory element, comprising adjusting including conditioning the frequency of a first oscillatory to the state of this element, and comparing the frequency of the first oscillator with the predetermined frequency of a second oscillator, selected between two possible frequency values for the first oscillator, according to the state of the storage element. | 2008-10-16 |
20080253201 | APPARATUS AND METHOD FOR CALIBRATING ON-DIE TERMINATION IN SEMICONDUCTOR MEMORY DEVICE - An on-die termination circuit in a semiconductor memory apparatus can comprise a comparing block for comparing a reference voltage with a code voltage corresponding to a code and outputting a comparison signal, a counting block for changing the code based on the comparison signal, and controlling block for controlling the counting block based on a match result of previous and current values of the comparison signal. | 2008-10-16 |
20080253202 | Communicating Information Using an Existing Light Source of an Electronic Device - An electronic device | 2008-10-16 |
20080253203 | DATA OUTPUT CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - A data output circuit for a semiconductor memory apparatus includes a data output control unit that generates a selection signal, an output timing signal, and an input control signal in response to a read command and a clock, and a signal-responsive data output unit that receives parallel data in response to the input control signal, arranges the parallel data in response to the selection signal, and sequentially outputs the arranged parallel data as serial data in synchronization with the output timing signal. | 2008-10-16 |
20080253204 | Semiconductor memory apparatus including synchronous delay circuit unit - A semiconductor memory apparatus includes a write driver that receives data transmitted through an input/output line, and a synchronous delay circuit unit that generates an enable signal so as to allow the data transmitted through the input/output line to be supplied to the write driver. | 2008-10-16 |
20080253205 | WRITE CONTROL SIGNAL GENERATION CIRCUIT, SEMICONDUCTOR IC HAVING THE SAME AND METHOD OF DRIVING SEMICOUNDUCTOR IC - A write control signal generation circuit includes a delay/comparison/transmission block that outputs one of a delayed write command signal and a write command signal according to a test mode signal, and a control signal generation unit that generates a write control signal by delaying the output of the delay/comparison/transmission block corresponding to a variable amount of delay. | 2008-10-16 |
20080253206 | METAL PROGRAMMABLE SELF-TIMED MEMORIES - A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory. | 2008-10-16 |
20080253207 | METHOD AND APPARATUS FOR TESTING THE FUNCTIONALITY OF A PAGE DECODER - A method and apparatus for testing correct operation of a page decoder in a memory is provided. In one implementation, the method includes erasing the memory to reset all memory cells associated with each of the N pages in the memory, and iteratively generating a unique bit sequence of M bits and programming the unique bit sequence into a plurality of the N pages at a given time until each of the N pages contains a unique bit sequence relative to other pages in the memory. Responsive to each of the N pages having a unique bit sequence, the method further includes using the page decoder to read out each unique bit sequence associated with the N pages to verify correct operation of the page decoder. | 2008-10-16 |
20080253208 | SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY CHECKING METHOD - The semiconductor integrated circuit includes a memory for storing secret data, a memory BIST circuit for executing a memory. BIST, a first selector for switching between a path for a memory isolation test via an external terminal and a path from the memory BIST circuit, a second selector for switching between a path from the output of the first selector and a path from a normal circuit and having an output coupled to the memory, and a third selector for switching between a path from the output of the memory and a path for receiving a pseudo signal and receiving a check completion signal outputted from the memory BIST circuit as a selection signal. In this semiconductor integrated circuit, after the memory is initialized by executing the memory BIST, the memory can be accessed from the external terminal via the path for the memory isolation test. | 2008-10-16 |
20080253209 | Semiconductor memory device and method of testing same - Disclosed is a semiconductor memory device in which a cell is connected to word lines of at least first and second ports, and control of timing of activation of the word lines of the first and second ports is performed based upon first and second clock signals, respectively, comprising first and second test control signals in correspondence with the first and second clock signals that control the respective timings of activation of the word lines of the first and second ports. With regard to the cell with the first and second ports being selected, when the first test control signal is in an activated state and the second test control signal is in a deactivated state, control is exercised so as to mask the second clock signal and, responsive to the first clock signal, activate the first and second word lines simultaneously. When the second test control signal is in an activated state and the first test control signal is in a deactivated state, control is exercised so as to mask the first clock signal and, responsive to the second clock signal, activate the first and second word lines. | 2008-10-16 |
20080253210 | SEMICONDUCTOR MEMORY APPARATUS - Disclosed is a semiconductor memory apparatus capable of improving precharge performance. The semiconductor memory apparatus includes a plurality of memory banks, data input/output lines commonly connected to the memory banks, and a plurality of precharge circuit units connected to the data input/output lines and aligned in an extension direction of the data input/output lines while being spaced apart from each other by a predetermined distance. | 2008-10-16 |
20080253211 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory cell is implemented in which the area of a row selection circuit is reduced and the effects of exposure, etching, and so on performed during manufacture are eliminated. The semiconductor memory device is provided with word line selection circuits connected with a row address signal line to select some desired word line according to an address input and dummy word line potential fixation circuits connected to word lines for dummy memory cells. As in the case of the word line selection circuits, the dummy word line potential fixation circuits each include a NAND gate NANDR(i) (i=−1, 0, m+1, or m+2) and an inverter INVR(i) (i=−1, 0, m+1, or m+2). The inputs of the dummy word line potential fixation circuits are connected with a row address signal line such that the word lines for the dummy memory cells are maintained in a non-selected state at all times. These make it possible to make the circuits which selectively drive all the word lines identical with each other in configuration, reduce the area of the row selection circuit, and eliminate the effects of exposure, etching, and so on during manufacture. | 2008-10-16 |
20080253212 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory blocks, a plurality of refresh block counters, a refresh word line counter, and an arbitration circuit. The plurality of refresh block counters generate block addresses of at least two memory blocks to select at least two memory blocks to be refreshed from the plurality of memory blocks. The refresh word line counter generates a common word line address that is common to the at least two memory blocks. The arbitration circuit generates at least one first word line address based on the at least two block addresses and the common word line address and arbitrate so that each word line indicated by the at least one first word line address is refreshed during a period in which a word line indicated by an externally applied second word line address is accessed. | 2008-10-16 |
20080253213 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD FOR THE SAME - A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized. | 2008-10-16 |
20080253214 | Method and apparatus for incorporating DDR SDRAM into portable devices - A portable electronic device is provided which comprises (a) a memory device ( | 2008-10-16 |
20080253215 | Semiconductor memory circuit - The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized. | 2008-10-16 |
20080253216 | Semiconductor package for forming a Double Die Package (DDP) - A semiconductor package for forming a Double Die Package (DDP) with a plurality of single chips includes: a buffer configured to buffer an external address to generate a row address which is defined only in a DDP mode; a column address control unit configured to replace the row address with a column address, which is defined only in the DDP mode, in a single chip mode; and a read operation control unit configured to output a bank read signal latched in an active bank in a read mode of the DDP, and to selectively activate a first address control signal and a second address control signal for activating a bank selected from the single chip or the DDP in response to the bank read signal. | 2008-10-16 |
20080253217 | Method for accessing a memory cell in an integrated circuit, method of determining a set of word line voltage identifiers in an integrated circuit, method for classifying memory cells in an integrated circuit, method for determining a word line voltage for accessing a memory cell in an integrated circuit and integrated circuits - Embodiments of the invention relate to a method for accessing a memory cell in an integrated circuit, a method of determining a set of word line voltage identifiers in an integrated circuit, a method for classifying memory cells in an integrated circuit, a method for determining a word line voltage for accessing a memory cell in an integrated circuit and integrated circuits. In an embodiment, a method of accessing a memory cell in an integrated circuit, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes selecting a word line voltage identifier from a pre-stored set of word line voltage identifiers, each one of the pre-stored set of word line voltage identifiers being assigned to at least one of the memory cells in the memory cell field and accessing the memory cell using a word line voltage being dependent on the selected word line voltage identifier. | 2008-10-16 |
20080253218 | Column decoder and semiconductor memory apparatus using the same - A column decoder according includes: a plurality of main decoding units coupled to different memory banks that decode a pre-decoding signal and output column selection signals to the corresponding memory banks; and one or more pre-decoders, having a lesser number than the main decoders, which generates and outputs the pre-decoding signal by decoding the column address and the bank information signal. | 2008-10-16 |
20080253219 | ACTIVE DRIVER CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - An active driver control circuit for a semiconductor memory apparatus includes an asynchronous decoding unit that can be activated in response to a bank selection signal, when an external command is a read or write command, can generate an enabled read/write enable signal, and when a precharge signal is enabled, disable the enabled read/write enable signal, a synchronous decoding unit that can be activated in response to the bank selection signal, can generate an enabled active enable signal when the external command is an active command, when the external command is a precharge command, can generate the precharge signal, and output the active enable signal and the precharge signal in synchronization with a clock, and an active driver control signal generating unit that can generate an active driver control signal in response to the active enable signal and the read/write enable signal. | 2008-10-16 |
20080253220 | Flexible RAM Clock Enable - A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block. | 2008-10-16 |
20080253221 | Cordless Electric Powered Concrete Vibrator - A concrete finishing tool includes a power unit ( | 2008-10-16 |
20080253222 | Machine for Dosing and Mixing Liquid Products and Operating Method Thereof - The present dosing and mixing machine for liquid products and its operation system is intended for dosing, mixing, and homogenizing any liquid products regardless of their nature and application, that can operate either statically or dynamically, that includes a tank ( | 2008-10-16 |
20080253223 | One-Way Mixer Homogenizer, Extractor, Fractioner or Slurry Producer - A single-use mixer or homogenizer is provided that includes a container provided with a lid which is provided as a compression element ( | 2008-10-16 |
20080253224 | Agitator for a food mixer - A food mixer ( | 2008-10-16 |
20080253225 | Seismic Cable Positioning Using Coupled Inertial System Units - An apparatus and a method of its use in a marine seismic survey are disclosed. The apparatus includes a seismic survey object ( | 2008-10-16 |
20080253226 | System and method for marine seismic surveying - A system for marine seismic surveying comprises at least one marine seismic streamer; at least one pressure sensor mounted in the at least one marine seismic streamer; at least one particle motion sensor mounted in the at least one marine seismic streamer and collocated with the at least one pressure sensor, wherein the at least one particle motion sensor has a resonance frequency above 20 Hz; and computer means for combining pressure data from the at least one pressure sensor and particle motion data from the at least one particle motion sensor for further processing. | 2008-10-16 |
20080253227 | Method for prediction of surface related multiples from marine towed dual sensor seismic streamer data - Particle motion sensor signals and the pressure sensor signals data from a towed marine seismic streamer are combined to generate an up-going pressure wavefield component and a down-going particle motion wavefield component. The down-going particle motion wavefield component is extrapolated from the receiver position depth level to the source position depth level. The up-going pressure wavefield component is multiplied by the extrapolated down-going particle motion wavefield component, generating a first product. Then, n | 2008-10-16 |
20080253228 | Drill string telemetry methods and apparatus - A method is provided which transmits information using a plurality of data transmission nodes situated along a drill string. In this method, a first node obtains a transmission status of a second node. When the transmission status of the second node indicates that the second node meets a selected performance threshold, information is sent from the first node to the second node. When the transmission status of the second node indicates that the second node does not meet its performance threshold, then the first node obtains a transmission status of a third node. When the transmission status of the third node indicates that the third node meets a selected performance threshold, information is transmitted from the first node to the third node for relaying along the drill string. | 2008-10-16 |
20080253229 | METHODS AND APPARATUS FOR EXTRACTING FIRST ARRIVAL WAVE PACKETS IN A STRUCTURAL HEALTH MONITORING SYSTEM - Methods and apparatus for extracting the first arrival wave packet of an acoustic signal in a structural health monitoring (SHM) system include receiving an acoustic signal transmitted between two transducers thereof. Electromagnetic cross-talk is removed from the signal. Signal amplitude threshold values used for picking out the first arrival wave packet are chosen based on signal characteristics or chosen adaptively as the value that leads to the minimum variance of the group velocity estimates of all the actuation-sensing transducer pairs. The group velocity is estimated as the known actuator-sensor distance divided by the propagation time of the first wave packet of which the envelope exceeds a candidate threshold value. The first arrival wave packet is determined as the signal segment where the signal envelope first exceeds the chosen amplitude threshold and the segment length exceeds a specified threshold of time width. | 2008-10-16 |
20080253230 | System and method for receiving and decoding electromagnetic transmissions within a well - Exemplary systems and methods are directed to transmission of electromagnetic (EM) pulses in a downhole environment, which is located below a surface of a landform. A sequence of EM energy pulses is generated from a signal generator located at the surface of the landform. The energy pulses are reflected at a ring frequency by one or more downhole transducers. The reflected energy pulse is received at a receiver, which is located at the surface, during a predetermined time interval. The receiver detects the received energy pulses through a time domain or frequency domain technique. The detected ring frequency is correlated to a parameter or condition of the downhole environment. | 2008-10-16 |
20080253231 | FUNCTIONAL ACTUATOR-SENSOR PATH OPTIMIZATION IN STRUCTURAL HEALTH MONITORING SYSTEM - A method for optimizing transducer performance in an array of transducers in a structural health monitoring system includes specifying a plurality of paths between pairs of the transducers on a monitored structure and evaluating the quality of signal transmissions along the paths so as to optimize the gain and frequency operating condition of the transducers. | 2008-10-16 |
20080253232 | ELECTRONIC DEVICE AND ELECTROMAGNETIC WAVE TIMEPIECE - An electronic device includes: a timer which measures a current time; a display which displays information based on the time; a receiver which, by receiving and decoding a signal, including time information indicating a standard time, which is encoded by means of a predetermined communication system, acquires the time information; and a controller which, as well as instructing the receiver to acquire the time information, corrects a deviation of the measured time, based on the time information, and instructs the display to display information based on the corrected time, wherein the controller gives an instruction in such a way that no time period occurs in which both the receiver's operation of acquiring the time information, and the display's operation of displaying the information based on the corrected time, are executed. | 2008-10-16 |
20080253234 | Elapsed Time Device - An elapsed time and remaining time liquid crystal measuring device having a display face around the periphery of which there are a plurality of numerical indicia marks arranged in a generally clockwise pattern with successive numerical indicia marks decreasing in numerical value in a clockwise direction from a twelve o'clock position. An annular ring of electronically generated graphic indicia are visible on the display face and spaced inwardly from the peripheral numerical indicia and a digital numerical read-out display of elapsed times is visible internally of the annular ring of graphic indicia. There is at least one electronic control element for setting a desired elapsed set time into the device, which desired elapsed set time is indicated both on the digital read-out display and as a complete ring or an arcuate section of the annular ring on the display face. There is also an actuator for initiating progressive clockwise disappearing movement of the electronically generated graphic indicia so as to expose decreasing areas of the annular ring in a clockwise direction as time elapses and while the digital numerical display remains synchronized with the graphic indicia until all of the set time has elapsed. Preferably, the device is in the form of a wrist watch. | 2008-10-16 |
20080253235 | Timepiece Display Apparatus, Movement, and Timepiece - A timepiece display apparatus causes a day hand to move reciprocally by means of center wheel, driven day wheel, cam, lever, and rack. These wheels, cam, lever, and rack can be easily arranged to fit the available space on the main plate of the movement, and the construction of the display apparatus can thus be simplified. Furthermore, locating the cam between the rotary shaft and rack of the lever portion enables arranging a plurality of parts more compactly than if the cam is disposed to a different location, and affords a simple assembly. | 2008-10-16 |
20080253236 | Motor Drive Control Circuit, Semiconductor Device, Electronic Timepiece, and Electronic Timepiece with a Power Generating Device - A motor drive control circuit that operates using a primary power supply and controls driving a motor has a drive circuit that drives the motor, a power supply circuit that is disposed between the primary power supply and the drive circuit, and uses electrical energy supplied from the primary power supply to supply a drive voltage to the drive circuit, and a power supply control circuit that controls operation of the power supply circuit. The power supply control circuit monitors the drive voltage, stops the power supply circuit and stops supplying the drive voltage when the drive voltage is greater than or equal to a prescribed constant voltage, and activates the power supply circuit and supplies the drive voltage when the drive voltage is less than the prescribed constant voltage. | 2008-10-16 |
20080253237 | Methods and Apparatus for Automatic Information Retrieval through Internet and Providing the Feedback to Service Providers - Apparatuses and methods for automatically downloading Information through Internet and providing the feedback to service provider are disclosed. The apparatus can contain an adaptor device and a portable device, can automatically download the online content, such as audio, video, etc, from the internet. The apparatus can also upload the voice mailbox and survey feedback automatically to content providers and provide the interactive communication between the subscribers and the content providers. A service system maintains a searchable program database that subscribers can choose their favorite programs from. The service system also maintains the subscriber's registration information, checks the audio/video program update, and directs the apparatus by sending it the new content list for download. The service system also collects/processes subscriber's feedback. | 2008-10-16 |
20080253238 | OPTICAL DISC DEVICE AND REPRODUCTION METHOD - Due to the axial runout of an optical disc, a frequency of a high-frequency current to be superimposed onto a DC current could not be maintained. In order to solve the problem described above, a drive signal is generated by superimposing a high-frequency signal onto a DC current, the drive signal is applied to a laser beam light source, thereby the light source is driven; and a servo signal at a signal level corresponding to a defocus amount of the laser beam relative to the surface of the optical disc is generated based on a reflected light of the laser beam from the recording surface of the optical disc, and a low-frequency component of the servo signal is extracted, and thereby the frequency of the high-frequency signal to be superimposed onto the DC current in the light source driver is controlled based on the low-frequency component of the servo signal. | 2008-10-16 |
20080253239 | OPTICAL PICKUP AND METHOD FOR MANUFACTURING THE SAME - To increase the speed of operations and improve vibration properties by rotating holders to wind coils in objective lens driving means of an optical pickup. In an optical pickup wherein a tracking coil and two focusing coils are wound on the same surface of a coil holder, the coil holder includes a tracking coil holder and two focusing coil holders, and each of the tracking coil holder and two focusing coil holders has a hole passing through the center of each coil. | 2008-10-16 |
20080253240 | METHOD AND SYSTEM FOR CALIBRATING RECORDING TRACK OFFSET OF OPTICAL STORAGE DEVICE - A method for calibrating a recording track offset of an optical storage device accessing an optical storage medium of a land and groove recording/reproduction type includes: setting at least one control parameter of a track offset control loop of the optical storage device to drive the track offset control loop to enter an first state; and recording data onto the optical storage medium with the track offset control loop being enabled to derive the latest value of the recording track offset, where the track offset control loop is utilized for controlling the recording track offset. The method further includes setting the control parameter to drive the track offset control loop to enter a second state, where a loop response of the track offset control loop in the first state is different from that in the second state. | 2008-10-16 |
20080253241 | Optical pickup - An optical pickup includes an objective lens for focusing a light beam onto an optical disc surface, a bobbin for supporting the objective lens, the bobbin having a first side face and a second side face on the opposite side of the bobbin with respect to the first side face, a first pair of suspension wires and a second pair of suspension wires, each wire having a first end and a second end, each of the first pair of suspension wires being attached to the first side face of the bobbin at the first end, and each of the second pair of suspension wires being attached-to the second side face of the bobbin at the first end, and a base to which each of the first and second pair of suspension wires is attached at the second end, for supporting the bobbin so that the bobbin can swing on the base. The first and second pair of suspension wires are plated in accordance with at least one different plating requirement between the first pair of suspension wires and the second pair of suspension wires. | 2008-10-16 |
20080253242 | Information recording medium, recording method of information recording medium, and information recording and reproducing device - A information recording medium includes a data area and a system area. In the data area, a user data is recorded. In the system area, management information for managing a recording status of the data area is recorded. The management information recorded in the system area includes recording mode information which indicates a recording procedure of the user data in the data area. By this construction, an information recording medium, a recording method of an information recording medium and an information recording and reproducing medium which are able to appropriately treat an information recording medium having an availability to a plurality of recording mode when being loaded. | 2008-10-16 |