42nd week of 2008 patent applcation highlights part 14 |
Patent application number | Title | Published |
20080251840 | ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE - An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array. | 2008-10-16 |
20080251841 | MOS TRANSISTOR AND MANUFACTURING METHOD THEREOF - The structure of the MOS transistor provided in this invention has LDD (lightly doped drain) and halo doped regions removed from the source, the drain or both regions in the substrate for improved linearity range when operated as a voltage-controlled resistor. The removal of the LDD and halo doped regions is performed by simply modifying the standard mask of the MOS process using a logic operation layer with no extra mask required. | 2008-10-16 |
20080251842 | P-Channel FET Whose Hole Mobility is Improved by Applying Stress to the Channel Region and a Method of Manufacturing the Same - A p-channel FET which has a buried insulating film in the noncontact part of each of the source/drain regions has been disclosed. Compressional stress produced by volume expansion at the time of oxidization for the formation of the buried oxide films is applied to the channel region of the FET. | 2008-10-16 |
20080251843 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a semiconductor memory device including a substrate; an insulating film provided above the substrate; a semiconductor layer provided above the insulating film and extending in a plane which is parallel to a surface of the substrate; a first gate dielectric film provided on an inner wall of a opening penetrating through the semiconductor layer; a first gate electrode penetrating through the opening and isolated from the semiconductor layer by the first gate dielectric film; a second gate dielectric film formed on a side surface and an upper surface of the semiconductor layer located on the first gate electrode; and a second gate electrode provided on the side surface and the upper surface of the semiconductor layer via the second gate dielectric film, isolated from the first gate electrode, and superimposed on the first gate electrode. | 2008-10-16 |
20080251844 | METHOD FOR FORMING PATTERN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for forming a pattern includes the step of forming an electrically conductive film by applying a liquid composition onto a first plate. The liquid composition includes an organic solvent and conductive particles surface-modified with a fatty acid or an aliphatic amine. Then, a second pattern, which is a reverse pattern of a first pattern, is formed on the first plate by pressing a second plate having a concave-convex pattern on a surface thereof on a surface of the first plate having the electrically conductive film on the surface thereof. Then, the first pattern of the electrically conductive film is transferred onto convex top faces of the second plate. Then, the second pattern is transferred onto a surface of a transfer substrate by pressing the surface of the first plate having the second pattern thereon on the surface of the transfer substrate. | 2008-10-16 |
20080251845 | Semiconductor Device and Manufacturing Method Thereof - Manufacture of TFTs corresponding to various circuits makes structures thereof complex, which involves a larger number of manufacturing steps. Such an increase in the number of the manufacturing steps leads to a higher manufacturing cost and a lower manufacturing yield. In the invention, a high concentration of impurities is doped by using as masks a tapered resist that is used for the manufacture of a tapered gate electrode, and the tapered gate electrode, and then the tapered gate electrode is etched in the perpendicular direction using the resist as a mask. A semiconductor layer under the thusly removed tapered portion of the gate electrode is doped with a low concentration of impurities. | 2008-10-16 |
20080251846 | METHOD AND STRUCTURE FOR LOW CAPACITANCE ESD ROBUST DIODES - A diode having a capacitance below 0.1 pF and a breakdown voltage of at least 500V. The diode has an anode of a first conductivity type and a cathode of a second conductivity type disposed below the anode. At least one of the cathode and anode have multiple, vertically abutting diffusion regions. The cathode and anode are disposed between and bounded by adjacent isolation regions. | 2008-10-16 |
20080251847 | MEMORY CELL ARRAY IN A SEMICONDUCTOR MEMORY DEVICE - A memory cell array in a semiconductor device includes a semiconductor substrate having active areas and isolation areas in parallel, a plurality of select lines having generally a U like shape and is configured to cross over the active areas and the isolation areas, and a plurality of word lines formed between the select lines. In view of the select line being formed in U like shape, an occurrence of a punch through phenomenon is prevented by a junction area formed between the select lines. As a result, a margin for reducing a width of the select line is increased. | 2008-10-16 |
20080251848 | Manufacturing method for homogenizing the environment of transistors and associated device - A semiconductor device is provided that includes a plurality of patterns. Each pattern includes at least one field effect transistor. Each field effect transistor includes a source region, a drain region, a channel region, and a gate region formed above the channel region. A portion of the plurality of patterns is formed in a single active area of a semiconductor substrate, where the area delimited by an isolation region. One of the source region and the drain region of each adjacent pattern are formed in said active area. | 2008-10-16 |
20080251849 | Semiconductor Device and Method for Manufacturing Same - A semiconductor device comprising a first semiconductor region and a second semiconductor region,
| 2008-10-16 |
20080251850 | PMD Liner Nitride Films and Fabrication Methods for Improved NMOS Performance - Semiconductor devices ( | 2008-10-16 |
20080251851 | STRAIN ENHANCED SEMICONDUCTOR DEVICES AND METHODS FOR THEIR FABRICATION - A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide contacts are formed to the source and drain regions so as not to relieve the induced strain. A layer of conductive material is selectively deposited in contact with the thin metal silicide contacts, and metallized contacts are formed to the conductive material. | 2008-10-16 |
20080251852 | E-FUSE AND METHOD - An e-fuse circuit, a method of programming the e-fuse circuit, and a design structure of the e-fuse circuit. The method includes in changing the threshold voltage of one selected field effect transistor of two field effect transistors connected to different storage nodes of the circuit so as to predispose the circuit place the storage nodes in predetermined and opposite states. | 2008-10-16 |
20080251853 | STRUCTURE AND METHOD TO OPTIMIZE STRAIN IN CMOSFETs - A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET. A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs. | 2008-10-16 |
20080251854 | SEMICONDUCTOR DEVICE - In one aspect of the present invention, semiconductor device, may include a p-channel semiconductor active region, an n-channel semiconductor active region, an element isolation insulating layer which electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region, and an insulating layer made of a material different from that of the element isolation insulating layer, and being in contact with both ends, in its channel length direction, of the p-channel semiconductor active region to apply a compression stress in the channel length direction to a channel of the p-channel semiconductor active region, wherein the p-channel semiconductor active region is surrounded by the insulating layer, which is in contact with the both ends, in the channel length direction, of the p-channel semiconductor active region, and the p-channel semiconductor active region is surrounded by the element isolation insulating layer, which is in contact with the side surfaces, approximately parallel to the channel length direction, of the p-channel semiconductor active region, and the n-channel semiconductor active region is surrounded by the element isolation insulating layer. | 2008-10-16 |
20080251855 | LOW CONTACT RESISTANCE CMOS CIRCUITS AND METHODS FOR THEIR FABRICATION - A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive barrier layer overlies each of the first transition metal and the second transition metal and a plug metal overlies the conductive barrier layer. | 2008-10-16 |
20080251856 | FORMING SILICIDED GATE AND CONTACTS FROM POLYSILICON GERMANIUM AND STRUCTURE FORMED - Methods of forming silicided contacts self-aligned to a gate from polysilicon germanium and a structure so formed are disclosed. One embodiment of the method includes: forming a polysilicon germanium (poly SiGe) pedestal over a gate dielectric over a substrate; forming a poly SiGe layer over the poly SiGe pedestal, the poly SiGe layer having a thickness greater than the poly SiGe pedestal; doping the poly SiGe layer; simultaneously forming a gate and a contact to each side of the gate from the poly SiGe layer, the gate positioned over the poly SiGe pedestal; annealing to drive the dopant from the gate and the contacts into the substrate to form a source/drain region below the contacts; filling a space between the gate and the contacts; and forming silicide in the gate and the contacts. | 2008-10-16 |
20080251857 | Semiconductor Device with Improved Contact Pad and Method for Fabrication Thereof - A semiconductor device and method of its manufacture is disclosed. The device comprises an active semiconductor region ( | 2008-10-16 |
20080251858 | FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved. | 2008-10-16 |
20080251859 | Semiconductor Module - A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, which forms a second external contact element. The first and the second carriers are arranged in such a way that the first and the second extension point in different directions. | 2008-10-16 |
20080251860 | Semiconductor Memory Device - The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line. | 2008-10-16 |
20080251861 | SEMICONDUCTOR APPARATUS AND PRODUCTION METHOD OF THE SAME - In order to provide a semiconductor apparatus and a production method of the semiconductor apparatus that achieves a small interface trap density by implantation of fluorine and that achieves both small property fluctuation and a small leak current, a semiconductor apparatus includes: a semiconductor substrate; a well layer formed on the semiconductor substrate; a channel dope layer formed on the well layer; a source/drain diffused layer provided at an upper peripheral of the channel dope layer; gate electrodes formed on the channel dope layer via a gate insulation film; a polycrystalline silicon plug which is formed between the gate electrodes and which touches the source/drain diffused layer while piercing the gate insulation film; and fluorine which is selectively implanted only in a source area of the source/drain diffused layer. | 2008-10-16 |
20080251862 | ACCUMULATION FIELD EFFECT MICROELECTRONIC DEVICE AND PROCESS FOR THE FORMATION THEREOF - A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by a channel portion dopant type and concentration. An insulative dielectric is in contact with the channel portion and overlaid in turn by a gate. A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion. This channel portion has a dimension normal to the gate which is fully depleted in the off-state. The dopant type is the same across the source, drain and the channel portion of the device. The device on-state current is determined by the doping and, unlike a MOSFET, is not directly proportional to device capacitance. | 2008-10-16 |
20080251863 | HIGH-VOLTAGE RADIO-FREQUENCY POWER DEVICE - A high-voltage RF power device includes a plurality of serially connected transistors. Each transistor includes a gate finger disposed on a substrate, a gate dielectric layer, a drain structure disposed on one side of the gate finger, and an N+ source region on the other side of the gate finger. The drain structure includes an N+ doping region encompassed by a shallow trench isolation (STI) structure, and an N well directly underneath the STI structure and the N+ doping region. | 2008-10-16 |
20080251864 | STACKED POLY STRUCTURE TO REDUCE THE POLY PARTICLE COUNT IN ADVANCED CMOS TECHNOLOGY - A method for implementing a stacked gate, comprising forming a gate dielectric on a semiconductor body, forming a first layer of gate electrode material on the gate dielectric, forming a second layer of gate electrode material on the first layer of gate electrode material, wherein the grain size distribution of the first layer of gate electrode material is different than the grain size distribution of the second layer of gate electrode material, implanting the first and second gate electrode materials, patterning the first and the second gate electrodes and the gate dielectric, and forming source and drain regions. | 2008-10-16 |
20080251865 | NANOELECTROMECHANICAL SYSTEMS AND METHODS FOR MAKING THE SAME - Nanoelectromechanical systems are disclosed that utilize vertically grown or placed nanometer-scale beams. The beams may be configured and arranged for use in a variety of applications, such as batteries, generators, transistors, switching assemblies, and sensors. In some generator applications, nanometer-scale beams may be fixed to a base and grown to a desired height. The beams may produce an electric potential as the beams vibrate, and may provide the electric potential to an electrical contact located at a suitable height above the base. In other embodiments, vertical beams may be grown or placed on side-by-side traces, and an electrical connection may be formed between the side-by-side traces when beams on separate traces vibrate and contact one another. | 2008-10-16 |
20080251866 | LOW-STRESS HERMETIC DIE ATTACH - A low-stress hermetic die attach apparatus is disclosed. An example apparatus includes a hermetic package, a device disposed within the hermetic package, and one or more elongated structures greater than 2 thousandths of an inch (mils) in length connected to the package at one end and to the device at the other end. In some embodiments, the apparatus includes elongated structures at least 30 mils long or at least 100 mils long and the device includes a microelectromechanical system (MEMS) die that includes accelerometer or gyro components. In some embodiments, the elongated structures include a column or a pin made of an alloy material such as Kovar. In one embodiment, the Kovar pin is gold plated, attached to the package with a high temperature solder, and attached to the die using gold stud bumps. | 2008-10-16 |
20080251867 | Nanowire Magnetic Random Access Memory - An integrated array of non volatile magnetic memory devices, each having a first magnetic layer ( | 2008-10-16 |
20080251868 | Standard component for calibration and electron-beam system using the same - The invention provides a standard component for calibration that enables a calibration position to be easily specified in order to calibrate accurately a scale factor in the electron-beam system, and provides an electron-beam system using it. High-accuracy metrology calibration capable of specifying a calibration position can be realized by forming a mark pattern or labeled material for identifying the calibration position in proximity of a superlattice pattern of the standard component for system calibration. The standard component for calibration is one that calibrates a scale factor of an electron-beam system based on a signal of secondary charged particles detected by irradiation of a primary electron beam emitted from the electron-beam system on a substrate having a cross section of a superlattice of a multi-layer structure in which different materials are deposited alternately. The substrate have linear patterns that are on the substrate surface parallel to the multi-layer and are arranged at a fixed interval in a direction crossing the cross section of the superlattice pattern, and is so configured that the cross sections of the linear patterns may exist on substantially the same plane of the superlattice cross section, so that the linear patterns enable a position of the superlattice pattern to be identified. | 2008-10-16 |
20080251869 | PHOTOSENSITIVE CHIP PACKAGE - A photosensitive chip package includes a substrate on which a photosensitive chip having a photo-active zone and a photo-inactive zone surrounding the photo-active zone is bonded. A light-transmissive film covers the photo-active zone of the photosensitive chip. Bonding wires are electrically connected with the photosensitive chip and the substrate. An encapsulant covers the photo-inactive zone of the photosensitive chip, a border periphery of the light-transmissive film and the bonding wires. The encapsulant has an opening corresponding to the photo-active zone. By means of the light-transmissive film, the photo-active zone of the photosensitive chip is protected, thereby lowering the chance of accidental damage to the photosensitive chip by the tool used during formation of the encapsulant and/or during a cleaning work. | 2008-10-16 |
20080251870 | DETECTOR FOR DETECTING ELECTROMAGNETIC WAVES - A detector for detecting electromagnetic waves, the detector having an antenna for receiving the electromagnetic waves, a semiconductor element, wherein a termination section of the semiconductor element establishes a termination resistor of the antenna, wherein the termination section is provided for heating a temperature-sensitive part of the semiconductor element, wherein the semiconductor element comprises a temperature-dependent characteristic that is dependent from the temperature of the temperature sensitive part and a measurement unit for measuring the temperature-dependent characteristic of the semiconductor element. | 2008-10-16 |
20080251871 | Semiconductor fabrication method and system - Embodiments of the present invention are generally directed to a method for manufacturing a semiconductor device. In one embodiment, the method includes providing a substrate that includes a via or interconnect. In this embodiment, the method also includes forming a sealed array, in which forming such an array includes attaching a carrier to a first surface of the substrate to form a sealed cavity between the carrier and the substrate. Further, the method of this embodiment also includes forming a redistribution layer on the sealed array over a second surface of the substrate. Devices and systems having a carrier attached to a substrate are also disclosed. | 2008-10-16 |
20080251872 | IMAGE SENSOR PACKAGE, METHOD OF MANUFACTURING THE SAME, AND IMAGE SENSOR MODULE INCLUDING THE IMAGE SENSOR PACKAGE - An image sensor package, a method of manufacturing the same, and an image sensor module including the image sensor package are provided. In the image sensor package, an image sensor chip is installed onto a depression of a transmissive substrate. An adhesive bonds the image sensor chip to the transmissive substrate and seals an Active Pixel Sensor (APS) on the image sensor chip, protecting it from fine particle contamination. An IR cutting film is disposed on the transmissive substrate to minimize the height of the image sensor package. The image sensor package is electrically connected to external connection pads in the depression. Consequently, the image sensor package has a minimum height, is not susceptible to particle contamination, and does not require expensive alignment processes during manufacturing. | 2008-10-16 |
20080251873 | SOLID-STATE IMAGING DEVICE, MANUFACTORING METHOD THEREOF AND CAMERA - A solid-state imaging device which includes a color filter having excellent color reproduction, a manufacturing method thereof and a camera are provided. | 2008-10-16 |
20080251874 | Solid-state image capturing Device, method for the same, and electronic information device - A solid-state image capturing device according to the present invention is provided, in which a plurality of conductive films is formed via respective insulation films, and an optical waveguide is formed above a light receiving section, a plurality of light receiving sections is provided in a surface portion of a semiconductor substrate, and the plurality of conductive films is formed on a region other than a region right above the light receiving section, wherein a plural-layered optical waveguide tube is formed as the optical waveguide, with the same material as at least one of the plural-layered conductive films. | 2008-10-16 |
20080251875 | SEMICONDUCTOR PACKAGE - An exemplary semiconductor package includes a substrate, at least one passive component, an insulative layer and a chip. The substrate defines a cavity therein. The at least one passive component is disposed within the cavity, and is electrically connected to the substrate. The insulative layer is received in the cavity, and encases the at least one passive component. The chip is disposed on the insulative layer, and is electrically connected to the substrate. The semiconductor package packaging the at least one passive component within the cavity and under the chip can improve a space usage thereof, thus a packaging scale of the semiconductor package could be reduced. | 2008-10-16 |
20080251876 | PHOTORECEIVER CELL WITH COLOR SEPARATION - A photoreceiver cell with separation of color components of light incident to its surface, formed in a silicon substrate of the conductivity of the first type with an ohmic contact and comprising: the first, second and third regions, which have mutual positioning and configuration, which provide formation of the first and the second channels for diffusion of the secondary charge carriers generated in the substrate regions located under the first and the second potential barriers to the first and the third p-n junctions respectively; in this case, the length of the channels does not exceed the diffusion length of the secondary charge carriers. Some embodiments provide increased spatial resolution of the projected image and its dynamic range. Some embodiments provide small photo-cell area. Some embodiments are used in multielement photoreceivers for video cameras and digital cameras. | 2008-10-16 |
20080251877 | METHODS FOR FABRICATING COMPLEX MICRO AND NANOSCALE STRUCTURES AND ELECTRONIC DEVICES AND COMPONENTS MADE BY THE SAME - This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices. Processing methods of the present invention are capable of making micro- and nano-scale electronic structures, such as T-gates, gamma gates, and shifted T-gates, having a selected non-uniform cross-sectional geometry. The present invention provides lithographic processing strategies for sub-pixel patterning in a single layer of photoresist useful for making and integrating device components comprising dielectric, conducting, metal or semiconductor structures having non-uniform cross-sectional geometries. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication platforms, and can be effectively integrated into existing photolithographic, etching and thin film deposition patterning strategies, systems and infrastructure. | 2008-10-16 |
20080251878 | STRUCTURE INCORPORATING SEMICONDUCTOR DEVICE STRUCTURES FOR USE IN SRAM DEVICES - Device structures embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes static random access memory (SRAM) devices. The design structure includes a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The design structure further comprises an electrically connective bridge extending across the first semiconductor region. A portion of the electrically connective bridge electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure. | 2008-10-16 |
20080251879 | Method for Manufacturing Simox Substrate and Simox Substrate Obtained by this Method - Heavy metal contamination in a device process can be efficiently trapped in a substrate. | 2008-10-16 |
20080251880 | MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER - The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed. | 2008-10-16 |
20080251881 | SEMICONDUCTOR DEVICE WITH DOUBLE BARRIER FILM - A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole. | 2008-10-16 |
20080251882 | Semiconductor device and method of fabricating the same - A semiconductor device includes a first insulating isolation film provided on a main surface of a semiconductor substrate, an active region surrounded by the first insulating isolation film, and a second insulating isolation film provided on the main surface of the semiconductor substrate, having a thickness smaller than that of the first insulating isolation film and separating the active region into a first active region and a second active region. | 2008-10-16 |
20080251883 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so that upper parts of the trenches have partial openings, respectively and buried in the second element isolation trenches respectively, and coating type oxide films formed so as to fill the openings of the first element isolation trenches, respectively. | 2008-10-16 |
20080251884 | Method and System for Controlling Multiple Electrical Fuses with One Program Device - A fuse circuit comprising one or more one-time programmable electrical fuses; one or more unidirectional conductive devices each coupled to one of the fuses; a programming device coupled to the unidirectional conductive devices; and a selection module coupled to the electrical fuses for selecting a predetermined electrical fuse, wherein upon a selection by the selection module, a programming current is introduced through at least one selected electrical fuse, wherein the selection module is an N-to-one multiplexer selecting one of the N number of electrical fuses to be programmed, and the unidirectional conductive devices not coupled to the selected electrical fuse to prevent the programming current from interfering with the remaining electrical fuses. | 2008-10-16 |
20080251885 | Fuse structure, semiconductor device, and method of forming the semiconductor device - There are provided a fuse structure and a semiconductor device having the fuse structure. The fuse structure includes an insulating layer having a hole, a resistance-variable material layer disposed on inner wall of the hole, a reference power layer that covers the resistance-variable material layer, and a plurality of leads in the insulating layer. Each lead has a first portion which reaches the inner wall of the hole and contacts the resistance-variable material layer. Each lead is configured to allow an electrical connection to outside. | 2008-10-16 |
20080251886 | Fuse structure, and semiconductor device - A fuse structure includes a reference power layer disposed between first and second resistance-variable material layers. The first and second resistance-variable material layer may at least partially overlap each other in plan view. First and second insulating layers are disposed over and under the first and second resistance-variable material layers. A plurality of first leads is disposed over the first insulating layer. A plurality of second leads is disposed under the second insulating layer. A plurality of first via contacts penetrates the first insulating layer and connects between the first leads and the first resistance-variable material layer. A plurality of second via contacts penetrates the second insulating layer and connects between the second leads and the second resistance-variable material layer. Each of the first leads extends in a second horizontal direction that crosses a first horizontal direction in which the first and second resistance-variable material layer extend. | 2008-10-16 |
20080251887 | SERIAL SYSTEM FOR BLOWING ANTIFUSES - A serial system and method for blowing antifuses are disclosed. One embodiment of antifuse system includes a plurality of latch devices connected in series from input to output. The system also includes a plurality of antifuses. The antifuses are configured to receive an output signal from a corresponding one of the latch devices. The plurality of latch devices includes a plurality of D flip-flops connected in series. Each of the D flip-flops is configured to receive an output signal from an immediately previous D flip-flop in the serial data flow and to provide an output signal to an immediately subsequent D flip-flop in the flow. In addition, the serial system provides self-detective antifuses, thus creating reliable electrical paths while saving antifuse blowing current resources and time. | 2008-10-16 |
20080251888 | Method and Apparatus for Self-Contained Automatic Decoupling Capacitor Switch-Out in Integrated Circuits - An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained. Because of the self-contained nature of the decoupling capacitor circuit, an integrated circuit may contain an array of decoupling capacitor circuits without expenditure of substantial chip real estate for respective decoupling capacitor control lines. | 2008-10-16 |
20080251889 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The first metal layer comprises a body-centered cubic lattice metal, and overlies the substrate. The dielectric layer overlies the first metal layer. The second metal layer overlies the dielectric layer. | 2008-10-16 |
20080251890 | Method of Forming Buffer Layer for Nitride Compound Semiconductor Light Emitting Device and Nitride Compound Semiconductor Light Emitting Device Having the Buffer Layer - A method of forming a buffer layer for a nitride compound semiconductor light emitting device includes placing a sapphire (Al | 2008-10-16 |
20080251891 | Semiconductor having passivated sidewalls - The layers of a semiconductor device have exposed edges. The layers that are susceptible to oxidation are protected from oxidation by coating them with a nitride passivation layer. The nitride passivation layer can be applied using plasma enhanced chemical vapor deposition (PECVD). A method of making a passivated sidewall semiconductor includes the steps of applying a nitride or other protective material over a wafer using PECVD or other appropriate deposition method. | 2008-10-16 |
20080251892 | INSULATING FILM FOR SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention relates to a polymeric compound comprising, as structural units, groups each represented by the following general formula (1); and an insulating film for a semiconductor integrated circuit which comprises the polymeric compound: —R | 2008-10-16 |
20080251893 | MOUNTING CLIPS FOR USE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING AND METHODS OF USING THE SAME - According to various aspects, exemplary embodiments are provided of clips that may be compatible with surface mount technology. The clips may be surface mountable to a substrate for allowing repeated releasable attachment and detachment of a shielding structure thereto. In one exemplary embodiment, a clip generally includes a base member having generally opposed first and second side edge portions. Two or more arms extend generally upwardly in a first direction from the base member. The clip also includes a generally flat pick-up surface configured to enable the clip to be picked up by a head associated with pick-and-place equipment. | 2008-10-16 |
20080251894 | Mounted Body and Method for Manufacturing the Same - A mounted body ( | 2008-10-16 |
20080251895 | APPARATUS FOR SHIELDING INTEGRATED CIRCUIT DEVICES - A high reliability radiation shielding integrated circuit apparatus comprising a plurality of package layers; a radiation shielding lid or base coupled to the plurality of package layers; wherein the circuit die are shielded from receiving an amount of radiation greater than the total dose of tolerance of the circuit die. In one embodiment, an integrated circuit apparatus for use in high reliability applications is disclosed. The integrated circuit apparatus is designed to be highly reliable and protect integrated circuit die from failing or becoming unreliable due to radiation, mechanical forces, thermal exposure, or chemical contaminates. | 2008-10-16 |
20080251896 | Method of manufacturing a coaxial trace in a surrounding material, coaxial trace formed thereby, and semiconducting material containing same - A method of manufacturing a coaxial trace ( | 2008-10-16 |
20080251897 | SEMICONDUCTOR DEVICE - The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. | 2008-10-16 |
20080251898 | Semiconductor device - A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized. | 2008-10-16 |
20080251899 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which a plurality of chips are packaged without increasing the thickness of the package. A plurality of semiconductor elements (a first and a second semiconductor elements) that are packaged in the semiconductor device are overlaid with each other. Specifically, the first semiconductor element is fixed on the top surface of the first island while the second semiconductor element is fixed on the bottom surface of the second island. Furthermore, each of the islands (a first and a second islands) on which the semiconductor elements are respectively mounted in the present invention provides a structure has an irregular shape, and the islands are overlaid with each other along the sides of the semiconductor element to be mounted. | 2008-10-16 |
20080251900 | Conductor Frame For an Electronic Component and Method For the Production Thereof - Disclosed is a leadframe for at least one electronic component, comprising at least two electrical lead elements, each of which comprises at least one electrical lead tab and at least one retention tab. Provided between the at least one retention tab and the lead element is a score defining a parallel offset between the retention tab and the adjacent region of lead element. An additional parallel offset is defined between the lead element and the electrical lead tab, such that the retention tab and the electrical lead tab are located in a common plane. The score enables the retention tab to be removed easily without the need for a disadvantageous punched gap between the lead element and the retention tab. | 2008-10-16 |
20080251901 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM - A stacked integrated circuit package system is provided providing a lead frame having a die paddle, attaching a first integrated circuit on the die paddle of the lead frame, connecting first electrical interconnects between the first integrated circuit and the lead frame, encapsulating the first integrated circuit and the first electrical interconnects with the lead frame directly on a bottom mold and clamped by a top mold, attaching a second integrated circuit on the die paddle of the first integrated circuit, connecting second electrical interconnects between the second integrated circuit and the lead frame, and encapsulating the second integrated circuit and the second electrical interconnects. | 2008-10-16 |
20080251902 | Plastic package and method of fabricating the same - A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals. | 2008-10-16 |
20080251903 | SEMICONDUCTOR MODULE - A module having a semiconductor chip with a first contact element on a first main surface and a second contact element on a second main surface is disclosed. The semiconductor chip is arranged on a carrier. An insulating layer and a wiring layer cover the second main surface and the carrier. | 2008-10-16 |
20080251904 | CURING LAYERS OF A SEMICONDUCTOR PRODUCT USING ELECTROMAGNETIC FIELDS - A semiconductor product including a substrate, a semiconductor chip fitted to the substrate, and a layer, which contains coated particles, located adjacent to the semiconductor chip, wherein the coated particles have a ferromagnetic, ferrimagnetic or paramagnetic core and a coating. | 2008-10-16 |
20080251905 | Package-on-package secure module having anti-tamper mesh in the substrate of the upper package - A package-on-package (POP) secure module includes a first ball grid array (BGA) package, and a second BGA package. The first BGA includes an array of bond balls that is disposed on a side of a substrate member, and an array of lands that is disposed on the opposite side of the substrate member. Bond balls of the second BGA are fixed to the lands of the first BGA such that the second BGA is piggy-back mounted to the first BGA. Embedded in the substrate member of the second BGA is an anti-tamper security mesh. An integrated circuit in the first BGA is coupled to, drives and monitors the security mesh. When the module is disposed on a printed circuit board within a point of sale (POS) terminal, the integrated circuit is coupled to, also drives and monitors a second security mesh embedded in the printed circuit board underneath the module. | 2008-10-16 |
20080251906 | Package-on-package secure module having BGA mesh cap - A package-on-package (POP) secure module includes a BGA mesh cap, a first BGA package, and a second BGA package. The first BGA package includes a first integrated circuit (for example, a microcontroller that includes tamper detect logic). The second BGA package includes a second integrated circuit (for example, a memory). The second BGA package is piggy-back mounted to the first BGA package and the BGA mesh cap is piggy-back mounted to the second BGA package. A printed circuit board substrate member of the BGA mesh cap includes an embedded anti-tamper mesh. This mesh is connected in a protected manner within the module to the first integrated circuit. When the module is in use, a mesh embedded in an underlying printed circuit board is coupled to the BGA cap mesh so that both anti-tamper meshes are controlled by the tamper detect logic. | 2008-10-16 |
20080251907 | Electronic Device With Stress Relief Element - The present invention relates to an electronic device whose component body contains at least one stress relief element ( | 2008-10-16 |
20080251908 | Semiconductor device package having multi-chips with side-by-side configuration and method of the same - The present invention provides a semiconductor device package with the die receiving through hole and connecting through hole structure comprising a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad. A die is disposed within the die receiving through hole. An adhesion material is formed under the die and filled in the gap between the die and sidewall of the die receiving though hole. Further, a wire bonding is formed to couple to the bonding pads and the first contact pad. A dielectric layer is formed on the wire bonding, the die and the substrate. A second contact pad is formed at the lower surface of the substrate and under the connecting through hole structure. | 2008-10-16 |
20080251909 | Power Semiconductor Module for Inverter Circuit System - A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insulation member. On the conducting member on the first dissipation plate is provided with a fixing portion that fixes a collector surface of the semiconductor chip and a gate conductor connected to a gate terminal of the semiconductor module. The gate electrode terminal and the gate conductor are wire bonded. The conducting member on the second heat dissipation member is connected to an emitter surface of the semiconductor chip connected to the first heat dissipation member. The productivity and reliability are improved by most of formation operations for the upper and lower arms series circuit on one of the heat dissipation member. | 2008-10-16 |
20080251910 | Fabricating method of semiconductor package and heat-dissipating structure applicable thereto - A method for fabricating semiconductor packages is disclosed, including mounting and electrically connecting a semiconductor chip onto a chip carrier; mounting a heat-dissipating structure on the semiconductor chip; placing the heat-dissipating structure into a mold cavity for filling therein a packaging material to form an encapsulant, wherein the heat-dissipating structure has a heat spreader having a size larger than that of the predetermined size of the semiconductor package, a covering layer formed on the, and a plurality of protrusions formed on edges of the covering layer that are free from being corresponding in position to the semiconductor chip, such that the protrusions can abut against a top surface of the mold cavity to prevent the heat spreader from being warped; and finally performing a singulation process according to the predetermined size and removing the encapsulant formed on the covering layer to form the desired semiconductor package. Also, this invention discloses a heat-dissipating structure applicable to the method described above. | 2008-10-16 |
20080251911 | System and method having evaporative cooling for memory - A system, in one embodiment, may include an in-line memory module with a plurality of memory circuits disposed on a circuit board, wherein the circuit board may have an edge connector with a plurality of contact pads. The system also may include a heat spreader disposed along the plurality of memory circuits. Finally, the system may include a heat pipe, a vapor chamber, or a combination thereof, extending along the heat spreader. In another embodiment, a system may include a heat spreader configured to mount to an in-line memory module, and an evaporative cooling system at least substantially contained within dimensions of the heat spreader. | 2008-10-16 |
20080251912 | Multi-Chip Module - A multi-chip module includes at least one integrated circuit chip that is electrically connected to first external terminals of the multi-chip module and at least one power semiconductor chip that is electrically connected to second external terminals of the multi-chip module. All first external terminals of the multi-chip module are arranged in a contiguous region of an terminal area of the multi-chip module. | 2008-10-16 |
20080251913 | SEMICONDUCTOR DEVICE INCLUDING WIRING SUBSTRATE HAVING ELEMENT MOUNTING SURFACE COATED BY RESIN LAYER - In one embodiment of the present invention, there is provided a semiconductor device including a first semiconductor element mounted, through flip-chip bonding, on the element mounting surface of a first wiring substrate, and a resin layer that coats substantially the entire element mounting surface of the first wiring substrate. The first semiconductor element has two opposite surfaces. One surface faces the element mounting surface of the first wiring substrate, and the other surface is not coated by the resin layer. | 2008-10-16 |
20080251914 | SEMICONDUCTOR DEVICE - In a structure for connecting a semiconductor element having a fine pitch electrode at 50 pm pitch or less and a pad or wirings on a substrate, for preventing inter-bump short-circuit or fracture of a connected portion due to high strain generated upon heating or application of load during connection, the substrate and the semiconductor element are connected by way of a bump having a longitudinal elastic modulus (Young's modulus) of 65 GPa or more and 600 GPa or less and a buffer layer including one of tin, aluminum, indium, or lead as a main ingredient and, further, protrusions are formed to at least one of opposing surfaces of the bump and the pad or the wirings on the substrate to each other, and the surfaces are connected by ultrasonic waves. | 2008-10-16 |
20080251915 | Structure of semiconductor chip and package structure having semiconductor chip embedded therein - A semiconductor chip is disclosed, which comprises a chip having an active surface; plural electrode pads disposed on the active surface of the chip; a first passivation layer disposed on the chip, which has openings corresponding to the electrode pads to expose the electrode pads, wherein the first passivation layer is made of a material having high alkali resistance and low coefficient of elasticity; and plural metal bumps disposed in the openings of the first passivation layer. Therefore, as forming the metal bumps by a chemical deposition technique, the damage to the passivation layer can be prevented. Besides, as the semiconductor chip is embedded in a package structure, the problem of delamination occurred due to the mismatch in the coefficients of thermal expansion of the semiconductor chip and the dielectric layers can be avoided. Accordingly, the yield of the package structure having the semiconductor chip embedded therein can be improved. | 2008-10-16 |
20080251916 | UBM structure for strengthening solder bumps - A novel UBM structure for improving the strength and performance of individual UBM layers in a UBM structure is disclosed. In one aspect, a UBM structure for disposal onto an electrically conductive element comprised of aluminum is disclosed. In one embodiment, the UBM structure comprises a tantalum layer disposed over the aluminum electrically conductive element, and a copper layer disposed over the tantalum layer, where the UBM structure is configured to receive a solder ball thereon. | 2008-10-16 |
20080251917 | SOLDER PAD AND METHOD OF MAKING THE SAME - A solder pad structure includes a first metal layer disposed on an insulation layer, wherein the first metal layer is electrically connected with an underlying interconnection circuit layer through a conductive through hole disposed in the insulation layer. A solder resist layer having an opening exposing a central portion of the first metal layer is disposed on the insulating layer. A pillar-shaped second metal layer is disposed within the opening directly on the first metal layer. A solder ball filled into the opening is in contact with the pillar-shaped second metal layer. | 2008-10-16 |
20080251918 | Wire Bonds Having Pressure-Absorbing Balls - A semiconductor device with a chip having at least one metallic bond pad ( | 2008-10-16 |
20080251919 | Ultra-low resistance interconnect - A method for fabricating a semiconductor interconnect device. A preferred embodiment comprises forming a low-k or very low-k dielectric layer on a wafer substrate and forming a recess in the dielectric layer that exposes a region on the substrate to which electrical contact is desired. A barrier layer is formed by first forming an organic layer on the walls of the substrate, then forming a catalyst metal layer on the organic layer, and finally forming a barrier metal layer over the catalyst layer. The remainder of the recess formed in the dielectric layer is then filled with a conductive material such as copper that will function as the main electrical connector to the contact region on the substrate. | 2008-10-16 |
20080251920 | Dielectric film forming method - In a film forming sequence for a HDP-CVD oxide film, Ar gas is introduced into a reactive chamber and then source power (or RF power) is applied to excite plasma. After that, a carrier gas (He) is introduced into the reactive chamber. After a semiconductor substrate is heated by plasma of the Ar and He gasses, introduction of the Ar gas is stopped. Subsequently, SiH | 2008-10-16 |
20080251921 | Structure for a Semiconductor Device and a Method of Manufacturing the Same - There is described a method of manufacturing a damascene interconnect ( | 2008-10-16 |
20080251922 | Transitional Interface between metal and dielectric in interconnect structures - An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line. | 2008-10-16 |
20080251923 | Seal ring structures with reduced moisture-induced reliability degradation - A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening. | 2008-10-16 |
20080251924 | Post Passivation Interconnection Schemes On Top Of The IC Chips - A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate. | 2008-10-16 |
20080251925 | TOP LAYERS OF METAL FOR INTEGRATED CIRCUITS - The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads. | 2008-10-16 |
20080251926 | Method of Fabricating Organic Silicon Film, Semiconductor Device Including the Same, and Method of Fabricating the Semiconductor Device - An organic silicon film is formed by carrying out chemical vapor deposition with organic silicon compound being used as a raw material gas. The organic silicon compound contains at least silicon, hydrogen and carbon as a constituent thereof, and contains two or more groups having unsaturated bond, per a molecule thereof. The organic silicon compound is used in mixture with a silicon hydride gas. | 2008-10-16 |
20080251927 | Electromigration-Resistant Flip-Chip Solder Joints - A semiconductor device contact structure practically eliminating the copper diffusion into the solder as well as the current crowding at the contact with the subsequent electromigration in the solder. A column-like electroplated copper stud ( | 2008-10-16 |
20080251928 | Carbonization of metal caps - An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring. | 2008-10-16 |
20080251929 | Semiconductor Device and Semiconductor Device Manufacturing Method - An inventive semiconductor device includes at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer. | 2008-10-16 |
20080251930 | SEMICONDUCTOR DEVICE AND DUMMY PATTERN ARRANGEMENT METHOD - A semiconductor device includes a plurality of wiring patterns arranged in a first wiring layer of the semiconductor device and extending in a first direction, and a plurality of dummy patterns arranged in the first wiring layer and extending in a second direction different from the first direction, wherein each of the plurality of dummy patterns is arranged spaced apart from each of the plurality of wiring patterns and includes one or more dummy lands formed by separating a part of the dummy pattern opposed to the wiring pattern, from the rest part of the dummy pattern. | 2008-10-16 |
20080251931 | MULTI CAP LAYER AND MANUFACTURING METHOD THEREOF - A method for manufacturing a multi cap layer includes providing a substrate, forming a multi cap layer comprising a first cap layer and a second cap layer formed thereon on the substrate, forming a patterned metal hard mask layer on the multi cap layer, and performing an etching process to etch the multi cap layer through the patterned hard mask layer and to form an opening in the second cap layer. | 2008-10-16 |
20080251932 | Method of forming through-silicon vias with stress buffer collars and resulting devices - A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed. | 2008-10-16 |
20080251933 | METAL INTERCONNECT STRUCTURE - A metal interconnect structure includes a plurality of first plugs adjacent to each other, a first metal line extending in a first direction and contacting each first plug to form a first section with a tapered second section in between, and a second plug adjacent to the second section, both in a second direction normal to the first direction. | 2008-10-16 |
20080251934 | Semiconductor Device Structures and Methods of Fabricating Semiconductor Device Structures for Use in SRAM Devices - Semiconductor device structures and methods of fabricating such semiconductor device structures for use in static random access memory (SRAM) devices. The semiconductor device structure comprises a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The device structure further comprises an electrically connective bridge extending across the first semiconductor region. The electrically connective bridge has a portion that electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure. | 2008-10-16 |
20080251935 | Low shrinkage polyester thermosetting resins - The invention is based on the discovery that a certain polyester compounds are useful as b-stageable adhesives for the microelectonic packaging industry. The polyester compounds described herein contain ring-opening or ring-forming polymerizable moieties and therefore exhibit little to no shrinkage upon cure. In addition, there are provided well-defined b-stageable adhesives useful in stacked die assemblies. In particular, there are provided assemblies wherein the b-stageable adhesive encapsulates a portion of the wiring members contained within the bondline gap between the stacked die. | 2008-10-16 |
20080251936 | SEMICONDUCTOR DEVICE - The generation of a wire bonding defect is reduced in the semiconductor device in which semiconductor chips are laminated. A wiring substrate, the first memory chip by which face-up mounting is done via the first filmy adhesive on the wiring substrate, the second memory chip by which face-up mounting is done via the second filmy adhesive on the first memory chip, and the microcomputer chip by which face-up mounting is done via the third filmy adhesive on the second memory chip are included. Since the third filmy adhesive adhered to the microcomputer chip of the highest stage is the thinnest, at the time of wire bonding of the microcomputer chip, the influence to the ultrasonic wave and load of wire bonding by softening of a filmy adhesive which takes place with the heat can be reduced, and lowering of wire bonding property can be suppressed. | 2008-10-16 |
20080251937 | Stackable semiconductor device and manufacturing method thereof - A stackable semiconductor device and a manufacturing method thereof are disclosed. The method includes providing a wafer comprised of a plurality of chips, wherein a plurality of solder pads are formed on the active surface of each chip, and a plurality of grooves are formed between the solder pads of any two adjacent ones of the chips; forming a dielectric layer on regions between the solder pads of any two adjacent ones of the chips ; forming a metal layer on the dielectric layer electrically connected to the solder pads and forming a connective layer on the metal layer, wherein the width of the connective layer is smaller than that of the metal layer; cutting along the grooves to break off the electrical connection between adjacent chips; thinning the non-active surface of the wafer to the extent that the metal layer is exposed from the wafer; and separating the chips to form a plurality of stackable semiconductor devices. Accordingly, a multi-chip stack structure can be obtained by stacking and electrically connecting a plurality of semiconductor devices through the electrical connection between the connective layer of a semiconductor device and the metal layer of another semiconductor device, thereby effectively integrating more chips without having to increase the stacking area, and further the problems of poor electrical connection, complicated manufacturing processes and high costs known in the prior art can be avoided. | 2008-10-16 |
20080251938 | SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MANUFACTURE - A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection. | 2008-10-16 |
20080251939 | CHIP STACK PACKAGE AND METHOD OF FABRICATING THE SAME - A chip stack package is provided, wherein semiconductor chips having different die sizes are stacked by arranging pads in a scribe region through a redistribution process, so that the thickness of the package can be reduced. A method of fabricating the chip stack package is also provided. In the chip stack package, a plurality of circuit patterns are arranged on one surface of a substrate, and a unit semiconductor chip is mounted thereon. The unit semiconductor chip includes a plurality of semiconductor chips sequentially stacked on the substrate. The semiconductor chips of the unit semiconductor chip have different die sizes. One of the semiconductor chips includes a plurality of first pads arranged in a first chip region, and the other semiconductor chips include second pads arranged in a scribe region at an outside of a second chip region defined by the scribe region. | 2008-10-16 |