42nd week of 2015 patent applcation highlights part 56 |
Patent application number | Title | Published |
20150294942 | INDEXING OF ELECTRONIC DEVICES DISTRIBUTED ON DIFFERENT CHIPS - A method for indexing electronic devices includes: forming first chips in a first wafer, forming second chips in a second wafer, forming the electronic devices by coupling each first chip with a corresponding second chip, and forming an index on each electronic device. The index is indicative of a position of the corresponding first chip in the first wafer. The step of forming an index includes forming a first portion of the index on the first chip, and forming a second portion of the index on the second chip. | 2015-10-15 |
20150294943 | METHOD FOR MANUFACTURING A DIGITAL CIRCUIT AND DIGITAL CIRCUIT - A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an output signal of the digital circuit in response to a predetermined input signal has an undefined logic state when the threshold voltages of the field effect transistors are equal and setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input signal has a predetermined defined logic state. | 2015-10-15 |
20150294944 | METHOD FOR MANUFACTURING A DIGITAL CIRCUIT AND DIGITAL CIRCUIT - A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an output signal of the digital circuit in response to a predetermined input has an undefined logic state when the threshold voltages of the field effect transistors are equal and setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input has a predetermined defined logic state. | 2015-10-15 |
20150294945 | APPARATUS AND METHODS FOR SHIELDING DIFFERENTIAL SIGNAL PIN PAIRS - The disclosure is related to pin layouts in a semiconductor package. One embodiment of the disclosure provides a rhombus shaped shared reference pin layout that isolates a set of differential pin pairs. The differential signal pin pairs are configured such that an axis formed by a vertical signal pin pair is orthogonal to and mutually bisecting an axis formed by a lateral signal pin pair. | 2015-10-15 |
20150294946 | INTEGRATED ELECTRONIC DEVICE WITH TRANSCEIVING ANTENNA AND MAGNETIC INTERCONNECTION - An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna. | 2015-10-15 |
20150294947 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film. | 2015-10-15 |
20150294948 | SOLDER BUMP REFLOW BY INDUCTION HEATING - A method of applying inductive heating to join an integrated circuit chip to an electrical substrate using solder bumps including applying a magnetic field to a magnetic liner in thermal contact with a solder bump on the integrated circuit chip, the magnetic field causes Joule heating in the magnetic liner sufficient to melt the solder bump, the solder bump comprising a lower portion embedded in a first dielectric layer and an upper portion at least partially embedded in a second dielectric layer, the lower | 2015-10-15 |
20150294949 | CHIP PACKAGING STRUCTURE AND PACKAGING METHOD - A chip packaging structure and packaging method. The packaging structure comprises: a semiconductor substrate; a metal pad provided inside the semiconductor substrate; an insulating layer provided on the semiconductor substrate, the insulating layer having an opening for exposing the metal pad; a sub-ball metal electrode provided on the metal pad; a solder ball provided on the surface of the sub-ball metal electrode, the solder ball having a first apron structure and the first apron structure covering partial metal pad on the periphery of the bottom of the under-ball metal electrode. The chip packaging structure of the present invention enhances the adhesion between the solder ball and the metal pad, and improves the reliability in chip packaging. | 2015-10-15 |
20150294950 | METHOD FOR TERNARY WAFER BONDING AND STRUCTURE THEREOF - The present invention relates to a method for ternary wafer bonding and the structure thereof. According to the present invention, silver island structures in the second bonding layer are distributed on the first bonding layer deposited on the surface of a single silicon wafer for forming a gold-silver combination structure, which is then bonded with another silicon wafer without any metal layers thereon at a low-temperature thermal process of 250° C. for completing gold-silver-silicon ternary wafer bonding. Thus, the temperature required for gold-silicon bonding is lowered and the process of wafer bonding is simplified as well. In addition, the quality of wafer bonding is also assured. | 2015-10-15 |
20150294951 | METHOD FOR BONDING BARE CHIP DIES - A method is provided for assembly of a micro-electronic component comprising the steps of: providing a conductive die bonding material comprising of a conductive thermosettable resin material or flux based solder and a dynamic release layer adjacent to the conductive thermoplastic material die bonding material layer; and impinging a laser beam on the dynamic release layer adjacent to the die bonding material layer; in such a way that the dynamic release layer is activated to direct conductive die bonding material matter towards the pad structure to be treated to cover a selected part of the pad structure with a transferred conductive die bonding material; and wherein the laser beam is restricted in timing and energy, in such a way that the die bonding material matter remains thermosetting. Accordingly adhesive matter can be transferred while preventing that the adhesive is rendered ineffective by thermal overexposure in the transferring process. | 2015-10-15 |
20150294952 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of the semiconductor chips on a respective one of the die pads; forming a sealing resin to cover the die pads and the semiconductor chips; and attaching a heat dissipation plate to the die pads by pressing the heat dissipation plate against the die pads via a resin sheet which is an adhesive layer after the sealing resin is formed. | 2015-10-15 |
20150294953 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device is provided. First, a mould is provided. The mould has a chamber, patterns in the chamber, and protrusions in the chamber. A carrier substrate having at least one die located thereon is disposed in the chamber, and the protrusions surround the die. A thermosetting material is injected into the chamber and is cured. The cured thermosetting material is separated from the mould, so as to form an interposer substrate. A plurality of through holes corresponding to the protrusions and a plurality of grooves corresponding to the patterns are formed on the interposer substrate. A conductive material is filled into the through holes and the grooves to form a plurality of conductive pillars and a first conductive pattern layer on a first surface of the interposer substrate. The first conductive pattern layer is electrically connected with the conductive pillars. | 2015-10-15 |
20150294954 | MULTIPLE DIE LAYOUT FOR FACILITATING THE COMBINING OF AN INDIVIDUAL DIE INOTO A SINGLE DIE - An apparatus includes a wafer portion and a plurality of die fabricated in the wafer portion in a defined pattern such that the die are separated from each other by a dicing area or a street. The apparatus includes a conductive connection between given adjacent die. The conductive connection is electrically coupled to circuitry disposed on the given adjacent die. | 2015-10-15 |
20150294955 | Stacked Semiconductor Structure and Method - A method for forming a stacked semiconductor structure comprises providing a first chip comprising a plurality of first active circuits and a first aluminum connection pad, depositing a first dielectric layer on a first side of the first chip, forming a first copper bonding pad on the first aluminum connection pad, providing a second chip comprising a plurality of second active circuits, depositing a second dielectric layer on a first side of the second chip, forming a second copper bonding pad in the second dielectric layer, stacking the first chip on the second chip, wherein the first copper bonding pad is in direct contact with the second copper bonding pad and bonding the first chip and the second chip to form a uniform bonded feature. | 2015-10-15 |
20150294956 | SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE - A semiconductor device may include the following elements: a first substrate; a second substrate; a dielectric layer, which may be positioned between the first substrate and the second substrate and may have a hole; a first conductive member, which may be positioned in the dielectric layer; a second conductive member, which may be positioned in the dielectric layer, may be spaced from the first conductive member, and may be positioned closer to the second substrate than the first conductive member; and a third conductive member, which may contact both the first conductive member and the second conductive member through the hole. | 2015-10-15 |
20150294957 | CHIP PACKAGING STRUCTURE - A chip packaging structure includes an encapsulating material, plurality of first leads, plurality of second leads, a first chip, a second chip and an adhesion layer. The encapsulating material has a top package surface and a corresponding bottom package surface. Each first lead has a first inner lead portion and a first outer lead portion. The first chip is located on the first inner lead portion and electrically coupled to the first leads. Each second lead has a second inner lead portion and a second outer lead portion. The second chip is located on the second inner lead portion and electrically coupled to the second leads. The adhesion layer is located between the first leads and second leads so that the first leads and second leads are connected to each other. | 2015-10-15 |
20150294958 | 3D INTEGRATED CIRCUIT PACKAGE WITH THROUGH-MOLD FIRST LEVEL INTERCONNECTS - 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die. | 2015-10-15 |
20150294959 | LED PACKAGE STRUCTURE - An LED package structure includes: an insulating substrate that has a front bonding pad assembly; a dark-colored die-attach adhesive; blue and green LED chips mounted on the front bonding pad assembly via the dark-colored die-attach adhesive; and a dark-colored and light-transmissible encapsulant that is disposed on the insulating substrate and that encapsulates the blue and green LED chips. The encapsulant has a light transmittance that ranges from 7% to 28% for the blue light and has a light transmittance that ranges from 9% to 30% for the green light. | 2015-10-15 |
20150294960 | INTERDIGITATED MULTIPLE PIXEL ARRAYS OF LIGHT-EMITTING DEVICES - The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistance with improved current spreading and improved heat-sinking Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel. | 2015-10-15 |
20150294961 | OPTOELECTRONIC COMPONENT WITH INTEGRATED PROTECTION DIODE AND METHOD OF PRODUCING SAME - An optoelectronic component includes an optoelectronic semiconductor chip having a first surface on which a first electrical contact and a second electrical contact are arranged, wherein the first surface adjoins a molded body, a first pin and a second pin are embedded in the molded body and electrically conductively connect to the first contact and the second contact, and a protection diode is embedded in the molded body and electrically conductively connect to the first contact and the second contact. | 2015-10-15 |
20150294962 | Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP - A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure. | 2015-10-15 |
20150294963 | METHOD FOR FORMING HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV) - Method for forming a semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a first polymer material and a second conductive material embedded in a second polymer material. The first conductive material is bonded to the second conductive material and the first polymer material is bonded to the second polymer material. The semiconductor device also includes at least one through silicon via (TSV) extending from a bottom surface of the first semiconductor wafer to a metallization structure of the first semiconductor wafer. The semiconductor device structure also includes an interconnect structure formed over the bottom surface of the first semiconductor wafer, and the interconnect structure is electrically connected to the metallization structure via the TSV. | 2015-10-15 |
20150294964 | IP PROTECTION - Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners. | 2015-10-15 |
20150294965 | SEMICONDUCTOR ISOLATION STRUCTURE - The invention relates to a semiconductor isolation structure. More particularly, the present invention relates to a semiconductor isolation structure suitable for providing high voltage isolation. Embodiments disclosed include a semiconductor structure ( | 2015-10-15 |
20150294966 | Semiconductor Device with Electrostatic Discharge Protection Structure - A semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further includes a first isolation layer on the first surface of the semiconductor body and a first electrostatic discharge protection structure on the first isolation layer. The first electrostatic discharge protection structure has a first terminal and a second terminal. A second isolation layer is provided on the electrostatic discharge protection structure. A gate contact area on the second isolation layer is electrically coupled to the first terminal of the first electrostatic discharge protection structure. An electric contact structure is arranged in an overlap area between the gate contact area and the semiconductor body. The electric contact structure is electrically coupled to the second terminal of the first electrostatic discharge protection structure and electrically isolated from the gate contact area. | 2015-10-15 |
20150294967 | ESD PROTECTION CIRCUIT WITH ISOLATED SCR FOR NEGATIVE VOLTAGE OPERATION - A semiconductor controlled rectifier (FIG. | 2015-10-15 |
20150294968 | FinFET AND TRANSISTORS WITH RESISTORS AND PROTECTION AGAINST ELECTROSTATIC DISCHARGE (ESD) - A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each source and each drain is coupled to a metal interconnect level by a metal resistive element that is subjacent the lowermost interconnect level. In one embodiment, a metal segment extending over a plurality of the fins includes contacts to each of the fins, thereby providing subjacent metal resistive elements of different lengths. The plurality of fins and subjacent metal segments are arranged such that each of the FinFET devices has the same total resistance provided by the source and drain metal resistive elements, even though the source metal resistive element and drain metal resistive element associated with the fins may have different lengths. The arrangement provides the same turn-on resistance and the same ESD failure current for each FinFET device. | 2015-10-15 |
20150294969 | FINFET-BASED SEMICONDUCTOR DEVICE WITH DUMMY GATES - A semiconductor device is provided. A substrate includes first and second active fins disposed in a row along a first direction. The first and second active fins are spaced apart from each other. A first dummy gate and a second dummy gate are disposed on the substrate and are extended in a second direction intersecting the first direction. The first dummy gate covers an end portion of the first active fin. The second dummy gate covers an end portion of the second active fin facing the end portion of the first active fin. A first dummy spacer is disposed on a sidewall of the first dummy gate. A second dummy spacer is disposed on a sidewall of the second dummy gate. The sidewall of the second dummy gate faces the sidewall of the first dummy gate. The first dummy spacer is in contact with the second dummy spacer. | 2015-10-15 |
20150294970 | CAPACITOR, RESISTOR AND RESISTOR-CAPACITOR COMPONENTS - Capacitor, resistor and resistor-capacitor components are described herein. In one embodiment, a die comprises first and second metal interconnect layers in a back end of line (BEOL) of the die, and an insulator between the first and second metal interconnect layers. The die also comprises a metal-insulator-metal (MIM) capacitor embedded in the insulator, the MIM capacitor comprising a first metal plate, a second metal plate, and a dielectric layer between the first and second metal plates. The die further comprises a metal resistor embedded in the insulator, wherein the metal resistor and the first metal plate of the MIM capacitor are formed from a same metal layer. In one example, the dielectric layer may have a higher dielectric constant than the insulator. In another example, the second metal plate of the MIM capacitor may overlap the metal resistor. | 2015-10-15 |
20150294971 | CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A capacitor includes a substrate, a multilayer over the substrate, a plurality of container-shaped storage node structures on the semiconductor substrate and surrounded by the multilayer, the storage node structure has a sidewall extending upwardly from the base to the top, where the sidewall includes an upper segment and a lower segment thinner than the upper segment, a capacitor dielectric material along a surface of each storage node structure, and a capacitor electrode material over the capacitor dielectric material. | 2015-10-15 |
20150294972 | SEMICONDUCTOR DEVICE - The instant disclosure relates to a semiconductor device includes a semiconductor substrate, a plurality of buried bit lines, a plurality of insulating structures, and a plurality of self-aligned spacers. The semiconductor substrate has a plurality of active areas defined thereon. The buried bit lines are disposed in the semiconductor substrate, wherein two of the buried bit lines are positioned in each of the active areas. The insulating structures are disposed on the semiconductor substrate, wherein each of the insulating structures is positioned on and opposite to the two of the buried bit lines. The self-aligned spacers are disposed on the sidewalls of the insulating structures respectively to partially expose the surface of the semiconductor substrate. | 2015-10-15 |
20150294973 | INTEGRATED CIRCUIT STRUCTURE WITH BULK SILICON FINFET - The present disclosure generally provides for an integrated circuit (IC) structure with a bulk silicon finFET and methods of forming the same. An IC structure according to the present disclosure can include: a bulk substrate; a finFET located on a first region of the bulk substrate; and a layered dummy structure located on a second region of the bulk substrate, wherein the layered dummy structure includes a first crystalline semiconductive layer, a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the first crystalline semiconductive layer comprises a material distinct from the second crystalline semiconductive layer, and a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the material distinct from the second crystalline semiconductive layer. | 2015-10-15 |
20150294974 | DYNAMIC MEMORY STRUCTURE - A dynamic memory structure is disclosed. The dynamic memory structure includes: a substrate; a first strip semiconductor material disposed on the substrate and extending along a first direction; a gate standing astride the first strip semiconductor material, extending along a second direction and dividing the first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region; a first dielectric layer sandwiched between the gate and the first strip semiconductor material; a first capacitor unit disposed on the substrate and comprising the first source terminal serving as a bottom electrode, a second dielectric layer covering the first source terminal to serve as a capacitor dielectric layer and a capacitor metal layer covering the second dielectric layer to serve as a top electrode. Preferably, the first source terminal and the first drain terminal have asymmetric shapes. | 2015-10-15 |
20150294975 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This semiconductor device comprises: a trench that is provided in a semiconductor substrate; an insulating film that covers the inner surface of the trench; and a buried wiring line that fills up the lower part within the trench and is in contact with the insulating film. A barrier insulating film is arranged at least at the interface between the insulating film and the buried wiring line. | 2015-10-15 |
20150294976 | METHODS OF FORMING FINFET DEVICES IN DIFFERENT REGIONS OF AN INTEGRATED CIRCUIT PRODUCT - In one example, the method includes performing at least one process operation to form a first plurality of active fins and at least one sacrificial fin in a first area of a substrate while forming only a second plurality of active fins in a second area of said substrate, forming a fin removal masking layer that covers all of the active fins in both said first and second areas and exposes said at least one sacrificial fin in the first area, with the fin removal masking layer in position, performing at least one etching process to remove the at least one sacrificial fin in the first area and removing the fin removal masking layer. | 2015-10-15 |
20150294977 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a memory cell array including a plurality of cell strings each having a plurality of memory cells stacked in a direction perpendicular to a substrate, and a peripheral circuit region including a plurality of transistors electrically connected to the memory cell array through a plurality of conductive lines. Each of the transistors includes a gate electrode crossing an active region of the substrate in a first direction and source and drain regions in the active region at the opposite sides of the gate electrode. In at least one of the transistors, the number of source contact plugs connected to the source region is different from the number of drain contact plugs connected to the drain region. | 2015-10-15 |
20150294978 | METHOD OF MAKING A VERTICAL NAND DEVICE USING A SACRIFICIAL LAYER WITH AIR GAP AND SEQUENTIAL ETCHING OF MULTILAYER STACKS - A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and forming a sacrificial material portion including an encapsulated cavity. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material portion to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening. | 2015-10-15 |
20150294979 | SEMICONDUCTOR DEVICE HAVING FIN-TYPE ACTIVE PATTERNS AND GATE NODES - A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode. | 2015-10-15 |
20150294980 | Semiconductor Memory Devices Including Fine Patterns and Methods of Fabricatring the Same - Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween. | 2015-10-15 |
20150294981 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity. | 2015-10-15 |
20150294982 | PRINTING ELECTRONIC CIRCUITRY LOGIC - A method of making a logic gate array includes providing a substrate; forming an array of first conductive lines with plurality of first gaps disposed on each of the first conductive lines on the substrate wherein the array of first conductive lines is disposed in a first direction; forming an array of isolation lines over the first conductive lines wherein the isolation lines are not disposed on the first gaps; forming an array of second conductive lines with plurality of second gaps disposed on each of the second conductive lines on the substrate wherein the array of second conductive lines is disposed in a second direction and wherein orientation of the second direction is different than the orientation of the first direction; and printing one or more conductive ink dots at least one intersection of the first conductive lines and the second conductive lines by connecting the corresponding first gaps and corresponding second gaps. | 2015-10-15 |
20150294983 | ISOLATED SEMICONDUCTOR LAYER OVER BURIED ISOLATION LAYER - An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate. | 2015-10-15 |
20150294984 | HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR INTEGRATED INTO EXTREMELY THIN SEMICONDUCTOR ON INSULATOR PROCESS - An electrical device including a first semiconductor device in a first region of the SOI substrate and a second semiconductor device is present in a second region of the SOI substrate. The first semiconductor device comprises a first source and drain region that is present in the SOI layer of the SOI substrate, raised source and drain regions on the first source and drain regions, and a first gate structure on a channel region portion of the SOI layer. The second semiconductor device comprises a second source and drain region present in a base semiconductor layer of the SOI substrate and a second gate structure, wherein a gate dielectric of the second gate structure is provided by a buried dielectric layer of the SOI substrate and a gate conductor of the second gate structure comprises a same material as the raised source and drain region. | 2015-10-15 |
20150294985 | DISPLAY PANEL - A display panel is provided. The display panel includes has an active area and a border area surrounding the active area. The display panel includes a plurality of pixels, a plurality of multiplexer portion, a gate driver portion and a source routing portion. The pixels are located in the activate area. The multiplexer portion is located in the border area. The gate driver portion is located in the border area. The source routing portion is located in the border area. In part of the border area, at least part of the multiplexer portion, at least part of the gate driver portion and at least part of the source routing portion are located and sequentially arranged from an internal edge of the border area to an external edge of the border area. | 2015-10-15 |
20150294986 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present invention provides an array substrate and a manufacturing method thereof, and a display device. The array substrate of the present invention comprises: common electrodes, pixel electrodes, common electrode lines and at least one auxiliary common electrode line, and the at least one auxiliary common electrode line is arranged to intersect with and be electrically connected to the common electrode lines. The manufacturing method of an array substrate of the present invention comprises a step of forming common electrode lines and a step of forming auxiliary common electrode lines, wherein the auxiliary common electrode lines are arranged to intersect with and be electrically connected to the common electrode lines. The display device of the present invention comprises the above array substrate. | 2015-10-15 |
20150294987 | TFT ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - A TFT array substrate, a display panel and a display device are disclosed. The TFT array substrate includes a substrate, a display area and a peripheral area surrounding the display area. The display area and the peripheral area are arranged above the substrate. The peripheral area comprises a signal line and a shielding layer arranged above the signal line, and the shielding layer covers the signal line to shield EMI caused by a signal on the signal line. The TFT array substrate, the display panel and the display device can protect the display panel against EMI caused by the signal on the signal lines in the peripheral area, thereby improving stability and reliability of the TFT array substrate, the display panel and the display device, and enhancing sensitivity of a cellphone having the display panel. | 2015-10-15 |
20150294988 | FAN-OUT STRUCTURE AND DISPLAY PANEL USING THE SAME - A display panel comprising a fan-out structure located in a peripheral region is provided. The peripheral region has two border regions and a central region. The fan-out structure of the peripheral region comprises a plurality of first fan-out wires and a plurality of second fan-out wires alternatively arranged with the first fan-out wires. In the border regions, resistance of the first fan-out wire is lower than that of the adjacent second fan-out wire. In the central region, resistance of the first fan-out wire is higher than that of the adjacent second fan-out wire. | 2015-10-15 |
20150294989 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING A LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device ( | 2015-10-15 |
20150294990 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A highly integrated semiconductor device is provided. A first region of a first semiconductor and a first region of a second semiconductor overlap each other. A first region of the first conductor and the first region of the first semiconductor overlap each other with a first insulator interposed therebetween. A first region of a second conductor and the first region of the second semiconductor overlap each other with a second insulator interposed therebetween. A first region of a third conductor is in contact with a second region of the first semiconductor. A second region of the third conductor is in contact with a second region of the second semiconductor. A first region of a fourth conductor is in contact with a second region of the first conductor. A second region of the fourth conductor is in contact with a second region of the second conductor. | 2015-10-15 |
20150294991 | SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - A semiconductor device having a novel structure. A multiport SRAM and a data memory portion including an OS transistor are stacked. Since the multiport SRAM includes more wirings and transistors, an area increase is not caused by an increase in the number of transistors in the data memory portion including an OS transistor. An increase in the number of transistors in the data memory portion enables static operation. Thus, the data memory portion can achieve stable recovery operation, higher speed operation, and simplification. | 2015-10-15 |
20150294992 | SEMICONDUCTOR DEVICE - A semiconductor with reduced area is provided. A first transistor includes a first conductor, a first insulator over the first conductor, an oxide semiconductor provided over the first insulator so as to overlap with the first conductor, a second insulator over the oxide semiconductor, a second conductor over the second insulator, and a third conductor and a fourth conductor in contact with the oxide semiconductor. The oxide semiconductor includes a region overlapping with the first region and not overlapping with the second region, and a region not overlapping with the first conductor and overlapping with the second conductor in a region positioned between the third conductor and the fourth conductor when viewed from above. The second transistor is a p-channel transistor. A layer in which the first transistor is provided and a layer in which the second transistor is provided are stacked together. | 2015-10-15 |
20150294993 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE - An array substrate and a manufacturing method thereof as well as a display device are disclosed. The array substrate includes a gate ( | 2015-10-15 |
20150294994 | METAL OXIDE FILM AND METHOD FOR FORMING METAL OXIDE FILM - A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nmφ and less than or equal to 10 nmφ. | 2015-10-15 |
20150294995 | DISPLAY DEVICE - A display device includes an array substrate and a color filter substrate. The array substrate including data lines in a periphery circuit area, and the color filter substrate including a common electrode. A portion of the common electrode of the color filter substrate corresponding to the periphery circuit area of the array substrate includes a plurality of stripe electrodes separated from each other, extending in a length direction of the data lines and overlapped with the data lines. For each data line, two adjacent stripe electrodes among the plurality of stripe electrodes overlapped with the data line are connected through a bypass electrode which is substantially not overlapped with the data line. In case of the data lines being broken or shorted with the common electrode, the data line can be repaired by using a separate stripe electrode, thereby enabling normal operation of the circuitry. | 2015-10-15 |
20150294996 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY APPARATUS - The present invention provides an array substrate and a manufacturing method thereof, a display panel and a display apparatus. The array substrate comprises: a base substrate; and a pixel region and a periphery region formed on the base substrate, wherein the periphery region is located around the pixel region, the pixel region comprises an amorphous silicon thin film transistor, and the periphery region comprises a low temperature poly-silicon structure. As the a-Si thin film transistor is used in the pixel region of the array substrate, the problem that there is a too large leakage current in the pixel region of the LTPS array substrate in the prior art is overcome, the leakage current in the pixel region is reduced, while as the LTPS structure is used in the periphery region of the array substrate, a narrow frame of the display panel and the display apparatus may be achieved. | 2015-10-15 |
20150294997 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor includes: a first inter-layer dielectric layer formed over a front side of a substrate including photoelectric conversion regions; isolation structures each of which penetrates through the first inter-layer dielectric layer and has a portion buried in the substrate; first metal lines formed over the first inter-layer dielectric layer to correspond to the photoelectric conversion regions; and an optical filter and a light condenser formed over a back side of the substrate. | 2015-10-15 |
20150294998 | Sensor and Lithographic Apparatus - A backside illuminated sensor comprising a supporting substrate, a semiconductor layer which comprises a photodiode comprising a region of n-doped semiconductor provided at a first surface of the semiconductor layer, and a region of p-doped semiconductor, wherein a depletion region is formed between the region of n-doped semiconductor and the region of p-doped semiconductor, and a layer of p-doping protective material provided on a second surface of the semiconductor layer, wherein the first surface of the semiconductor layer is fixed to a surface of the supporting substrate. | 2015-10-15 |
20150294999 | IMAGE SENSOR PIXEL STRUCTURE WITH OPTIMIZED UNIFORMITY - An image sensor includes at least a first row and a second row of photodiodes, each photodiode being coupled with an associated transistor, each associated transistor including a gate, the first and second row of photodiodes forming a series of 2×2 Bayer-pattern units. In each Bayer-pattern unit, a first photodiode and a second photodiode in the first row are designated respectively as a first green pixel and a blue pixel, and a third photodiode and a fourth photodiode in the second row are designated respectively as a red pixel and a second green pixel, wherein a position of the gate of the transistor associated with the first photodiode relative to the first photodiode and a position of the gate of the transistor associated with the fourth photodiode relative to the fourth photodiode are the same. | 2015-10-15 |
20150295000 | IMAGING APPARATUS - There is provided an imaging apparatus in which improvements in the moisture-proof and insulation properties of an imaging device and miniaturization of the entire apparatus can be realized. The imaging apparatus is configured to include: an imaging device in which a plurality of photoelectric conversion elements are arrayed; a substrate on which the imaging device is provided and which has a larger outer shape than the imaging device; a transparent cover member that is provided on an opposite surface side to a surface of the imaging device facing the substrate and has a larger outer shape than the imaging device; and a sealing resin that fills a gap between the substrate and the cover member in order to seal a side surface of the imaging device. | 2015-10-15 |
20150295001 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor includes: a substrate including a photoelectric conversion region; a charge control layer overlapping with the photoelectric conversion region that is formed over the substrate; an inter-layer dielectric layer including lines that are formed over the charge control layer; and color filters and a light condensing pattern formed over the inter-layer dielectric layer to correspond to the photoelectric conversion region. | 2015-10-15 |
20150295002 | PIXEL STRUCTURE OF CMOS IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - A pixel structure of a CMOS image sensor pixel structure and a manufacturing method thereof. The structure comprises a photosensitive element ( | 2015-10-15 |
20150295003 | METHOD OF SIMULTANEOUSLY MANUFACTURING PARTIALLY SHIELDED PIXELS - A method of simultaneously manufacturing First and second pixels respectively shielded on a first and on a second side are simultaneously manufactured using a process wherein a first insulator is deposited on an active area. A first metal level is deposited and defined, with a first mask, to form a shield on the first side of the first pixel and on the second side of the second pixel, and a line opposite to the shield. A second insulator is deposited, and via openings therein are defined, with a second mask. An overlying second metal level is deposited and defined, with a third mask, to form two connection areas covering the via openings on each side of the first and second pixels. The second and third masks are identical for the first and second pixels. | 2015-10-15 |
20150295004 | IMAGE SENSOR MODULE AND METHOD FOR ADJUSTING FOCUS OF IMAGE SENSOR MODULE - An image sensor module includes a substrate, an image sensor mounted on the substrate, a holder position on the substrate, a lens barrel for holding a lens module and at least one spring. The spring is positioned between the holder and the lens barrel, and the spring exerts forces on the holder and the lens barrel; and the lens barrel has at least one hole, and a screw penetrates through the hole and is screwed into the holder. | 2015-10-15 |
20150295005 | DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSORS - Some embodiments of the present disclosure relate to a deep trench isolation structure. This deep trench isolation structure is formed on a semiconductor substrate having an upper semiconductor surface. A deep trench, which has a deep trench width as measured between opposing deep trench sidewalls, extends into the semiconductor substrate beneath the upper semiconductor surface. A fill material is formed in the deep trench, and a dielectric liner is disposed on a lower surface and sidewalls of the deep trench to separate the fill material from the semiconductor substrate. A shallow trench region has sidewalls that extend upwardly from the sidewalls of the deep trench to the upper semiconductor surface. The shallow trench region has a shallow trench width that is greater than the deep trench width. A dielectric material fills the shallow trench region and extends over top of the conductive material in the deep trench. | 2015-10-15 |
20150295006 | LIGHT SENSING DEVICE AND MANUFACTURING METHOD THEREOF - A light sensing device includes a substrate, a control unit and a light sensing unit. The control unit and the light sensing unit are disposed on the substrate. The control unit includes a gate electrode, a gate insulation layer, an oxide semiconductor pattern, a source electrode and a drain electrode. The gate insulation layer is disposed on the gate electrode, and the oxide semiconductor pattern is disposed on the gate insulation layer. The light sensing unit includes a bottom electrode, a light sensing diode and a top electrode. The light sensing diode is disposed on the bottom electrode, and the top electrode is disposed on the light sensing diode. The gate insulation layer partially covers the top electrode, and the gate insulation layer has a first opening partially exposing the bottom electrode. The drain electrode is electrically connected to the bottom electrode via the first opening. | 2015-10-15 |
20150295007 | IMAGE SENSOR WITH DIELECTRIC CHARGE TRAPPING DEVICE - An image sensor pixel includes a photosensitive element, a floating diffusion region, a transfer gate, a dielectric charge trapping region, and a first metal contact. The photosensitive element is disposed in a semiconductor layer to receive electromagnetic radiation along a vertical axis. The floating diffusion region is disposed in the semiconductor layer, while the transfer gate is disposed on the semiconductor layer to control a flow of charge produced in the photosensitive element to the floating diffusion region. The dielectric charge trapping device is disposed on the semiconductor layer to receive electromagnetic radiation along the vertical axis and to trap charges in response thereto. The dielectric charge trapping device is further configured to induce charge in the photosensitive element in response to the trapped charges. The first metal contact is coupled to the dielectric charge trapping device to provide a first bias voltage to the dielectric charge trapping device. | 2015-10-15 |
20150295008 | RADIATION DETECTORS, AND METHODS OF MANUFACTURE OF RADIATION DETECTORS - Radiation detectors are disclosed. The radiation detectors comprise a substrate and at least one radiation sensitive region on the substrate, the at least one radiation sensitive region comprising an array of elongate nanostructures projecting from the substrate. Methods of manufacture of such radiation detectors are also disclosed. | 2015-10-15 |
20150295009 | LIGHT EMITTING DIODE DEVICE WITH RECONSTITUTED LED COMPONENTS ON SUBSTRATE - Disclosed herein are technologies for forming a plurality of known good die (KGD)—light emitting diode (LED) components into a larger size optically coherent LED chips or devices. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims | 2015-10-15 |
20150295010 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes a transistor comprising a semiconductor substrate including an active region defined by an isolation layer; and a gate which is formed over the active region and the isolation layer and extends in a first direction to cross the active region, wherein the active region includes a head portion towering over the isolation layer, a body portion disposed under the head portion, and a neck portion which is disposed between the head portion and the body portion and is recessed compared to the head portion and the body portion in the first direction, in a region where the gate and the active region overlap with each other. | 2015-10-15 |
20150295011 | Compact Three-Dimensional Memory - The present invention discloses a compact three-dimensional memory (3D-M | 2015-10-15 |
20150295012 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes: a pair of first wirings extending in a first direction; a second wiring extending in a second direction crossing the first direction; a pair of third wirings extending in the second direction; and a fourth wiring located between the pair of the third wirings. The nonvolatile memory device has four resistance-change elements each which is provided adjacent to respective four crossing areas in which each of the pair of first wirings intersects with each of the pair of third wirings, and a first contact plug disposed at an intersection of two diagonals of a virtual tetragon defined by the four resistance-change elements. Two transistors arranged in the second direction, among four transistors, share each one first main terminal located between the pair of the first wirings, the shared each one first main terminal being connected to the second wiring. | 2015-10-15 |
20150295013 | DISPLAY DEVICE AND MANUFACTURING METHOD FOR DISPLAY DEVICE - A display device includes a first substrate on which a plurality of pixel electrodes are disposed in a matrix shape, a pixel separating film provided in a convex shape to expose a part of the pixel electrodes and divide the plurality of pixel electrodes, an organic layer provided on the exposed pixel electrodes and including a light emitting layer, a counter electrode provided to be overlapped with the light emitting layer and the pixel separating film, a sealing insulating film provided on the counter electrode, and a colored layer provided to fill a region surrounded by the convex pixel separating film and to be overlapped with an upper surface of the pixel separating film. | 2015-10-15 |
20150295014 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus includes a substrate, a first electrode disposed on the substrate, a pixel-defining layer which is disposed on the substrate and the first electrode and in which an opening which exposes a central part of the first electrode is defined, an interlayer which is disposed on the first electrode and comprises an organic light-emitting layer; and a second electrode disposed on the interlayer, where a sidewall of the opening comprises a bumpy structure in which a plurality of bumps is disposed. | 2015-10-15 |
20150295015 | DOUBLE-SIDED DISPLAY AND METHOD OF MANUFACTURING SAME - A double-sided display and a method of manufacturing the double-side display are provided. The double-sided display includes a substrate having a plurality of holes penetrating through the substrate, a TFT driving circuit, a front-side light-emitting structure, a back-side light-emitting structure, and a plurality of driving electrodes. The front-side and the back-side light-emitting structures are respectively disposed on two opposite sides of the substrate. The TFT driving circuit is disposed on one of the two opposite sides, and the driving electrodes are disposed on the other one of the two opposite sides. The TFT driving circuit is configured to drive one of the front-side and back-side light-emitting structures to display images, and is further configured to drive the other one of the front-side and back-side light-emitting structures to display images in cooperation with the driving electrodes connected to the TFT driving circuit via the holes. | 2015-10-15 |
20150295016 | DOUBLE-SIDED DISPLAY AND CONTROL METHOD THEREOF - A double-sided display and a method for controlling the same are provided. The double-sided display includes a plurality of pixel units and a plurality of circuits. The pixel units are disposed on each of a front side and a back side of the double-sided display, and the pixel units on the front side are opposite to the pixel units on the back side in a one-to-one manner. A pixel unit on the front side and a pixel unit on the back side opposite to the pixel unit on the front side are controlled by an identical circuit. Each of the circuits includes a switching transistor. The switching transistor includes a first input terminal connected to a scan line, a second input terminal connected to a data line, and an output terminal connected to the opposite pixel units on the front side and the back side. | 2015-10-15 |
20150295017 | DISPLAY UNIT - A display unit includes a plurality of light emitting devices, each of the light emitting devices including a function layer including at least an organic layer is sandwiched between a first electrode and a second electrode, and which have a resonator structure for resonating light by using a space between the first electrode and the second electrode as a resonant section and extracting the light through the second electrode are arranged on a substrate, wherein in the respective light emitting devices, the organic layer is made of an identical layer, and a distance of the resonant section between the first electrode and the second electrode is set to a plurality of different values. | 2015-10-15 |
20150295018 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device including a substrate having an isolation structure therein is disclosed. A capacitor is disposed on the isolation structure and includes a polysilicon electrode, an insulating layer disposed on the polysilicon electrode, and a metal electrode disposed on the insulating layer. A method for forming the semiconductor device is also disclosed. | 2015-10-15 |
20150295019 | MIM CAPACITOR STRUCTURE - The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor. | 2015-10-15 |
20150295020 | MIM CAPACITOR STRUCTURE - The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer. | 2015-10-15 |
20150295021 | INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE AND METHODS FOR MANUFACTURING THE SAME - A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material. | 2015-10-15 |
20150295022 | SCANDIUM-DOPED HAFNIUM OXIDE FILM - A method for preparing a scandium-doped hafnium oxide film, includes preparing a hafnium target having scandium granules distributed on a peripheral surface thereof; and proceeding a sputtering process to form a scandium-doped hafnium oxide film on a substrate, wherein the scandium doping of the scandium-doped hafnium oxide film is in the range of 3-13%. Such scandium-doped hafnium oxide film is able to be used as an oxide layer in semiconductor element which effectively suppresses the current leakage and reduces the dimension of the semiconductor element. | 2015-10-15 |
20150295023 | SCHOTTKY-BARRIER DEVICE AND RELATED SEMICONDUCTOR PRODUCT - In one general aspect, a power rectifier device can include a drift layer including silicon carbide of n-type conductivity, and a Schottky electrode disposed on the drift layer where the Schottky electrode and a surface of the drift layer can provide a Schottky contact. The power rectifier device can also include an array of p-type regions disposed underneath the Schottky electrode. | 2015-10-15 |
20150295024 | SEMICONDUCTOR DEVICE HAVING SUPER-JUNCTION STRUCTURES AND FABRICATION THEREOF - A semiconductor device is disclosed. The device includes an epitaxial layer on a substrate, wherein the epitaxial layer includes first trenches and second trenches alternately arranged along a first direction. The epitaxial layer between the adjacent first and second trenches includes a first doping region and a second doping region, and the first doping region and the second doping region have different conductivity types. An interface is between the first doping region and the second doping region to form a super-junction structure. A gate structure is on the epitaxial layer. The epitaxial layer under the gate structure includes a channel extending along a second direction, and the first direction is perpendicular to the second direction. | 2015-10-15 |
20150295025 | ELECTRONIC DEVICE HAVING A TERMINATION REGION INCLUDING AN INSULATING REGION - An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region. | 2015-10-15 |
20150295026 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a plurality of stacked semiconductor layers; a plurality of composite doped regions separately and parallelly disposed in a portion of the semiconductor layers along a first direction; a gate structure disposed over a portion of the semiconductor layers along a second direction, wherein the gate structure covers a portion of the composite doped regions; a first doped region formed in the most top semiconductor layer along the second direction and being adjacent to a first side of the gate structure; and a second doped region formed in the most top semiconductor layer along the second direction and being adjacent to a second side of the gate structure opposite to the first side thereof. | 2015-10-15 |
20150295027 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor layer, a plurality of first doped regions, a gate structure, and second and third doped regions. The semiconductor layer has a first conductivity type. The first doped regions are in parallel disposed in a portion of the semiconductor layer along a first direction and have a second conductivity type and a rectangular top view. The gate structure is disposed over a portion of the semiconductor layer along a second direction, covering a portion of the first doped regions. The second doped region is disposed in the semiconductor layer along the second direction, being adjacent to a first side of the gate structure and having the second conductivity type. The third doped region is formed in the semiconductor layer along the second direction, being adjacent to a second side of the gate structure opposing the first side and having the second conductivity type. | 2015-10-15 |
20150295028 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device has a deep layer with a higher impurity concentration than that of a super junction structure. The deep layer is formed from a position deeper from a surface of a semiconductor layer by a predetermined depth, and comes in contact with a high impurity layer and also comes in contact with the super junction structure. The deep layer overlaps with a portion between a first end which is an outermost peripheral side of a portion that comes in contact with the high impurity layer in a front surface electrode and an end on an outer peripheral side in the high impurity layer when viewed from a substrate normal direction. | 2015-10-15 |
20150295029 | PROCESS OF FORMING AN ELECTRONIC DEVICE HAVING A TERMINATION REGION INCLUDING AN INSULATING REGION - An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region. | 2015-10-15 |
20150295030 | INSULATING TRENCH FORMING METHOD - A method of manufacturing an insulating trench including the successive steps of: a) forming, on a semiconductor substrate, a first masking structure including a layer of a first selectively-etchable material and etching a trench into the substrate; b) forming an insulating coating on the trench walls and filling the trench with doped polysilicon; c) forming a silicon oxide plug penetrating into the trench substantially all the way to the upper surface of the substrate and protruding above the upper surface of the substrate; and d) removing the layer of the first material. | 2015-10-15 |
20150295031 | VERTICAL DEVICES AND METHODS OF FORMING - Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch. | 2015-10-15 |
20150295032 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device is disclosed. The semiconductor device includes a substrate having an isolation region and an active region defined by the isolation region. At least one trench is formed in the active region and extends along a first direction. A gate layer is disposed on the active region and extends along a second direction, wherein the gate layer conformably fills the at least one trench and covers a bottom surface and sidewalls of the at least one trench. The disclosure also provides a method for manufacturing the semiconductor device. | 2015-10-15 |
20150295033 | APPARATUS AND METHOD FOR MANUFACTURING SAME - This apparatus is composed of an insulating film having a high dielectric constant and an electrode film including a metal material, layered in that order on a substrate divided into an active region and an element separation region surrounding the active region, and has a gate structure extending from the active region to the element separation region. The element separation region is provided with: a groove formed in the substrate; a first insulating film covering the side wall face of the groove and embedded in the bottom part of the groove; and a second insulating film covering the first insulating film embedded in the bottom part of the groove and embedded in the top part of the groove. | 2015-10-15 |
20150295034 | SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR MESA INCLUDING A CONSTRICTION - A semiconductor device includes a body zone in a semiconductor mesa, which is formed between neighboring control structures that extend from a first surface into a semiconductor body. A drift zone forms a first pn junction with the body zone. In the semiconductor mesa, the drift zone includes a first drift zone section that includes a constricted section of the semiconductor mesa. A minimum horizontal width of the constricted section parallel to the first surface is smaller than a maximum horizontal width of the body zone. An emitter layer between the drift zone and the second surface parallel to the first surface includes at least one first zone of a conductivity type of the drift zone. | 2015-10-15 |
20150295035 | SEMICONDUCTOR FILM, SOLAR CELL, LIGHT-EMITTING DIODE, THIN FILM TRANSISTOR, AND ELECTRONIC DEVICE - A semiconductor film includes a cluster of semiconductor quantum dots each having a metal atom and ligands coordinating to respective semiconductor quantum dots, and the semiconductor quantum dots have an average shortest inter-dot distance of less than 0.45 nm. A solar cell, a light-emitting diode, a thin film transistor, and an electronic device include the semiconductor film. | 2015-10-15 |
20150295036 | NANOWIRE DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region. | 2015-10-15 |
20150295037 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 2015-10-15 |
20150295038 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 2015-10-15 |
20150295039 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 2015-10-15 |
20150295040 | SYSTEMS AND METHODS FOR FABRICATING VERTICAL-GATE-ALL-AROUND TRANSISTOR STRUCTURES - Systems and methods are provided for fabricating nanowire devices on a substrate. A first nanowire and a second nanowire are formed on a substrate, the first nanowire and the second nanowire extending substantially vertically relative to the substrate. A first source region and a first drain region are formed with n-type dopants, the first nanowire being disposed between the first source region and the first drain region. A second source region and a second drain region are formed with p-type dopants, the second nanowire being disposed between the second source region and the second drain region. | 2015-10-15 |
20150295041 | ELECTRONIC DEVICE CONTAINING NANOWIRE(S), EQUIPPED WITH A TRANSITION METAL BUFFER LAYER, PROCESS FOR GROWING AT LEAST ONE NANOWIRE, AND PROCESS FOR MANUFACTURING A DEVICE - The electronic device comprises a substrate ( | 2015-10-15 |