42nd week of 2015 patent applcation highlights part 53 |
Patent application number | Title | Published |
20150294642 | DISPLAY DEVICE, METHOD OF DRIVING DISPLAY DEVICE, AND ELECTRONIC APPARATUS - A display device includes: an image display panel including a plurality of pixels each including first to fourth sub-pixels; and a signal processing unit. The signal processing unit determines an expansion coefficient related to the image display panel, obtains output signals of the first to the third sub-pixels based on at least input signals of the first to the third sub-pixels and the expansion coefficient to be output to the first to the third sub-pixels respectively, obtains a fourth sub-pixel correction value as a correction value of an output signal of the fourth sub-pixel based on the input signals of the first to the third sub-pixels and the expansion coefficient, and obtains the output signal of the fourth sub-pixel based on the input signals of the first to third sub-pixels, the expansion coefficient, and the fourth sub-pixel correction value to be output to the fourth sub-pixel. | 2015-10-15 |
20150294643 | CORRECTING METHOD, CORRECTING APPARATUS AND METHOD FOR ESTABLISHING COLOR PERFORMANCE DATABASE FOR DISPLAY APPARATUS - A correcting method for a display apparatus is provided. For N original grayscale combinations, color performances of the display apparatus are respectively measured to generate N measurement results. A set of color blending equations are utilized for M original grayscale combinations according to the N measurement results to generate M blended results. From the N measurement results and the M blended results, P color performances respectively most approximate to P target performances are identified. The P target color performances correspond to P target grayscale combinations. The P color performances correspond to P original grayscale combinations in the (N+M) original grayscale combinations. A look-up table for correcting the display apparatus is established according to the P target grayscale combinations and the P corresponding original grayscale combinations. | 2015-10-15 |
20150294644 | DISPLAY DEVICE AND ELECTRONIC APPARATUS - According to an aspect, a display device includes a display unit that includes a dielectric material between two substrates that face each other and a plurality of pixel circuits that apply an electric field to the dielectric material according to an image input gradation for each of a plurality of pixels arranged in a matrix, and displays an image using the plurality of pixels; a capacitance detection unit that outputs a detection signal of a magnitude corresponding to a value of capacitance of the dielectric material; and a control device determines, on the basis of the detection signal from the capacitance detection unit, that the display is normal when a correlation value of the capacitance to the image input gradation is in a predetermined correlation. | 2015-10-15 |
20150294645 | COMMUNICATION TERMINAL, SCREEN DISPLAY METHOD, AND RECORDING MEDIUM - A communication terminal includes: a screen; an operation acceptance unit; a communication establishment unit; a data transmitting unit that transmits determination image data currently being displayed on the local terminal to another terminal; a data receiving unit that receives determination image data from the other terminal; a relative position sensing unit; a data display region detection unit that acquires a user operation, senses a display position movement operation, and detects a data display region; and a display control unit that, when at least part of the data display region after the movement operation for the determination image data is included in a region that can be displayed on the screen of the local terminal, displays the determination image data in the data display region after the movement operation, only in the region that can be displayed on the screen of the local terminal. | 2015-10-15 |
20150294646 | DISPLAY APPARATUS AND METHOD FOR DISPLAYING SCREEN IMAGES FROM MULTIPLE ELECTRONIC DEVICES - A method for displaying screen images from multiple electronic devices using a display apparatus, the display apparatus includes a display screen and a connection device. The method includes establishing connections between the connection device and two or more of the multiple electronic devices when the connection device receives connection requests from two or more of the multiple electronic devices, and controlling the connection device to receive screen image signals sent from the connected two or more electronic devices. The method further includes generating a number of display windows on a display area of the display screen, associating each of the connected two or more electronic devices with one of the plurality of generated display windows, and displaying screen images generated from the display image signals sent from each of the connected two or more electronic devices in the display windows associated with the connected two or more electronic devices. | 2015-10-15 |
20150294647 | DISPLAY SYSTEM - A display system is provided. The display system includes a perframe controller configured to receive a frame synchronization signal and to change values of M and N in synchronization with at least one pulse of the frame synchronization signal, where M and N are natural numbers; and a fractional divider configured to generate and output a pixel clock signal by dividing an input clock signal by a division ratio of N/M. | 2015-10-15 |
20150294648 | ENERGY CONSERVATION IN A CONTROLLER USING DYNAMIC FREQUENCY SELECTION - Systems and methods of adjusting a frequency of a graphics controller may include a logic to determine a metric associated with an input/output (I/O) queue. The metric may be used to determine whether an I/O limited condition exists. The I/O limited condition may be associated with a graphics controller. There may be a logic to cause a frequency of the graphics controller to be decreased when the I/O limited condition exists, and a logic to cause the frequency of the graphics controller to be increased when the I/O limited condition does not exist. The I/O limited condition may exist when a magnitude of the metric is equal to or greater than a first threshold. The I/O limited condition may not exist when the magnitude of the metric is equal to or less than a second threshold. | 2015-10-15 |
20150294649 | DISPLAY CONTROL APPARATUS, DISPLAY CONTROL PROGRAM AND DISPLAY CONTROL METHOD - A display control apparatus ( | 2015-10-15 |
20150294650 | KEY FOR KEYBOARD MUSICAL INSTRUMENT, AND METHOD FOR MANUFACTURING THE KEY - A key includes upper, front and side walls each having a flat shape, and a downwardly-opening space. The key includes a first part (e.g., the upper and front walls) normally visible from outside with the key assembled to the keyboard musical instrument; and a second part (e.g., the side walls) normally invisible from outside with the key assembled to the keyboard musical instrument. In molding, a first molding process is performed where resin is poured into a first mold to mold one of the part normally visible from outside and the part normally invisible from outside, and then a second molding process is performed where the one part molded by the first molding process is inserted into a second mold and resin is poured into the second mold so that the other of the parts is molded and thus the upper wall, front wall and side walls are insert-molded. | 2015-10-15 |
20150294651 | GUITAR STRING TUNING AND ANCHOR SYSTEM - An apparatus for securing one end of a guitar string to a guitar is disclosed. The apparatus includes a mount adapted to be secured to and extend upwardly from the bridge of the guitar, and where the mount defines a pivot axis above the bridge of the guitar. The apparatus also can include a string holder pivotally connected to the mount at the pivot axis, the string holder comprising an anchor to securely hold the end of the guitar string, the string holder having a first end and a second end, the first end positioning the guitar string below the saddle height of the bridge. Additionally, the apparatus can include a position adjuster operatively connected to the mount and the string holder, where the position adjuster can be used for adjusting the pivot angle of the string holder to adjust tension on the guitar string. | 2015-10-15 |
20150294652 | FASTENING DEVICE FOR AN ELECTRIC GUITAR - String fastener in the guitar body of an electric guitar, includes a bridge, carrying one saddle per string located at the upper side of the bridge, across which a string is arranged to run, one saddle per string fastened to the upper side, a downwards directed, pivoted lever arranged at each saddle, at which lever one string end is fastened, a tuning spring fastened with one of its ends to the lever and with its other end to the guitar body, which tuning spring strives to maintain a constant pulling force in a string, and which string fastener is provided with a vibrato arm, which when activated results in the bridge angling towards the guitar body, the vibrato arm being pivotally fastened to and running through the bridge. A fastening element maintains each lever in position, and a release device cooperates with the fastening element to release the levers. | 2015-10-15 |
20150294653 | Guitar Pick - A guitar pick that is operable to be releasably secured to a user's thumb and biased thereagainst so as to maintain a position for transition from a finger-play style of play to a pick-play style of play. The guitar pick includes a body that is planar in manner and substantially rigid. The body is formed in an asymmetrical shape so as to inhibit contact between the perimeter edge of the body and the fingers of a hand of a user during a finger-play style of play. The guitar pick further includes an aperture journaled therethrough. An attachment member is provided that is releasably secured to the body of the guitar pick by being journaled through the aperture. The attachment member forms a loop that is operable to receive a thumb and wherein the loop functions to bias the guitar pick against the thumb. | 2015-10-15 |
20150294654 | Piccolo - A piccolo having a flute body ( | 2015-10-15 |
20150294655 | PITCH AND TONE ALTERING DRUM COVER - A pitch altering cover for a drumhead is provided. The pitch altering cover includes a circular drumhead cover having an upper surface and a lower surface. The lower surface is formed to rest on a drumhead. A gasket is attached at least a portion of a parameter of the upper surface of the circular drumhead cover. | 2015-10-15 |
20150294656 | METHOD AND SYSTEM FOR GENERATING SOUNDS USING PORTABLE AND INEXPENSIVE HARDWARE AND A PERSONAL COMPUTING DEVICE SUCH AS A SMART PHONE - Disclosed is a method and system describing an electronic musical instrument which outsources processing, memory, and audio output functions to a personal computing device such as a smart phone in order to achieve an electronic musical instrument with minimal hardware components, minimal cost, and potential for high portability. In an embodiment, the electronic musical instrument can be as small as an individual sensor which can be removably attached to any surface, although the technology is such that the instrument could be shaped in nearly any shape or size desired. | 2015-10-15 |
20150294657 | INSTRUMENT CASE - Methods, systems, and apparatus for the protection and transportation of musical instruments can include cases constructed of a semi-rigid and lightweight material to enable convenient transportation of the instrument and instrumental accessories, such as in internal and compartmentalized storage areas. Extendable/collapsible legs can enable the case to be placed in a standing position and to enable instruments to be retrieved and/or inserted whilst the case is in the standing position. The lid may be foldable over the front of the case or removed entirely from the case. | 2015-10-15 |
20150294658 | ELECTRONIC PERCUSSION INSTRUMENT WITH ENHANCED PLAYING AREA - Electronic percussion instruments with enhanced playing areas and methods and systems for generating electrical signals in response to impacts to a playing surface are disclosed. A semi-permeable playing surface covering an acoustic noise reducing cavity of an electronic percussion instrument may receive an impact within a predefined impact region, and an electrical signal may be generated in response by an electromechanical sensor that senses the impact. In many instances, the generated electrical signal may be configured to be equivalent in magnitude to any other electrical signal generated by the electromechanical sensor, in response to any other received impact within the same predefined impact region. | 2015-10-15 |
20150294659 | SYSTEM AND METHOD FOR SWITCHING SOUND PICKUPS IN AN ELECTRIC GUITAR USING A SPIN WHEEL ARRANGEMENT - The embodiments herein provide a system and method for instantly switching sound pickups in an electric guitar using a spin wheel arrangement in the middle of a song. The spin wheel houses a pickup assembly with multiple pickups. The spin wheel allows a guitar player to easily roll neck pickup to bridge position and bridge pickup to neck position in middle of a song by rotating the spin wheel. A click stop arrangement halts wheel rotation after completing a semi-circular rotation around a center screw. The backend portion of pickups is connected to spring loaded plunger. The contact pads at bottom portion of guitar body establishes electrical connections between pickups and control components. The pickups under the strings get activated. The spin wheel arrangement allows a guitar player to add favorite pickups for generating various tonalities beyond the limit of a single guitar. | 2015-10-15 |
20150294660 | SONAR TRANSDUCER SUPPORT ASSEMBLY SYSTEMS AND METHODS - Techniques are disclosed for systems and methods for providing accurate and reliable compact sonar systems for mobile structures. In one embodiment, a sonar system includes a mounting bracket, a transducer support arm, and a pivoting mechanism pivotably coupling the transducer support arm to the mounting bracket such that, for forces acting on the transducer support arm that are less than a preselected kick-up level, the pivoting mechanism holds the transducer support arm against such forces and at a user selectable first angular position relative to the mounting bracket, and for forces acting on the transducer support arm that are equal to or greater than the preselected kick-up level, allows the transducer support arm to be moved by those forces to a second angular position relative to the mounting bracket. | 2015-10-15 |
20150294661 | ACOUSTIC ANTENNA ELEMENT FOR EMITTING AND/OR RECEIVING WAVES UNDER WATER AND ASSOCIATED ACOUSTIC ANTENNA - An acoustic antenna element for receiving and/or emitting low-frequency underwater waves comprises an acoustic panel formed by at least one acoustic pick-up enclosed in a flexible jacket, the acoustic panel being generally rectangular and being mounted against a curved support by a mounting device including a clamping device comprising at least two flanges the ends of which are mounted on the support, the respective flanges comprising at least one tie between the two ends thereof, and the clamping device capable of adjusting the tension in the ties between the two respective ends thereof, the flanges being arranged so that the support is bent between the two respective ends of the ties and so that the panel is clamped against the support by the ties when they are under tension. | 2015-10-15 |
20150294662 | Selective Noise-Cancelling Earphone - An earphone adapted to fit within a human ear that generates sound via the propagation of one or more diaphragms aligned to fit the structure and shape of the earphone. The earphone allows ambient sound to pass through the device in order to be heard by the user. The earphone includes a variety of sensors adapted to characterize the surrounding acoustic environment and actively negate undesired sounds by generating a cancelling signal specific to the undesired sound or sounds. The earphone allows users to select particular sounds to cancel or to negate all of the surrounding noise. The earphone itself can be used to characterize repetitive environmental sounds that are predictable by the system. Additionally, the earphone can be used in conjunction with a buffering device in communication with a source of non-repetitive, unpredictable sounds in order to characterize and negate those sounds. | 2015-10-15 |
20150294663 | CAPACITIVE MICRO-MACHINED TRANSDUCER AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of manufacturing a capacitive micro-machined transducer ( | 2015-10-15 |
20150294664 | NAVIGATION DEVICE AND INFORMATION PROVIDING METHOD - A navigation device includes: an acquisition section for acquiring plurality of updated content introductory information each representing the latest updated content in a predetermined web site based on user's preference information; a detection section for detecting surrounding position information covering an area around the current position from large number of position information stored in a predetermined storage section; and a search section for searching for particular updated content introductory information corresponding to the surrounding position information detected by the detection section as surrounding updated content introductory information from the plurality of updated content introductory information acquired by the acquisition section. | 2015-10-15 |
20150294665 | UNSUPERVISED TRAINING METHOD, TRAINING APPARATUS, AND TRAINING PROGRAM FOR N-GRAM LANGUAGE MODEL - A computer-based, unsupervised training method for an N-gram language model includes reading, by a computer, recognition results obtained as a result of speech recognition of speech data; acquiring, by the computer, a reliability for each of the read recognition results; referring, by the computer, to the recognition result and the acquired reliability to select an N-gram entry; and training, by the computer, the N-gram language model about selected one of more of the N-gram entries using all recognition results. | 2015-10-15 |
20150294666 | DEVICE INCLUDING SPEECH RECOGNITION FUNCTION AND METHOD OF RECOGNIZING SPEECH - A device including a speech recognition function which recognizes speech from a user, includes: a loudspeaker which outputs speech to a space; a microphone which collects speech in the space; a first speech recognition unit which recognizes the speech collected by the microphone; a command control unit which issues a command for controlling the device, based on the speech recognized by the first speech recognition unit; and a control unit which prohibits the command issuance unit from issuing the command, based on the speech to be output from the loudspeaker. | 2015-10-15 |
20150294667 | NOISE CANCELLATION APPARATUS AND METHOD - Disclosed herein is a noise cancellation apparatus and method, which select in advance parameters to be used for noise cancellation in a reference voice signal section by generating a reference voice signal in advance before a voice signal is generated, thus improving noise cancellation effects. The noise cancellation apparatus includes a parameter initialization unit for determining an initial value of a parameter to be used for noise cancellation, based on reference signals filtered for respective frequencies, a parameter estimation unit for receiving the initial value of the parameter, and estimating the parameter in response to signals that are input after being filtered for respective frequencies, a gain estimation unit for calculating gains for respective frequencies based on the parameter from the parameter estimation unit, and a gain application unit for cancelling noise by applying the gains to the signals that are input after being filtered for respective frequencies. | 2015-10-15 |
20150294668 | Word-Level Correction of Speech Input - The subject matter of this specification can be implemented in, among other things, a computer-implemented method for correcting words in transcribed text including receiving speech audio data from a microphone. The method further includes sending the speech audio data to a transcription system. The method further includes receiving a word lattice transcribed from the speech audio data by the transcription system. The method further includes presenting one or more transcribed words from the word lattice. The method further includes receiving a user selection of at least one of the presented transcribed words. The method further includes presenting one or more alternate words from the word lattice for the selected transcribed word. The method further includes receiving a user selection of at least one of the alternate words. The method further includes replacing the selected transcribed word in the presented transcribed words with the selected alternate word. | 2015-10-15 |
20150294669 | Speaker and Call Characteristic Sensitive Open Voice Search - Techniques disclosed herein include systems and methods for open-domain voice-enabled searching that is speaker sensitive. Techniques include using speech information, speaker information, and information associated with a spoken query to enhance open voice search results. This includes integrating a textual index with a voice index to support the entire search cycle. Given a voice query, the system can execute two matching processes simultaneously. This can include a text matching process based on the output of speech recognition, as well as a voice matching process based on characteristics of a caller or user voicing a query. Characteristics of the caller can include output of voice feature extraction and metadata about the call. The system clusters callers according to these characteristics. The system can use specific voice and text clusters to modify speech recognition results, as well as modifying search results. | 2015-10-15 |
20150294670 | TEXT-DEPENDENT SPEAKER IDENTIFICATION - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for speaker verification. The methods, systems, and apparatus include actions of inputting speech data that corresponds to a particular utterance to a first neural network and determining an evaluation vector based on output at a hidden layer of the first neural network. Additional actions include obtaining a reference vector that corresponds to a past utterance of a particular speaker. Further actions include inputting the evaluation vector and the reference vector to a second neural network that is trained on a set of labeled pairs of feature vectors to identify whether speakers associated with the labeled pairs of feature vectors are the same speaker. More actions include determining, based on an output of the second neural network, whether the particular utterance was likely spoken by the particular speaker. | 2015-10-15 |
20150294671 | SECURITY ALARM SYSTEM WITH ADAPTIVE SPEECH PROCESSING - A regional monitoring system includes speech recognition circuitry having smart filtering capability to interpret speech input from a user to provide interactions between the user and the system. Received voice commands can be filtered using key words to interpret security commands which can then be executed. The system can provide audible feedback using one or more of prerecorded voice data files or synthesized speech. | 2015-10-15 |
20150294672 | Method And Device For Decoding An Audio Soundfield Representation For Audio Playback - Soundfield signals such as e.g. Ambisonics carry a representation of a desired sound field. The Ambisonics format is based on spherical harmonic decomposition of the soundfield, and Higher Order Ambisonics (HOA) uses spherical harmonics of at least 2 | 2015-10-15 |
20150294673 | SPEECH AUDIO ENCODING DEVICE, SPEECH AUDIO DECODING DEVICE, SPEECH AUDIO ENCODING METHOD, AND SPEECH AUDIO DECODING METHOD - By the present invention, the number of encoding bits allocated to encoding of extended-band spectrum is reduced while degradation of sound quality in the extended band is suppressed. A band compression unit creates combinations of sub-band spectra in pairs of two samples each in order from a low-range side in a band compression target sub-band, selects a spectrum having a large absolute-value amplitude among the combinations, and arranges the selected spectrum close to the low-range side on a frequency axis. A number-of-units recalculation unit redistributes bits saved in the sub-band for which band compression was performed to a low range outside the extended band, and redistributes the number of units on the basis of the redistributed bits. | 2015-10-15 |
20150294674 | AUDIO SIGNAL PROCESSOR, METHOD, AND PROGRAM - The invention provides an audio signal processing device capable of improving sound quality by causing a voice switch to operate appropriately. Delay-subtraction processing is performed on an input signal to form a first and second directional signal with nulls in a first and second specific direction, respectively, and a coherence is obtained using the two directional signals. The coherence is then compared to a determination threshold value to determine whether the input audio signal is a target-sound segment arriving from a target-direction, or a non-target-sound segment other than the target-sound segment. A gain is set according to the determination result, and any non-target-sound is attenuated by multiplying the input signal by the gain. The determination threshold value is controlled based on an average value of coherence in interfering-sound segments. | 2015-10-15 |
20150294675 | Audio Signal Processing - Disclosed is a device having an audio interface configured to generate from the audio signal an outgoing audio signal for supplying to a loudspeaker component. The audio interface is configured, in generating the outgoing audio signal, to apply dynamic range compression to the audio signal. Device software is configured to receive an incoming audio signal and generate an audio signal from the incoming audio signal. The audio signal generated by the software is supplied to the audio interface for outputting by the loudspeaker component and is also used as a reference in audio signal processing. Generating the audio signal comprises the software applying initial nonlinear amplitude processing to the incoming audio signal to modify its power envelope. The modified power envelope is sufficiently smooth to be substantially unaffected by the dynamic range compression when applied by the audio interface. | 2015-10-15 |
20150294676 | METHOD FOR MANUFACTURING MAGNETIC CORE MODULE IN MAGNETIC HEAD, MAGNETIC CORE MODULE IN MAGNETIC HEAD AND MAGNETIC HEAD - A method for manufacturing a magnetic core module in a magnetic head, the magnetic core module and the magnetic head. The method for manufacturing the magnetic core module includes: a process for placing a magnetic core group in a holder mold cavity as an insert; and a process for injection-molding in the holder mold cavity. A method for manufacturing the magnetic core module allows the magnetic core group and the holder to be integrally injection-molded with a method of injection molding which uses the magnetic core group as an insert. The method simplifies the process of manufacturing a magnetic head to improve production efficiency, and saves labor and production costs. Further, the method prevents failures such as positional displacement and scattering of magnetic cores, which tends to occur when assembling thin and small magnetic cores, and ensures an ideal yield for a product. | 2015-10-15 |
20150294677 | THERMALLY-ASSISTED MAGNETIC RECORDING HEAD - In one embodiment, a device includes a near-field light transducer having multiple apexes including a trailing-side apex positioned on a trailing side of the near-field light transducer. The device also includes a first material positioned near the trailing-side apex of the near-field light transducer, and a second material positioned near another apex of the near-field light transducer. The first material is physically characterized as etching more slowly than the second material. | 2015-10-15 |
20150294678 | THERMAL ASSISTED MAGNETIC RECORDING HEAD UTILIZING UNCOUPLED LIGHT - A thermal assisted magnetic recording head has a magnetic head slider having an air bearing surface that is opposite to a magnetic recording medium, a core that can propagate laser light as propagating light, a plasmon generator that includes a generator front end surface facing the air bearing surface, and a main pole facing the air bearing surface, and a laser light generator that supplies the laser light to the core. The plasmon generator generates near-field light (NF light) at the generator front end surface to heat the magnetic recording medium. The main pole includes a main pole end surface that faces the air bearing surface and that is positioned in the vicinity of the generator front end surface, and emits a magnetic flux to the magnetic recording medium from the main pole end surface. At least a portion of the laser light that is not coupled with the plasmon generator thermally deforms the air bearing surface so that a part of the air bearing surface positioned closer to the leading side than the generator front end surface and the main pole end surface in the down track direction protrudes toward the magnetic recording medium. | 2015-10-15 |
20150294679 | PERPENDICULAR MAGNETIC RECORDING MEDIUM WITH GRAIN BOUNDARY CONTROLLING LAYERS - In one embodiment, a perpendicular magnetic recording medium includes an oxide recording layer including an oxide and a non-oxide recording layer which does not contain an oxide positioned above the oxide recording layer. The oxide recording layer includes a first recording layer, a second recording layer, a third recording layer, and a fourth recording layer. Also, an oxide concentration of the first recording layer is greater than an oxide concentration of the second recording layer, an oxide concentration of the third recording layer is greater than an oxide concentration of the fourth recording layer, and the oxide concentration of the third recording layer is greater than the oxide concentration of the second recording layer. | 2015-10-15 |
20150294680 | METHOD OF FABRICATING A BPM TEMPLATE USING HIERARCHICAL BCP DENSITY PATTERNS - The embodiments disclose a method including patterning a template substrate to have different densities using hierarchical block copolymer density patterns in different zones including a first pattern and a second pattern, using a first directed self-assembly to pattern a first zone in the substrate using a first block copolymer material, and using a second directed self-assembly to pattern a second zone in the substrate using a second block copolymer material. | 2015-10-15 |
20150294681 | OPTICAL INFORMATION RECORDING DEVICE, OPTICAL INFORMATION RECORDING AND REPRODUCING DEVICE, OPTICAL INFORMATION RECORDING METHOD, OPTICAL INFORMATION RECORDING AND REPRODUCING METHOD, AND OPTICAL ELEMENT - The optical information recording and reproducing method realizes an increased number of multiplexing in recording and favorably stabilized signal recording in a manner of uniforming media consumption in angle-multiplexed recording by changing a phase of signal light on a pixel basis in a manner in which the speed of a phase change on a pixel basis is constant or is greater than or equal to a certain speed in a page and between pages when the driving speed of a phase mask changes at the time of recording. The optical information recording and reproducing method, while moving an optical element that adds phase information to a light flux which includes two-dimensional page data information in a direction that is perpendicular to an optical axis of the light flux, records the page data on the recording medium by adding the phase information to the light flux. | 2015-10-15 |
20150294682 | OPTICAL INFORMATION APPARATUS - In order to correct signal-to-noise ratio degradation caused by a position error of an aperture filter relative to a signal beam and ensure a high recording signal quality in an optical information apparatus using holography, an optical detection system capable of conducting position adjustment of the aperture filter by using the signal beam is provided and the aperture filter is positioned with high precision. | 2015-10-15 |
20150294683 | REDUCED REEL MOTOR DISTURBANCES IN A TAPE DRIVE SYSTEM - An apparatus according to one embodiment includes a motor having: a rotor, a magnet, and a damping layer positioned between the rotor and the magnet. The damping layer is constructed of a material characterized by converting kinetic energy into heat. | 2015-10-15 |
20150294684 | BAND REWRITE OPTIMIZATION - Implementations disclosed herein provide a method comprising comparing high-latency data sectors of a storage band, the high-latency data sectors having latency above a predetermined threshold, with target sectors for storing new data to determine one or more of the high-latency data sectors that may be skipped during retrieval of at-rest data from the storage band. | 2015-10-15 |
20150294685 | SYSTEMS AND METHODS FOR CREATING LINEAR VIDEO FROM BRANCHED VIDEO - Computer-implemented methods and systems for creating non-interactive, linear video from video segments in a video tree. Selectably presentable video segments are stored in a memory, with each segment representing a predefined portion of one or more paths in a traversable video tree. A linear, non-interactive video is automatically created from the selectably presentable video segments by traversing at least a portion of a first path in the video tree and, upon completion, is provided to a viewer for playback. | 2015-10-15 |
20150294686 | TECHNIQUE FOR GATHERING AND COMBINING DIGITAL IMAGES FROM MULTIPLE SOURCES AS VIDEO - Electronic arrangement, optionally a number of servers, including: a computing entity configured to receive image entities from a plurality of electronic devices, optionally mobile terminals, and configured to process the image entities, the computing entity being specifically configured to: obtain a plurality of image entities from the plurality of electronic devices, and combine the obtained image entities into a video representation according to the metadata associated with the image entities, optionally date and/or time data, and/or the source of the image entities. A corresponding method is also presented. | 2015-10-15 |
20150294687 | Automatic Transitions, Wipes and Fades, In A Common Video Recording/Playback Device - Systems and algorithms for inserting transitions (wipes and fades) into segments of recorded video are described. Automatic insertion of transitions into video makes video more beautiful and interesting, and also eliminates the need for user intervention, saving the user time. Additionally described are custom/proprietary wipe and fade effects (transitions) that are inserted. These effects include but are not limited to the categories: Through solid color or image, Bring back previous User Footage, Sequence of Images Overlay, Random Images Overlay, Mirroring User Footage, Reversing User Footage, Current Location Integration, and Blurring User Footage. Any combination of one or all of these categories of transition can be used simultaneously and combined to achieve the desired final transition that is applied to user footage. Insertion of these effects into video is based on random and temporal algorithms. | 2015-10-15 |
20150294688 | APPLICATION TUNE MANIFESTS AND TUNE STATE RECOVERY - In accordance with one or more aspects, a request to run an application is received. The application has an associated tune manifest that identifies one or more resources that the application may use. The tune manifest is compared to a device resource record, and a check is made, based at least in part on the comparing, whether the one or more resources identified in the tune manifest can be satisfied by the device. If the one or more resources identified in the tune manifest can be satisfied by the device, then the application is run; otherwise, a notification of a conflict between the application and the device is presented. Additionally, when the application exits, a device tune state that identifies a content source to which the device was tuned prior to running the application can be retrieved and the device restored to this device tune state. | 2015-10-15 |
20150294689 | MOTOR BASED FAILURE PREDICTION - Provided herein is a method, including detecting a plurality of pieces of data associated with a motor and determining a percent drag change based on the plurality of pieces of data associated with the motor. The method further includes determining a failure prediction based on the percent drag change. | 2015-10-15 |
20150294690 | MAGNETIC DISK APPARATUS AND DATA RECORDING METHOD - A magnetic disk apparatus of one of the embodiments stores read position dependency information on read signal quality of a data region at a first track and measures the read signal quality at a predetermined radial position in a second data region of a second track different from the first track. A positioning error of the second data region is determined based on the read position dependency information and the read signal quality at the predetermined radial position. Data is recorded in a recording target data region in a singled recording so as to prevent data written in the second data region from being overwritten by data in a recording target data region adjacent to the second data region by using the determined positioning error. | 2015-10-15 |
20150294691 | SEALED DISK MEDIA ENCLOSURE - A sealed disk media enclosure is provided. The sealed disk media enclosure in one example includes a media enclosure structure formed of a porous material and including a disk media chamber and a chamber aperture on one side of the media enclosure structure, one or more disk media located in the disk media chamber, a Diamond-Like Carbon (DLC) coating on at least a portion of the media enclosure structure, with the DLC coating preventing passage of gas molecules through the media enclosure structure, and a cover affixed to the media enclosure structure and substantially sealing the chamber aperture, wherein a predetermined gas or gas mixture is sealed within the disk media chamber. | 2015-10-15 |
20150294692 | Mixed Three-Dimensional Printed Memory - The present invention discloses a mixed three-dimensional printed memory (3D-P). The slow contents (e.g., e.g., digital books, digital maps, music, movies, and/or videos) are stored in large memory blocks and/or large memory arrays, whereas the fast contents (e.g., operating systems, software, and/or games) are stored in small memory blocks and/or small memory arrays. | 2015-10-15 |
20150294693 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device | 2015-10-15 |
20150294694 | AREA EFFICIENT LAYOUT WITH PARTIAL TRANSISTORS - A CMOS apparatus includes a first transistor having a first transistor gate, a second transistor having a second transistor gate, a partial transistor having a gate and only one of a drain or a source. The CMOS apparatus further includes a gate interconnect connecting the first transistor gate to the second transistor gate through the gate of the partial transistor. The CMOS apparatus may be a bit cell. A write word enable line may include the gate interconnect, and the first and second transistors may enable write bit lines to the bit cell. | 2015-10-15 |
20150294695 | SEMICONDUCTOR RESISTIVE MEMORY DEVICES INCLUDING SEPARATELY CONTROLLABLE SOURCE LINES - A magnetic memory device can include a plurality of separately controllable magnetic memory segments configured to store data. A plurality of separately controllable source lines can each be coupled to a respective one of the plurality of separately controllable magnetic memory segments. | 2015-10-15 |
20150294696 | STABILIZING CIRCUIT - A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V. | 2015-10-15 |
20150294697 | HIGH SPEED DEGLITCH SENSE AMPLIFIER - A sense amplifier is provided that includes a skewed latch that latches a voltage difference developed responsive to a read operation on an accessed memory cell. The skewed latch includes a loaded logic gate that is cross-coupled with an unloaded logic gate. The loaded logic gate drives the unloaded logic gate and an output transistor whereas the unloaded logic gate drives only the loaded logic gate. | 2015-10-15 |
20150294698 | System and Method for Offsetting The Data Buffer Latency of a Device Implementing a JEDEC Standard DDR-4 LRDIMM Chipset - A system and method for offsetting the data buffer latency in a CPIO device having a JEDEC standard DDR-4 LRDIMM chipset as the front end is disclosed. According to one embodiment, a CPIO ASIC provides variable timing control for its DDR-4 LRDIMM interface such that propagation delay of the data buffers can be offset by the CPIO ASIC, allowing the CPIO LRDIMM to be timing compatible with an RDIMM. | 2015-10-15 |
20150294699 | SEMICONDUCTOR DEVICES INCLUDING PIPE LATCH UNITS AND SYSTEM INCLUDING THE SAME - The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data output portion receives an input control signal, a latch pulse signal, and a first output control signal. The data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and the data output portion also shifts the first output control signal in response to the shift clock signal to generate a second output control signal. | 2015-10-15 |
20150294700 | MEMORY TIMING CIRCUIT - A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit. | 2015-10-15 |
20150294701 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first buffer suitable for receiving and buffering data, a second buffer suitable for receiving and buffering a data strobe signal, a strobe line suitable for transferring the data strobe signal; a plurality of data transfer lines suitable for transferring data inputted at corresponding turns among data inputted in series through the first buffer, a latch signal generation block suitable for generating a plurality of latch signals which are sequentially activated, based on the data strobe signal transferred through the strobe line, a data latch block suitable for latching and aligning in parallel the data inputted in series through the first buffer, based on the latch signals, and a data transfer block suitable for transferring the data latched by the data latch block to the plurality of data transfer lines, according to a correspondence relationship determined based on an input start signal that is activated at a time when the input of data corresponding to the data input command is started. | 2015-10-15 |
20150294702 | ELECTRONIC DEVICE - Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes two variable resistance elements in each storage cell, thereby increasing margin and speed of a read operation. One disclosed electronic device includes a semiconductor memory unit which, in one implementation, in addition to two variable resistance elements, further includes a bit line and a bit line bar formed at a metal level; a first word line formed at a transistor level lower than the metal level, and extended in a direction perpendicular to the bit line or the bit line bar; a first selecting element formed at the transistor level and coupled to the bit line and the first word line; a second selecting element formed at the transistor level and coupled to the bit line bar and the first word line. | 2015-10-15 |
20150294703 | METHOD AND SYSTEM FOR PROVIDING A THERMALLY ASSISTED SPIN TRANSFER TORQUE MAGNETIC DEVICE INCLUDING SMART THERMAL BARRIERS - A magnetic device usable in electronic devices is described. The magnetic device includes a magnetic junction and at least one smart thermal barrier that is thermally coupled with the magnetic junction. The magnetic junction includes at least one reference layer, at least one nonmagnetic spacer layer and a free layer. The nonmagnetic spacer layer(s) are between the reference layer(s) and the free layer. The free layer is switchable between stable magnetic states when a write current passed through the magnetic junction. The smart thermal barrier has a low heat conductance below a transition temperature range, and a high heat conductance above the transition temperature range. | 2015-10-15 |
20150294704 | ELECTRONIC DEVICE - Provided is an electronic device including a semiconductor memory unit. The semiconductor memory unit may include one or more storage cells for storing data, and each of the storage cells includes: a first resistance variable element having a first resistance value when a first value is stored therein, and having a second resistance value when a second value is stored therein; and a second resistance variable element having the second resistance value when the first value is stored therein, and having the first resistance value when the second value is stored therein. | 2015-10-15 |
20150294705 | ELECTRONIC DEVICE - A semiconductor memory unit includes first to N | 2015-10-15 |
20150294706 | Offset-Cancelling Self-Reference STT-MRAM Sense Amplifier - Embodiments are directed to a self-reference STT-MRAM sensing scheme that uses offset-cancellation to reduce the impact of FET mismatch and thereby allow the sensing of lower read voltages. In some embodiments, the sensing scheme includes a differential amplifier having a first input connected to a memory cell. In some embodiments, a second input of the differential amplifier may be connected to ground, a common mode voltage of the system or a mid-level supply voltage. The present disclosure provides flexibility with respect to the voltage level at which the sensing is performed (e.g., ground, Voc, Vmid, etc.). The present disclosure provides further flexibility with respect to the sense voltage polarity. | 2015-10-15 |
20150294707 | METHOD AND SYSTEM FOR PROVIDING THERMALLY ASSISTED MAGNETIC JUNCTIONS HAVING A MULTI-PHASE OPERATION - A magnetic junction usable in magnetic devices is described. The magnetic junction includes at least one reference layer, at least one nonmagnetic spacer layer and a free layer. The nonmagnetic spacer layer(s) are between the reference layer(s) and the free layer. The free layer has a magnetic thermal stability coefficient having a plurality of magnetic thermal stability coefficient phases. A first phase magnetic thermal stability coefficient has a first slope below a first temperature. A second phase magnetic thermal stability coefficient has a second slope above the first temperature and below a second temperature greater than the first temperature. The first and second slopes are unequal at the first temperature. The magnetic thermal stability coefficient is zero only above the second temperature. The free layer is switchable between stable magnetic states when a write current passed through the magnetic junction. | 2015-10-15 |
20150294708 | MULTIBIT SELF-REFERENCE THERMALLY ASSISTED MRAM - A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier. | 2015-10-15 |
20150294709 | SENSOR READ/WRITE CIRCUIT AND METHOD - A sensor read/write circuit having a sensor, an integrator, a pulse generator, at least a first and second memory device, and a counter. The sensor senses a parameter and produces a sensor output representative of the sensed parameter. The sensor output is provided to the integrator which produces an integrated output representative of the sensed parameter. The integrated output triggers the pulse generator to produce a pulse which causes the first memory device to be written. The above sequence is repeated whereby a new sensor reading is generated and a second pulse causes the second memory device to be written but only if the first memory device has been substantially completely written, the first memory device has been subsequently disabled and the second memory device has been enabled. | 2015-10-15 |
20150294710 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE - Provided is a memory device with a reduced layout area. The memory device includes a sense amplifier electrically connected to first and second wirings and positioned in a first layer, and first and second circuits positioned in a second layer over the first layer. The first circuit includes a first switch being turned on and off in accordance with a potential of a third wiring, and a first capacitor electrically connected to the first wiring via the first switch. The second circuit includes a second switch being turned on and off in accordance with a potential of a fourth wiring, and a second capacitor electrically connected to the second wiring via the second switch. The first wiring intersects the third wiring and does not intersect the fourth wiring in the second layer. The second wiring intersects the fourth wiring and does not intersect the third wiring in the second layer. | 2015-10-15 |
20150294711 | PERFORMING REFRESH OF A MEMORY DEVICE IN RESPONSE TO ACCESS OF DATA - An access of data in a memory device is sampled. In response to the sampled access of data, a refresh operation is performed in the memory device. | 2015-10-15 |
20150294712 | PRINTED CIRCUIT BOARD AND PRINTED WIRING BOARD - A first reception circuit and a second reception circuit are mounted on a printed circuit board, and receive signals via wiring thereof from a transmission circuit. The printed wiring board includes a trunk wiring, a first branched line branching from a first branch connection point, and a second branched line branching from a second branch connection point in order. A wiring area between the start end and the first branch connection point is divided into a first wiring portion and a second wiring portion, in order from the start end, and a wiring area between the first branch connection point and the second branch connection point is a third wiring portion. The characteristic impedance of the first wiring portion is set to equal or lower than the characteristic impedance of the third wiring portion, and the characteristic impedance of the second wiring portion is set higher than the characteristic impedance of the first wiring portion. | 2015-10-15 |
20150294713 | STATIC RANDOM ACCESS MEMORY DEVICES - The present application relates to an improved static random access memory (SRAM) device having a plurality of storage cells and a separate read/write circuit. Each of the plurality of storage cells is connected to a read/write data node of the read/write circuit by a dedicated connection, and an access switch which permits read/write access to the storage cell. The dedicated connection exhibits a greater capacitance than the read/write data node of the read/write circuit, such that the primary read mechanism of the SRAM is charge equalisation. The SRAM write data connection to the read/write node of the read/write circuit, to permit data to be written to the plurality of storage cells. Write assist techniques are disclosed which assist writing of a ‘1’ to the plurality of storage cells. | 2015-10-15 |
20150294714 | LOW-POWER SRAM CELLS - The present invention provides a memory unit ( | 2015-10-15 |
20150294715 | PRE-CHARGING A DATA LINE - A circuit includes a signal generating circuit that generates a pre-charge signal based on a clock signal and a column select signal for a column of memory cells associated with the signal generating circuit. A first state of the pre-charge signal depends on a first state of the column select signal, and the first state of the column select signal corresponds to selection of the column of memory cells. The circuit also includes a charge circuit associated with the signal generating circuit and a first data line coupled to the charge circuit. The charge circuit charges the first data line in response to the first state of the pre-charge signal and allows the first data line to float in response to a second state of the pre-charge signal. | 2015-10-15 |
20150294716 | APPARATUSES AND METHODS OF READING MEMORY CELLS - The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse. | 2015-10-15 |
20150294717 | APPARATUSES, SENSE CIRCUITS, AND METHODS FOR COMPENSATING FOR A WORDLINE VOLTAGE INCREASE - Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit. | 2015-10-15 |
20150294718 | DRIFT ACCELERATION IN RESISTANCE VARIABLE MEMORY - The present disclosure includes apparatuses and methods including drift acceleration in resistance variable memory. A number of embodiments include applying a programming signal to the resistance variable memory cell to program the cell to a target state, subsequently applying a pre-read signal to the resistance variable memory cell to accelerate a drift of a resistance of the programmed cell, and subsequently applying a read signal to the resistance variable memory cell. | 2015-10-15 |
20150294719 | NON-VOLATILE MEMORY SYSTEM WITH RESET VERIFICATION MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state. | 2015-10-15 |
20150294720 | STORAGE DEVICE WITH 2D CONFIGURATION OF PHASE CHANGE MEMORY INTEGRATED CIRCUITS - A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels. | 2015-10-15 |
20150294721 | Memory Card - A memory card is provided comprising a plurality of electrical contacts, a controller, and a memory, where a housing encloses the controller and the memory and exposes the plurality of electrical contacts. In one embodiment, the memory card further comprises an extendible gripping portion movable between first and second positions, wherein the extendible gripping portion is more exposed from the housing in the second position than in the first position. In another embodiment, the end of the housing forms a notch shaped to mate with a mating removal tool. In yet another embodiment, the length of the memory card is less than about 32 mm and the width of the memory card is about 24 mm, and the memory card has a fingernail grip on the housing. Other embodiments are possible, and each of the embodiments can be used alone or together in combination. | 2015-10-15 |
20150294722 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group. | 2015-10-15 |
20150294723 | NONVOLATILE MEMORY SYSTEM, METHOD OF OPERATING THE SAME AND METHOD OF MANUFACTURING THE SAME - An operating method of a nonvolatile memory system including first and second. areas is provided. Data stored in the first area is migrated to the second area when a first booting operation is performed. The data stored in the second area is reprogrammed. The first booting operation is a booting operation performed when the nonvolatile memory system is first powered on after mounted on a printed circuit board. The reprogramming is a program operation performed on the data stored in the second area without performing an erasing operation on the data stored in the second area. | 2015-10-15 |
20150294724 | MEMORY DEVICES AND METHODS OF OPERATING THE SAME - According to example embodiments, a memory device includes a memory cell array, a controller including a normal program controller and a dummy program controller, and a driver. The memory cell array includes a first memory block on a substrate. The first memory block includes a plurality of cell strings on the substrate extending in a vertical direction. The normal program controller is configured to generate a first control signal for programming normal cells of a selected cell string that is selected based on an address received by the controller. The dummy program controller is configured to generate a second control signal for programming at least one dummy cell included in each of the plurality of cell strings before generation of the first control signal. The driver is configured to apply a first operation voltage set for programming the normal cells of the selected cell string to the first memory block in response to the first controller signal. The driver is configured to apply a second operation voltage set for programming the at least one dummy cell to the first memory block in response to the second control signal. | 2015-10-15 |
20150294725 | MEMORY SYSTEM, METHOD OF PROGRAMMING THE MEMORY SYSTEM, AND METHOD OF TESTING THE MEMORY SYSTEM - A method of programming a memory system includes repetitively performing N program loops for a selected memory cell (where N is a natural number equal to or greater than two). Each of the N program loops includes a program operation and a program verify operation. At least one of the N program loops includes performing the program operation on the selected memory cell and on at least one additionally selected memory cell by applying a program voltage to at least one word line to which the selected memory cell and at least one additionally selected memory cell are connected, and performing the program verify operation on the selected memory cell by applying a program verify voltage to a selected word line to which the selected memory cell is connected. | 2015-10-15 |
20150294726 | NAND-TYPE FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A NAND-type flash memory device and method for programming the NAND-type flash memory device are provided. The method may include applying a voltage of 0 V to an unselected string select line, applying the voltage of 0 V to a selected bit line, applying a supply voltage to a selected string select line, and applying a dummy pass voltage to a dummy word line, the dummy pass voltage being in a range between 0 V to a pass voltage. The method may further include applying the supply voltage to an unselected bit line, applying the pass voltage to a selected word line, applying the pass voltage to an unselected word line; and applying a program voltage to the selected word line. | 2015-10-15 |
20150294727 | SENSING MEMORY CELLS COUPLED TO DIFFERENT ACCESS LINES IN DIFFERENT BLOCKS OF MEMORY CELLS - In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the memory device are sensed concurrently while a read voltage is applied to a selected access line coupled to the target memory cell in the first block of memory cells and while a read voltage is applied to another selected access line coupled to the target memory cell in the second block of memory cells. | 2015-10-15 |
20150294728 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations. | 2015-10-15 |
20150294729 | COMPENSATING FOR OFF-CURRENT IN A MEMORY - A memory cell is accessed by determining an off-current of a set of memory cells, accessing a memory cell of the set of memory cells during an access period, and compensating for the off-current of the set of memory cells. | 2015-10-15 |
20150294730 | METHOD OF SHAPING A STROBE SIGNAL, A DATA STORAGE SYSTEM AND STROBE SIGNAL SHAPING DEVICE - A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal. | 2015-10-15 |
20150294731 | Method to Reduce Program Disturbs in Non-Volatile Memory Cells - A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V | 2015-10-15 |
20150294732 | Circuit and System of Using Junction Diode as Program Selector for One-Time Programmable Devices with Heat Sink - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, metal-0, thermally isolated active region, CMOS gate, or combination thereof. | 2015-10-15 |
20150294733 | SHIFT REGISTER CELL, SHIFT REGISTER, GATE DRIVER AND DISPLAY PANEL - A shift register cell comprising a first drive signal input terminal, a first drive signal output terminal, a first clock signal input terminal, a first pull-up transistor, a first output pull-down transistor, a switch transistor, a reset transistor and a bootstrap capacitor, wherein the shift register cell further comprises a pull-down unit, wherein a first terminal of the pull-down unit is connected with a gate of the switch transistor, a second terminal of the pull-down unit is connected with a gate of the reset transistor, a third terminal of the pull-down unit is connected with a gate of the first output pull-down transistor, a source of the reset transistor is connected with a second low level input terminal, and a source of the first output pull-down transistor is connected with a third low level input terminal. Depletion type transistors may be applied to above shift register cell. | 2015-10-15 |
20150294734 | GATE DRIVER AND SHIFT REGISTER - A gate driver has a plurality of shift registers. Each of the shift registers has at least three input terminals, two signal input terminals, a pull-up circuit, a driving circuit, a stability pull-down control circuit, and a stability pull-down circuit. The three input terminals of each shift register receive three different clock signals. Accordingly, the driving circuit and the stability pull-down control circuit of each shift register are controlled according to the three clock signals, such that a glitch causing by the coupling effect of the parasitic capacitor of the driving circuit is avoided and the stability of the gate driver is improved. | 2015-10-15 |
20150294735 | UNIT TESTING OF DATA STORAGE DEVICES AT A DATA CENTER - A plurality of data storage devices from a storage device provider are received, at a data center. A tester is received at the data center via the storage device provider. A unit test of the data storage devices is performed at the data center via the tester contemporaneously with using the data storage devices in the data center. | 2015-10-15 |
20150294736 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - A semiconductor device includes a nonvolatile memory block suitable for outputting data stored in a plurality of nonvolatile memory cells included therein based on first control information, and programming data in the nonvolatile memory cells based on second control information; a control block suitable for generating the first control information based on an initialization signal, wherein the control block sequentially generates the second control information and the first control information when a program mode is activated; and a test control block suitable for deactivating the nonvolatile memory block and determining whether at least one control signal among a plurality of control signals included in the first and second control information is normally generated, in a test operation on the program mode. | 2015-10-15 |
20150294737 | METHOD AND APPARATUS FOR PROVIDING PRELOADED NON-VOLATILE MEMORY CONTENT - An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test system and responsive to at least completion of testing and passing the testing, loading non-testing content into the memory unit for delivery to a customer. | 2015-10-15 |
20150294738 | TEST STRUCTURE AND METHOD OF TESTING A MICROCHIP - A tristate inverter array test structure and method of testing structures in a microchip are disclosed. The structure includes: a PFET stack in series with an NFET stack; an inverted wordline driving a PFET of the PFET stack; a worldline driving an NFET of the NFET stack; a data_in line connecting to an input of the PFET stack and the NFET stack; and a data_out line connecting to an output of the PFET stack and the NFET stack. | 2015-10-15 |
20150294739 | ONLINE HISTOGRAM AND SOFT INFORMATION LEARNING - A system includes a processor configured to read information from a plurality of memory cells. The processor initiates a first read of raw data from a group of memory cells using a first reference voltage. The processor also initiates a second read of raw data from the group of memory cells using a second reference voltage different from the first reference voltage. The processor further compares the first read to the second read to identify memory cells read with a bit value that changes between the first and second reads. The processor also assigns the memory cells read with a bit value that changes between the first and second reads to a region associated with the second reference voltage. The processor further counts the number of cells read with a bit value that changes to generate a histogram corresponding to soft information for the group of memory cells. | 2015-10-15 |
20150294740 | MEMORY DEVICE AND OPERATION METHOD THEREOF - A memory device includes a memory array, a test circuit suitable for detecting a first repair address corresponding to a defective cell in the memory array, in a test mode, an external input circuit suitable for receiving a second repair address from an exterior, in response to an address input command, in an external input mode, and a nonvolatile memory circuit suitable for programming the first repair address in a first region in response to a first program command in the test mode, and programming the second repair address in a second region in response to a second program command in the external input mode, wherein the first repair address is programmed in the second region in response to the second program command while the address input command is deactivated in the external input mode. | 2015-10-15 |
20150294741 | METHOD AND APPARATUS FOR DEFECT REPAIR IN NAND MEMORY DEVICE - System and method of selecting defective columns in NAND memory devices for repair. After locating the defective blocks and defective columns in a NAND memory device, a weight value is calculated for each defective block by dividing a total number of defective blocks that would be inherently repaired as a result of repairing the respective defective block by a number of defective data columns in the respective defective block. A defective block with the greatest weight value is selected for repair in which the defective columns in the selected block are substituted by redundant columns. Other defective blocks with defective columns having the same column addresses with the defective columns in the selected defective block are automatically selected for repair as well. Remaining defective columns are selected for repair by iteratively updating weight values and selecting a defective block that has the greatest weight value among the remaining defective blocks. | 2015-10-15 |