42nd week of 2009 patent applcation highlights part 35 |
Patent application number | Title | Published |
20090258426 | Preferred segments of neural thread protein and method of using the same - The invention is directed to preferred repeat sequences of Neural Thread Protein (NTP), peptides, mimetics, antibodies, and nucleic acids of the preferred sequences, and diagnostic and therapeutic methods of using such preferred NTP sequences. | 2009-10-15 |
20090258427 | Method and Reagent Mixture for the Visualization of Amino Acids and Peptides - The invention relates to a method and reagent mixture for the staining and thus visualisation of amino acids, peptides and similar compounds, in particular after separation by means of thin-layer chromatography. The staining is carried out using NIN-HYDRIN for the detection of amino acids, peptides or proteins in combination with at least one ionic liquid. | 2009-10-15 |
20090258428 | METHOD FOR ANALYZING LOW MOLECULAR WEIGHT COMPOUND IN SAMPLE CONTAINING WATER-SOLUBLE POLYMER AND LOW MOLECULAR WEIGHT COMPOUND - The invention relates to an analysis method which can conduct analysis on low molecular weight compound in a sample containing water-soluble polymer and low molecular weight compound under isocratic conditions without being affected by proteins or the like and in which water-soluble polymer and low molecular weight compound can be separated efficiently and to a column for such an analysis by high performance liquid chromatography, packed with a packing material comprising a crosslinked organic polymer compound obtained by polymerizing glycerin dimethacrylate at 90 mass % or more as starting material, having the exclusion limit molecular weight measured with pullulan of 30000 or less but 3000 or more and having a mass average particle diameter of 0.1 to 100 μm. | 2009-10-15 |
20090258429 | Colorimetric detection of cyanide with a chromogenic oxazine - A chromogenic oxazine compound for the colorimetric detection of cyanide was designed. Indeed, the [1,3]oxazine ring of our compound opens to form a phenolate chromophore in response to cyanide. The heterocyclic com-pound may be comprised of fused benzooxazine and indoline rings: | 2009-10-15 |
20090258430 | Method for identifying electrophiles and nucleophiles in a sample - A method and device for identifying a molecule in a sample, the molecule comprising an electrophilic or nucleophilic moiety. The method comprises contacting the sample with a plurality of chemosensors, each of the chemosensors comprising a π-conjugated system and a moiety having a nucleophilic property or an electrophilic property; and measuring an electromagnetic property of each of the chemosensors in the sample; whereby the pattern of changes in the electromagnetic properties of the plurality of chemosensors after chemically reacting with the electrophile or nucleophile of the molecule identifies the molecule in said sample. The device comprises a substrate carrying a plurality of chemosensor molecules having at least one predetermined electromagnetic property, the at least one electromagnetic property being changeable by subjecting the chemosensor molecules to a sample containing at least one electrophile or nuclephile, wherein the pattern of change of the electromagnetic property of the plurality of chemosensor molecules allows the device to identify the electrophile or nuclephile in the sample. | 2009-10-15 |
20090258431 | DEVICE AND METHOD FOR PRESSURE AND FLOW CONTROL IN PARALLEL REACTORS - The present invention relates to a method and a device for the parallel study of chemical reactions in at least two spatially separated reaction spaces. In particular, the invention is suitable for reactions which are not constant volume reactions and/or for reactions in which fluid flows through at least two spatially separated reaction spaces are intended to be controlled together for all the reaction spaces, or for related subsets of them, in the most straightforward way possible. | 2009-10-15 |
20090258432 | Composition and Method - A fire-stop product comprising a characterising marker, wherein the presence of said characterising marker can be detected by a diagnostic method at the site where the product is located. | 2009-10-15 |
20090258433 | ABNORMALITY-IDENTIFYING METHOD AND ANALYZER - Provided is an abnormality-identifying method for identifying an abnormality of an analyzer which analyzes a specimen based on optical characteristics. All predetermined analysis processes to be performed on the specimen but an analysis process whose abnormality is to be examined are eliminated, and the abnormality of the analyzer is identified based on a measurement result which is obtained through the analysis process whose abnormality is to be examined and a reaction process in which a substance whose abnormality is to be identified or a predetermined reagent is reacted with a predetermined reactant. | 2009-10-15 |
20090258434 | FLUORESCENT PROBE FOR PEROXYNITRITE - A compound represented by the following general formula (I): | 2009-10-15 |
20090258435 | BIOTIN-RECEPTOR REAGENTS FOR SENSITIVITY MODULATION IN ASSAYS - Methods are disclosed for designing an antibody reagent for use in an assay for the detection of an analyte to obtain an optimum assay sensitivity and/or dynamic range. The antibody reagent is a conjugate of a small molecule attached by a spacer group to an antibody for the analyte. The method comprises controlling, in the preparation of the conjugate, reaction parameters comprising the hydrophobicity or hydrophilicity of the spacer group, the length of the spacer group, the number of molecules of the small molecule attached to the antibody and the point of attachment of the small molecule to the antibody to obtain an optimum assay sensitivity and/or dynamic range. In some embodiments the method comprises preparing two or more conjugates by selecting a set of parameters for each conjugate wherein the set of parameters is different for each conjugate, conducting an assay for the analyte employing each conjugate and selecting for use in the assay the conjugate that provides the optimum assay sensitivity and/or dynamic range. | 2009-10-15 |
20090258436 | Reagents for the Detection of Protein Phosphorylation in Signaling Pathways - The invention discloses novel phosphorylation sites identified in signal transduction proteins and pathways, and provides phosphorylation-site specific antibodies and heavy-isotope labeled peptides (AQUA peptides) for the selective detection and quantification of these phosphorylated sites/proteins, as well as methods of using the reagents for such purpose. Among the phosphorylation sites identified are sites occurring in the following protein types: adaptor/scaffold proteins, adhesion/extracellular matrix protein, apoptosis proteins, calcium binding proteins, cell cycle regulation proteins, chaperone proteins, chromatin, DNA binding/repair/replication proteins, cytoskeletal proteins, endoplasmic reticulum or golgi proteins, enzyme proteins, G/regulator proteins, inhibitor proteins, motor/contractile proteins, phosphatase, protease, Ser/Thr protein kinases, Protein kinase (Tyr)s, receptor/channel/cell surface proteins, RNA binding proteins, transcriptional regulators, tumor suppressor proteins, ubiquitan conjugating system proteins and proteins of unknown function. | 2009-10-15 |
20090258437 | COMPOUNDS AND METHODS FOR RAPID LABELING OF N-GLYCANS - The present invention provides compounds and methods for rapid labeling of N-glycans, for example, rapid fluorescent labeling of N-glycans. In one aspect, the present invention provides fluorescent carbamate or thiocarbamate compounds. Upon contacting with N-glycans, the compounds undergo facile reactions with N-glycans to form fluorescent-labeled N-glycans. | 2009-10-15 |
20090258438 | Method for universal biodetection of antigens and biomolecules - A universal signal molecule is generated in response to the presence within a biological fluid sample of a target agent. Two probes that bind to the target agent are provided within the sample and the target agent is captured, purified, and concentrated on a bead. One of the probes is attached to a signal nucleic acid that does not bind to the target agent. The signal nucleic acid is caused to be released from the probe, thereby generating a universal signal molecule. The presence of the universal signal molecule in the sample is detected, thereby providing for detection of the target agent within the sample. | 2009-10-15 |
20090258439 | IMMUNOCHROMATOASSAY METHOD AND IMMUNOCHROMATOASSAY KIT - An immunochromatoassay method that allows high detection sensitivity measurement. The method including the steps of: permeating an analyte solution that includes a visibly labeled second binding substance that specifically binds to a detection target substance into a test area of a chromatography medium provided with a first binding substance that specifically binds to the detection target substance, simultaneously with or after the permeation of the analyte solution into the test area, permeating a visual recognition aid solution into the chromatograph medium, the solution having a refractive index whose refractive index difference Δn from that of the chromatograph medium is −0.1=Δn=0.1, and visually observing the test area while the visual recognition aid solution is permeated in the test area. | 2009-10-15 |
20090258440 | SURFACE FOR LABEL INDEPENDENT DETECTION AND METHOD THEREOF - A functional group and spacer group modified polymer composition, articles incorporating the composition, and methods for label-independent-detection using the articles, as defined herein. | 2009-10-15 |
20090258441 | METHOD OF PROVIDING PARTICLES HAVING BIOLOGICAL-BINDING AREAS FOR BIOLOGICAL APPLICATIONS - The present invention includes micro-sphere composition, methods of making binding assays. The present invention also includes a micro-sphere for binding biological molecules without pretreatment. The micro-sphere includes a spherical glass substrate having one or more metal nanoparticle regions that are exposed from within the glass, wherein the micro-sphere is capable of binding biological molecules without pretreatment. | 2009-10-15 |
20090258442 | Reagents for the detection of protein phosphorylation in carcinoma signaling pathways - The invention discloses nearly 474 novel phosphorylation sites identified in signal transduction proteins and pathways underlying human carcinoma, and provides phosphorylation-site specific antibodies and heavy-isotope labeled peptides (AQUA peptides) for the selective detection and quantification of these phosphorylated sites/proteins, as well as methods of using the reagents for such purpose. Among the phosphorylation sites identified are sites occurring in the following protein types: Kinase, Adaptor/Scaffold proteins, Phosphatase, G protein Regulator/Guanine Nucleotide Exchange Factors/GTPase Activating Proteins, Cytoskeleton Proteins, DNA Binding Proteins, Phospholipase, Receptor Proteins, Enzymes, DNA Repair/Replication Proteins, Adhesion Proteins, and Proteases, as well as other protein types. | 2009-10-15 |
20090258443 | Nonvolatile memory devices and methods of fabricating the same - Nonvolatile memory devices and methods of fabricating the same are provided. In some embodiments, a nonvolatile memory device includes a lower conductive member formed on an upper part of or inside a substrate, a ferroelectric organic layer formed on the lower conductive member, a protective layer formed on the ferroelectric organic layer, and an upper conductive member formed on the protective layer to cross the lower conductive member. | 2009-10-15 |
20090258444 | APPARATUS AND METHODS FOR MANUFACTURING THIN-FILM SOLAR CELLS - Improved methods and apparatus for forming thin-film layers of semiconductor material absorber layers on a substrate web. According to the present teachings, a semiconductor layer may be formed in a multi-zone process whereby various layers are deposited sequentially onto a moving substrate web. | 2009-10-15 |
20090258445 | MULTI-VARIABLE REGRESSION FOR METROLOGY - A method for assessing metrology tool accuracy is described. Multi-variable regression is used to define the accuracy of a metrology tool such that the interaction between different measurement parameters is taken into account. A metrology tool under test (MTUT) and a reference metrology tool (RMT) are used to measure a set of test profiles. The MTUT measures the test profiles to generate a MTUT data set for a first measurement parameter. The RMT measures the test profiles to generate RMT data sets for the first measurement parameter, and at least a second measurement parameter. Multi-variable regression is then performed to generate a best-fit plane for the data sets. The coefficient of determination (R | 2009-10-15 |
20090258446 | PATTERN VERIFICATION METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIA - A pattern verification method according to an embodiment includes, dividing a pattern data region or a pattern formation region formed based on the pattern data to a plurality of unit regions, calculating a pattern area ratio with respect to each unit region, calculating differences in the amount of the pattern area ratio between each unit region and adjacent unit regions thereto, setting the number or density of measurement point with respect to each unit region to the pattern of the pattern data region or the pattern formation region according to the difference in the amount of pattern area ratio, measuring the pattern size at each measurement point, and verifying whether the size measurement value is within a predetermined range or not. | 2009-10-15 |
20090258447 | METHOD OF DETECTING HEAVY METAL IN SEMICONDUCTOR SUBSTRATE - A method of detecting heavy metal in a semiconductor substrate, includes: a gate oxide film forming step of forming an organic oxide film by spin coating or a sol-gel process, and forming a metal/oxide film/semiconductor junction element by using a mercury probe method; and a step of detecting and quantifying heavy metal by calculating the surface concentration of the heavy metal from junction capacitance characteristics of the element. | 2009-10-15 |
20090258448 | Method for making thermal electron emitter - A method for making the thermal electron emitter includes following steps. Providing a carbon nanotube film including a plurality of carbon nanotubes. Treating the carbon nanotube film with a solution comprising of a solvent and compound or a precursor of a compound, wherein the compound and the compound that is the basis of the precursor of a compound has a work function that is lower than the carbon nanotubes. Twisting the treated carbon nanotube film to form a carbon nanotube twisted wire. Drying the carbon nanotube twisted wire. Activating the carbon nanotube twisted wire. | 2009-10-15 |
20090258449 | FABRICATING METHOD OF LIGHT EMITTING DIODE PACKAGE - A method of fabricating a light emitting diode package structure is provided. First, a first circuit substrate having a first surface and a corresponding second surface and a second circuit substrate having a third surface and a corresponding fourth surface are provided. The second surface and the third surface respectively have a plurality of electrodes. Then, a plurality of N-type semiconductor materials and a plurality of P-type semiconductor materials alternatively arranged on the electrodes are formed. Then, the first circuit substrate and the second circuit substrate are assembled. The two type semiconductor materials are located between the electrodes of the first circuit substrate and the second circuit substrate. The two type semiconductor materials are electrically connected to the first circuit substrate and the second circuit substrate through the electrodes. Finally, an LED chip is arranged on the first surface and electrically connected to the first circuit substrate. | 2009-10-15 |
20090258450 | METHOD FOR MANUFACTURING WIRING, THIN FILM TRANSISTOR, LIGHT EMITTING DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE, AND DROPLET DISCHARGE APPARATUS FOR FORMING THE SAME - As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO | 2009-10-15 |
20090258451 | Liquid crystal display device - An LCD device is disclosed in which column spacers for a cell gap are arranged between gate and common lines to reduce a contact area between the column spacers and an opposing substrate, and a stable cell gap is maintained over the whole panel by reducing variation of a thickness per area of a thin film transistor (TFT) substrate corresponding to the column spacers. The LCD device includes first and second substrates facing each other, gate and data lines formed on the first substrate to cross each other, and pixel regions, a thin film transistor formed in each portion where the gate and data lines cross, common and pixel electrodes alternately formed in the pixel regions, common lines formed adjacent to the gate lines substantially parallel to the gate lines, a first column spacer formed on the second substrate corresponding to a portion between the gate line and the common line, and a liquid crystal layer filled between the first and second substrates. | 2009-10-15 |
20090258452 | METHOD FOR FORMING QUANTUM WELL STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT - A method for forming a quantum well structure that can reduce the variation in the In composition in the thickness direction of a well layer and a method for manufacturing a semiconductor light emitting element are provided. In a step of forming a quantum well structure (active layer) by alternately growing barrier layers and well layers on a primary surface of a GaN substrate, the well layers are each formed by growing InGaN, the barrier layers are each grown at a first temperature, the well layers are each grown at a second temperature which is lower than that of the first temperature, and when the well layers are each formed, before a starting material gas for Ga (trimethylgallium) is supplied, a starting material gas for In is supplied. | 2009-10-15 |
20090258453 | METHOD FABRICATING NITRIDE-BASED COMPOUND LAYER, GaN SUBSTRATE AND VERTICAL STRUCTURE NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE - In a method for fabricating a nitride-based compound layer, first, a GaN substrate is prepared. A mask layer with a predetermined pattern is formed on the GaN substrate to expose a partial area of the GaN substrate. Then a buffer layer is formed on the partially exposed GaN substrate. The buffer layer is made of a material having a 10% or less lattice mismatch with GaN. Thereafter, the nitride-based compound is grown laterally from a top surface of the buffer layer toward a top surface of the mask layer and the nitride-based compound layer is vertically grown to a predetermined thickness. Also, the mask layer and the buffer layer are removed via wet-etching to separate the nitride-based compound layer from the GaN substrate. | 2009-10-15 |
20090258454 | METHOD OF MANUFACTURING GALLIUM NITRIDE BASED LIGHT EMITTING DIODE HAVING SURFACE IRREGULARITIES - An n-type GaN layer is formed on a substrate, and an active layer is formed on the n-type GaN layer. A p-type GaN layer is formed on the active layer, and portions of the p-type GaN layer and the active layer are mesa-etched so as to expose a portion of the n-type GaN layer. An irregularities forming layer is formed on the p-type GaN layer and a photosensitive film pattern for forming a surface irregularities pattern is formed on the irregularities forming layer. The irregularities forming layer is selectively wet-etched by using the photosensitive film pattern as an etching mask, thereby forming surface irregularities. A p-electrode is formed on the p-type GaN layer having the surface irregularities formed thereon, and an n-electrode is formed on the exposed n-type GaN layer.” | 2009-10-15 |
20090258455 | METHOD OF MINIMIZING BEAM BENDING OF MEMS DEVICE BY REDUCING THE INTERFACIAL BONDING STRENGTH BETWEEN SACRIFICIAL LAYER AND MEMS STRUCTURE - The beam bending of a MEMS device is minimized by reducing interfacial strength between a sacrificial layer and a MEMS structure. | 2009-10-15 |
20090258456 | Method for manufacturing a solid-state image capturing apparatus, and electronic information device - A method for manufacturing a solid-state image capturing apparatus including a pixel array constituted of a plurality of pixels, is provided, where each of the plurality of pixels includes a photoelectric conversion section, the method comprising the steps of: forming an impurity diffusion area in a surface area of a semiconductor substrate; and forming a plurality of different impurity diffusion areas in the surface area of the semiconductor substrate, other than the impurity diffusion area constituting the photoelectric conversion section. | 2009-10-15 |
20090258457 | BUFFER LAYER DEPOSITION FOR THIN-FILM SOLAR CELLS - Improved methods and apparatus for forming thin-film buffer layers of chalcogenide on a substrate web. Solutions containing the reactants for the buffer layer or layers may be dispensed separately to the substrate web, rather than being mixed prior to their application. The web and/or the dispensed solutions may be heated by a plurality of heating elements. | 2009-10-15 |
20090258458 | DFN semiconductor package having reduced electrical resistance - A dual flat non-leaded semiconductor package is disclosed. A method of making a dual flat non-leaded semiconductor package includes forming a leadframe having a die bonding area with an integral drain lead, a gate lead bonding area and a source lead bonding area, the gate lead bonding area and a source lead bonding area being of increased area; bonding a die to the die bonding area; coupling a die source bonding area to the source lead bonding area; coupling a die gate bonding area to the gate lead bonding area; and partially encapsulating the die, the drain lead, the gate lead and the source lead to form the dual flat non-leaded semiconductor package. | 2009-10-15 |
20090258459 | Packaged System of Semiconductor Chips Having a Semiconductor Interposer - A semiconductor system ( | 2009-10-15 |
20090258460 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes a film state underfill resin adhering step wherein film state underfill resin in a semi-cured state is adhered on the first surface of the board main body without forming a gap between the first surface of the board main body and the pad; a flattening step wherein an upper surface of the film state underfill resin is flattened; a chip connecting step wherein the semiconductor chip is pressed onto the upper surface of the film state underfill resin after the flattening step so that the semiconductor chip is flip chip connected to the pad; and an underfill resin forming step wherein the film state underfill resin is cured so that the underfill resin is formed between the semiconductor chip and the wiring board. | 2009-10-15 |
20090258461 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device, includes: mounting a semiconductor chip having an electrode on a wiring substrate having a base substrate and a wiring formed on the base substrate; forming a eutectic alloy by contacting the wiring with the electrode and by heating and pressurizing, and; forming the eutectic alloy so as a part of the eutectic alloy enters between the wiring and the base substrate. | 2009-10-15 |
20090258462 | METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS - The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells. | 2009-10-15 |
20090258463 | METHODS OF FABRICATING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS ON SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES FABRICATED THEREBY - Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas. | 2009-10-15 |
20090258464 | METHODS FOR MANUFACTURING A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR USING A HYBRID ORIENTATION TECHNOLOGY WAFER - Methods for manufacturing a high voltage junction field effect transistor. The method includes forming an opening extending from a top surface of a device layer of a hybrid orientation technology (HOT) wafer through the device layer and an insulating layer to expose a portion of a bulk layer, and filling the opening with epitaxial semiconductor material having the crystalline orientation of the bulk layer. The method further includes forming first and second p-n junctions in the epitaxial semiconductor material that are arranged in depth within the epitaxial semiconductor material between the second semiconductor layer and the top surface of the first semiconductor layer. | 2009-10-15 |
20090258465 | MASK FOR SILICON CRYSTALLIZATION, METHOD OF FORMING POLY-SILICON THIN FILM, AND MANUFACTURING METHOD OF THIN FILM TRANSISTOR - A silicon crystallization mask of the present invention includes; a main exposure portion including a plurality of complete light transmission regions which completely transmit light therethrough, and a preliminary exposure portion including a plurality of incomplete light transmission regions, which each partially transmit light therethrough, wherein at least two of the incomplete light transmission regions have different magnitudes of light transmittance from each other. | 2009-10-15 |
20090258466 | Nonvolatile Memory Device and Method for Fabricating the Same - A nonvolatile (e.g., flash) memory device includes a substrate having a plurality of isolation areas and active areas; a trench formed on the isolation area; a first electrode layer formed on an inner wall of the trench; a first gate oxide layer formed between the inner wall of the trench and the first electrode layer; a junction area formed on the active area; a second gate oxide layer formed on the entire surface of the substrate including the first electrode layer, the first gate oxide layer, the trench and the junction area; a tunnel oxide layer formed on a part of the second gate oxide layer corresponding to the active area; and a second electrode layer formed on the active area and in the trench. | 2009-10-15 |
20090258467 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a vertical transistor in a semiconductor device improves integration of the semiconductor device according to a design rule. After a semiconductor substrate is etched to form a buried bit line, a gate electrode pattern that surrounds a cylindrical channel region pattern of the vertical transistor is formed, thereby preventing damage to the gate electrode pattern due to an etching process. The gate electrode pattern surrounds the channel region pattern where a width is narrower than second source and drain regions. The second source and drain regions are then deposited over the channel region pattern and the gate electrode pattern. As a result, a neck-shaped channel region does not collapse due to the weight of the second source and drain regions. | 2009-10-15 |
20090258468 | MINIMIZING TRANSISTOR VARIATIONS DUE TO SHALLOW TRENCH ISOLATION STRESS - The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor ( | 2009-10-15 |
20090258469 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a carbon-containing film having electrical conductivity is formed so as to cover a first insulating film, a discharge plug and a conductor plug. A first conductive film is formed so as to pass through the carbon-containing film and to be in contact with the conductor plug. The first conductive film is exposed by removing the carbon-containing film. | 2009-10-15 |
20090258470 | Method of Manufacturing a Semiconductor Device Using an Atomic Layer Deposition Process - Methods of manufacturing a semiconductor device include forming an absorption layer on a surface of a substrate by exposing the surface of the substrate to a first reaction gas at a first temperature. A metal oxide layer is then formed on the surface of the substrate by exposing the absorption layer to a second reaction gas at a second temperature. The first reaction gas may include a precursor containing zirconium (e.g., tetrakis(ethylmethylamino)zirconium) and the second reaction gas may include an oxidizing agent. | 2009-10-15 |
20090258471 | Application of Different Isolation Schemes for Logic and Embedded Memory - The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic. | 2009-10-15 |
20090258472 | Semiconductor array and method for manufacturing a semiconductor array - Method for manufacturing a semiconductor array, in which
| 2009-10-15 |
20090258473 | Nonvolatile memory device and method of manufacturing the same - Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner. | 2009-10-15 |
20090258474 | Method for producing SOl substrate - Provided is a method for producing an SOI substrate having a thick-film SOI layer, in which an ion-implanted layer is formed by implanting at least one kind of ion of hydrogen ion and a rare gas ion into a surface of a bond wafer, an SOI substrate having an SOI layer is produced by, after the ion-implanted surface of the bond wafer and a surface of a base wafer are bonded together via an oxide film, delaminating the bond wafer along the ion-implanted layer, heat treatment is performed on the SOI substrate having the SOI layer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, and, after the surface of the SOI layer is polished by CMP, a silicon epitaxial layer is grown on the SOI layer of the SOI substrate. | 2009-10-15 |
20090258475 | Method for producing bonded wafer - Even if an oxygen ion implanted layer in a wafer for active layer is not a completely continuous SiO | 2009-10-15 |
20090258476 | APPARATUS AND METHODS FOR MANUFACTURING THIN-FILM SOLAR CELLS - Improved methods and apparatus for forming thin-film layers of semiconductor material absorber layers on a substrate web. According to the present teachings, a semiconductor layer may be formed in a multi-zone process whereby various layers are deposited sequentially onto a moving substrate web. | 2009-10-15 |
20090258477 | METHODS OF FORMING PHASE-CHANGE MEMORY UNITS, AND METHODS OF MANUFACTURING PHASE-CHANGE MEMORY DEVICES USING THE SAME - In a method of forming a phase-change memory unit, a conductive layer is formed on a substrate having a trench. The conductive layer is planarized until the substrate is exposed to form a first electrode. A spacer partially covering the first electrode is formed. A phase-change material layer is formed on the first electrode and the second spacer. A second electrode is formed on the phase-change material layer. Reset/set currents of the phase-change memory unit may be reduced and deterioration of the phase-change material layer may be reduced and/or prevented. | 2009-10-15 |
20090258478 | METHOD FOR PROVIDING A NANOSCALE, HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) ON INSULATOR - Various embodiments include forming a silicon-germanium layer over a substrate of a device; forming a layer in the silicon-germanium layer, the layer including at least one of boron and carbon; and forming a silicon layer over the silicon-germanium layer. Additional embodiments are described. | 2009-10-15 |
20090258479 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a second insulating layer interposed therebetween. The semiconductor layer includes a channel formation region provided in a region overlapping with the gate electrode, a first impurity region for forming a source region or drain region, which is provided to be adjacent to the channel formation region, and a second impurity region provided to be adjacent to the channel formation region and the first impurity region. A conductivity type of the first impurity region is different from that of the second impurity region. | 2009-10-15 |
20090258480 | METHOD OF SELECTIVELY ADJUSTING ION IMPLANTATION DOSE ON SEMICONDUCTOR DEVICES - A first semiconductor region and a second semiconductor region separated by a shallow trench isolation region are formed in a semiconductor substrate. A photoresist is applied and patterned so that the first semiconductor region is exposed, while the second semiconductor region is covered. Depending on the setting of parameters for the location of an edge of the patterned photoresist, the slope of sidewalls of the photoresist, the thickness of the photoresist, and the direction of ion implantation, ions may, or may not, be implanted into the entirety of the surface portion of the first semiconductor region by shading or non-shading of the first semiconductor region. The semiconductor substrate may further comprise a third semiconductor region into which the dopants are implanted irrespective of the shading or non-shading of the first semiconductor region. The selection of shading or non-shading may be changed from substrate to substrate in manufacturing. | 2009-10-15 |
20090258481 | SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon. | 2009-10-15 |
20090258482 | METHOD FOR FABRICATING A METAL GATE STRUCTURE - A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process. | 2009-10-15 |
20090258483 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Embodiments relate to a method of manufacturing a semiconductor device that may simplify a manufacturing process and may reduce process costs. According to embodiments, the method may include simultaneously forming a first gate of a first device area and a second gate of a second device area, patterning a PMD layer to form a first contact hole exposing the first gate, depositing and planarizing a high dielectric constant material and first and second metallic materials on the semiconductor substrate to expose PMD layer, forming an insulating layer, a metal layer and a third gate in the first contact hole, patterning the PMD layer to form a second contact hole exposing the second gate, and depositing a third metallic material on the semiconductor substrate and planarizing it such that the PMD layer is exposed, thereby forming a contact in the second contact hole. | 2009-10-15 |
20090258484 | METHODS FOR FABRICATING DUAL MATERIAL GATE IN A SEMICONDUCTOR DEVICE - A method for fabricating dual material gate structures in a device is provided. The dual material gate structures have different gate electrode materials in different regions of the device. In one embodiment, the method includes providing a substrate having a patterned first gate electrode and a patterned first gate dielectric layer disposed on the substrate, removing a portion of the first gate electrode from the substrate to define a trench on the substrate, and filling the trench to form a second gate electrode. | 2009-10-15 |
20090258485 | Semiconductor Processing Methods - Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition. | 2009-10-15 |
20090258486 | SEMICONDUCTOR DEVICE FABRICATION METHOD - A method of forming a semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. This surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is deposited on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer having openings exposing part of the conductive pattern is formed. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The method enables the thickness of the protective layer, which may function as a package of the semiconductor device, to be reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes. | 2009-10-15 |
20090258487 | Method for Improving the Reliability of Low-k Dielectric Materials - A method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; generating hydrogen radicals using a remote plasma method; performing a first hydrogen radical treatment to the low-k dielectric layer using the hydrogen radicals; forming an opening in the low-k dielectric layer; filling the opening with a conductive material; and performing a planarization to remove excess conductive material on the low-k dielectric layer. | 2009-10-15 |
20090258488 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING STORAGE NODE LANDING PADS SEPARATED FROM BIT LINE CONTACT PLUGS - A method can include forming gate lines on a semiconductor substrate and forming a first interlayer dielectric layer for insulating the gate lines from each other. First and second contact plugs are formed on the semiconductor substrate and landing pads are formed on the first contact plugs and the first interlayer dielectric layer to overlap portions of the first contact plugs. Recessed contact plugs are formed to have recessed portions by etching the second contact plugs, to be located below an upper surface of the first interlayer dielectric layer, where a cross-sectional total distance between the landing pads and the recessed contact plugs increases due to the recessed portions. | 2009-10-15 |
20090258489 | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same - A method of making a non-volatile memory device includes forming a first electrode, forming a steering element, forming at least one feature, forming a carbon resistivity switching material on at least one sidewall of the at least one feature such that the carbon resistivity switching material electrically contacts the steering element, and forming a second electrode. | 2009-10-15 |
20090258490 | METHOD FOR FORMING CONDUCTIVE FILM - A method for forming a conductive film, includes: applying a dispersion liquid above a substrate, the dispersion liquid including a plurality of conductive fine-particles made of one conductive material selected from the group consisting of copper, nickel, and an alloy that includes copper or nickel as a main component; and forming the conductive film made from the conductive fine-particles, by heating the dispersion liquid that has been applied above the substrate in an atmosphere including formic acid, by baking the conductive fine-particles so that the conductive fine-particles are mutually fusion bonded. | 2009-10-15 |
20090258491 | Method of inhibiting background plating - Methods of inhibiting background plating on semiconductor substrates using oxidizing agents are disclosed. | 2009-10-15 |
20090258492 | MULTIPLE SPACER STEPS FOR PITCH MULTIPLICATION - Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed. | 2009-10-15 |
20090258493 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A substance to be polished made of a silicon oxide film formed on a semiconductor substrate is chemically and mechanically polished and planarized by bringing the substance to be polished into contact with a polishing pad having a modulus of elasticity within a range of 400 to 600 megapascals and by relatively sliding the substance to be polished and the polishing pad, in a condition that a polishing pressure is within a range of 50 to 200 hectopascals and that a rotation number of the polishing pad is within a range of 10 to 80 rpm, and in a state that a polishing slurry containing cerium oxide particles and an anionic surfactant is supplied to the polishing pad. | 2009-10-15 |
20090258494 | INLINE INTEGRATED CIRCUIT SYSTEM - An integrated circuit package system including: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe. | 2009-10-15 |
20090258495 | Modified darc stack for resist patterning - A method of making a device includes forming a device layer, forming an organic hard mask layer over the device layer, forming a first oxide hard mask layer over the organic hard mask layer, forming a DARC layer over the first oxide hard mask layer, forming a photoresist layer over the DARC layer, patterning the photoresist layer to form a photoresist pattern, and transferring the photoresist pattern to the device layer using the DARC layer, the first oxide hard mask layer and the organic hard mask layer. | 2009-10-15 |
20090258496 | Method for fabricating semiconductor devices using strained silicon bearing material - A method of manufacturing an integrated circuit on semiconductor substrates, e.g., silicon wafer. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. In a specific embodiment, the semiconductor substrate has an overlying film of material with a second lattice with a second structure and a second spacing, the second spacing placing the film of material in a strain mode characterized by a first tensile and/or compressive mode along a single film surface crystal axis across a first portion of the film of material relative to the semiconductor substrate with the first structure and the first spacing. The method patterns a predetermined region of the first portion of the film of material to cause the first tensile and/or compressive mode in the first portion of the film of material to change to a second tensile and/or compressive mode in a resulting patterned portion of the first portion of the film of material. In a preferred embodiment, the patterns are made using a masking and etching process. | 2009-10-15 |
20090258497 | PHOTORESIST RESIN, AND METHOD FOR FORMING PATTERN AND METHOD FOR MANUFACTURING DISPLAY PANEL USING THE SAME - A photoresist resin composition, a method for forming a pattern and a method for manufacturing a display panel using the photoresist resin composition are disclosed. The photoresist resin composition includes an alkali soluble resin, a photoresist compound, and a solvent, wherein the alkali soluble resin includes a first polymer resin represented by the following Chemical Formula 1, wherein, of R | 2009-10-15 |
20090258498 | Method for Manufacturing a Semiconductor Device - A method for manufacturing a semiconductor device using a photoresist polymer comprising a fluorine component, a photoresist composition containing the photoresist polymer and an organic solvent to reduce surface tension, by forming a photoresist film uniformly on the whole surface of an underlying layer pattern to allow a subsequent ion-implanting process to be stably performed. | 2009-10-15 |
20090258499 | METHOD OF FORMING AT LEAST AN OPENING USING A TRI-LAYER STRUCTURE - A method of forming openings is disclosed. A substrate is first provided, and the tri-layer structure is formed on the substrate. The tri-layer structure includes a bottom photoresist layer, a silicon-containing layer and a top photoresist layer form bottom to top. Subsequently, the top photoresist layer is patterned, and the silicon-containing layer is etched by utilizing the top photoresist layer as an etching mask to partially expose the bottom photoresist layer. Next, the partially exposed bottom photoresist layer is etched through two etching steps in turn by utilizing the patterned silicon-containing layer as an etching mask. The first etching step includes an oxygen gas and at least one non-carbon-containing halogen-containing gas, while the second etching step includes at least one halogen-containing gas. The substrate is thereafter etched by utilizing the patterned bottom photoresist layer as an etching mask to form at least an opening in the substrate. | 2009-10-15 |
20090258500 | METHOD OF FORMING A PATTERN FOR A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE RELATED MOS TRANSISTOR - A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes. | 2009-10-15 |
20090258501 | Double patterning method - A method of making a device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer to form a first photoresist pattern, rendering the first photoresist pattern insoluble to a solvent, forming a second photoresist layer over the first photoresist pattern, patterning the second photoresist layer to form a second photoresist pattern over the underlying layer, and etching the underlying layer using both the first and the second photoresist patterns as a mask. | 2009-10-15 |
20090258502 | SELECTIVE ETCH OF HIGH-K DIELECTRIC MATERIAL - A method for selectively etching a high-k dielectric layer with respect to a polysilicon material is provided. The high-k dielectric layer is partially removed by Ar sputtering, and then the high-k dielectric layer is etched using an etching gas comprising BCl | 2009-10-15 |
20090258503 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND COMPUTER READABLE MEDIUM FOR STORING PATTERN SIZE SETTING PROGRAM - A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps. | 2009-10-15 |
20090258504 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device. The substrate processing apparatus includes a reaction vessel configured to process a substrate, a heater configured to heat an inside of the reaction vessel, a gas supply line configured to supply gas into the reaction vessel, a first valve installed at the gas supply line, a flow rate controller installed at the gas supply line, a main exhaust line configured to exhaust the inside of the reaction vessel, a second valve installed at the main exhaust line, a slow exhaust line installed at the main exhaust line, a third valve installed at the slow exhaust line, a throttle part installed at the slow exhaust line, a vacuum pump installed at the main exhaust line, and a controller configured to control the valves and the flow rate controller. | 2009-10-15 |
20090258505 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A manufacturing method for semiconductor devices having MOSFET gate insulation films The method includes forming a silicon oxide film, forming a silicon nitride film, nitriding the silicon nitride film, and first and second heat treatments. | 2009-10-15 |
20090258506 | Substrate Processing Method and Substrate Processing Apparatus - Substrate contamination from tungsten is prevented. | 2009-10-15 |
20090258507 | Substrate Treatment Device and Substrate Treatment Method - In order to solve the problem of contamination caused by static electricity on the surface of a substrate after plasma treatment, the invention provides a substrate treatment device comprising a standby chamber in which is arranged a transfer device for loading a substrate out of/into a cassette rack accommodating a substrate, said substrate treatment device capable of retaining said substrate transferred by the transfer device in a boat and loading, by way of a boat elevator, the boat into/out of a treatment furnace capable of applying plasma treatment to said substrate, wherein a static eliminator for eliminating static electricity of said substrate is arranged in said standby chamber. | 2009-10-15 |
20090258508 | Electrical Connector And Method Of Manufacturing Same - Embodiments of electrical connectors and related methods of manufacture are described herein. Other embodiments and related methods are also disclosed herein. | 2009-10-15 |
20090258509 | Adjustable connector for electrical cable - An adjustable connector for armored that includes a body, a hub, a clamp and a coupling nut. The body has a flanged end that is angularly disposed to the longitudinal axis and the hub has a mating flange that is angularly disposed to the central axis. The mating flange has a dovetail for receiving the flanged end and joining the body and hub together. The clamp is placed over the flanged end and mating flange and secured in place by tightening the coupling nut on the hub. | 2009-10-15 |
20090258510 | Electrical connector assembled into a hinge - An electrical connector ( | 2009-10-15 |
20090258511 | PRINTED WIRING BOARD SOLDER PAD ARRANGEMENT - A printed wiring board includes solder pads to which component leads may be soldered. L-shaped solder pads of the printed wiring board allow component leads to approach the board from any of the four major sides of the printed wiring board. Each solder pad includes two legs and two respective axes. A component lead may be selectively soldered to one of the two legs of the solder pad. Thus, a component lead may approach a solder pad from one of four orthogonal directions. | 2009-10-15 |
20090258512 | IC SOCKET - The object of the present invention is to provide an IC socket having a constitution for simplifying the motion of an activating member for operating a lever, whereby the operation of the lever may be easily applied to an automated machine. A lever member | 2009-10-15 |
20090258513 | ELECTRICAL ADAPTER ASSEMBLY AND LOADING MEMBER THEREOF - An electrical adapter assembly for connecting a first hard disk drive and a second hard disk drive is provided. The electrical adapter assembly includes a connector capable of electrically inserting into the first hard disk drive, a printed circuit board (PCB) module electrically connecting the connector, and a loading member for loading the first hard disk drive. The PCB module includes a chip for controlling data transfer between the first hard disk drive and the second hard disk drive. The loading member includes a base and at least two guiding portions pivotally attached on the base to allow the first hard disk drive to be able to slide between the at least two guiding portions. | 2009-10-15 |
20090258514 | Electrical connector with improved contact arrangement - An electrical connector ( | 2009-10-15 |
20090258515 | Connector - A connector includes a first connection member and a second connection member that come in electrical contact with terminal units of a board module. The first and second connection members have connection bodies with connection terminal units formed thereon, and press members that at the time of setting the board module, cause the connection terminals of the connection bodies to deform toward the terminal units of the board module and come in contact with the terminal units when the press members comes in contact with the leading edge of the board module. | 2009-10-15 |
20090258516 | USB Device With Connected Cap - A USB device including a housing and a protective cap that are slidably and/or pivotably connected together such that the protective cap is able to slide and/or pivot between an open position, in which a plug connector extending from the front of the housing is exposed for operable coupling to a host system, and a closed position, in which the protective cap is disposed over the front end portion of the housing to protect the plug connector. A pivoting/sliding mechanism is provided on the housing and cap that secures the protective cap to the housing at all times, including during transitional movements of the protective cap between the opened and closed positions. | 2009-10-15 |
20090258517 | BASIC INSULATING PLUG AND METHOD OF MANUFACTURE - A basic insulating plug (BIP) provides connection to a deadbreak connector. The basic insulating plug includes a first conductive insert and a second conductive insert. An insulative coupling supports the inserts in spaced apart position. An insulative body is molded substantially about the first and second conductive inserts. One of the conductive inserts and the insulative coupling define a flow path to permit flow of insulative material entering one of the conductive inserts to flow through the coupling so as to surround the coupling and substantially surround the first and second inserts. | 2009-10-15 |
20090258518 | Electrical card connector with a flange-like plane portion - A card connector, comprising: an insulative housing having a base, first and second sidewalls extending upwardly from two opposite sides of the base, a card receiving space defined by the base and the first and second sidewalls; a plurality of contacts held within the housing, the contacts having contact sections extending beyond the base; a pair of detecting switches including a stable switch and a movable switch both around a region located backwardly of the first sidewall; and a flange-like plane portion on said first sidewall and essentially vertical to said first sidewall, a front guiding entrance defined by said flange-like plane portion, the first sidewall, the second sidewall and the base. | 2009-10-15 |
20090258519 | CONNECTOR CARTRIDGE STACK FOR ELECTRICAL TRANSMISSION - Connector assemblies for use with implantable medical devices having easy to assemble contacts are disclosed. The connector assemblies are generally formed by coupling a plurality of ring contacts, sealing rings, and spring contact elements together with at least one holding ring to form a connector having a common bore for receiving a medical lead cable. Contact grooves or spring chambers for positioning the spring contact elements are formed in part by assembling multiple components together. A further aspect is a provision for encasing each connector assembly or stack inside a thermoset layer or a thermoplastic layer before over-molding the same to a sealed housing. | 2009-10-15 |
20090258520 | Moisture Proof Telescoping Coupler Assembly for Electric Metal Tubes with Enhanced Grounding and Sealing - A moisture proof, telescoping coupler assembly for electric metal tubes and threaded rigid pipe with an enhanced grounding arrangement both internally and externally for electrically grounding the telescoping tube to the coupler body, Moisture proof sealing is improved by centering the electric metal tube within the coupler body adjacent the seal preventing possible leaking after securing the electric metal tube to one end. A modified arrangement utilizes a snap fitting retaining ring for securing an electric metal tube to the coupler body to provide for unidirectional insertion of an electric metal tube into the open end of a coupler body in a manner that prohibits unintentional separation of the tube and/or retainer ring from the coupler body. | 2009-10-15 |
20090258521 | Waterproof connector and method for producing the same - The present invention is intended to provide a novel waterproof connector in which liquid such as water is securely prevented from adhering to the connection between a terminal fitting and an electrical conduit, and a novel method for producing the waterproof connector. | 2009-10-15 |
20090258522 | Weather resistant electrical connector - An electrical connector is provided including a housing supporting an electrical device and for receiving an electrical cord or cable. A cap having internal threads and an axial passage for receiving the electrical cord and clamping the electrical cord to the housing to form a waterproof connection. The cap includes a conical shaped seal member for forming a waterproof seal with the outer surface of the electrical cord. A conical shaped bushing is received in a frustoconical shaped bore of the housing and is axially and radially compressed by the threaded cap onto the housing. The bushing has an axial bore for receiving the electrical cable and an outer surface with at least one annular recess to facilitate the axial and radial compression of the bushing. The bottom end of the cap has a chamfered edge which mates with a frustoconical shaped outer surface of the housing to form a waterproof seal. | 2009-10-15 |
20090258523 | CONNECTOR - A connector which makes it possible to positively maintain a locked state of an actuator, even if a flat cable is pulled. The actuator is mounted on a housing in a manner pivotally movable between an open position for accommodating a front end of an FPC in an accommodating space and a closed position for pressing the front end of the FPC against contact portions of contacts. Locking members are mounted on the housing in a manner slidable between a locked position for inhibiting the actuator in the closed position from opening and an unlocked position for allowing the actuator to open, along a direction of arrangement of the contacts. | 2009-10-15 |
20090258524 | Electrical Fixture Connection Assembly - An electrical fixture connection assembly comprising a socket assembly, a plug assembly, and first and second fixing arms. A socket plate defines first and second socket apertures. Live and neutral electrical terminals are provided on the internal face of the socket plate. An earth terminal is provided within the socket housing at the distal end of a spring. The first and second fixing arms are provided on a carrier member and are movable between an open position in which the fixing arms extend out through fixing apertures in the socket housing and a closed position in which they are received within the socket housing. A resilient spring acts to bias the fixing arms in the open position. A live contact, a neutral contact, and an earth contact are provided on first, second and third plug arms of the plug assembly. | 2009-10-15 |
20090258525 | Connector With Improved Latching Mechanism - The invention relates to a connector including a connector housing and a latch including a first beam and a second beam, which first and second beam are connected with each other. The first beam includes a first locking structure and the second beam includes a second locking structure capable of locking said connector onto a counterpart in a locking position of said first and second locking structure. The first beam includes a force application element and the second beam and the connector housing are arranged to interact with each other in order to move the second locking structure from said locking position to a release position on application; of a force on said force application element. The invention further relates to a latch and a method of releasing a cable connector from a board connector. | 2009-10-15 |