42nd week of 2009 patent applcation highlights part 16 |
Patent application number | Title | Published |
20090256525 | Power storage apparatus - A power storage apparatus mounted with a plurality of connected power storage modules and capable of charging or discharging an electric power, and in which a housing is partitioned by a partition plate to be divided into a power storage area and a control device area; in the power storage area, an opening is formed, and the power storage modules are contained; in the control device area, an opening is formed, and a switching protective device section to switch and protect the power storage modules is contained; a main circuit wiring from the power storage modules is led out of the control device area via the switching protective device section; the opening of the power storage area is covered with a detachable cover; and the opening of the control device area is covered with a detachable cover independent of the cover of the opening of the power storage area. | 2009-10-15 |
20090256526 | APPARATUS AND METHOD FOR PRE-CHARGING IN CHARGING/DISCHARGING EQUIPMENT FOR AN ENERGY-STORAGE DEVICE - An apparatus includes a switching circuit operable with an arrangement configured to effectuate a charging or discharging of an energy-storage device to a circuit including electrically-parallel condenser. The switching circuit includes a main switch electrically connectable to the condenser, and a control circuit electrically connected in parallel with the main switch, and electrically connectable to the condenser. The main switch and control circuit are each configured to independently, switchably pass current from the energy-storage device to the condenser and a power load/source. In this regard, the main switch and control circuit are controllable to pass current from the energy-storage device to the power load, and in a manner whereby current from the energy-storage device to the condenser is diverted from passing through the main switch for a period during which a voltage disparity between the condenser and energy-storage device decreases to within a predetermined range. | 2009-10-15 |
20090256527 | AMBULATORY MEDICAL DEVICE WITH ELECTRICAL ISOLATION FROM CONNECTED PERIPHERAL DEVICE - Methods and apparatus are provided for electrically isolating an ambulatory medical device for infusing treatment materials into a patient when the medical device is connected to a peripheral device via an active communication cable. In one embodiment, the ambulatory medical device include first circuitry controlling infusion of a medicament to the patient by a fluid conduit connectable to the patient and second circuitry controlling communications when an active communication cable is connected to the medical device. The first and second circuitry are electrically isolated using a pair of first and second isolation transceivers, where the first pair of isolation transceivers communicate a control signal and the second pair of isolation transceivers are giant magneto-resistive (GMR) transceivers that communicate at least one data signal. | 2009-10-15 |
20090256528 | DIFFUSION-LIMITED ADAPTIVE BATTERY CHARGING - Some embodiments of the present invention provide a system that adaptively charges a battery, wherein the battery is a lithium-ion battery which includes a transport-limiting electrode governed by diffusion, an electrolyte separator and a non-transport-limiting electrode. During operation, the system determines a lithium surface concentration at an interface between the transport-limiting electrode and the electrolyte separator based on a diffusion time for lithium in the transport-limiting electrode. Next, the system calculates a charging current or a charging voltage for the battery based on the determined lithium surface concentration. Finally, the system applies the charging current or the charging voltage to the battery. | 2009-10-15 |
20090256529 | BATTERY CHARGING CONTROL CIRCUIT - The present disclosure provides a battery charging control circuit. The charging control circuit includes: a constant-current charging unit and a trickle charging unit. The charging control circuit further includes a branch switch, a control unit, and a detection unit. The branch switch is connected between a power source and the rechargeable battery for enabling or disabling the constant-current charging unit. The control unit is between the constant-current charging unit and the branch switch for controlling the branch switch. The detection unit is used to detect a state of the rechargeable battery. If the detection unit detects the state of the rechargeable battery is correspond to a predetermined state, then the control unit controls the branch switch to disable the constant-current charging unit and enable the trickle charging unit. | 2009-10-15 |
20090256530 | BATTERY CHARGING CONTROL CIRCUIT - The present invention provides a charging control circuit for a rechargeable battery. The charging control circuit includes: a constant-current charging unit and a trickle charging unit. The charging control circuit further includes a branch switch, a detection switch, a control unit, and a detection unit. The branch switch is connected between a power source and the rechargeable battery for enabling or disabling the constant-current charging unit, the detection switch is turned on or off depending on the enable or disable state of the constant-current charging unit. The control unit is connected between the detection switch and the branch switch for controlling the branch switch to turn on or off depending on the off or on state of the detection switch. | 2009-10-15 |
20090256531 | CHARGE INJECTION DISCHARGE CIRCUIT - Disclosed is a method and circuit for dissipating injected parasitic charge including a circuit stage, a pulse generating circuit and a switch. The circuit stage having an input node and an output node that injects a parasitic charge when switched OFF to the output node. The pulse generating circuit can generate a pulsed signal having an input for receiving a control signal. The control signal indicates the circuit stage is switching OFF, and has an output for outputting a pulsed signal in response to the control signal at the input. The pulsed signal can have a predetermined duration. The switch can be configured to be actuated by the pulsed signal output by the pulse generating circuit, and having a terminal connected to the output node of the circuit stage and a terminal connected to circuit to substantially dissipate the injected parasitic charge. | 2009-10-15 |
20090256532 | Kinetic Energy Harvesting in a Drill String - An apparatus and method for harvesting energy in a wellbore is disclosed. In one embodiment, a harvester tool positioned in a wellbore for capturing energy in the wellbore is disclosed. The harvester tool includes a rotor comprising a magnet. The magnet is disposed eccentric to a center of the harvester tool. In addition, the rotor is rotatable around the center of the harvester tool. The harvester tool also includes a stator. Rotation of the rotor induces a voltage in the stator. | 2009-10-15 |
20090256533 | Current-level Decision Device for a Power Supply Device and Related Power Supply Device - An current-level decision device for a power supply device includes a reception end for receiving a current sense signal, a reference voltage generator for generating a first reference voltage, a reference voltage correction unit coupled to the reference voltage generator and the reception end for adjusting the reference voltage according to variation of the current sense signal, so as to generate a second reference voltage, a comparator coupled to the reception end and the reference voltage correction unit for comparing the current sense signal and the second reference voltage to generate a comparison result, and a control unit coupled to the comparator for controlling a switch transistor of the power supply according to the comparison result. | 2009-10-15 |
20090256534 | POWER SUPPLY CONTROL METHOD AND APPARATUS - A power supply system including a controller capable of regulating a pulsed output voltage. The power supply system includes a load, a switching circuit connected to the load, and a controller electrically connected to the switching circuit. The controller is adapted to transmit a switching signal to the switching circuit for generating an adjustable duty cycle pulsed voltage to provide power to the controller and the load. The controller is further adapted to adjust the pulsed output voltage against a reference voltage by varying the duty cycle of the switching signal. The power supply system may include a start-up circuit electrically connected to the controller and adapted to provide a start-up voltage to the controller until the controller is powered by an operating voltage through the switching circuit. | 2009-10-15 |
20090256535 | VARYING OPERATION OF A VOLTAGE REGULATOR, AND COMPONENTS THEREOF, BASED UPON LOAD CONDITIONS - A method for operating a voltage regulator controller, for use in a voltage regulator including coupled inductors, is provided as follows. A first signal is generated for driving a first switch of the voltage regulator. A second signal is generated driving a first switch of the voltage regulator. The voltage regulator determines whether a light-load condition exists. Upon determining the existence of a light-load condition, adjusting the phase difference between said first and second signals so that the first and second signals are approximately in-phase. | 2009-10-15 |
20090256536 | INTEGRATED SWITCH WITH INTERNALLY ADJUSTED CONDUCTION TIME - An apparatus and method of providing a pulse width modulated signal that is responsive to a current are disclosed. An integrated circuit according to aspects of the present invention regulates an output of a power supply and includes a switch coupled to receive an external current. The integrated circuit also includes a controller coupled to the switch to control a switching of the external current by the switch in response to an external control signal and an internal current sense signal. The internal current sense signal is proportional to a current in the switch. The output of the power supply is also regulated in the absence of the internal current sense signal. | 2009-10-15 |
20090256537 | Multiphase Voltage Regulators And Methods For Voltage Regulation - A multiphase voltage regulator system comprises a microcontroller unit (MCU) including a reference voltage generator, and a timing generator for generating n-phase start timing signals; a load for receiving an output voltage; a comparator comparing the reference voltage and output voltage to generate a comparison result; and at least n points of load (POLs) coupled between the MCU and load for controlling output voltage in response to the n-phase start timing signals and the comparison result. Each POL may include a high-side and low-side transistor; and a D-FlipFlop, the D terminal coupled High, the clock terminal coupled to receive a control signal based on a respective one of the n-phase start timing signals, the Q terminal coupled to drive the high-side transistor, the /Q terminal coupled to drive the low-side transistor, and the reset terminal coupled to receive a reset control signal based on the comparison result. | 2009-10-15 |
20090256538 | POWER SUPPLY MODULE - A power supply module includes an inductor circuit, a switch circuit, a sensor circuit, and a controller. The inductor circuit includes an inductor and a voltage feedback wire returning the terminal voltage of the inductor. The switch circuit is electrically connected to the inductor circuit for driving the inductor circuit. The sensor circuit is electrically connected to the switch circuit and the voltage feedback wire, in which the sensor circuit controls the switch circuit and generates a current feedback signal according to the terminal voltage of the inductor. The controller is electrically connected to the sensor circuit, in which the controller controls the sensor circuit according to the current feedback signal. | 2009-10-15 |
20090256539 | Circuits and Methods for Sensing Current - Embodiments of the present invention include techniques for sensing current. In one embodiment, a switch in a switching regulator is coupled to a power supply. Input current from the supply is translated into an output current of the switching regulator. A signal corresponding to the output current is generated. The signal is selectively turned off with the input switch is open. Accordingly, the signal tracks the input current into the regulator. The signal may be used to determine the input current. In one embodiment, the signal is a voltage signal generated by a current corresponding to the output current provided into a resistor. | 2009-10-15 |
20090256540 | LOW DROP-OUT REGULATOR PROVIDING CONSTANT CURRENT AND MAXIMUM VOLTAGE LIMIT - A low drop-out regulator according to the present invention comprises an unregulated DC input terminal receiving an input voltage. A pass circuit is coupled between the unregulated DC input terminal and a regulated DC output terminal for supplying a power to the regulated DC output terminal. An amplifying circuit controls the pass circuit for providing a constant voltage or/and a constant current in response to an output voltage or/and an output current. | 2009-10-15 |
20090256541 | POWER SEQUENCE TECHNIQUE - Methods, systems, and devices are described for a power-on sequence for a circuit. A sequence generator for an electronic system may control various power domains to enter known states and prevent unwanted states as other domains of the system power-up. Regulator modules may be controlled to remain in an inoperable state until a reference voltage stabilizes at a predetermined reference level. The regulator modules regulate a received voltage supply to output a regulated voltage at the reference level, the regulated voltage set via a comparison to the reference voltage. Various analog and digital modules may be controlled to remain in an known state until the regulated voltage stabilizes at substantially the reference level. Additional sequencing is described for other dependencies, as well. | 2009-10-15 |
20090256542 | POWER SUPPLY CIRCUIT - A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage. | 2009-10-15 |
20090256543 | HIGH EFFICIENCY BRIDGELESS PFC POWER CONVERTER - A bridgeless PFC power converter comprises a first inductor and a second inductor coupled from a first input-terminal and a second input-terminal to a first transistor and a second transistor. A first diode and a second diode are coupled from the first transistor and the second transistor to an output capacitor. A first capacitor and a second capacitor are coupled from the input-terminals to the ground terminal through a third transistor and a fourth transistor. A control circuit generates a first-switching signal and a second-switching signal to control the first transistor and the second transistor. The second-switching signal will turn on the second transistor when the first-switching signal switches the first transistor. The first-switching signal will turn on the first transistor when the second-switching signal switches the second transistor. The control circuit turns off the third transistor and the fourth transistor during the light-load of the PFC power converter. | 2009-10-15 |
20090256544 | METHOD AND APPARATUS TO LIMIT OUTPUT POWER IN A SWITCHING POWER SUPPLY - Techniques are disclosed to adjust a current limit in a switching regulator. One example switching regulator includes a comparator having first and second inputs and an output. The first input of the comparator is adapted to sense a current flow through a switch and the second input of the comparator is adapted to sense a variable current limit value. A controller is coupled to the output of the comparator and to the switch to control switching of the switch to regulate an output of a power supply in response a feedback signal. The controller disables the switch if the sensed current flow through the switch is greater than the sensed variable current limit value. The variable current limit value is set to a first variable current limit value by the controller in response to an input line voltage of the power supply if there is not an over current condition during a first switching cycle that occurs after a skipped switching cycle of the switch. The variable current limit value is set to a second variable current limit value by the controller in response to the input line voltage if there is the over current condition during the first switching cycle that occurs after the skipped switching cycle. | 2009-10-15 |
20090256545 | Current-level Controlling Device for a Power Supply Device and Related Power Supply Device - A current-level controlling device for a power supply includes a reception end for receiving a current sense signal, a reference voltage generator for generating a reference voltage, an adaptive reference voltage generator, coupled to the reference voltage generator and the reception end, for adjusting the reference voltage according to variation of peak values of the current sense signal, so as to generate an adaptive reference voltage, a comparator, coupled to the reception end and the adaptive reference voltage generator, for comparing the current sense signal and the adaptive reference voltage, to generate a comparison result, and a control unit, coupled to the comparator, for controlling a switch transistor of the power supply according to the comparison result. | 2009-10-15 |
20090256546 | MOTHERBOARD WITH OVERCLOCKING AND OVERVOLTING FUNCTIONS - A motherboard with overclocking and overvolting functions is provided. The motherboard with an overvolting function includes a specified component, a voltage regulator and a micro-controller. The specified component receives an operating voltage. The voltage regulator generates the operating voltage according to a reference voltage. The micro-controller is electrically connected to an external input device for receiving a control signal issued by the external input device and adjusting the reference voltage according to the control signal. | 2009-10-15 |
20090256547 | STANDBY REGULATOR - A standby regulator circuit includes a standby bias circuit and a standby operational amplifier. The standby regulator circuit provides a standby regulated control voltage to a multiplexer. A regular operational amplifier provides a regulated control voltage to the multiplexer. During regular operation, the multiplexer selects the regular operational amplifier and selects the standby regulator circuit in a low-power mode. The multiplexer couples to a native pass transistor gate having a threshold voltage about equal to 0 V. The native pass transistor provides a regulated output voltage with relatively low-level input control voltages. In low-power mode, a power-down signal, provided to the multiplexer, smoothly transitions regulated control voltage from the regular operational amplifier to regulated control voltage sourcing from the standby operational amplifier. In low-power operation regular operational amplifier power is saved and the standby operational amplifier is appropriate for regulating the low threshold voltage native pass transistor. | 2009-10-15 |
20090256548 | ELECTRONIC IDENTIFICATION DEVICE AND METHOD - An electronic identification device for identifying, among conductors of a wiring system including multiple conductors, at least one conductor that is series-connected to a magnetically controlled switch The device comprises a test connector having pins that are connected to respective conductors to be tested, a microcontroller commanding, in a predetermined order and in two steps, the sending of a test signal to each of the pins of the test connector, and conducting measurements and comparisons for the identification of the conductors, a signal source that is connected both to the pins of the test connector and to the microcontroller, a magnetic field source, and a display for the display of the identification. | 2009-10-15 |
20090256549 | CONTROLLING METHOD OF CALIBRATING THE AIR-CORE POINTER ASSEMBLY AND DEVICE THEREOF - A controlling method and a device are disclosed to calibrate a pointer assembly of an air-core meter. The pointer assembly of the instrument includes a calibrating magnet, a cosine coil, a sine coil and a pointer. According to the polarity of the return-to-zero magnetic field established by the calibrating magnet, a compensating voltage is imposed on the cosine coil or the sine coil or both under either a voltage driving mode or a current driving mode. The compensating voltage establishes a compensating magnetic field to cancel the return-to-zero magnetic field. Therefore, without modifying the structure of the pointer set, the pointer has good linearity and is not affected by the calibrating magnet. | 2009-10-15 |
20090256550 | Wheel Speed Detecting Apparatus And A Wheel Bearing Apparatus Incorporated With A Wheel Speed Detecting Apparatus - A wheel speed detecting apparatus incorporated with a wheel bearing apparatus. The wheel speed detecting apparatus has an encoder, and an annular sensor holder arranged opposite to the encoder. The sensor holder has an annular fitting member formed from a steel plate. A holding portion is integrally molded with the annular fitting member. A wheel speed sensor is arranged opposite to the encoder. Several substantially circular arc notches are formed on the outer circumference of the holding portion so that portions of the periphery of the annular fitting member are exposed from the holding portion. | 2009-10-15 |
20090256551 | Rolling Bearing With Rotational Speed Sensor - The object is to produce even an magnetic encoder having a large outer diameter at a low cost, provide a sensor case which is compact in size and can be easily mounted and dismounted with a sensor element received therein, and to provide a double row rolling bearing with a preload application means and a rotational speed sensor which comprises a small number of parts and thus can be assembled easily. | 2009-10-15 |
20090256552 | GEAR TOOTH SENSOR WITH SINGLE MAGNETORESISTIVE BRIDGE - The invention discloses a rotation sensor suitable for gear wheels. MR (magneto-resistive) sensors are placed inside a zero field region generated by at least two permanent magnets. Said sensors are divided into two groups that are immersed in different locally generated magnetic environments. A differential signal taken between the two groups then senses the movement of the wheel's teeth. A single wafer method for manufacturing the device is also briefly described. | 2009-10-15 |
20090256553 | MAGNETORESISTIVE ARRAY DESIGN FOR IMPROVED SENSOR-TO-MAGNET CARRIER TOLERANCES - An AMR array magnetic position sensing method and system for improving sensor-to-magnet carrier misposition. A magnetic carrier can be provided, which maintains two or more magnets with angled magnetic vectors position above an array of AMR array sensors. The magnet carrier can then be passed over the AMR array sensors to generate an output signal having less susceptibility to variations in air gap because the angles of flux lines generated by the magnets do not change much with air gap variation. The AMR array sensors are generally sensitive to variation in a direction being sensed, because a constant magnetic field angle sensed by AMR runners located on the AMR array sensors do not change with respect to variation in other directions. | 2009-10-15 |
20090256554 | Position measuring apparatus - A position measuring apparatus includes (a) a sleeve that has an open first end and a second end opposite the first end, (b) a guide pin guided at least partly in the sleeve, (c) a spring, (d) a linear magnetic field sensor and (e) a magnet disposed adjacent to the linear magnetic field sensor. To avoid wear even in the presence of large temperature fluctuations, the magnet is disposed on a face of the guide pin facing the second end of the sleeve, and the spring is disposed between the second end of the sleeve and the magnet such that the spring urges the magnet against the guide pin. | 2009-10-15 |
20090256555 | LINEAR INDUCTIVE POSITION SENSOR - A linear position sensor having a transmitter coil which generates electromagnetic radiation when excited by a source of electrical energy and wound in a first direction. A receiver coil is contained within the transmitter coil and the receiver coil includes both a first loop wound in a first direction and a second loop wound in the opposite direction. A coupler element linearly moves along a first direction relative to the transmitter coil which varies the inductive coupling between the transmitter coil and the receiver coil as a function of the linear position of the coupler element to thereby vary the electrical output signal from the receiver coil when excited by the transmitter coil. The first and second loops of the receiver coil are linearly aligned with each other along the first direction. | 2009-10-15 |
20090256556 | MEASURING ARRANGEMENT FOR DETECTING A 1/ROTARY MOMENTUM OF AN ENGINE ROTOR, AND ASSOCIATED METHOD - A measurement system for detecting a rotary movement of a rotor that is situated in particular in rotatable fashion in a compressor housing of a jet engine, includes the rotor having vane elements that are preferably situated equidistant from one another on its periphery, and in addition at least one sensor being provided, and at least one material measure being fashioned on the rotor that can be periodically detected by the sensor due to the rotational movement, the material measure is forned by at least one modified vane element that is truncated in the area of the vane tip, the sensor outputting an identical measurement signal in each case when the vane elements travel past, and outputting a modified measurement signal when the modified vane element travels past. | 2009-10-15 |
20090256557 | TESTING METHOD OF MAGNETIC HEAD BY USING INDUCTANCE - It is an object of the present invention to provide a method for investigating magnetic domains, the method capable of easily grasping behavior of the magnetic domains in a head manufacturing process, and further to provide a testing method of a magnetic head capable of evaluating whether the writing performance of the magnetic head is good or not. The method for investigating magnetic domains comprises supplying direct current (DC) to a coil of an electromagnetic transducer provided in a magnetic head for writing data onto a magnetic recording medium; measuring an inductance of the electromagnetic transducer at each current value while varying the current value of the direct current; and investigating behavior of magnetic domains in a magnetic core of the electromagnetic transducer based on a relationship between the current values and the inductances. The testing method of a magnetic head comprises evaluating whether writing performance of the magnetic head is good or not, based on a relationship between the current values and the inductances. | 2009-10-15 |
20090256558 | Film thickness measuring apparatus and film thickness measuring method - Coil is made to be disposed with gap opposed to the surface of wafer, and wafer stage is made to move in X and Y direction and R and θ direction. When supplying an alternating current to coil with the frequency swept by impedance analyzer, the magnetic field made to be induced in coil will operate on the conductive film of wafer. By changing a parameter (a frequency or an angle) influencing the skin effect of the conductive film and giving the parameter to coil, the state where a magnetic field is not made to penetrate relatively the film of wafer and the state where the magnetic field is made to penetrate relatively the film can be formed. From the variation of various values corresponding to the eddy current induced based on the change of state influenced by the skin effect of the conductive film, the film thickness of wafer can be measured with sufficient accuracy. | 2009-10-15 |
20090256559 | HALL EFFECT DEVICE AND METHOD - A semiconductor device including a Hall effect sensor and related method. The Hall effect device includes a substrate having a first conductivity type and an epitaxial layer having a second conductivity type defining a Hall effect portion. A conductive buried layer having the second conductivity type is situated between the epitaxial layer and the substrate. First and second output terminals and first and second voltage terminals are provided, with the second voltage terminal being coupled to the conductive buried layer. | 2009-10-15 |
20090256560 | Sensor system embedded in metal - A sensor system, which can be embedded in a metal bed or metal face and has a good performance, has been demanded. A sensor system arranged in the following manner fulfills the above-mentioned demand. When the sensor system employs a square bracket shaped magnetic substance core, a magnetic path is formed and a strong magnetic field vertical to the metal face is obtained, even if the square bracket shaped magnetic substance core is embedded in a concave of the metal bed. A strong vertical magnetic field is obtained in the center portion of a combined magnetic substance cores even by using a surface current on the metal face. | 2009-10-15 |
20090256561 | INTEGRATED MICROCHIP INCORPORATING ATOMIC MAGNETOMETER AND MICROFLUIDIC CHANNEL FOR NMR AND MRI - An integral microfluidic device includes an alkali vapor cell and microfluidic channel, which can be used to detect magnetism for nuclear magnetic resonance (NMR) and magnetic resonance imaging (MRI). Small magnetic fields in the vicinity of the vapor cell can be measured by optically polarizing and probing the spin precession in the small magnetic field. This can then be used to detect the magnetic field of in encoded analyte in the adjacent microfluidic channel. The magnetism in the microfluidic channel can be modulated by applying an appropriate series of radio or audio frequency pulses upstream from the microfluidic chip (the remote detection modality) to yield a sensitive means of detecting NMR and MRI. | 2009-10-15 |
20090256562 | NMR METHOD OF DETECTING PRECIPITANTS IN A HYDROCARBON STREAM - A method for detecting the presence of precipitants in a hydrocarbon stream, the method comprising introducing at least a portion of the hydrocarbon stream into a measurement chamber of an NMR measuring device, assaying the fluids in the chamber with proton nuclear magnetic resonance to obtain NMR signals, and processing the NMR signals to detect the formation of precipitants in the hydrocarbon stream. The method may be carried out at first and second locations, and NMR signals obtained at the two locations compared to detect precipitation of precipitant between the two locations. A method of monitoring the water content of a hydrocarbon stream in a flowline comprising introducing at least a portion of the hydrocarbon stream into an NMR measuring device, measuring a baseline NMR water signal of the hydrocarbon stream and comparing subsequent NMR water signals with the baseline NMR water signal to detect changes in the water content of the hydrocarbon stream. | 2009-10-15 |
20090256563 | PREPARING THE MAGNETIZATION STATE OF A SAMPLE FOR ALTERNATING REPETITION TIME STEADY STATE FREE PRECESSION MAGNETIC RESONANCE IMAGING - Techniques and systems for magnetic resonance imaging. In one aspect, preparatory pulse sequences precede alternating repetition time steady state free precession (ATR SSFP) pulse sequences to enable image acquisition before reaching a steady-state equilibrium. The design of the preparatory sequences is based on a two step process: First an oscillatory residue is expressed in terms of a window (e.g., a Kaiser-Bessel window) and scale parameters. Second the oscillatory residue is minimized to determine the scale parameters according to a desired application (e.g. ATR SSFP, optimized for fat, water, etc.) The preparation scheme described in this specification can be applied to arbitrary repetition times and RF phase cycling combinations. | 2009-10-15 |
20090256564 | MAGNETIC RESONANCE RADIO FREQUENCY SYSTEM AND OPERATING METHOD THEREFOR - In a method for processing radio frequency signals of a magnetic resonance imaging system in which the coil portion of the magnetic resonance imaging system includes a body coil and a local coil, radio frequency signals are supplied to the body coil, and these radio frequency signals are coupled to said local coil, and transmitted by said local coil into a region to be examined. A corresponding radio frequency system has a local coil and a body coil, with power coupling between the local coil and the body coil; during the phase for transmitting the radio frequency signals. The body coil serves to couple the radio frequency signals to be transmitted to the local coil, and the local coil serves to transmit the coupled radio frequency signals to a region to be examined. This method and system allow the transmitting function of the local coil to be achieved without having a coil plug on a patient bed to provide a radio frequency signal transmitting channel. | 2009-10-15 |
20090256565 | METHOD AND SYSTEM FOR RECONSTRUCTING IMAGES - A method for reconstructing an image in a magnetic resonance imaging system is provided. The method includes steps of acquiring magnetic resonance signals from a plurality of receiver coils placed about a subject, each receiver coil having a coil sensitivity, iteratively polling each acquired magnetic resonance signal for determining one or more significant wavelet components of each acquired magnetic resonance signal by utilizing a coil sensitivity function of each receiver coil for each acquired magnetic resonance signal, iteratively determining one or more coefficients based on the one or more significant wavelet components to generate a plurality of coefficients for each acquired magnetic resonance signal, reconstructing an image utilizing a corresponding plurality of coefficients corresponding to each acquired magnetic resonance signal, and generating a composite image by combining the reconstructed images. | 2009-10-15 |
20090256566 | MEDICAL IMAGING METHOD AND SYSTEM WITH AUTOMATED ASSOCIATION OF IMAGES WITH MEASUREMENT SEQUENCES - A medical imaging system is operated corresponding to a measurement sequence to acquire data of an examination subject. A control device associates a reference to the measurement sequence with the acquired data and stores the acquired data including the associated reference. The control device determines an image of the examination subject using the acquired data and outputs the determined image to an operator of the medical imaging system via a viewing device. When a corresponding activation command is provided to it by the operator, the control device automatically determines the corresponding measurement sequence using the reference associated with the displayed image, and automatically associates a reference to at least one image corresponding with the displayed image with the measurement sequence. The control device provides the measurement sequence (S) for search purposes upon retrieval of the measurement sequence, the control device also automatically retrieves the images associated with the retrieved measurement sequence as well. | 2009-10-15 |
20090256567 | THREE-POINT METHOD AND SYSTEM FOR FAST AND ROBUST FIELD MAPPING FOR EPI GEOMETRIC DISTORTION CORRECTION - A system and method for MR magnetic field mapping includes a computer programmed to acquire a first data point at a first location in a first phase image data set, a second data point at the first location in a second phase image data set, a third data point at the first location in a third phase image data set. The first, second, and third phase images are acquired using a first, second, and third TE, respectively. Phase wrapping does not occur among the first and second phase image data sets; however, phase wrapping does occur among the second and third phase image data sets. The computer is also programmed to determine a magnetic field inhomogeneity, wherein the determination of the magnetic field inhomogeneity is based on the first, second, and third data points. | 2009-10-15 |
20090256568 | SYSTEM AND METHOD FOR CORRECTING FLOW VELOCITY MEASUREMENTS IN PHASE CONTRAST IMAGING USING MAGNETIC FIELD MONITORING - A system and method of phase contrast imaging includes a system control programmed to acquire a first set of data and a second set of data via the RF coil assembly during a scan and acquire a third set of data and a fourth set of data via the plurality of magnetic field monitoring devices during the scan. A first single data set from the first and third sets of data is formed, and a second single data set from the second and fourth sets of data is formed. The system control is also programmed to reconstruct a phase contrast image based on the first and second single data sets to correct for spatially-dependent background phase variations. | 2009-10-15 |
20090256569 | MULTI-FREQUENCY RF COIL - A multi-frequency imaging radio frequency (RF) coil operational at three or more different frequencies, with a shifting frequency loop structure proximate the coil and switchably coupled to provide different frequencies when the loop structure is coupled to the coil. In one embodiment one of the frequencies is a proton frequency, one is a sodium frequency, and one of the frequencies is a carbon frequency. One example involves imaging examinations using hyperpolarized compounds. | 2009-10-15 |
20090256570 | Method For Joint Sparsity-Enforced K-Space Trajectory and Radiofrequency Pulse Design - A system and method is provided for simultaneously designing a radiofrequency (“RF”) pulse waveform and a magnetic field gradient waveform in a magnetic resonance imaging (“MRI”) system. The method includes determining a desired pattern of RF excitation and determining, from the desired pattern of RF excitation, a plurality of k-space locations indicative of the magnetic field gradient waveform and a plurality of complex weighting factors indicative of RF energy deposited at each k-space location. The method also includes calculating, from the determined k-space locations, the magnetic field gradient waveform and calculating, from the complex weighting factors, the RF pulse waveform that will produce the desired pattern of RF excitation when produced with the calculated magnetic field gradient. | 2009-10-15 |
20090256571 | MAGNETIC RESONANCE APPARATUS WITH RF AMPLIFIER(S) DISPOSED WITHIN THE SPACED DISTANCE BETWEEN THE PRIMARY AND SECONDARY GRADIENT COIL WINDINGS - An arrangement for controlling an antenna arrangement in a magnetic resonance device has an antenna arrangement that surrounds an examination region and that has at least one antenna element for emitting an amplified transmit signal. At least one amplifier is provided, at the input of which a high-frequency transmit signal is connected, which is present on the output side of the amplifier as an amplified transmit signal. The amplifier is connected to a feed point of the antenna arrangement on the output side, in order to emit the amplified transmit signal. Coil windings of a primary gradient coil are also provided, which at least partially include the antenna arrangement and the examination region. Coil windings of a secondary gradient coil at least partially include the coil windings of the primary gradient coil, the antenna arrangement (and the examination region). The coil windings of the secondary gradient coil and the coil windings of the primary gradient coil are at a distance from one another, in which the at least one amplifier is arranged. | 2009-10-15 |
20090256572 | Tuning Low-Inductance Coils at Low Frequencies - A method and apparatus for tuning and matching extremely small sample coils with very low inductance for use in magnetic resonance experiments conducted at low frequencies. A circuit is disclosed that is appropriate for performing measurements in fields where magnetic resonance is beneficially utilized. The circuit has a microcoil, an adjustable tuning capacitance, and added inductance in the form of a tuning inductor. The microcoil is an electrical coil having an inductance of about 25 nanohenries (nH) or less. Because additional inductance is purposefully added, the capacitance required for resonance and apparatus function is proportionally and helpfully reduced. The apparatus and method permit the resonant circuit and the magnet to be made extremely small, which is crucial for new applications in portable magnetic resonance imaging, for example. | 2009-10-15 |
20090256573 | Magnetic resonance imaging system, apparatus and associated methods - In one aspect, a magnet comprising a pair of pole supports spaced apart from one another and extending in a generally horizontal direction. The magnet includes a pair of flux return members extending between the pole supports so as to define a frame, each of the flux return members including a first columnar section that extends parallel to the polar axis and a second columnar section that extends perpendicular to the polar axis and projects towards the pole. In another aspect, a magnetic resonance imaging system comprises a ferromagnetic frame that is operative to support an upper pole member and a lower pole member along a vertical polar axis such that a gap is defined between the upper and lower pole members and an access floor that is isolated from the ferromagnetic frame and pole members for providing access to the gap. | 2009-10-15 |
20090256574 | TRANSMISSION PATH FOR USE IN RF FIELDS PROVIDING REDUCED RF HEATING - A transmission path ( | 2009-10-15 |
20090256575 | ELECTROLOCATION APPARATUS AND METHODS FOR MAPPING FROM A SUBTERRANEAN WELL - In some embodiments, apparatus useful for determining at least one dimension of at least one geological feature of an earthen formation from a subterranean well bore includes at least two emitting electrodes and at least one sensing electrode disposed in the well bore. The emitting electrodes are configured to create an electric field and the at least one sensing electrode is configured to detect perturbations in the electric field created by at least one target object. | 2009-10-15 |
20090256576 | APPARATUS AND METHOD FOR GROUND FAULT DETECTION AND LOCATION IN ELECTRICAL SYSTEMS - The present invention is implemented by deploying an enhanced ground fault detection and location apparatus and by using the apparatus in conjunction with specific circuit analysis methods, using the information generated by the ground fault detection and location apparatus. The ground fault detection and location apparatus comprises the functionality of a voltmeter, an ammeter, a phase angle meter, a frequency generator, and a variable power supply, thereby providing for a variety of signals and analyses to be performed on a unintentionally grounded circuit in an ungrounded AC or DC power distribution system. The ground fault detection and location apparatus is capable of operating in six different modes, with each mode providing a different capability or opportunity for detecting, analyzing, and locating one or more unintentionally grounded circuits in an normally ungrounded AC or DC power distribution system. Additionally, the present invention is configured to manipulate a ground fault current at a first target frequency and a second target frequency, thereby enabling more rapid and efficient location of ground faults. | 2009-10-15 |
20090256577 | Delay Lock Loop Circuit, Timing Generator, Semiconductor Test Device, Semiconductor Integrated Circuit, and Delay Amount Calibration Method - A method replaces a delay amount measurement in which an initially set value of a counter is determined by a technique which replaces measurement of a delay amount, whereby a time required for calibration of a delay circuit can be reduced. One counter set value of a plurality of counter set values is loaded, a delay lock loop circuit is switched to a lock mode, and a sequence circuit of a cycle slip detection circuit is reset. Thereafter, a cycle slip detection signal output from the sequence circuit is read, and on the basis of this cycle slip detection signal, it is judged whether or not an output signal of a delay circuit causes cycle slip. If the cycle slip is caused, the counter set value is switched. On the other hand, if any cycle slip is not caused, the counter set value is locked, thereby terminating the process. | 2009-10-15 |
20090256578 | ANTI-PINCH SENSOR - An anti-pinch sensor, particularly for detecting an obstacle in the path of an actuating element of a motor vehicle is provided, having a sensor body, a measuring electrode, which is disposed in the sensor body and to which a measuring potential can be applied, a calibrating electrode, which is electrically disconnected and disposed in the sensor body adjacent to the measuring electrode, and a control unit. The control unit controls the measuring electrode and the calibrating electrode such that the measuring potential and the calibrating potential are equal in a measuring phase, and differ from each other in a calibrating phase. | 2009-10-15 |
20090256579 | SELF-CHECKING ANALYZER METHOD AND SYSTEM USING REFLECTED POWER/INSERTION LOSS - A self-checking analyzer system is provided according to an embodiment of this disclosure. The analyzer system includes a pipeline for receiving a multi-phase fluid flow. The analyzer system also includes a first measuring device configured to provide a first reflected power/insertion loss measurement corresponding to the multi-phase fluid flow, and a second measuring device differing in frequency response from the first measuring device and configured to provide a second reflected power/insertion loss measurement corresponding to the multi-phase fluid flow. The analyzer system is configured to validate the first reflected power/insertion loss measurement using the second reflected power/insertion loss measurement | 2009-10-15 |
20090256580 | ORTHOGONAL RADIO FREQUENCY VOLTAGE/CURRENT SENSOR WITH HIGH DYNAMIC RANGE - A radio frequency (RF) sensor that measures RF current includes a substrate that has an inner perimeter that defines an aperture. A conductor extends through the aperture. Sensor pads are arranged on the aperture and are connected to form two sensor loops. The loops generate an electrical signal that represents RF current flow through the center conductor. Additionally, a plurality of circular conductive rings may be included in the RF sensor to generate a signal representing the voltage of the conductor. | 2009-10-15 |
20090256581 | SOLAR PARAMETRIC TESTING MODULE AND PROCESSES - Embodiments of the present invention generally relate to a module that can test and analyze various regions of a solar cell device in an automated or manual fashion after one or more steps have been completed in the solar cell formation process. The module used to perform the automated testing and analysis processes can also be adapted to test a partially formed solar cell at various stages of the solar cell formation process within an automated solar cell production line. The automated solar cell production line is generally an arrangement of automated processing modules and automation equipment that is used to form solar cell devices. | 2009-10-15 |
20090256582 | TEST CIRCUIT BOARD - A test circuit board used for disposing at least one device under test is disclosed. The circuit board transmits a plurality of testing signals generated by a tester to test the device under test. The test circuit board includes a circuit board, a plurality of transforming slots, a plurality of connecting slots and a plurality of connecting lines. The transforming slots, the connecting slots and the connecting lines are located on the circuit board. The connecting lines are located on the circuit board according to a predetermined manner. | 2009-10-15 |
20090256583 | Vertical Microprobes for Contacting Electronic Components and Method for Making Such Probes - Multilayer probe structures for testing or otherwise making electrical contact with semiconductor die or other electronic components are electrochemically fabricated via depositions of one or more materials in a plurality of overlaying and adhered layers. In some embodiments the structures may include configurations intended to enhance functionality, buildability, or both. | 2009-10-15 |
20090256584 | GAP INSPECTION APPARATUS - An apparatus for inspection of a gap between two surfaces, at least one of which is ferromagnetic, for example in a generator, includes a sensor platform ( | 2009-10-15 |
20090256585 | DATA LINE TERMINATION CIRCUIT - A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal. The swing-width sensing unit can sense if the swing width is less than or greater than a predetermined swing width, and the swing width of the voltage of the data line can be reduced or increased to maintain the voltage of the data line within a predetermined range. | 2009-10-15 |
20090256586 | SEMICONDUCTOR DEVICE AND IMPEDANCE ADJUSTMENT METHOD OF THE SAME - A 4-bit counter outputs a 4-bit counted value CNTp based on an up-and-down signal Sp supplied from a comparator. A weighting selection circuit performs weighting based on a deviation from an average value of the DC characteristic of each PMOS transistor, and assigns a transistor having the smallest deviation to Bit | 2009-10-15 |
20090256587 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device, a first ODT (On Die Termination) circuit is provided between a termination voltage port and a command input port. A first ODT controlling circuit is connected between the termination voltage port and controls the first ODT circuit to connect the termination voltage port and the command input port based on the detection result. | 2009-10-15 |
20090256588 | PROGRAMMABLE ARRAY LOGIC CIRCUIT EMPLOYING NON-VOLATILE FERROMAGNETIC MEMORY CELLS - A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line. Additionally, the integrated circuit may further include a logical AND array and a logical OR array. | 2009-10-15 |
20090256589 | PROGRAMMABLE DEVICE, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING PROGRAMMABLE DEVICE - A programmable device connected to a storage unit which stores logic circuit configuration information to form a logic circuit and control circuit configuration information to form a control circuit includes a first programmable logic device and a second programmable logic device, and a configuration unit which forms the control circuit in the first programmable logic device, by providing the control circuit configuration information in the storage unit to the first programmable logic device. The control circuit formed in the first programmable logic device forms the logic circuit in the second programmable logic device, by providing the logic circuit configuration information in the storage unit to the second programmable logic device. | 2009-10-15 |
20090256590 | STORAGE ELEMENT FOR CONTROLLING A LOGIC CIRCUIT, AND A LOGIC DEVICE HAVING AN ARRAY OF SUCH STORAGE ELEMENTS - The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A multiplexer has an input, a switched input and two outputs. The output node is connected to the input of the multiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output. | 2009-10-15 |
20090256591 | STRUCTURE FOR SYSTEMS AND METHODS OF MANAGING A SET OF PROGRAMMABLE FUSES ON AN INTEGRATED CIRCUIT - Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit. | 2009-10-15 |
20090256592 | SIGNAL DRIVER CIRCUIT HAVING ADJUSTABLE OUTPUT VOLTAGE FOR A HIGH LOGIC LEVEL OUTPUT SIGNAL - A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage. | 2009-10-15 |
20090256593 | PROGRAMMABLE SAMPLE CLOCK FOR EMPIRICAL SETUP TIME SELECTION - A system and method for efficient improvement of timing analysis for faster processor designs with negligible impact on die-area. Rather than provide a single clock to flip-flop circuits on a semiconductor chip, split clocks are used. A flip-flop receives a master clock signal for a master latch and receives a separate slave clock signal for a slave latch. Master and slave clock gater circuits are coupled to a global clock distribution system and the local flip-flops. The master clock gater circuit receives a delay control signal used to select a delay, wherein the selected delay determines an additional amount of time the master clock signal transitions after the slave clock signal transitions. The use of the delayed master clock on the semiconductor chip may allow a timing path to have more computation time without increasing the clock cycle time. Further, the delay may be chosen to fix timing paths in post-silicon. | 2009-10-15 |
20090256594 | NANOELECTROMECHANICAL DIGITAL INVERTER - A digital inverter formed by three carbon nanotubes (CNTs) extending vertically from a substrate, one CNT functioning as first source (S | 2009-10-15 |
20090256595 | Phase Detecting Module and Detecting Method Thereof - A phase detecting module capable of optimizing detection accuracy and noise robustness, and a detecting method, are included. The phase detecting module includes a phase detecting circuit, an energy estimating circuit and a selecting circuit. The phase detecting circuit detects a phase of an input signal to generate a phase detection value. The energy estimating circuit estimates energy of the input signal to generate an energy estimation value. The selecting circuit selectively outputs the phase detection value according to the energy estimation value. | 2009-10-15 |
20090256596 | FLIP-FLOP, FREQUENCY DIVIDER AND RF CIRCUIT HAVING THE SAME - A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output a signal based on the first signal; and at least one switch unit that is switched in response to a control signal to modify a signal transfer path between the plurality of the flip-flops, wherein a different number of flip-flops are activated in response to each first and second status of the control signal so that the frequency of the first signal is divided by different multiples. | 2009-10-15 |
20090256597 | POWER-ON RESET CIRCUIT - A power-on reset circuit according to an embodiment of the present invention includes an input control unit configured to generate a default input signal in response to a power-on reset signal and a clock, a counting unit configured to perform a counting operation in response to the default input signal to generate a count offset signal, and a power-on reset unit configured to perform a counting operation in response to the count offset signal to generate the power-on reset signal. | 2009-10-15 |
20090256598 | POWER-UP SIGNAL GENERATOR OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR CONTROLLING THE SAME - A power-up signal generator of a semiconductor memory apparatus includes a power-up signal generating unit that includes a MOS transistor having a gate receiving a divided voltage of an external supply voltage, the power-up signal generating unit determining a level of a power-up signal according to a turn-ON state of the MOS transistor, and a bulk bias voltage generating unit that applies a bulk bias voltage to a bulk of the MOS transistor to adjust a threshold voltage of the MOS transistor, wherein the bulk bias voltage varies according to a temperature of the semiconductor memory device. | 2009-10-15 |
20090256599 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device generating internal power from external power, an abnormal operation may occur due to an indefinite state of a control signal when the external power is applied and the internal power rises. The semiconductor integrated circuit includes an internal power generating circuit, a control circuit receiving internal power and supplying a first control signal, and a power-on reset circuit generating a reset signal at rising of the internal power. When internal power rises, the reset signal masks an indefinite state of the first control signal supplied from the control circuit. | 2009-10-15 |
20090256600 | INPUT CLOCK DETECTION CIRCUIT FOR POWERING DOWN A PLL-BASED SYSTEM - An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal. | 2009-10-15 |
20090256601 | PHASE TO DIGITAL CONVERTER IN ALL DIGITAL PHASE LOCKED LOOP - A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock. | 2009-10-15 |
20090256602 | VARIABLE LOOP BANDWIDTH PHASE LOCKED LOOP - An apparatus comprising a voltage controlled oscillator, a first charge pump, a second charge pump, a switch circuit and a comparator circuit. The voltage controlled oscillator may be configured to generate an output signal oscillating at a first frequency in response to a control signal. The charge pump circuit may be configured to generate a first component of the control signal in response to a first adjustment signal and a second adjustment signal. The second charge pump may be configured to generate a second component of the control signal in response to a first intermediate signal and a second intermediate signal. The switch circuit may be configured to generate the first intermediate signal and the second intermediate signal in response to the first adjustment signal and the second adjustment signal. The comparator circuit may be configured to generate the first and second adjustment signals in response to a comparison between (i) an input signal having a second frequency and (ii) the output signal. | 2009-10-15 |
20090256603 | REGISTER CONTROLLED DELAY LOCKED LOOP CIRCUIT - A register controlled delay locked loop (DLL) circuit, including: a phase comparator configured to compare phases of a source clock and a feedback clock with each other, and a clock delay circuit configured to delay a phase of an internal clock synchronized with a clock edge of the source clock in response to an output signal of the phase comparator. The clock delay circuit delays the phase of the internal clock using first delay units for a predetermined delay duration, and thereafter delays the phase of the internal clock using second delay units, the second delay unit providing a longer delay than the first delay unit. A delay replica model is configured to reflect actual delay conditions of the source clock in an output clock of the clock delay circuit to output the feedback clock. | 2009-10-15 |
20090256604 | REGISTER CONTROLLED DELAY LOCKED LOOP CIRCUIT - A register controlled DLL circuit occupies a relatively small area in a semiconductor device by reducing the number of flip-flops for generating timing pulses that are used to control a DLL operation and sequentially toggled. The registered controlled DLL circuit for generating a DLL clock by delaying internal clocks includes a timing pre-pulse generating unit configured to generate a plurality of timing pre-pulses activated sequentially in response to a source clock, the plurality of pre-pulses being repeated two or more times in each delay shifting update period, a mask signal generating unit configured to generating a mask signal having a logic level varied according to toggling of a predetermined one of the timing pre-pulses, and a timing pulse outputting unit configured to output the plurality of timing pre-pulses as a plurality of timing pulses in response to the mask signal. | 2009-10-15 |
20090256605 | PHASE CONTROLLING APPARATUS, PHASE-CONTROL PRINTED BOARD, AND CONTROLLING METHOD - In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be externally switched to a signal different in frequency is accepted, in a second delay line, a delay amount is added to the phase of the external signal by each delay unit. The phase of a delay signal delayed by all delay units of the second delay line and the phase of the external signal to which no delay amount added are compared to output a phase difference. A control voltage value that is a value for synchronizing the delay signal to be compared by the phase comparator and is generated from the phase difference output from the phase comparator is input to each of the delay units. | 2009-10-15 |
20090256606 | DIGITAL SIGNAL INPUT DEVICE AND METHOD OF CONTROLLING THE SAME - A digital signal input device has a first input terminal and a second input terminal, a charging circuit connected between the first input terminal and the second input terminal, and a digital signal detection unit that outputs a digital signal of a logical value corresponding to a level of a charging voltage to an internal circuit. A pulse control unit generates a pulse signal having a fixed period using designated pulse width and pulse period. A switching element is provided between the charging circuit and the first input terminal or the second input terminal, which controls a period of applying a DC voltage to the charging circuit using a pulse width of the pulse signal. | 2009-10-15 |
20090256607 | POWERED RING TO MAINTAIN IO INDEPENDENT OF THE CORE OF AN INTEGRATED CIRCUIT DEVICE - In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode. | 2009-10-15 |
20090256608 | Low leakage data retention flip flop - A disclosed embodiment is a low leakage data retention flip flop comprising a master circuit for retaining data during sleep mode, wherein the master circuit is configured to receive a reduced supply voltage during the sleep mode. The flip flop includes a slave circuit having low threshold voltage transistors, where the slave circuit is turned off during the sleep mode. In various embodiments, the master circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. Similarly, the slave circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. To begin the sleep mode, the master circuit receives a reduced supply voltage and the slave circuit is coupled to ground and is thus turned off. During the sleep mode, the slave circuit experiences virtually no leakage current, and the master circuit experiences a reduced leakage current. | 2009-10-15 |
20090256609 | LOW POWER FLIP FLOP THROUGH PARTIALLY GATED SLAVE CLOCK - A system and method for reducing power consumption within a flip-flop circuit on a semiconductor chip. A gated input clock signal is received by a slave latch. The gated input clock is derived from an ungated input clock signal and a clock gating condition. The clock gating condition determines when an input data signal of the flip-flop and the stored internal state of the slave latch have the same logic value, such as only a logic low value. If they have the same value, toggling of the ungated input clock signal is not received by the slave latch, signal switching of internal nodes of the slave latch is reduced, and power consumption is reduced. | 2009-10-15 |
20090256610 | Quadrature phase correction circuit - A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out; a storage configured to store N-bit code values according to a plurality of detected phase differences; and a controller configured to share the N-bit code counter, control the generation of the N-bit code values according to the plurality of detected phase differences, and control the storing of the N-bit code values in an allocated space of the storage. | 2009-10-15 |
20090256611 | Semiconductor device and timing adjusting method for semiconductor device - In a semiconductor device, a delaying circuit is configured to delay an input signal based on an internal setting data to output as a timing signal. A delay determining section is configured to determine a delay state of each of a plurality of delay signals obtained by delaying the timing signal, based on the plurality of delay signals. A program section is configured to change the internal setting data based on the delay state. | 2009-10-15 |
20090256612 | DELAY CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A delay circuit that includes a logic gate through which an input signal passes, a capacitor configured to be charged and discharged at an output terminal of the logic gate and delaying the input signal, and a mirroring unit configured to constantly maintain current output by the logic gate by mirroring current output by a constant current source. | 2009-10-15 |
20090256613 | PULSE SIGNAL GENERATING DEVICE, TRANSPORT DEVICE, IMAGE FORMING APPARATUS, AND PULSE GENERATING METHOD - A pulse signal generating device includes: an encoder that outputs a pulse with a period corresponding to the speed of an object to be detected; a measurement unit that measures a period of the pulse; a storage unit that stores the measured period; an operation unit that calculates a reasonable period, which is estimated to be statistically reasonable, on the basis of a result of period measurement of a plurality of pulses; a detection unit that detects period abnormalities when the measured period of the measurement unit satisfies a period abnormality condition specified from the reasonable period; and a pulse generating unit that generates a pulse on the basis of the measured period when the period abnormalities are not detected and generates a pulse on the basis of the reasonable period when the period abnormalities are detected. | 2009-10-15 |
20090256614 | Apparatus and Method for Generating Clock Signal - The invention is related to an apparatus and a method for generating an output clock. The method comprises: receiving a transmitted signal comprising at least one data signal and at least one synchronized signal; producing a reference signal according to the synchronization signal; counting the first reference signal according to a free-run clock outputted by a free-run clock generator to produce a counter signal; and generating the output clock according to the counter signal and the free-run clock. | 2009-10-15 |
20090256615 | PULSE SIGNAL GENERATING DEVICE, TRANSPORT DEVICE, IMAGE FORMING APPARATUS, AND PULSE GENERATING METHOD - A pulse signal generating device includes: the plurality of encoders each of which outputs an encoder signal with a pulse period corresponding to the speed of an object to be detected; delay amount control unit that controls a relative delay amount with respect to a pulse signal for each of the plurality of pulse output signals output from the plurality of encoders; a detection unit that individually detects abnormalities in pulses of the plurality of encoder signals; a switching unit that performs switching to one pulse output signal, in which pulse abnormalities are not detected, of the plurality of pulse output signals; and a pulse generating unit that generates a pulse signal by delaying the one pulse output signal switched by the switching unit by the corresponding relative delay amount. | 2009-10-15 |
20090256616 | HOT SWAP CONTROLLER WITH ZERO LOADED CHARGE PUMP - The present invention includes a pass transistor that limits current drawn from a circuit without using a series resistor and while drawing minimal current from an external supply. A current mirror of the output current is formed and compared to a reference current. When the output current increases, the mirror current increases proportionally, and when a threshold is crossed, the pass transistor is turned off. The pass transistor is biased from a charge pump that provides a voltage, a current from which a current mirror is drawn that controls the pass transistor. | 2009-10-15 |
20090256617 | VOLTAGE LEVEL SHIFTER - Methods, systems, and devices are described for providing voltage level shifting that may operate reliably and at low power, even at high voltages and/or high switching frequencies. Embodiments receive an input signal representing input information, and effectively generate two voltage responses as a function of the input signal. Each voltage response includes exponential terms as a function of resistive and capacitive loading effects of components of the embodiments. A combined response signal is generated substantially as a superposition of the first response signal and the second response signal. A high-side driver signal is then generated as a function of the combined response signal, such that the high-side driver signal substantially preserves the input information represented by the input signal, and such that the first exponential response and the second exponential response are substantially absent from the high-side driver signal. | 2009-10-15 |
20090256618 | SWITCHING ELEMENT DRIVING DEVICE AND SWITCHING ELEMENT DRIVING METHOD - A switching element driving device has a first transistor that decreases the gate voltage of a power element at a faster rate than during a normal turn-off, and a second transistor that decreases the gate voltage of the power element at a slower rate than during a normal turn-off. If the gate voltage detected by the gate voltage monitoring means when an overcurrent in the power element is detected by overcurrent detection means is greater than a predetermined value, the gate voltage is decreased by the first transistor, and then, while the power element remains on, the gate voltage is decreased by the second transistor. If the gate voltage detected by the gate voltage monitoring means when an overcurrent in the power element is detected by overcurrent detection means is less than or equal to the predetermined value, the gate voltage is decreased only by the second transistor. | 2009-10-15 |
20090256619 | HIGH-SIDE DRIVER - A high-side driving circuit is provided, where Q terminal and | 2009-10-15 |
20090256620 | PROGRAMMABLE SIGNAL ROUTING - A distributed signal multiplexer circuit programmably routes electronic signals. The circuit includes at least two distributor subcircuits. Each distributor subcircuit is configured to connect an input port to an output port through a switch, with a state of each switch being controlled by information received at a control port. The first and second distributor subcircuits are part of a first and second power domain, respectively. The distributed multiplexer circuit also includes an aggregator subcircuit. The aggregator subcircuit is configured to have a first input port connected with the output port of the first distributor subcircuit, a second input port connected to the output port of the second distributor subcircuit, and the output port signal being a signal selected from among the signals received at the input ports of the distributor subcircuits. | 2009-10-15 |
20090256621 | Signal transfer circuit - There is provided a signal transfer circuit, comprising a first pull-up transistor and a first pull-down transistor configured to drive a first signal transmission line in response to a signal of a second signal transmission line, a first path controlling unit configured to prevent a signal from being transferred through a first path by controlling a gate of the first pull-up transistor and a gate of the first pull-down transistor when a first path enable signal is deactivated, a second pull-up transistor and a second pull-down transistor configured to drive the second signal transmission line in response to a signal of the first signal transmission line, and a second path controlling unit configured to prevent a signal from being transferred through a second path by controlling a gate of the second pull-up transistor and a gate of the second pull-down transistor when a second path enable signal is deactivated. | 2009-10-15 |
20090256622 | SOFT THERMAL FAILURE IN A HIGH CAPACITY TRANSMISSION SYSTEM - A method of managing operation of an Integrated Circuit (IC) designed to process a signal A temperature of the IC is detected, and signal processing performed by the IC adjusted based on the detected temperature. | 2009-10-15 |
20090256623 | Temprature sensor circuit - In a temperature sensor circuit, a temperature sensor is configured to output a first voltage corresponding to temperature. A voltage source is configured to output a second voltage having the same nonlinear dependence on the temperature as a nonlinear dependence of the first voltage on the temperature. An amplifier is configured to amplify the second voltage with a first amplification factor to output a third voltage. An inversion amplifier is configured to perform inversion amplification on a difference between the first voltage and the third voltage with a second amplification factor to output a fourth voltage. | 2009-10-15 |
20090256624 | Antifuse and methods of operating and manufacturing the same - Provided are an antifuse and methods of operating and manufacturing the same. The antifuse may include first and second conductors separate from each other; a dielectric layer for an antifuse between the first and second conductors; and a diffusion layer between one of the first and second conductors and the dielectric layer. | 2009-10-15 |