41st week of 2010 patent applcation highlights part 37 |
Patent application number | Title | Published |
20100261261 | CELL/TISSUE MASS SELECTING APPARATUS AND DIVIDING MECHANISM THEREOF - A selecting apparatus for selecting cell/tissue mass includes a base, a feeding mechanism and a dividing mechanism. The base has a platform for placing the cell/tissue mass. The feeding mechanism, disposed on the base, moves relative to the platform. The dividing mechanism, disposed on the feeding mechanism, includes a first cutting set and a second cutting set connected therewith. The second cutting set reciprocally moves between a first position and a second position, toward the first cutting set. The feeding mechanism moves the dividing mechanism above the platform, aligning the dividing mechanism with a portion of the cell/tissue mass, and moves the first cutting set toward the cell/tissue mass, cutting into the portion of the cell/tissue mass. The second cutting set moves from the first position to the second position, limiting the portion of the cell/tissue mass between the first cutting set and the second cutting set. | 2010-10-14 |
20100261262 | SYSTEM FOR FORMING AND MAINTAINING BIOLOGICAL TISSUE | 2010-10-14 |
20100261263 | UP AND DOWN CONVERSION SYSTEMS FOR PRODUCTION OF EMITTED LIGHT FROM VARIOUS ENERGY SOURCES - A system for energy upconversion and/or down conversion and a system for producing a photostimulated reaction in a medium. These systems include 1) a nanoparticle configured, upon exposure to a first wavelength λ | 2010-10-14 |
20100261264 | TEST APPARATUS - A test apparatus is disclosed for measuring a component. The test apparatus maintains the amount of a specimen to be used for a reaction with a reagent at a constant value by allowing all of a fluid specimen to be measured and thus improves the accuracy and reproducibility of a test. The test apparatus includes a solution storage unit capable of holding a solution beforehand or allowing a solution to be filled therein, a capillary having a first end part and a second end part for storing the fluid specimen, and a test piece for measuring the component to be measured in the specimen. The solution storage unit and the second end part of the capillary are communicable with each other, and the first end part of the capillary is placed so as to be in contact with the test piece. | 2010-10-14 |
20100261265 | METHOD AND DEVICE FOR TESTING CELL RESPONSES TO POLYMER PARTICLES IN VITRO - This invention provides a method and device for testing cell responses to polymer particles in vitro. Cells and culture medium are added to a 24-well plate and incubated for 24 hours to make the cells adhere to the interior bottom surface of the plate. The old medium is then drained out and fresh medium and polymer particles are added to fill up the wells. The plate was covered with a light and transparent film such as polyvinyl chloride (PVC) with small holes for ventilation and inverted carefully. The polymer particles float and contact with the cells adhered to the interior bottom surface of the plate. Then the cells are incubated for an intended period for further experiments. | 2010-10-14 |
20100261266 | BIOLOGICAL DESULFURIZATION APPARATUS - Disclosed is a biological desulfurization apparatus including a reaction tower | 2010-10-14 |
20100261267 | Circular permutant GFP insertion folding reporters - Provided are methods of assaying and improving protein folding using circular permutants of fluorescent proteins, including circular permutants of GFP variants and combinations thereof. The invention further provides various nucleic acid molecules and vectors incorporating such nucleic acid molecules, comprising polynucleotides encoding fluorescent protein circular permutants derived from superfolder GFP, which polynucleotides include an internal cloning site into which a heterologous polynucleotide may be inserted in-frame with the circular permutant coding sequence, and which when expressed are capable of reporting on the degree to which a polypeptide encoded by such an inserted heterologous polynucleotide is correctly folded by correlation with the degree of fluorescence exhibited. | 2010-10-14 |
20100261268 | Superoxide dismutase (SOD) gene and a method of identifying and cloning thereof - The present invention provides a superoxide dismutase gene from | 2010-10-14 |
20100261269 | Activation and Expansion of T-Cells Using An Engineered Multivalent Signaling Platform as a Research Tool - Provided are a system and methods for selectively inducing expansion of a population of T cells in the absence of exogenous growth factors, such as lymphokines, and accessory cells for research purposes. The cell based expansion system and methods permit the long-term growth of CTLs, preferably human CTLs. In addition, T cell proliferation can be induced without the need for antigen, thus providing an expanded T cell population that is polyclonal with respect to antigen reactivity. Further provided are methods for using the system and methods to screen and identify antigens related to specific diseases or conditions, tumors, autoimmune disorders, or an infectious disease or pathogen, and to identify target molecule for research purposes, or for developing a vaccine based thereon. | 2010-10-14 |
20100261270 | PATTERNED CELL SHEETS AND A METHOD FOR PRODUCTION OF THE SAME - The present invention is related to a method for the production of cell sheets comprising at least two different cell types, said method comprising the steps of providing a continuous cell sheet which is disposed on a substrate comprising shape transition properties and/or alterable surface characteristics; exposing said continuous cell sheet to a releasing agent in a patterned fashion; washing the cell sheet after exposure to the releasing agent in order to remove cells which have been affected by the releasing agent, and repopulating the gaps remaining after the cells which have been affected by the releasing agent have been removed with a second cell type. | 2010-10-14 |
20100261271 | Regulation of endogenous gene expression in cells using zinc finger proteins - The present invention provides methods for modulating expression of endogenous cellular genes using recombinant zinc finger proteins. | 2010-10-14 |
20100261272 | Compositions for Reducing Cell Adhesion to Bubbles - Compositions and methods for reducing gas-cell surface interface damage include a protective composition having at least sugar moiety where the sugar moiety provides a hydrophilic component to the protective composition. | 2010-10-14 |
20100261273 | Mammalian Receptor Proteins; Related Reagents and Methods - Nucleic acids encoding mammalian, e.g., primate, receptors, purified receptor proteins and fragments thereof. Antibodies, both polyclonal and monoclonal, are also provided. Methods of using the compositions for both diagnostic and therapeutic utilities are described. | 2010-10-14 |
20100261274 | GENERATION OF CLONAL MESENCHYMAL PROGENITORS AND MESENCHYMAL STEM CELL LINES UNDER SERUM-FREE CONDITIONS - Methods for obtaining multipotent Apelin receptor-positive lateral plate mesoderm cells, mesenchymal stem cells, and mesangioblasts under serum-free conditions are disclosed. | 2010-10-14 |
20100261275 | Production of Recombinant Interferon Proteins - A method of purifying a recombinant interferon protein involves providing an aqueous mixture of the recombinant protein and contaminating proteins; precipitating the contaminating proteins from the aqueous mixture at a pH in a range of from 0.5 to 6; separating the aqueous mixture from the precipitated contaminating proteins; and, eluting the separated aqueous mixture through a cation exchange column using a mobile phase with a salt or pH gradient, the gradient being from lower salt concentration or pH to higher salt concentration or pH, to produce a recombinant interferon protein fraction separated from other components of the aqueous mixture. The method provides for the recovery of recombinant interferon proteins in better yield and purity. | 2010-10-14 |
20100261276 | Method For The Preparation Of Dermal Papilla Tissue Employing Mesenchymal Stem Cells - A method for the preparation of dermal papilla tissue comprising the step of culturing mesenchymal stem cells in a medium having a specific composition is provided. The method makes it possible to form in vitro a quantity of dermal papilla tissues having hair follicle inducting ability and, accordingly, it can be effectively used for the treatment of alopecia through cell transplantation. | 2010-10-14 |
20100261277 | METHODS AND COMPOSITIONS FOR ENHANCED DIFFERENTIATION FROM EMBRYONIC STEM CELLS - The invention provides methods for differentiating pluripotent stem cells such as ES cells with improved progenitor and differentiated cell yield using low oxygen conditions and optionally in the absence of exogenously added differentiation factors. | 2010-10-14 |
20100261278 | METHOD CAPABLE OF INCREASING COMPETENCY OF BACTERIAL CELL TRANSFORMATION - The invention concerns bacterial strains capable of enhanced transformation efficiencies that are produced by the introduction of the F′ genetic material. The invention also concerns processes for producing transformable competent bacteria with enhanced transformation efficiencies. | 2010-10-14 |
20100261279 | MASS SPECTRUM-BASED IDENTIFICATION AND QUANTITATION OF PROTEINS AND PEPTIDES - Method to quantitate peptides in a sample by mass spectroscopy wherein the improvement comprises providing internal standard peptides isobarically tagged at the N and C terminus. | 2010-10-14 |
20100261280 | Biological and chemical monitoring - A biological and chemical detection system is provided that detects and identifies biological and/or chemical particulates of interest. The biological and chemical detection system comprises a collector, a first optical device, a second optical device and a processor. The collector is configured to deposit particulates drawn from a fluid stream onto a sample substrate to define a sample area. The first optical device derives first data relative to at least a portion of the sample area, which is analyzed to determine at least one field of view and/or specific target location. The second optical device then interrogates the sample area at each determined target location, e.g., using Raman spectroscopy, to produce interrogation data. The processor determines whether the sample area includes predetermined biological or chemical particulates of interest based upon an analysis of the interrogation data and triggers an event such as an alarm or message if the predetermined biological or chemical particulates of interest are identified. | 2010-10-14 |
20100261281 | ANALYTICAL TECHNIQUE FOR MEASURING BOUND GLYCERIDES IN A BIODIESEL COMPOSITION - A method of estimating the amount of unreacted starting materials (glycerides, methyl esters, etc.) and the composition of a biodiesel using TLC in conjunction with a lipophilic dye, Nile Red is described herein. The dye based TLC method of the present invention is convenient and provides significant advantages over existing methods for estimating the purity of a biodiesel composition. | 2010-10-14 |
20100261282 | Method of evaluating IGT, IGT-evaluating apparatus, IGT-evaluating method, IGT--evaluating system, IGT-evaluating program, recording medium, and method of searching for prophylactic/ameliorating substance for IGT - According to the method of evaluating IGT of the present invention, amino acid concentration data on concentration values of amino acids in blood collected from a subject to be evaluated is measured, and an impaired glucose tolerance state in the subject is evaluated based on the measured amino acid concentration data of the subject. | 2010-10-14 |
20100261283 | SURFACTANT PROTEINS B AND D FOR DIFFERENTIAL DIAGNOSIS OF DYSPNEA - The present invention relates to means and methods for differentially diagnosing the cause of acute shortness of breath. Specifically, contemplated is a method of differentiating in a subject suffering from shortness of breath (dyspnea) between a pulmonary disease and a cardiovascular complication as the cause of the dyspnea comprising the steps of determining the amount of SP-B and SP-D in a sample of a subject and comparing the amounts of SP-B and SP-D with reference amounts, whereby it is differentiated between a pulmonary disease and a cardiovascular complication as the cause of the dyspnea. Furthermore, the present invention encompasses a device and a kit adopted for carrying out the aforementioned method. | 2010-10-14 |
20100261284 | USING GDF 15 TO ASSESS PATIENTS PRESENTING TO EMERGENCY UNITS - Described is a method of identifying if a subject is to be admitted to the hospital or intensive care unit, the method comprising a) determining the amount of GDF 15 in a sample of the subject, and b) comparing the amount of GDF 15 determined in step a) to a reference amount, whereby a subject to be admitted to the hospital or intensive care unit is to be identified. Also described is a method for predicting the risk of mortality based on determining the amount of GDF 15 in a subject. Also described are devices and kits for carrying out the aforementioned methods. | 2010-10-14 |
20100261285 | TAGGED-FRAGMENT MAP ASSEMBLY - A method for determining a sequence of a biomolecule, the method including binding a plurality of uniform probes to a biomolecule fragment, creating a collection of binding signatures for the fragment with each binding signature representing a series of distances between binding sites within the fragment, and grouping the binding signatures into a plurality of signature clusters based at least in part on distances between the binding sites in each binding signature. For each binding signature in a first cluster, a potential successor binding signature is selected from signature clusters other than the first signature cluster, and one of the potential successor binding signatures is identified as a successor binding signature. The last two steps are repeated until the successor signature represents a terminal signature, resulting in a sequence of signatures representing at least a portion of the biomolecule. | 2010-10-14 |
20100261286 | Microfluidic devices and methods of preparing and using the same - Microfluidic devices include a photoresist layer in which an inlet chamber, an optional reaction chamber and at least one detection chamber are in fluid contact, a support arranged under the photoresist layer and a cover arranged above the photoresist layer. The devices further include a set of absorbent channels downstream of the last detection chamber. Biogenic or immunoreactive substances are placed in the reaction chamber and detection chamber(s). When a liquid sample is dropped into the inlet chamber, the sample liquid is drawn through the devices by capillary action. Detection methods include electrochemical detection, colorimetric detection and fluorescence detection. | 2010-10-14 |
20100261287 | Method and apparatus for match quality analysis of analyte binding - Described are devices and methods for detecting the match quality and concentration of analytes binding to an electrode surface. The devices utilize a clock to measure capacitance change as a function of time and a temperature controller to measure the capacitance change as a function of temperature. | 2010-10-14 |
20100261288 | TIP TRAY ASSEMBLY FOR OPTICAL SENSORS - An apparatus and method for packaging of an optical sensing fiber is disclosed. The apparatus includes a substrate with a plurality of openings, and each opening is configured for holding an optical sensing assembly. The assembly is positioned in the opening with a tip of the assembly extending through the opening to be suspended from the substrate. In addition, openings are arranged so the assembly positioned therein avoids contacting another assembly positioned therein. The apparatus can include a support member for supporting the substrate and positioning the substrate so the tip of the assembly suspended from the opening in the substrate contacts solution in one of a plurality of wells in a container adjacent to the substrate. The assembly can be configured for preparing of the optical assembly for assay. An agitation assembly for agitating the container to create flow of the solution in the container wells over an optical sensing assembly is also disclosed. | 2010-10-14 |
20100261289 | WATER-SOLUBLE POLYMERS HAVING CHELATORS - The present invention relates to a functionalized polymer having a high solubility in at least one solvent having high E | 2010-10-14 |
20100261290 | Method of reaction in flow channel of microchip and analysis device - In the case of passing a reagent in a reaction channel in a microchip, which carries a reactant capable of reacting with the reagent on the wall thereof, and bringing the reactant into contact with the reagent so as to carry out a reaction, the reagent is efficiently passed to the reactant to thereby promote the progress of the reaction. In carrying out the reaction as described above, the reagent ( | 2010-10-14 |
20100261291 | Nucleic acids specifically binding bioactive ghrelin - The present invention is related to a nucleic acid specifically binding bioactive ghrelin, more preferably n-octanoyl ghrelin, and its use for the diagnosis of ghrelin mediated diseases and disorders. | 2010-10-14 |
20100261292 | Methods for Conducting Assays - The invention relates to methods for conducting solid-phase binding assays. One example is an assay method having improved analyte specificity where specificity is limited by the presence of non-specific binding interactions. | 2010-10-14 |
20100261293 | DIAGNOSTIC DETECTION DEVICE - The invention comprises a device for detecting an analyte in a liquid sample deposited on a first portion of the device for transport to a second portion of the device that is in fluid contact with the first portion. In specific embodiments, the device comprises a labeled conjugate comprising a binding member reactive with a first epitope of the analyte and a label comprising a gold colloid, preferably having a mean particle size of 50 nm to 100 nm. In further embodiments, the device comprises a capture component comprising polymerized streptavidin. The diagnostic device is particularly useful in the preparation of pregnancy test kits. | 2010-10-14 |
20100261294 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - After a first via hole leading to a ferroelectric capacitor structure are formed in an interlayer insulating film by dry etching, a second via hole to expose part of the ferroelectric capacitor structure is formed in a hydrogen diffusion preventing film so as to be aligned with the first via hole by wet etching, and a via hole constructed by the first via hole and the second via hole communicating with each other is formed. | 2010-10-14 |
20100261295 | High performance MTJ element for STT-RAM and method for making the same - A method of forming a STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co | 2010-10-14 |
20100261296 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is disclosed. The semiconductor device includes a ferroelectric capacitor formed on a substrate and a wiring structure formed on the ferroelectric capacitor. The wiring structure includes a dielectric inter layer and a Cu wiring section formed in the dielectric inter layer. In addition, an etching stopper layer including a hydrogen diffusion preventing layer is formed so as to face the dielectric inter layer. | 2010-10-14 |
20100261297 | REMOTE CHIP ATTACHMENT - A method of attaching a pair of chips, each having primary contacts that can be mated to each other, involves forming one or more secondary contacts on each of the two chips of a shape sufficient to prevent an initial attachment material from contacting any of the primary contacts during a preliminary attachment operation, the secondary contacts further having a height that will prevent the primary contacts from touching when the secondary contacts are brought into contact with each other, bringing the secondary contacts into closer and closer aligned proximity to each other at least until the primary contacts touch in a first phase, and heating the primary contacts until material between each of corresponding primary contacts on each of the chips in the pair forms an electrical connection. | 2010-10-14 |
20100261298 | CURVATURE REDUCTION FOR SEMICONDUCTOR WAFERS - A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ≦5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization. | 2010-10-14 |
20100261299 | PACKAGING PROCESS OF LIGHT EMITTING DIODE - A packaging process of a light emitting diode (LED) is provided. First, an LED chip is bonded with a carrier to electrically connect to each other. After that, the carrier is heated to raise the temperature thereof. Next, an encapsulant is formed on the heated carrier by a dispensing process to encapsulate the LED chip, wherein the viscosity of the encapsulant before contacting the carrier is lower than that of the encapsulant after contacting the carrier. Thereafter, the encapsulant is cured. | 2010-10-14 |
20100261300 | METHOD FOR SEPARATING SUBSTRATE FROM SEMICONDUCTOR LAYER - A method for separating an epitaxial substrate from a semiconductor layer initially forms a patterned silicon dioxide layer between a substrate and a semiconductor layer, and then separates the substrate from the patterned silicon dioxide layer using two wet etching processes. | 2010-10-14 |
20100261301 | COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE - A compound semiconductor light-emitting device has a light-emitting layer, on a substrate, wherein at least a part of a substrate portion of the device side surface has recessed portions in a side direction of the device. A method of producing the compound semiconductor light-emitting device includes the steps of: (a) forming a compound semiconductor layer including a light-emitting layer of an n-type or p-type compound semiconductor on a wafer that serves as a substrate, (b) arranging a negative electrode and a positive electrode at predetermined positions for passing a drive current through the light-emitting layer, (c) forming a separation zone for separating the individual light-emitting devices, (d) perforating many small holes linearly in the wafer that serves as the substrate along the separation zone, and (e) dividing the wafer into individual light-emitting devices along the separation zone, whereby a rugged shape which is periodical in a side direction and is undulating in a plane or cross section, is formed on a substrate side surface of the light-emitting device. | 2010-10-14 |
20100261302 | DRY CLEANING OF SILICON SURFACE FOR SOLAR CELL APPLICATIONS - A method and apparatus for cleaning layers of solar cell substrates is disclosed. The substrate is exposed to a reactive gas that may comprise neutral radicals comprising nitrogen and fluorine, or that may comprise anhydrous HF and water, alcohol, or a mixture of water and alcohol. The reactive gas may further comprise a carrier gas. The reactive gas etches the solar cell substrate surface, removing oxygen and other impurities. When exposed to the neutral radicals, the substrate grows a thin film containing ammonium hexafluorosilicate, which is subsequently removed by heat treatment. | 2010-10-14 |
20100261303 | Manufacturing method for solid state image pickup device - A method of manufacturing a solid state image pickup device including photoelectric conversion elements which are two-dimensionally arranged in a semiconductor substrate, and a color filter having a plurality of color filter patterns differing in color from each other and disposed on a surface of the semiconductor substrate according to the photoelectric conversion elements. The method includes successively subjecting a plurality of filter layers differing in color from each other to a patterning process to form the plurality of color filter patterns. At least one color filter pattern to be formed at first among the plurality of color filter patterns is formed by dry etching, and the rest of the plurality of the color filter pattern is formed by photolithography. | 2010-10-14 |
20100261304 | Solution-based process for making inorganic materials - Disclosed embodiments provide a solution-based process for producing useful materials, such as semiconductor materials. One disclosed embodiment comprises providing at least a first reactant and a second reactant in solution and applying the solution to a substrate. The as-deposited material is thermally annealed to form desired compounds. Thermal annealing may be conducted under vacuum; under an inert atmosphere; or under a reducing environment. The method may involve using metal and chalcogen precursor compounds. One example of a metal precursor compound is a metal halide. Examples of suitable chalcogen precursor compounds include a chalcogen powder, a chalcogen halide, a chalcogen oxide, a chalcogen urea, a chalcogen or dichalcogen comprising organic ligands, or combinations thereof. Certain disclosed embodiments concern a method for making a solar cell from I-III-VI semiconductors. | 2010-10-14 |
20100261305 | Method for making multi-cystalline film of solar cell - A method is disclosed to make a multi-crystalline silicon film of a solar cell. The method includes the step of providing a ceramic substrate, the step of providing a titanium-based film on the ceramic substrate, the step of providing a p | 2010-10-14 |
20100261306 | Method of Making Photovoltaic Cell - A photovoltaic cell is made by coating a metal foil substrate with cadmium telluride powder, moving the powder coated foil across a cold plate or series of cooled rollers to prevent the substrate from melting, while melting the cadmium telluride powder by passing the powder coated foil under a microwave energy source. This forms a thin film of cadmium telluride on the foil. The cadmium telluride coated foil is then coated with cadmium sulfide powder, which is melted by passing the powder coated foil under a microwave energy source, thereby creating a P-N junction, and the cadmium sulfide layer is coated with indium, which is fused to the cadmium sulfide layer by microwave heating. | 2010-10-14 |
20100261307 | PATTERNING ELECTRODE MATERIALS FREE FROM BERM STRUCTURES FOR THIN FILM PHOTOVOLTAIC CELLS - A method for forming a thin film photovoltaic device having patterned electrode films includes providing a soda lime glass substrate with an overlying lower electrode layer comprising a molybdenum material. The method further includes subjecting the lower electrode layer with one or more pulses of electromagnetic radiation from a laser source to ablate one or more patterns associated with one or more berm structures from the lower electrode layer. Furthermore, the method includes processing the lower electrode layer comprising the one or more patterns using a mechanical brush device to remove the one or more berm structures followed by treating the lower electrode layer comprising the one or more patterns free from the one or more berm structures. The method further includes forming a layer of photovoltaic material overlying the lower electrode layer and forming a first zinc oxide layer overlying the layer of photovoltaic material. | 2010-10-14 |
20100261308 | SOLAR CELL AND PROCESS FOR PRODUCING THE SAME - The present invention provides a method of manufacturing a solar cell, comprising forming a buffer layer comprising a group-III nitride semiconductor on a substrate using a sputtering method, and forming a group-III nitride semiconductor layer and electrodes on the buffer layer. The group-III nitride semiconductor layer is formed on the buffer layer by at least one selected from the group consisting of the sputtering method, a MOCVD method, an MBE method, a CBE method, and an MLE method, and the electrodes are formed on the group-III nitride semiconductor layer. | 2010-10-14 |
20100261309 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device in which a second semiconductor chip is bonded to a surface of a first semiconductor chip. The method includes: a back side grinding step for grinding the back side of a wafer including a device area where a plurality of first semiconductor chips are formed, the grinding applied to an area corresponding to the device area, so as to reduce the thickness of the wafer in the device area to a predetermined finished thickness; a chip bonding step for bonding the second semiconductor chip to a predetermined position of the surface of each of the first semiconductor chips formed on the face-side surface of the wafer; and a wafer dividing step for dividing the wafer along streets to separate the device area of the wafer into individual semiconductor devices in each of which the second semiconductor chip is bonded to the surface of the first semiconductor chip. | 2010-10-14 |
20100261310 | Via First Plus Via Last Technique for IC Interconnect - A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias. | 2010-10-14 |
20100261311 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A chip stack is created by stacking a plurality of semiconductor chips while connecting respective through electrodes of the semiconductor chips to each other, and forming a first sealing resin layer for covering the periphery of the plurality of stacked semiconductor chips, and filling gaps between the semiconductor chips. Subsequently, the chip stack is fixed on a supporting board or a wiring board which is formed with predetermined wiring. | 2010-10-14 |
20100261312 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - While an adhesive layer is provided over the rear surface of a semiconductor chip in die bonding, a lamination processing (main pressure bonding) is necessary for securing the adhesive state of the adhesive layer after the die bonding process (temporary pressure bonding). In this case, typically the hardening of the adhesive is developed by applying heat while pressing down the rear surface of the chip from above with a pressurization member. It has become clear that various problems exist in the lamination processing of the laminate chips by such a mechanical pressurization method as the chip becomes thinner. That is, the problems include chip damage at a part in an overhang state, a chip position shift caused by bending and non-uniform pressurization, and the like. | 2010-10-14 |
20100261313 | SEMICONDUCTOR PACKAGE AND METHOD OF PACKAGING SEMICONDUCTOR DEVICES - A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate. | 2010-10-14 |
20100261314 | THERMOSETTING DIE BONDING FILM - The present invention has been made and an object thereof is to provide a thermosetting die-bonding film which can remarkably reduce working hours at the time of die bonding of a semiconductor chip, and a dicing die-bonding film including the thermosetting die-bonding film and a dicing film layered to each other. The present invention relates to a thermosetting die-bonding film used to produce a semiconductor device, comprising a thermosetting catalyst in a non-crystalline state in an amount within a range from 0.2 to 1 part by weight based on 100 parts by weight of an organic component in the film. | 2010-10-14 |
20100261315 | WAFER LEVEL PACKAGING METHOD - A wafer level packaging method is revealed. Firstly, a wafer with a plurality of bumps disposed on a surface is provided. Placing a dielectric tape on a mold plate is followed. Then, the wafer is laminated with the mold plate to make the dielectric tape be compliantly bonded to the surface of the wafer and to make the bumps be embedded in the dielectric tape. After removing the mold plate, flattening the dielectric tape to form a plurality of exposed surfaces of the bumps wherein the exposed surfaces and the flattened surface of the dielectric tape are coplanar. Therefore, the exposed surfaces of the bumps can be regarded as effective alignment points for easy pattern recognition of the wafer level packaged wafers during singulation process. | 2010-10-14 |
20100261316 | SEMICONDUCTOR DEVICE WITH SURFACE MOUNTING TERMINALS - A semiconductor device has a sealing body formed of an insulating resin and a semiconductor chip positioned within the sealing body. A gate electrode and a source electrode are on a first main surface of the semiconductor chip and a back electrode (drain electrode) is on a second main surface thereof. An upper surface of a portion of a drain electrode plate that projects in a gull wing shape is exposed from the sealing body and a lower surface thereof is connected to the back electrode through an adhesive. A gate electrode plate projects in a gull wing shape on an opposite end side of the sealing body and is connected to the gate electrode within the sealing body. A source electrode plate projects in a gull wing shape on the opposite end side of the sealing body and is connected to the source electrode within the sealing body. | 2010-10-14 |
20100261317 | OFFSET NON-VOLATILE STORAGE - A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements. | 2010-10-14 |
20100261318 | 3D CHIP-STACK WITH FUSE-TYPE THROUGH SILICON VIA - Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack. | 2010-10-14 |
20100261319 | N-type carrier enhancement in semiconductors - A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage. Repeating the implantation and the thermal annealing until the target n-type carrier concentration has been reached. | 2010-10-14 |
20100261320 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps. | 2010-10-14 |
20100261321 | METHOD FOR MANUFACTURING FLEXIBLE SEMICONDUCTOR DEVICE - There is provided a method for manufacturing a flexible semiconductor device. The manufacturing method is characterized by comprising (i) a step of forming an insulating film on the upper surface of a resin film, (ii) a step of forming a pattern of extraction electrodes on the upper surface of the resin film, (iii) a step of forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the pattern of extraction electrodes, and (iv) a step of forming a sealing resin layer on the upper surface of the resin film in such a manner that the sealing resin layer covers the semiconductor layer and the pattern of extraction electrodes, wherein at least one forming step among the above (i) to (iv) is carried out by a printing method. In the manufacturing method, various layers can be formed by a simple printing process without using a vacuum process, photolithography, or the like. | 2010-10-14 |
20100261322 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed. | 2010-10-14 |
20100261323 | METHOD OF FORMING METAL-OXIDE-SEMICONDUCTOR TRANSISTOR - A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has agate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Thereafter, a stressed cap layer is formed on the stress buffer layer, and a tensile stress value of the stressed cap layer is higher than a tensile stress value of the stress buffer layer. Since the stress buffer layer can prevent the stressed cap layer from breaking, the MOS transistor device can be covered by a stressed cap layer having an extremely high tensile stress value in the present invention. | 2010-10-14 |
20100261324 | Trap-charge non-volatile switch connector for programmable logic - A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion. | 2010-10-14 |
20100261325 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING A DUAL GATE INSULATION LAYER - A method for manufacturing a semiconductor device having a dual gate insulation layer is presented. The method includes a step of forming a first insulation layer on a semiconductor substrate which has a first region and a second region. The method includes a step of selectively removing a portion of the first insulation layer formed the second region of the semiconductor substrate. The removal of the portion of the first insulation layer is conducted using an etching solution comprising propylene glycol, HF and amine. The method also includes a step of forming a second insulation layer on the first insulation layer in the first region and on the semiconductor substrate in the second region. | 2010-10-14 |
20100261326 | ISOLATED-NITRIDE-REGION NON-VOLATILE MEMORY CELL AND FABRICATION METHOD - An isolated-nitride-region non-volatile memory cell is formed in a semiconductor substrate. Spaced-apart source and drain regions are disposed in the semiconductor substrate forming a channel therebetween. An insulating region is disposed over the semiconductor substrate. A gate is disposed over the insulating region and is horizontally aligned with the channel. A plurality of isolated nitride regions are disposed in the insulating region and are not in contact with either the channel or the gate. | 2010-10-14 |
20100261327 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n | 2010-10-14 |
20100261328 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING FIN-FIELD EFFECT TRANSISTOR - A semiconductor device includes an element isolation region formed in a semiconductor substrate, an active region surrounded by the element isolation region, and a gate electrode formed in one direction to cross the active region. The semiconductor substrate includes two gate trenches formed in parallel to a major axis direction of the active region in the active region, and a fin-shaped part which is located between the two gate trenches. The gate electrode is buried in the two gate trenches and formed on the fin-shaped part. The fin-shaped part serves as a channel region. A fin field effect transistor in which a width of the channel region is smaller than a gate length is thereby obtained. | 2010-10-14 |
20100261329 | MEMORY DEVICE HAVING WIDE AREA PHASE CHANGE ELEMENT AND SMALL ELECTRODE CONTACT AREA - A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. Methods for making the memory cell are described. | 2010-10-14 |
20100261330 | METHOD OF MANUFACTURING NONVOLATILE STORAGE DEVICE - A method of manufacturing a nonvolatile storage device having memory cell arrays according to an embodiment of the present invention includes forming, in a memory cell array forming region above a processed film, first columnar members arrayed at substantially equal intervals in the first direction and the second direction, forming, concerning at least arrays as a part of arrays of the first columnar members in the first direction, second columnar members long in section having major axes longer than sections of the first columnar members outside of the memory cell array forming region such that the major axes are set in the first direction and the second columnar members continue to ends of the arrays, and forming, in the same manner as above, third columnar members, which continue to arrays of the first columnar members in the second direction. | 2010-10-14 |
20100261331 | Methods Of Forming A Plurality Of Capacitors - The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node locations. Insulative material is deposited over the first material laterally about sidewalls of the projecting pillars, and is anisotropically etched effective to expose underlying first material and leave electrically insulative material received laterally about the sidewalls of the projecting pillars. Openings are formed within a second material to the pillars. The pillars are etched from the substrate through the openings in the second material, and individual capacitor electrodes are formed within the openings in electrical connection with the storage node locations. The individual capacitor electrodes have the anisotropically etched insulative material received laterally about their outer sidewalls. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other implementations and aspects are contemplated. | 2010-10-14 |
20100261332 | WAFER CLEANING METHOD AND WAFER BONDING METHOD USING THE SAME - The present invention relates to a wafer cleaning and a wafer bonding method using the same that can improve a yield of cleaning process and bonding property in bonding the cleaned wafer by cleaning the wafer using atmospheric pressure plasma and cleaning solution. The wafer cleaning method includes the steps of providing a process chamber with a wafer whose bonding surface faces upward, cleaning and surface-treating the bonding surface of the wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the wafer, and withdrawing out the wafer from the process chamber. The wafer bonding method includes the steps of: providing a first process chamber with a first wafer whose bonding surface faces upward; cleaning and surface-treating the bonding surface of the first wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the first wafer; withdrawing out the first wafer from the first process chamber and providing a second process chamber with the first wafer; providing a third process chamber with a second wafer whose bonding surface faces upward; cleaning and surface-treating the bonding surface of the second wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the second wafer; withdrawing out the second wafer from the third process chamber and providing the second process chamber with the second wafer whose bonding surface faces to the bonding surface of the first wafeη and bonding the bonding surfaces of the first and second wafers to each other. | 2010-10-14 |
20100261333 | Silicon carbide semiconductor device and manufacturing method therefor - With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate. | 2010-10-14 |
20100261334 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region. | 2010-10-14 |
20100261335 | PROCESS FOR WET SINGULATION USING A DICING MOAT STRUCTURE - A method includes receiving at least one wafer having a front side and a backside, where the front side has a plurality of integrated circuit chips thereon. The backside of the wafer is thinned, a pattern of material is removed from the backside of the wafer to form a plurality of dicing trenches. Each of the dicing trenches are positioned opposite a location on the front side of the wafer that corresponds to edges of each of the plurality of chips. The dicing trenches are filled with a filler material and a dicing support is attached to a front side of the wafer. The filler material is removed from the dicing trenches, and a force is applied to the dicing support to separate each of the plurality of chips on the wafer from each other along the dicing trenches. | 2010-10-14 |
20100261336 | Chip manufacturing method - A substrate table used for manufacturing a chip is provided. The substrate table includes a substrate stage, a substrate placement surface formed on the substrate stage, and on which a substrate is placed, and a guiding member that can project and retract from the substrate placement surface. The guiding member positions the substrate when the guiding member is at a projected position abutting an edge portion of the substrate placed on the substrate placement surface, and the guiding member retracts at a time of applying a tape to the substrate. | 2010-10-14 |
20100261337 | METHOD FOR MANUFACTURING DIES FORMED WITH A DIELECTRIC LAYER - A method of manufacturing dies formed with a dielectric layer is revealed. A liquid dielectric layer is formed on the dicing tape. The liquid dielectric layer is heated to be sticky. Then, a wafer is attached to the dielectric layer on the dicing tape. The wafer is diced into a plurality of dies on the dicing tape. The dies with attached portions of the dielectric layer are picked up to be peeled and separated from the dicing tape. The implementation of the dicing tape can be expanded to resolve various issues such as wafer contaminations, wafer warpage due to multiple heating and mismatching of thermal expansion coefficients, and wafer singulating problems due to alignment difficulties. The wafer handling steps can further be reduced to increase processing yield and to enhance easy and better processing. | 2010-10-14 |
20100261338 | Nanostructures, methods of depositing nanostructures and devices incorporating the same - A method for depositing nanowires is disclosed. The method includes depositing multiple nanowires onto a surface of a liquid. The method also includes partially compressing the nanowires. The method also includes dipping a substrate into the liquid. The method further includes pulling the substrate out of the liquid at a controlled speed. The method also includes transferring the nanowires onto the substrate parallel to a direction of the pulling. | 2010-10-14 |
20100261339 | SINGLE CRYSTAL GROWTH ON A MIS-MATCHED SUBSTRATE - A process for forming a single crystal layer of one material type such as III-V semiconductor) onto a substrate of a different material type such as silicon. A substrate of a first material type is provided. At least one discrete region of catalyst material is deposited onto the substrate, the discrete region defining a seed area of the substrate. A second material type such as III-V semiconductor is grown as a single crystal nanowire onto the substrate between the substrate and catalyst material, the nanowire of second material type extending upward from the substrate with lateral dimensions not substantially exceeding the seed area. After growth of the nanowire, growth conditions are changed so as to epitaxially grow the second material type laterally from the single crystal nanowire in a direction parallel to the substrate surface. | 2010-10-14 |
20100261340 | CLUSTER TOOL FOR LEDS - The present invention generally provides apparatus and methods for forming LED structures. One embodiment of the present invention provides a method for fabricating a compound nitride structure comprising forming a first layer comprising a first group-III element and nitrogen on substrates in a first processing chamber by a hydride vapor phase epitaxial (HVPE) process or a metal organic chemical vapor deposition (MOCVD) process, forming a second layer comprising a second group-III element and nitrogen over the first layer in a second processing chamber by a MOCVD process, and forming a third layer comprising a third group-III element and nitrogen over the second layer by a MOCVD process. | 2010-10-14 |
20100261341 | METHOD FOR MANUFACTURING EPITAXIAL WAFER - An epitaxial wafer is provided capable of eliminating particles in a device process, particles being generated from a scratch in a boundary area between a rear surface and a chamfered surface of a wafer. The scratch in the boundary area between the rear surface and the chamfered surface is removed in a scratch removal process. Thus, no particles exist caused by a scratch, at a time of immersion in an etching solution in the device process, and thus a device yield is increased. | 2010-10-14 |
20100261342 | SEMICONDUCTOR DEVICE CONTAINING A BURIED THRESHOLD VOLTAGE ADJUSTMENT LAYER AND METHOD OF FORMING - A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described. | 2010-10-14 |
20100261343 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE WITH BRISTLED CONDUCTIVE NANOTUBES - Electrodes formed in a partial surface area of a semiconductor substrate and distal ends of conductive nanotubes bristled on a surface of a growth substrate, are bombarded with rare gas plasma. The distal ends of the conductive nanotubes bombarded with the rare gas plasma are brought into contact with the electrodes bombarded with the rare gas plasma to fix the conductive nanotubes to the electrodes. The growth substrate is separated from the semiconductor substrate in such a manner that the conductive nanotubes fixed to the electrodes remain on the electrodes formed on the semiconductor substrate. | 2010-10-14 |
20100261344 | ACTIVE AREA BONDING COMPATIBLE HIGH CURRENT STRUCTURES - A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad. | 2010-10-14 |
20100261345 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a semiconductor device and method of manufacturing thereof, a first insulation interlayer is formed on a substrate including a lower conductive pattern. The first insulation interlayer has a first opening through which the lower conductive pattern is exposed. An interconnection is formed in the first opening such that the interconnection is contact with the lower conductive pattern and protruded from the first insulation interlayer. A second insulation interlayer is formed on the first insulation interlayer in such a manner that the second insulation interlayer has a second opening through the interconnection is exposed and the second opening is centrally aligned with the interconnection. An upper conductive pattern is formed in the second opening such that the upper conductive pattern is contacted with the interconnection. Accordingly, a mis-alignment between the upper conductive pattern and the interconnection is prevented. | 2010-10-14 |
20100261346 | CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT - Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor. | 2010-10-14 |
20100261347 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME8027 - A method of forming a semiconductor device includes the following processes. A first insulating film is formed over an etching stopper film. The etching stopper film has wet-etching resistance. A second insulating film is formed over the second etching stopper. The second insulating film is higher in wet-etching rate than the first insulating film. An opening is formed, which penetrates the etching stopper and the first and second insulating films. A bottom electrode is formed in the opening. The second insulating film is removed by carrying out a wet etching process to expose the bottom electrode. | 2010-10-14 |
20100261348 | Method for fabricating semiconductor package substrate having different thicknesses between wire bonding pad and ball pad - A method for fabricating a semiconductor package substrate, including: preparing a copper clad laminate and half etching a copper foil on a wire bonding pad side of the copper clad laminate; depositing a first etching resist on the opposite sides of the copper clad laminate; forming circuit patterns on the first etching resist, constructing circuits including a wire bonding pad and a ball pad after the model of the circuit patterns, and removing the first etching resist; applying a solder resist to the copper clad laminate in such a way to expose the wire bonding pad and the ball pad; and plating the wire bonding pad with gold and subjecting the ball pad to surface treatment. | 2010-10-14 |
20100261349 | UV TREATMENT FOR CARBON-CONTAINING LOW-K DIELECTRIC REPAIR IN SEMICONDUCTOR PROCESSING - A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric enables process-induced damage repair. The method is particularly applicable in the context of damascene processing. A method provides for forming a semiconductor device by depositing a carbon-containing low-k dielectric layer on a substrate and forming a trench in the low-k dielectric layer, the trench having sidewalls ending at a bottom. The trench is then exposed to UV radiation and, optionally a gas phase source of —CH | 2010-10-14 |
20100261350 | METHODS OF FORMING THIN METAL-CONTAINING FILMS BY CHEMICAL PHASE DEPOSITION - Methods of forming thin metal-containing films by chemical phase deposition, particularly atomic layer deposition (ALD) and chemical vapor deposition (CVD), are provided. The methods comprise delivering at least one organometallic precursor to a substrate, wherein the at least one precursor corresponds in structure to Formula (II); wherein: M is Ru, Fe or Os; R is Q-C | 2010-10-14 |
20100261351 | Spacer Linewidth Control - A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step. | 2010-10-14 |
20100261352 | METHOD FOR LOW-K DIELECTRIC ETCH WITH REDUCED DAMAGE - A method for etching features in a low-k dielectric layer disposed below an organic mask is provided by an embodiment of the invention. Features are etched into the low-k dielectric layer through the organic mask. A fluorocarbon layer is deposited on the low-k dielectric layer. The fluorocarbon layer is cured. The organic mask is stripped. | 2010-10-14 |
20100261353 | WAFER PLANARITY CONTROL BETWEEN PATTERN LEVELS - A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present. | 2010-10-14 |
20100261354 | GASKET WITH POSITIONING FEATURE FOR CLAMPED MONOLITHIC SHOWERHEAD ELECTRODE - An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which is mechanically attached to a backing plate by a series of spaced apart cam locks. A thermally and electrically conductive gasket with projections thereon is compressed between the showerhead electrode and the backing plate at a location three to four inches from the center of the showerhead electrode. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release locking pins extending from the upper face of the electrode. | 2010-10-14 |
20100261355 | METHOD FOR FORMING A HIGH QUALITY INSULATION LAYER ON A SEMICONDUCTOR DEVICE - A method for forming a high quality insulation layer on a semiconductor device is presented. The method includes a first step of supplying any one of a silicon source gas and an oxygen source gas into a process chamber in which a semiconductor substrate is placed; a second step of simultaneously supplying the silicon source gas and the oxygen source gas into the process chamber having undergone the first step and depositing a silicon oxide layer on the semiconductor substrate; and a third step of supplying any one of the silicon source gas and the oxygen source gas into the process chamber having undergone the second step. | 2010-10-14 |
20100261356 | RF ELECTRONIC SYSTEM AND CONNECTION ASSEMBLY THEREFORE - An electronic system is disclosed for RF signals, and comprises coaxial interconnection systems for interconnection with a printed circuit board and which provides an interface with the printed circuit boards. | 2010-10-14 |
20100261357 | CO-AXIAL PLUG-IN-INSERTION CONNECTOR HAVING A CODING HOUSING - The invention relates to a co-axial plug-in-insertion connector which has a center conductor part, an outer conductor part, and an insulating part made of a dielectric material which holds the center conductor part co-axial to the outer conductor part, a coding housing being provided in which the outer conductor part and the center conductor part are arranged, the co-axial plug-in-insertion connector having an insertion end for connection to a complementary co-axial plug-in-insertion connector. Provision is made for the insulating part to be of a one-piece form with the housing. | 2010-10-14 |
20100261358 | ELECTRONIC DEVICE AND ASSEMBLING METHOD THEREOF - An electronic device and an assembling method thereof are provided. The electronic device includes a first electronic module, a second electronic module, and a through connection element. The first electronic module includes a plurality of electronic units, a plurality of lead wires, a daughterboard, and a first connector. The first connector is disposed on the daughterboard. The lead wires are separately connected between the electronic units and the daughterboard. The daughterboard is electrically connected between the lead wires and the first connector. The second electronic module includes a motherboard and a second connector, wherein the second connector disposed on the motherboard is electrically connected with the motherboard. The through connection element being assembled between the first and the second connectors is electrically connected to the first and the second connectors to connect the first electronic module with the second electronic module. | 2010-10-14 |
20100261359 | EMI SHIELD SPRING DEVICE - An electro-magnetic interference device attached to a surface of an object by soldering is disclosed. The device comprises a base comprising a surface defining at least one recessed portion. The at least one recessed portion comprises a side wall. An angle between the side wall and the surface of the base is equal to or greater than 90 degrees. | 2010-10-14 |
20100261360 | ELECTRONIC DEVICE AND POWER ADAPTOR AND METHOD FOR AUTOMATICALLY DISCONNECTING ELECTRONIC DEVICE AND POWER ADAPTOR - A power adaptor is connected between a power supply and an electronic device. The electronic device includes a device charging connector, and an electricity storing unit connected to the device charging connector. The power adaptor includes a power source connector and a first magnetic body. The power source connector is capable of electrically connecting with the device charging connector such that the electricity storing unit is charged by the power supply. The first magnetic body is arranged on the power source connector. The electronic device further includes a second magnetic body. When the electricity storing unit is fully charged, a direction of magnetic field of the second magnetic body is set such that a repelling force is generated between the first magnetic body and the second magnetic body, thus an electrical connection between the power source connector and the device charging connector is disconnected. | 2010-10-14 |