41st week of 2019 patent applcation highlights part 51 |
Patent application number | Title | Published |
20190312072 | IMAGE SENSOR AND METHOD OF MANUFACTURING IMAGE SENSOR - An image sensor and a method of manufacturing the image sensor are provided. The image sensor includes a block layer including an absorption layer and a transparent layer, a lens element located below the block layer, and a sensing element located to face the lens element. | 2019-10-10 |
20190312073 | IMAGE SENSOR - The present disclosure relates to an image sensor comprising: a photodiode; a color filter located above the photodiode; and a converging lens located between the photodiode and the color filter, wherein the converging lens is configured to converge light onto the photodiode. The image sensor can make the configuration of the image sensor more compact while preventing crosstalk of light between pixel cells. | 2019-10-10 |
20190312074 | SOLID-STATE IMAGING DEVICE WITH LAYERED MICROLENSES AND METHOD FOR MANUFACTURING SAME - A solid-state imaging device includes: a first lens layer; and a second lens layer, wherein the second lens layer is formed at least at a periphery of each first microlens formed based on the first lens layer, and the second lens layer present at a central portion of each of the first microlenses is thinner than the second lens layer present at the periphery of the first microlens or no second lens layer is present at the central portion of each of the first microlenses. | 2019-10-10 |
20190312075 | SOLID-STATE IMAGE SENSOR - A solid-state image sensor including a semiconductor layer having a light incident side, a support substrate positioned on an opposite side of the light incident side of the semiconductor layer, photoelectric conversion elements formed two-dimensionally in the semiconductor layer, light reflection structures formed on a surface of the support substrate which faces toward the semiconductor layer, and positioned such that the light reflection structures face the photoelectric conversion elements, respectively, and an interlayer insulating layer formed between adjacent ones of the light reflection structures. The light reflection structures include a light transmission layer and a reflective metal that covers a surface of the light transmission layer opposite to a surface facing the semiconductor layer, and the reflective metal has a concave curved surface facing the photoelectric conversion elements. | 2019-10-10 |
20190312076 | SYSTEM-ON-CHIP CAMERA WITH INTEGRATED LIGHT SENSOR(S) AND METHOD OF PRODUCING A SYSTEM-ON-CHIP CAMERA - The system-on-chip camera comprises a semiconductor body ( | 2019-10-10 |
20190312077 | SENSOR CHIP AND ELECTRONIC APPARATUS - A time of flight sensor is disclosed. In one example, it includes a pixel array with pixels arranged in rows and columns. A global control circuit disposed along a first side of the pixel array outputs a global control signal to the pixels. The global control circuit has a clock tree structure that includes buffer circuits and driving circuits. A rolling control circuit disposed along a second side of the pixel array outputs a rolling control signal to the pixels. A column circuit with analog-to-digital converters is coupled to the pixels. | 2019-10-10 |
20190312078 | MULTI-SPECTRAL SENSOR WITH STACKED PHOTODETECTORS - A multi-spectral photodetector is provided, comprising: a plurality of N photodetectors where N is an integer such that N≥2, each photodetector comprising an anode and a cathode separated from one another by a region of interest, all produced in a semiconductor material; at least one electrical contact for all of the N anodes; and an electrical contact associated with each of the N cathodes; said photodetectors being stacked on top of one another such that the anodes and the cathodes and finally the regions of interest of two consecutive photodetectors in the stack are arranged face to face, this stack making it possible to define a face, termed the active face of the multi-spectral photodetector, common to all the photodetectors of the stack, defined by the face of the first region of interest of the first photodetector of the stack via which photons are intended to enter the stack. | 2019-10-10 |
20190312079 | IMAGING ELEMENT AND IMAGING DEVICE - To simplify the interconnection of signal lines in an imaging element including two semiconductor chips. An imaging element includes a pixel chip and a circuit chip. The pixel chip includes a plurality of pixels each including a charge transfer section configured to transfer a charge generated in accordance with incident light to a charge retention section in accordance with a control signal, and a plurality of first control signal transmission sections each configured to transmit the control signal for each of the charge transfer sections. The circuit chip includes a control signal generation section configured to generate the control signal for each of the charge transfer sections of the plurality of pixels, and a plurality of second control signal transmission sections provided to individually correspond to the first control signal transmission sections and each configured to transmit the generated control signal. | 2019-10-10 |
20190312080 | IMAGING SYSTEM AND IMAGING METHOD - An imaging system includes an imaging optical system, an imaging device, an actuator, and control circuitry. The actuator changes a relative position of a plurality of pixel cells and an image of a subject. The pixel cells have variable sensitivity, and include a photoelectric converter and a charge accumulation region. The control circuitry sets the relative position to a first position, and also sets the sensitivity of each pixel cell to a first sensitivity. A first signal charge obtained at the photoelectric converter is accumulated in the charge accumulation region. The relative position is set to a second position different from the first position, and also the sensitivity of each pixel cell is set to a second sensitivity different from the first sensitivity. A second signal charge obtained at the photoelectric converter is accumulated in the charge accumulation region in addition to the first signal charge. | 2019-10-10 |
20190312081 | SOLID STATE TRANSDUCER DEVICES, INCLUDING DEVICES HAVING INTEGRATED ELECTROSTATIC DISCHARGE PROTECTION, AND ASSOCIATED SYSTEMS AND METHODS - Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment, a solid state transducer device includes a solid state emitter, and an electrostatic discharge device carried by the solid state emitter. In some embodiments, the electrostatic discharge device and the solid state emitter share a common first contact and a common second contact. In further embodiments, the solid state lighting device and the electrostatic discharge device share a common epitaxial substrate. In still further embodiments, the electrostatic discharge device is positioned between the solid state lighting device and a support substrate. | 2019-10-10 |
20190312082 | Device With Multiple Vertically Separated Terminals and Methods for Making the Same - A light emitting device that includes: a plurality of light emitting elements arranged at different locations in a common plane, each light emitting element including: at least one layer of a semiconductor material; a first electrical terminal located at a first location; a second electrical terminal located at a second location; and a third electrical terminal located at a third location; a first electrode layer including one or more electrodes; a second electrode layer including one or more electrodes; a third electrode layer including one or more electrodes; a first electrically insulating layer disposed between the plurality of light emitting elements and also disposed between the first and second electrode layers; and a second electrically insulating layer disposed between the plurality of light emitting elements and also disposed between the second and third electrode layers. | 2019-10-10 |
20190312083 | LIGHT EMITTING DIODE DISPLAY DEVICE - A light emitting diode display device is provided. The light emitting diode display device includes a first light emitting diode pixel including a first light emitting diode layer and a first color conversion material on the first light emitting diode layer, a second light emitting diode pixel including a second light emitting diode layer and a second color conversion material on the second light emitting diode layer, a separation film disposed between the first light emitting diode layer and the second light emitting diode layer and a partition disposed between the first color conversion material and the second color conversion material and including a partition material, wherein the first and second light emitting diode pixels are divided by the separation film and the partition, the partition is disposed on the separation film in alignment with the separation film such that the partition includes linear portions that extend in a first direction and the separation film includes linear portions that also extend in the first direction and vertically overlap the linear portions of the partition, and the partition material includes an insulating material different from silicon. | 2019-10-10 |
20190312084 | LIGHT EMITTING DIODE APPARATUS AND MANUFACTURING METHOD THEREOF - A method of manufacturing a light emitting diode is provided. The method of manufacturing a light emitting diode includes the steps of forming a mask layer including a plurality of grooves on one side of a substrate, forming an insulating layer on the other side of the substrate, preparing a plurality of sub pixel areas on the substrate on which the mask layer has been formed, forming a nanostructure in at least one groove included in each of the plurality of sub pixel areas, forming a first electrode on the mask layer and the nanostructure corresponding to each of the plurality of sub pixel areas, etching an area of the insulating layer corresponding to each of the plurality of sub pixel areas and forming a first semiconductor layer and a second electrode, forming a metallic substance in a via hole which is provided between the plurality of sub pixel areas and connects the one side and the other side of the substrate, and forming a second semiconductor layer and a third electrode in an area corresponding to the via hole on the other side of the substrate. | 2019-10-10 |
20190312085 | LIGHTING AND/OR SIGNALLING DEVICE FOR A MOTOR VEHICLE - A semiconductor light source includes at least one substrate and a plurality of submillimetre-sized light-emitting rods that extend from a first face of the substrate. The light-emitting rods are arranged in a plurality of groups the selective activation of which allows a plurality of light beams to be produced. At least two groups of rods are electrically connected to one another by an irreversibly modifiable conductive bridge such that the irreversible modification of this conductive bridge irreversibly modifies the electrical dependence of the two groups on one another. | 2019-10-10 |
20190312086 | QUATERNARY SPIN HALL MEMORY - An apparatus is provided which comprises: a first magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; a second magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; and a first layer of spin orbit coupling material adjacent to the first magnetic junction and the second magnetic junction via their respective 4-state free magnetic layers. Described is an apparatus which comprises a 4-state free magnetic layer; a layer of SOC material adjacent to the 4-state free magnetic layer; a first interconnect coupled to the layer of SOC material. | 2019-10-10 |
20190312087 | INTEGRATED CIRCUIT INCLUDING TRANSISTORS HAVING A COMMON BASE - The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench. | 2019-10-10 |
20190312088 | INTEGRATED CIRCUIT INCLUDING BIPOLAR TRANSISTORS - The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions. | 2019-10-10 |
20190312089 | COLOR FILTER ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE USING THE SAME - A method of fabricating an organic light emitting diode display device, includes forming a thin film transistor on a first substrate, forming an organic light emitting element, which is electrically connected to the thin film transistor, on the first substrate, forming a black matrix, in which openings are formed, on one surface of a second substrate opposite to the first substrate, forming a color filter layer in the openings, forming a transparent insulation layer having a first surface and a second surface opposing the first surface on the second substrate, with the first surface of the transparent insulating layer in direct contact with the color filter layer, forming a plurality of optical patterns at the second surface of the transparent insulation layer, and attaching the first substrate and the second substrate such that the second surface of the transparent insulating layer is closer to the thin film transistor than the first substrate. | 2019-10-10 |
20190312090 | ELECTRONIC DEVICE INCLUDING BENDABLE DISPLAY - An electronic device is provided. The electronic device includes a pixel layer including a plurality of pixels, a substrate including a first area, and a second area, a display driver integrated circuit (DDI) configured to apply a signal to the pixel layer, and one or more wiring layers disposed on the substrate. The substrate includes a planar zone including at least a portion of the first area and at least a portion of the second area, and a bending zone extending from the at least a portion of the second area. A bending start point of the bending zone is adjacent to the second point, and the one or more wiring layers are disposed in at least a portion of the planar zone and at least a portion of the bending zone. | 2019-10-10 |
20190312091 | DISPLAY DEVICE - A display device is provided that may prevent peeling of a sealing layer between a first partition and a second partition formed at an end portion of the sealing layer that seals a light emitting layer. An organic EL display device includes a sealing layer that is configured to seal a light emitting element layer and is doubly enclosed at an end portion by a first bank and a second bank that is formed more on the outer side than the first bank with a gap in between. An outer side wall surface of the first bank facing the second bank is formed as a gentle slope with an inclination angle smaller than an inner side wall surface of the first bank on the side opposite to the second bank. | 2019-10-10 |
20190312092 | FLEXIBLE DISPLAY DEVICE - A display device includes: a flexible substrate; a pixel over the flexible substrate, the pixel including a transistor and a display element; a first wiring for transmitting a signal to the pixel, the first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; an inorganic insulating layer on a higher level than the first wiring or the second wiring; and an organic insulating layer on a higher level than the inorganic insulating layer, wherein the inorganic insulating layer has an opening exposing a part of the upper surface of the first wiring or the second wiring is exposed, and the organic insulating layer is provided in such a way as to fill the opening. | 2019-10-10 |
20190312093 | DISPLAY PANEL AND PHOTOELECTRIC DETECTION METHOD - The present disclosure relates to a display panel, a photoelectric detection method, a photoelectric detection device and a computer readable storage medium. The display panel includes a pixel array including a plurality of subpixels, wherein through holes are arranged within gaps among the plurality of subpixels, and a photoelectric detection unit including a photoelectric detection array configured to detect incident light passing through the through holes. The photoelectric detection method includes determining a plurality of target subpixels from the plurality of subpixels; determining a time period when the plurality of target subpixels do not emit light, and during the time period, detecting incident light passing through the through holes by the photoelectric detection array. | 2019-10-10 |
20190312094 | DISPLAY DEVICE - A display device includes a display panel, a light shielding member, a first cover member, a first light transmitting member, and a second cover member. The display panel includes a display region where a plurality of display structures are arranged and a peripheral region surrounding the display region. The light shielding member is in the peripheral region on the display panel, and has a first opening that exposes the display region. The first cover member is arranged on the light shielding member. The first light transmitting member is in the peripheral region on the first cover member, and includes a second opening that overlaps the first opening. The first light transmitting member has a first color. The second cover member is arranged on the first light transmitting member. | 2019-10-10 |
20190312095 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are an organic light-emitting display device and a method of manufacturing the same. The organic light-emitting display device includes a panel including a display unit on which an image is formed and a pad unit including a plurality of terminals connected to the display unit and arranged in a plurality of rows on a substrate, and a flexible circuit board including metal wirings arranged in a plurality of layers so as to be respectively connected in correspondence to the plurality of rows of terminals in the pad unit and being coupled to the pad unit, in which the pad unit includes a one-row terminal zone in which only terminals in a single row from among the plurality of rows of terminals electrically connect the metal wirings to the display unit. | 2019-10-10 |
20190312096 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode (“OLED”) display device includes a substrate having a display region having a light emitting region and a peripheral region surrounding the light emitting region, a pad region at a first side of the display region, and a trench at a second side of the display region, a plurality of light emitting structures on the light emitting region of the substrate, an active pattern along a profile of the trench on the peripheral region of the substrate, the active pattern being adjacent to the trench and including a pattern protrusion, and an upper gate wiring on and overlapping the active pattern, the upper gate wiring having a wiring protrusion adjacent to the pattern protrusion. | 2019-10-10 |
20190312097 | DISPLAY APPARATUS - A display apparatus includes a substrate including a display area and a peripheral area disposed outside of the display area, a plurality of wiring lines disposed in the peripheral area, and an interlayer insulating layer covering the plurality of wiring lines. The interlayer insulating layer includes an upper surface having a first concave-convex surface corresponding to the plurality of wiring lines. The display apparatus further includes a first conductive layer disposed on the interlayer insulating layer and including a second upper surface having a second concave-convex surface corresponding to the first concave-convex surface, a planarization layer disposed on the first conductive layer and having a flat upper surface, a second conductive layer disposed on the planarization layer and having a flat upper surface, and a polarization plate disposed on the second conductive layer. | 2019-10-10 |
20190312098 | DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE - The first type of pixel lines include first type of end pixels disposed at the end on the opposite side of the first direction and at the end on the opposite side of the second direction of a pixel line in the second direction. The second type of pixel lines include second type of end pixels disposed at the end on the opposite side of the first direction and at the end on the opposite side of the second direction of a pixel line in the second direction. Channel widths of driving transistors for light-emitting elements of the first type of end pixels are narrower than channel widths of driving transistors for light-emitting elements of internal pixels surrounded by other pixels in four directions of the first direction, the opposite direction of the first direction, the second direction, and the opposite direction of the second direction. | 2019-10-10 |
20190312099 | DISPLAY DEVICE - First type of pixel lines include first type of end pixels each disposed at the end on the opposite side of the first direction and at the end on the opposite side of the second direction of a pixel line extending in the second direction. The second type of pixel lines include second type of end pixels each disposed at the end on the opposite side of the first direction and at the end on the opposite side of the second direction of a pixel line extending in the second direction. Luminance values of the plurality of first type of end pixels are smaller than luminance values of internal pixels surrounded by other pixels in four directions of the first direction, the opposite direction of the first direction, the second direction, and the opposite direction of the second direction in response to the same input picture signal. | 2019-10-10 |
20190312100 | METAL-INSULATOR-METAL CAPACITOR STRUCTURE - The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material. | 2019-10-10 |
20190312101 | SEMICONDUCTOR DEVICE - A semiconductor device having a trench gate structure is provided. A semiconductor device is provided, including: a first-conductivity-type drift region provided in a semiconductor substrate; a first-conductivity-type accumulation region provided above the drift region and having a higher doping concentration than the drift region; a second-conductivity-type base region provided above the accumulation region; and an electric-field relaxation layer provided between the accumulation region and the base region and having a lower doping concentration than the accumulation region. The electric-field relaxation layer may include a first-conductivity-type region including a region having a same doping concentration as the drift region. | 2019-10-10 |
20190312102 | RADIATION-TOLERANT UNIT MOSFET HARDENED AGAINST SINGLE EVENT EFFECT AND TOTAL IONIZATION DOSE EFFECT - Provided is a radiation-tolerant 3D unit MOSFET having at least one selected from a dummy drain (DD), an N-well layer (NW), a deep N-well layer (DNW), and a P+ layer to minimize an influence by a total ionization dose effect and an influence by a single event effect. | 2019-10-10 |
20190312103 | Semiconductor Assemblies Having Semiconductor Material Regions with Contoured Upper Surfaces; and Methods of Forming Semiconductor Assemblies Utilizing Etching to Contour Upper Surfaces of Semiconductor Material - Some embodiments include an integrated assembly having a region of first semiconductor material. The region has an upper surface along a cross-section. The upper surface has a flat-topped peak and a concavity adjacent the flat-topped peak. A pillar of second semiconductor material is over the region and directly against the region. The pillar extends vertically from the upper surface. Some embodiments include a method of forming an integrated assembly. A construction is formed to have a semiconductor region, and to have an insulative region extending over the semiconductor region and alongside the semiconductor region. A combination of three etches is utilized to expose an upper surface of the semiconductor region and to modify the upper surface of the semiconductor region to form said upper surface to include, along a cross-section, a flat-topped peak portion and an adjacent concavity portion. | 2019-10-10 |
20190312104 | Bulk Nanosheet with Dielectric Isolation - Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided. | 2019-10-10 |
20190312105 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a drift region having a first conductivity type provided on a semiconductor substrate; a plurality of trench portions provided above the drift region, on a top surface side of the semiconductor substrate; a base region having a second conductivity type provided in a mesa portion sandwiched between the plurality of trench portions, in the semiconductor substrate; an emitter region having the first conductivity type provided above the base region, on a top surface of the mesa portion; and a contact region having the second conductivity type and a higher doping concentration than the base region, provided adjacent to the emitter region on the top surface of the mesa portion, wherein a mesa width of the mesa portion is less than or equal to 100 nm, and a bottom end of the contact region is shallower than a bottom end of the emitter region. | 2019-10-10 |
20190312106 | ENHANCEMENTS TO CELL LAYOUT AND FABRICATION TECHNIQUES FOR MOS-GATED DEVICES - An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor. | 2019-10-10 |
20190312107 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method includes forming a plurality of first semiconductor layers and second semiconductor layers in an alternate manner over a substrate; etching the first semiconductor layers and second semiconductor layers to form a fin structure, in which the fin structure comprises a plurality of first nanowires and second nanowires alternately arranged, the first nanowires have respective remaining portions of the first semiconductor layers, and the second nanowires have respective remaining portions of second semiconductor layers; forming a dummy gate over the fin structure; forming a plurality of gate spacers on opposite sidewalls of the dummy gate, respectively; replacing the dummy gate with a metal gate; removing first portions of the second nanowires exposed by the metal gate and metal gate and the gate spacers suspended; and forming an epitaxy layer wrapping around the first portions of the first nanowires, in which opposite sidewalls of the epitaxy layer have zig-zag contour. | 2019-10-10 |
20190312108 | FIELD EFFECT TRANSISTOR WITH CONTROLLABLE RESISTANCE - A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer. | 2019-10-10 |
20190312109 | FIELD-EFFECT TRANSISTORS WITH A COMPOSITE CHANNEL - Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is formed that includes first and second semiconductor layers, and a gate structure is formed that is arranged over the first and second semiconductor layers. First and second source/drain regions are formed in which the second source/drain region is separated from the first source/drain region by the channel region. The first semiconductor layer is composed of a semiconductor material having a first carrier mobility, and the second semiconductor layer is composed of a semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer. | 2019-10-10 |
20190312110 | GALLIUM-NITRIDE-BASED MODULE WITH ENHANCED ELECTRICAL PERFORMANCE AND PROCESS FOR MAKING THE SAME - The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening. | 2019-10-10 |
20190312111 | SELF-STANDING GaN SUBSTRATE, GaN CRYSTAL, METHOD FOR PRODUCING GaN SINGLE CRYSTAL, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - An object is to provide a nonpolar or semipolar GaN substrate having improved size and crystal quality. A self-standing GaN substrate has an angle between the normal of the principal surface and an m-axis of 0 degrees or more and 20 degrees or less, wherein: the size of the projected image in a c-axis direction when the principal surface is vertically projected on an M-plane is 10 mm or more; and when an a-axis length is measured on an intersection line between the principal surface and an A-plane, a low distortion section with a section length of 6 mm or more and with an a-axis length variation within the section of 10.0×10 | 2019-10-10 |
20190312112 | POROUS AND NANOPOROUS SEMICONDUCTOR MATERIALS AND MANUFACTURE THEREOF - Methods for forming porous or nanoporous semiconductor materials are described. The methods allow for the formation of arrays pores or nanopores in semiconductor materials with advantageous pore size, spacing, pore volume, material thickness, and other aspects. Porous and nanoporous materials also are provided. | 2019-10-10 |
20190312113 | SEMICONDUCTOR DEVICE AND POWER CONVERTER - A semiconductor device includes gate trenches and dummy gate trenches formed on the upper surface side of a semiconductor substrate, gate electrodes embedded in the gate trenches, dummy gate electrodes embedded in the dummy gate trenches, a channel layer formed in the surface portion on the upper surface side of the semiconductor substrate, a carrier storage layer formed below the channel layer, and a collector layer formed on the lower surface side of the semiconductor substrate. A relationship D | 2019-10-10 |
20190312114 | Semiconductor Device with Trench Structure and Production Method - A semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type on the semiconductor substrate, such that a first section of a pn junction is formed between the semiconductor layer and the semiconductor substrate. A trench structure extends through the semiconductor layer into the semiconductor substrate. The trench structure includes an insulation structure and a contact structure. The insulation structure is formed between the semiconductor layer and the contact structure. The contact structure is electrically connected to the semiconductor substrate at a bottom of the trench. A first semiconductor region of the second conductivity type adjoins the insulation structure and extends along the trench structure into a depth range between the first section of the pn junction and the bottom, such that a second section of the pn junction is formed between the first semiconductor region and the semiconductor substrate. | 2019-10-10 |
20190312115 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes the following elements. A substrate includes a ground portion to which a ground potential is supplied. A semiconductor chip is mounted on the substrate and includes first and second output terminals, a first terminator, and a ground terminal. First and second amplifiers are respectively formed in first and second regions of the semiconductor chip and respectively amplify first and second input signals of first and second frequency bands and output first and second amplified signals from the first and second output terminals via first and second output wires. A first harmonic termination circuit includes a first wire which electrically connects the first terminator and the ground portion. A ground wire is disposed between the first wire and the second output wire in a plan view of a main surface of the semiconductor chip and electrically connects the ground terminal and the ground portion. | 2019-10-10 |
20190312116 | VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH SELF-ALIGNED CONTACTS - Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack. | 2019-10-10 |
20190312117 | FINFET DEVICE WITH A WRAP-AROUND SILICIDE SOURCE/DRAIN CONTACT STRUCTURE - One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure. | 2019-10-10 |
20190312118 | SEMICONDUCTOR DEVICES AND CONTACT PLUGS - A semiconductor device has a high electric connection reliability and includes a base substrate having a connection target layer, a lower contact plug formed over the base substrate and electrically connected to the connection target layer, and an upper contact plug formed over the lower contact plug, wherein the lower contact plug includes a lower plug layer having a gap portion extending inward from a top portion of the lower plug layer, a gap cover layer filling the gap portion, and an upper cover layer covering a top surface of the lower plug layer. | 2019-10-10 |
20190312119 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor. | 2019-10-10 |
20190312120 | GATE STACK QUALITY FOR GATE-ALL-AROUND FIELD-EFFECT TRANSISTORS - A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels, interfacial layers formed around the first channels, and dielectric material including first and second portions having respective thicknesses formed on the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels, the interfacial layers formed around the second channels, and the dielectric material formed on the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material. | 2019-10-10 |
20190312121 | METHOD FOR MANUFACTURING HORIZONTAL-GATE-ALL-AROUND DEVICES WITH DIFFERENT NUMBER OF NANOWIRES - A method is provided. First and second fins are etched to form a first recess over the etched first fin and a second recess over the etched second fin. A first composite fin and a second composite fin are concurrently epitaxially grown respectively in the first recess and the second recess. The first composite fin includes a plurality of nanowire channels and at least one sacrificial layer. The second composite fin includes at least one nanowire channel and at least one sacrificial layer. A number of the plurality of nanowire channels of the first composite fin is greater than a number of the at least one nanowire channel of the second composite fin. A dielectric material is recessed to expose at least a portion of the first composite fin and at least a portion of the second composite fin. | 2019-10-10 |
20190312122 | ELECTRONIC COMPONENT, METHOD FOR MANUFACTURING ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - An electronic component includes: a conductor portion containing a first element; a compound layer disposed around the conductor portion and containing a second element and a third element which are different from the first element; and an isolation layer, disposed between the conductor portion and the compound layer and containing a fourth element which is different from the first element, the second element, and the third element, to isolate the first element in the conductor portion from the second element and the third element outside the conductor portion. | 2019-10-10 |
20190312123 | CONTACT OVER ACTIVE GATE EMPLOYING A STACKED SPACER - A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric over the HKMGs, forming first contacts to source/drain of a transistor between the HKMGs, and forming a second dielectric over the first contacts. The method further includes selectively removing the first dielectric to form second contacts to the HKMGs, selectively removing the second dielectric to form third contacts on top of the first contacts, removing the sacrificial upper portion of the stacked spacers, and depositing a third dielectric that pinches off the remaining first and second dielectrics to form air-gaps between the first contacts and the HKMGs. | 2019-10-10 |
20190312124 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a first fin type pattern and a second fin type pattern which protrude from a substrate and are spaced apart from each other to extend in a first direction, a dummy fin type pattern protruding from the substrate between the first fin type pattern and the second fin type pattern, a first gate structure extending in a second direction intersecting with the first direction, on the first fin type pattern, a second gate structure extending in the second direction, on the second fin type pattern, and a capping pattern extending in the second direction, on the first gate structure and the second gate structure, wherein the capping pattern includes a separation part which is in contact with an upper surface of the dummy fin type pattern, and the dummy fin type pattern and the separation part separate the first gate structure and the second gate structure. | 2019-10-10 |
20190312125 | BIPOLAR JUNCTION TRANSISTOR (BJT) FOR LIQUID FLOW BIOSENSING APPLICATIONS WITHOUT A REFERENCE ELECTRODE AND LARGE SENSING AREA - A bipolar junction transistor (BJT) containing sensor that includes a vertically orientated stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region in contact with a first sidewall of a vertically orientated base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region in contact with a second sidewall of the base region. The second extrinsic base region including a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element. | 2019-10-10 |
20190312126 | DIRECT GROWTH OF LATERAL III-V BIPOLAR TRANSISTOR ON SILICON SUBSTRATE - A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region. | 2019-10-10 |
20190312127 | Methods of Manufacturing Semiconductor Devices with a Deep Barrier Layer - A method of manufacturing a semiconductor device includes: etching a plurality of trenches to a first depth in a semiconductor substrate; doping a region of the semiconductor substrate surrounding a bottom of the trenches at the first depth to form a doped region in the semiconductor substrate; after the doped region is formed, etching the plurality of trenches deeper into the semiconductor substrate to a second depth greater than the first depth, adjacent ones of the trenches being separated from one another by a semiconductor mesa; and forming a body region above the doped region in the semiconductor mesas. | 2019-10-10 |
20190312128 | QUANTUM DOT DEVICE PACKAGES - Disclosed herein are quantum dot device packages, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device package may include a die having a quantum dot device, wherein the quantum dot device includes a quantum well stack, gates disposed above the quantum well stack, and conductive pathways coupled between associated ones of the gates and conductive contacts of the die. The quantum dot device package may also include a package substrate, wherein conductive contacts are disposed on the package substrate, and first level interconnects are disposed between the die and the package substrate, coupling the conductive contacts of the die with associated conductive contacts of the package substrate. | 2019-10-10 |
20190312129 | VFET Bottom Epitaxy Formed with Anchors - Techniques for forming VFET bottom source and drain epitaxy with anchors are provided. In one aspect, a method of forming a VFET device includes: patterning at least one fin in a substrate; forming anchors on opposite ends of the at least one fin; laterally etching a base of the at least one fin, wherein the anchors prevent the lateral etching from being performed on the ends of the at least one fin; forming bottom source and drains at the base of the at least one fin between the anchors; removing the anchors; forming bottom spacers on the bottom source and drains; forming gates above the bottom spacers alongside the at least one fin; forming top spacers above the gates; and forming top source and drains above the top spacers at a top of the at least one fin. VFET devices are also provided. | 2019-10-10 |
20190312130 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a substrate including a first device region and a second device region; a first fin separation insulating portion on the first device region; a pair of first fin-type active regions spaced from each other with the first fin separation insulating portion therebetween in the first device region and collinearly extending in a first horizontal direction; a second fin separation insulating portion extending in a second horizontal direction over the first device region and the second device region; and a pair of second fin-type active regions spaced from each other with the second fin separation insulating portion therebetween and collinearly extending in the first horizontal direction, wherein the first fin separation insulating portion and the second fin separation insulating portion vertically overlap each other. | 2019-10-10 |
20190312131 | SEMICONDUCTOR DEVICE - A transistor includes a semiconductive fin having a channel portion, a gate stack over the channel portion of the semiconductive fin, source and drain structures on opposite sides of the gate stack and adjoining the semiconductive fin, and a sidewall structure extending along sidewalls of a body portion of the source structure. The source structure has a curved top, and the source structure has a top portion protruding over a top of the sidewall structure. | 2019-10-10 |
20190312132 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other. | 2019-10-10 |
20190312133 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode. | 2019-10-10 |
20190312134 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device including (a) a drift region of a first-conductivity-type, (b) a base region of a second-conductivity-type, (c) a plurality of trench portions arranged next to each other in a predetermined arrangement direction on the upper surface of the semiconductor substrate, (d) an emitter region of a first-conductivity-type which has a higher doping concentration than the drift region, (e) an accumulation region of a first-conductivity-type which has a higher doping concentration than the drift region, and (f) a second-conductivity-type region of a second-conductivity-type which has a higher doping concentration than the base region, wherein the accumulation region and the second-conductivity-type region are provided between the base region and the drift region in a non-channel mesa portion that does not have the emitter region provided therein and that is of mesa portions between adjacent ones of the plurality of trench portions. | 2019-10-10 |
20190312135 | SEMICONDUCTOR DEVICE - A semiconductor device is provided comprising a semiconductor substrate of a first conductivity type and a dummy trench portion having a main body portion and one or more branch portions, the main body portion formed in a front surface of the semiconductor substrate and extending in a predetermined extending direction, the branch portions extending from the main body portion in directions different from the extending direction. The semiconductor substrate has an emitter region of first conductivity type and a base region of a second conductivity type which are provided sequentially from the front surface side of the semiconductor substrate, and the dummy trench portion has a dummy trench which penetrates the emitter region and the base region from the front surface of the semiconductor substrate, and a dummy insulating portion which is provided within the dummy trench. | 2019-10-10 |
20190312136 | BALLISTIC TRANSPORT DEVICE AND CORRESPONDING COMPONENT - A device includes a particle propagation channel, a particle deflector, a particle source, and a particle sink. The particle deflector facilitates ballistic transport of particles from a particle inflow portion through a particle flow deflection portion to a particle outflow portion. The particle deflector is arranged at the particle flow deflection portion and is activatable to deflect particles in the flow deflection portion and is configured to selectively prevent the particles from reaching the particle outflow portion. The particle source and particle sink are configured to cause a current path of the particles through the device. | 2019-10-10 |
20190312137 | HIGH-ELECTRON-MOBILITY TRANSISTOR WITH BURIED INTERCONNECT - A high-electron-mobility transistor (HEMT) includes a substrate layer of silicon, a first contact disposed on a first surface of the substrate layer, and a number of layers disposed on a second surface of the substrate layer opposite the first surface. A second contact and a gate contact are disposed on those layers. A trench containing conducting material extends completely through the layers and into the substrate layer. In an embodiment of the HEMT, the first contact is a drain contact and the second contact is a source contact. In another embodiment of the HEMT, the first contact is a source contact and the second contact is a drain contact. | 2019-10-10 |
20190312138 | Metal Gate Electrode of a Semiconductor Device - Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other | 2019-10-10 |
20190312139 | AVALANCHE ROBUST LDMOS - A semiconductor device includes an active region formed over a substrate. The active region includes a FET and a diode. The FET includes one or more FET fingers. Each FET finger includes a FET source region, a FET drain region, and a lateral FET gate electrode. The diode includes one or more diode fingers. Each of the diode fingers includes a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode. The FET fingers are active fingers of the semiconductor device and the diode fingers are dummy fingers of the semiconductor device. The diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region. | 2019-10-10 |
20190312140 | VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED GATE LENGTH VARIATIONS - A method of forming a fin field effect transistor is provided. The method includes forming an elevated substrate tier on a substrate, and forming a fin mesa on the elevated substrate tier with a fin template layer on the fin mesa, wherein the elevated substrate tier is laterally larger than the fin mesa and fin template layer. The method includes forming a fill layer on the substrate, wherein the fill layer surrounds the fin mesa, elevated substrate tier, and fin template layer, forming a plurality of fin masks on the fill layer and fin template layer, and removing portions of the fill layer, fin template layer, and fin mesa to form a plurality of dummy fins from the fill layer, one or more vertical fins from the fin mesa, and a dummy fin portion on opposite ends of each of the one or more vertical fins from the fill layer. | 2019-10-10 |
20190312141 | VERTICAL TRANSISTOR PASS GATE DEVICE - A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device. | 2019-10-10 |
20190312142 | SEALED CAVITY STRUCTURES WITH NON-PLANAR SURFACE FEATURES TO INDUCE STRESS - The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor. | 2019-10-10 |
20190312143 | Gradient Doped Region of Recessed Fin Forming a FinFET Device - An embodiment is a method of manufacturing a semiconductor device. The method includes forming a fin on a substrate. A gate structure is formed over the fin. A recess is formed in the fin proximate the gate structure. A gradient doped region is formed in the fin with a p-type dopant. The gradient doped region extends from a bottom surface of the recess to a vertical depth below the recess in the fin. A source/drain region is formed in the recess and on the gradient doped regions. | 2019-10-10 |
20190312144 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends substantially along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet. | 2019-10-10 |
20190312145 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin. | 2019-10-10 |
20190312146 | SEMICONDUCTOR DEVICE - One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal. | 2019-10-10 |
20190312147 | THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode. | 2019-10-10 |
20190312148 | THIN FILM TRANSISTOR HAVING LIGHT SHIELDING STRUCTURE - Provided is a thin film transistor including a substrate, a first spacer on the substrate, a second spacer on the first spacer, a light shield layer intervened between the first spacer and the second spacer, a semiconductor layer on the second spacer, and a gate electrode on the semiconductor layer, wherein the light shield layer includes a plurality of inclined surfaces against a top surface of the substrate. | 2019-10-10 |
20190312149 | SEMICONDUCTOR DEVICE - A high-performance and highly reliable semiconductor device is provided. The semiconductor device includes: a first oxide; a source electrode; a drain electrode; a second oxide over the first oxide, the source electrode, and the drain electrode; a gate insulating film over the second oxide; and a gate electrode over the gate insulating film. The source electrode is electrically connected to the first oxide. The drain electrode is electrically connected to the first oxide. Each of the first oxide and the second oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. Each of the first oxide and the second oxide includes more In atoms than element M atoms. An atomic ratio of the In, the Zn, and the element M in the first oxide is equal to or similar to an atomic ratio of the In, the Zn, and the element M in the second oxide. | 2019-10-10 |
20190312150 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SAME - A semiconductor element capable of adjusting a barrier height ϕ | 2019-10-10 |
20190312151 | STACKED III-V SEMICONDUCTOR COMPONENT - A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a p | 2019-10-10 |
20190312152 | BURIED OXIDE TRANSCAP DEVICES - Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, a first insulator region disposed below the semiconductor region, a first non-insulative region disposed below the first insulator region, a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, wherein the semiconductor region is disposed between the second non-insulative region and the third non-insulative region. In certain aspects, the semiconductor variable capacitor may include a second insulator region disposed above the semiconductor region and a second semiconductor region disposed above the second insulator region. | 2019-10-10 |
20190312153 | VARIABLE THICKNESS GATE OXIDE TRANSCAP - Aspects of the present disclosure provide semiconductor variable capacitor devices. In one embodiment, a semiconductor variable capacitor includes a gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a first non-insulative region disposed above the gate oxide layer; a first semiconductor region disposed beneath the gate oxide layer; a second semiconductor region disposed beneath the gate oxide layer and adjacent to the first semiconductor region, wherein the second semiconductor region comprises a different doping type than the first semiconductor region a second non-insulative region coupled to the first semiconductor region; and a control terminal coupled to a control region coupled to the second semiconductor region such that a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region. | 2019-10-10 |
20190312154 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, a well region formed in the substrate, first and second isolation regions formed in the substrate, a dielectric layer formed on the well region, a conductive layer formed on the dielectric layer, a first doped region, an insulating layer, and first and second contact vias. The dielectric layer is disposed between the first and second isolation regions. The first doped region is formed in the well region. The insulating layer is formed on the dielectric layer, the first and second isolation regions, and the first doped region. The first contact via is formed in the insulating layer and electrically connected to the conductive layer. The first contact via is disposed on an overlapping area between the dielectric layer and the conductive layer. The second contact via is formed in the insulating layer and electrically connected to the doped region. | 2019-10-10 |
20190312155 | MIXED CATION PEROVSKITE SOLID STATE SOLAR CELL AND FABRICATION THEREOF - A perovskite material including an organic-inorganic perovskite structure of formula (I), A | 2019-10-10 |
20190312156 | LOCAL METALLIZATION FOR SEMICONDUCTOR SUBSTRATES USING A LASER BEAM - Local metallization of semiconductor substrates using a laser beam, and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, are described. For example, a solar cell includes a substrate and a plurality of semiconductor regions disposed in or above the substrate. A plurality of conductive contact structures is electrically connected to the plurality of semiconductor regions. Each conductive contact structure includes a locally deposited metal portion disposed in contact with a corresponding a semiconductor region. | 2019-10-10 |
20190312157 | LASER ASSISTED METALLIZATION PROCESS FOR SOLAR CELL FABRICATION - A method for fabricating a solar cell and the and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, are described. The method can include: providing a solar cell having metal foil having first regions that are electrically connected to semiconductor regions on a substrate at a plurality of conductive contact structures, and second regions; locating a carrier sheet over the second regions; bonding the carrier sheet to the second regions; and removing the carrier sheet from the substrate to selectively remove the second regions of the metal foil. | 2019-10-10 |
20190312158 | Photo-detecting apparatus - A photo-detecting apparatus includes an absorption layer configured to absorb photons and to generate photo-carriers from the absorbed photons, wherein the absorption layer includes germanium. A carrier guiding unit is electrically coupled to the absorption layer, wherein the carrier guiding unit includes a first switch including a first gate terminal. | 2019-10-10 |
20190312159 | RECONFIGURABLE PHOTOVOLTAIC LAMINATE(S) AND PHOTOVOLTAIC PANEL(S) - Reconfigurable PV panels can have features that include cut lines for separating full panels into smaller subpanels, connector ribbons for assembling several reconfigurable PV panels into a one-dimensional or two-dimensional array and can be stacked upon each other and unstacked by rotating them about a shared connection. | 2019-10-10 |
20190312160 | METHOD FOR MANUFACTURING FINGER ELECTRODE FOR SOLAR CELL AND FINGER ELECTRODE FOR SOLAR CELL PREPARED THEREBY - A method of manufacturing an electrode for a solar cell includes printing a conductive paste on a front surface of a substrate using a printing mask having an opening rate of 65% or more, and baking the printed conductive paste. The conductive paste may include a conductive powder, a glass fit, and an organic vehicle, the glass fit may include lithium oxide and tungsten oxide, and, in the glass fit, a weight ratio of lithium oxide to tungsten oxide may be about 0.5 to about 5.5. | 2019-10-10 |
20190312161 | MANUFACTURING METHOD FOR SOLAR CELL - A manufacturing method for a solar cell is provided. The method includes: preparing a photoelectric converter which includes a light receiving surface and a back surface opposed to the light receiving surface and has n-type regions and p-type regions alternately arranged in a first direction on the back surface; forming a groove which is extended in the first direction on the light receiving surface after an electrode layer is formed on the n-type regions and the p-type regions; and dividing the photoelectric converter into a plurality of sub-cells along the groove. | 2019-10-10 |
20190312162 | SOLAR CELLS FORMED VIA ALUMINUM ELECTROPLATING - Electroplating of aluminum may be utilized to form electrodes for solar cells. In contrast to expensive silver electrodes, aluminum allows for reduced cell cost and addresses the problem of material scarcity. In contrast to copper electrodes which typically require barrier layers, aluminum allows for simplified cell structures and fabrication steps. In the solar cells, point contacts may be utilized in the backside electrodes for increased efficiency. Solar cells formed in accordance with the present disclosure enable large-scale and cost-effective deployment of solar photovoltaic systems. | 2019-10-10 |
20190312163 | LASER ASSISTED METALLIZATION PROCESS FOR SOLAR CELL STRINGING - Metallization of semiconductor substrates using a laser beam, and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, solar cell circuit, solar cell strings, and solar cell arrays are described. A solar cell string can include a plurality of solar cells. The plurality of solar cells can include a substrate and a plurality of semiconductor regions disposed in or above the substrate. A plurality of conductive contact structures is electrically connected to the plurality semiconductor regions. Each conductive contact structure includes a locally deposited metal portion disposed in contact with a corresponding one of the semiconductor regions. | 2019-10-10 |
20190312164 | SOLAR CELL MODULE - A solar cell module includes a front surface substrate, a seal layer arranged under the front surface substrate to seal a photoelectric converter, a low thermal expansion-contraction layer arranged under the seal layer, and a rear surface substrate arranged under the low thermal expansion-contraction layer. The solar cell module further includes a stress-reducing resin layer arranged between the low thermal expansion-contraction layer and the rear surface substrate. The low thermal expansion-contraction layer has a smaller coefficient of linear expansion than the rear surface substrate, and the stress-reducing resin layer has a smaller tensile modulus of elasticity than the low thermal expansion-contraction layer and the rear surface substrate. | 2019-10-10 |
20190312165 | SOLAR DEVICE WITH INSULATED INTERCONNECTORS - Aspects of the disclosure provide a solar device and a method for making the solar device. The solar device can include solar cells configured to form a solar cell string with at least a string terminal, and an insulated interconnector including two conductive ends configured to connect the string terminal to peripheral circuitry of the solar device. The method can include disposing the solar cells to form a solar cell string with at least a string terminal, and disposing an insulated interconnector with two conductive ends to connect the string terminal to peripheral circuitry of the solar device. | 2019-10-10 |
20190312166 | LASER ASSISTED METALLIZATION PROCESS FOR SOLAR CELL CIRCUIT FORMATION - A method of fabricating solar cell, solar laminate and/or solar module string is provided. The method may include: locating a metal foil over a plurality of semiconductor substrates; exposing the metal foil to laser beam over selected portions of the plurality of semiconductor substrates, wherein exposing the metal foil to the laser beam forms a plurality conductive contact structures having of locally deposited metal portion electrically connecting the metal foil to the semiconductor substrates at the selected portions; and selectively removing portions of the metal foil, wherein remaining portions of the metal foil extend between at least two of the plurality of semiconductor substrates. | 2019-10-10 |
20190312167 | Photovoltaic Cells - A photovoltaic cell incorporating a semiconductor element ( | 2019-10-10 |
20190312168 | Epitaxy-Free Nanowire Cell Process for the Manufacture of Photovoltaics - Photovoltaics configured to be manufactured without epitaxial processes and methods for such manufacture are provided. Methods utilize bulk semiconducting crystal substrates, such as, for example, GaAs and InP such that epitaxy processes are not required. Nanowire etch and exfoliation processes are used allowing the manufacture of large numbers of photovoltaic cells per substrate wafer (e.g., greater than 100). Photovoltaic cells incorporate electron and hole selective contacts such that epitaxial heterojunctions are avoided during manufacture. | 2019-10-10 |
20190312169 | PHOTODIODE AND METHOD OF MAKING THEREOF - A photodiode in a CMOS image sensor and a method for making the photodiode are described. To make the photodiode, protrusions and trenches are alternately patterned on the surface of a semiconductor substrate. The protrusions and trenches are doped to form a first doped layer; and an upper portion of the first doped layer is doped to form a second doped layer, the first and second doped layers comprise dopants having opposite polarities. The photodiode further includes a dielectric layer on the second doped layer. A CMOS image sensor with the photodiode has an improved quantum efficiency and enhanced performance. | 2019-10-10 |
20190312170 | SINGLE PHOTON AVALANCHE GATE SENSOR DEVICE - A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions. | 2019-10-10 |
20190312171 | GRAPHENE DEVICES FOR TERAHERTZ DETECTION AND EMISSION - Devices and methods for Terahertz (THz) sensing/detection, imaging, spectroscopy, and communication are provided. A graphene-based field effect transistor (FET) can have a quality factor of greater than 400 and a responsivity of at least 400 Volts per Watt. A FET sensor can include a substrate, a gate disposed on the substrate, an insulation layer disposed on the gate and the substrate, a source terminal and a drain terminal disposed on the substrate, and a graphene layer disposed on the insulation layer. | 2019-10-10 |