41st week of 2008 patent applcation highlights part 13 |
Patent application number | Title | Published |
20080245999 | Use of Phosphonic and Diphosphonic Diesters, and Silane-Functional, Curable Mixtures Comprising Phosphonic and Diphosphonic Diesters - Disclosed herein is a silane-functional mixture, comprising at least one phosphonic diester (A), at least one diphosphonic diester (A), or at least one phosphonic diester and one diphosphonic diester (A), and at least one compound (B) comprising at least two condensable silane groups. | 2008-10-09 |
20080246000 | Bleaching Composition - An object of the present invention is to provide a bleaching composition capable of performing a safe and convenient bleaching without using any peroxidant. The present invention provides a bleaching composition which substantially comprises a visible light-type titanium oxide and water. | 2008-10-09 |
20080246001 | Liquid crystal composition and liquid crystal display device - The invention relates to a liquid crystal composition that satisfies at least one characteristic among the characteristics such as a high maximum temperature of a nematic phase, a low minimum temperature of a nematic phase, a small viscosity or a small rotation viscosity, a large optical anisotropy, a large dielectric anisotropy, a large specific resistance, a high stability to ultraviolet light, a high stability to heat and so forth, and provide an AM device that has a short response time, a large voltage holding ratio, a large contrast ratio, a long service life and so forth. | 2008-10-09 |
20080246002 | POLAR LIQUID CRYSTAL - Compounds that are useful in compositions for flat panel displays, for example, are provided. The compounds provided are polar, and are useful in low threshold voltage mixtures. The compounds provided have the general structure: CpCOCH | 2008-10-09 |
20080246003 | Thermodynamically Stable Solutions Of Chalcogenide-Bound Lanthanide Compounds With Improved Quantum Efficiency - Thermodynamically stable solutions of chalcogenide-bound Ln compounds with one or more Ln ions coordinated or bound by chalcogenolate, chalcogenide or polychalcogenido ligands by means of the ligand chalcogenide atom, wherein the Ln compounds are dissolved at a level up to about 90 vol. % in a host solvent optically transparent to wavelengths at which excitation, fluorescence or luminescence of the Ln ions occurs. | 2008-10-09 |
20080246004 | SCINTILLATOR NANOPARTICLES AND METHOD OF MAKING - A nanomaterial comprising a plurality of nanoparticles. The plurality of nanoparticles includes at least one dopant and at least one of a metal oxide, a metal phosphate, a metal silicate, a metal hafnate, a metal aluminate, and combinations thereof. The metal is one of an alkali earth metal, a lanthanide, and a transition metal. The plurality of nanoparticles is formed by forming a homogenized precursor solution of at least one metal precursor and at least one dopant precursor, adding a fuel and optionally at least one of a phosphate source, a silicate source, a hafnate source, and an aluminate source to the precursor solution, removing water from the precursor solution to leave a reaction concentrate, and igniting the reaction concentrate to form a powder comprising the nanomaterial. In one embodiment, the nanomaterial is a scintillator material. | 2008-10-09 |
20080246005 | Phosphor for blue-light led, blue-light led using same - A phosphor for blue-light LEDs formed by different solid solutions of (ΣLn) | 2008-10-09 |
20080246006 | Cdte/Gsh Core-Shell Quantum Dots - Quantum dots, each having a core comprising CdTe and a shell comprising GSH covering the core, are provided. The Quantum dots can be formed in a solution comprising a telluride (Te) precursor and a cadmium (Cd) precursor for forming the cores, and glutathione (GSH) for forming shells covering the cores. The cores can comprise CdTe nanocrystals grown in the solution. The growth of the nanocrystals can be limited. The quantum dots can have high fluorescence emission quantum yield such as up to about 45%, and small sizes such as from about 3.8 nm to about 6 nm. | 2008-10-09 |
20080246007 | Process For Producing Articles Having an Electrically Conductive Coating - The present invention relates to a process for producing articles having on at least part of their surface an electrically conductive coating by at least partly coating a substrate with a composition comprising finely divided electrically conductive metal particles and a binder and subjecting the coated substrate to at least one treatment with water in the presence of a halide ion source at a temperature in the range from ambient temperature to 200° C. The process of the invention allows articles having an electrically conductive coating to be produced in a simple, rapid and mild way. | 2008-10-09 |
20080246008 | SEMICONDUCTOR-ENCAPSULATING RESIN COMPOSITION AND SEMICONDUCTOR DEVICE - A semiconductor-encapsulating resin composition includes a curing agent and a compound (A) having a plurality of glycidyl ether groups. When ion viscosity of the resin composition is measured under conditions of a measurement temperature of about 175° C. and a measurement frequency of about 100 Hz, minimum ion viscosity appears at about 5 seconds or later and within about 40 seconds from a measurement starting point. The minimum ion viscosity is at least about 4.0 and at most about 7.0. A maximum slope of the ion viscosity appears at about 10 seconds or later and within about 60 seconds from the measurement starting point. The maximum slope is at least about 2.0 and at most about 6.0. | 2008-10-09 |
20080246009 | Chemiluminescent Compositions - A composition exhibiting significantly increased luminance as compared with that of a known luminescent composition is provided. The composition constitutes a system in which chemiluminescence is effected by mixing two types of compositions and includes a composition A in which an oxalic ester is present in a solid state in a solution containing the oxalic ester and a luminescent substance both dissolved therein and a composition B in which aqueous hydrogen peroxide and a catalyst is dissolved in a solution. | 2008-10-09 |
20080246010 | Apparatus And Method For Enhancing The Reconductoring Of Overhead Electric Power Lines - Equipment and associated methods for replacing existing overhead transmission line conductors with new ones while the transmission line remains in service and carrying power. The old conductor is used to pull the new conductor through a series of sheaves installed at the bottom of the insulator at each tower. Conventional tension-stringing equipment is used but it is elevated to line potential that is achieved by use of an insulating platform or insulating jacks. Current transfer between stationary and moving conductors is achieved by a current transfer device that may consist of transmission line contacting wheels and liquid metal contactors. Sag control in various conductor spans is enhanced by a stringing block with controllable friction. Equipment is also introduced which will prevent release of the conductor by the pulling device should it break while engaged by that device. | 2008-10-09 |
20080246011 | Portable Pulling Tool - A portable pulling tool is provided including an integrally formed one-piece gear case for positioning all of the gear train components. The gear train includes a combination of helical gears and a differential planetary gear unit in a unique configuration. A motor control system is provided to automatically shut off the motor when a predetermined current load is detected. A multi-segment LED is provided to indicate to the user the amount of load that is being applied. | 2008-10-09 |
20080246012 | Brush guard - A trim guard, that surrounds wooden posts sunken into the ground, as well as other embedded structures is disclosed. The trim guard protects the posts or support structures from mechanical abrasion from devices such as rotary weed trimmers. | 2008-10-09 |
20080246013 | FENCE MODULE - A fence module includes a frame, multiple panels and multiple fasteners. The frame has multiple posts and multiple rails mounted at intervals on the posts. The panels are mounted on the frame between adjacent rails. The fasteners are mounted between the panels and the rails to attach the panels to the rails. | 2008-10-09 |
20080246014 | Memory Structure with Reduced-Size Memory Element Between Memory Material Portions - A memory cell device includes a memory cell access layer, a dielectric material over the memory cell access layer, a memory material structure within the dielectric material, and a top electrode in electrical contact with the memory material structure. The memory material structure has upper and lower memory material portions and a memory material element therebetween. The lower memory material layer is in electrical contact with a bottom electrode. The lower memory material layer has an average lateral dimension. The memory material element defines an electrical property state change region therein and has a minimum lateral dimension which is substantially less than the average lateral dimension. In some examples the memory material element is a tapered structure with the electrical property state change region at the junction of the memory material element and the lower memory material layer. | 2008-10-09 |
20080246015 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 2008-10-09 |
20080246016 | Device With Damaged Breakdown Layer - A device utilizing a breakdown layer in combination with a programmable resistance material, a phase-change material or a threshold switching material. The breakdown layer having damage. | 2008-10-09 |
20080246017 | LIGHT-EMITTING DEVICE HAVING SEMICONDUCTOR NANOCRYSTAL COMPLEXES - Light-emitting devices are provided that incorporate one or more underlying LED chips or other light sources and a layer having one or more populations of nanoparticles disposed over the light source. The nanoparticles may absorb some light emitted by the underlying source, and re-emit light at a different level. By varying the type and relative concentration of nanoparticles, different emission spectra may be achieved. White light and specialty-color emission may be achieved. Devices also may include multiple LED chips, with nanoparticles disposed over one or more underlying chips in an array. | 2008-10-09 |
20080246018 | Light-emitting device - A light-emitting device includes a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer; wherein the active layer is a multi-quantum-well (MQW) active layer with a predetermined n-type doping profile. More specifically, the MQW active layer is doped with n-type dopants in the region near the p-type semiconductor layer and the n-type semiconductor layer, and the central region is not doped with the n-type dopants. | 2008-10-09 |
20080246019 | DEFECT REDUCTION BY OXIDATION OF SILICON - A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation. | 2008-10-09 |
20080246020 | Nanowire, method for fabricating the same, and device having nanowires - A nanowire according to the present invention includes: a nanowire body made of a crystalline semiconductor as a first material; and a plurality of fine particles, which are made of a second material, including a constituent element of the semiconductor, and which are located on at least portions of the surface of the nanowire body. The surface of the nanowire body is smooth. | 2008-10-09 |
20080246021 | Single electron transistor and method of manufacturing the same - A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot. | 2008-10-09 |
20080246022 | Method for Producing Planar Transporting Resonance Heterostructures - An electron transport device, including at least one transport layer in which at least one periodic dislocation and/or defect array is produced, and a mechanism for guiding electrons in the transport layer. | 2008-10-09 |
20080246023 | Transistor Based on Resonant Tunneling Effect of Double Barrier Tunneling Junctions - The present invention relates to a transistor based on resonant tunneling effect of double barrier tunneling junctions comprising: a substrate, an emitter, a base, a collector and a first and a second tunneling barrier layers; wherein the first tunneling barrier layer is located between the emitter and the base, and the second tunneling barrier layer is located between the base and the collector; furthermore, the junction areas of the tunneling junctions which are formed between the emitter and the base and between the base and collector respectively are 1 μm | 2008-10-09 |
20080246024 | Method For Patterning An Organic Material To Concurrently Form An Insulator And A Semiconductor And Device Formed Thereby - A method for fabricating an electronic device includes forming a layer of precursor material for forming a semi-conductor material in a cured state and exposing the precursor material to light. The precursor is heated in the presence of the light to form an insulator in areas exposed to light and a semiconductor in areas not exposed to the light. The light is preferably in the visible range. Suitable precursors may include 6,13-dihydro-6,13-(2,3,4,5-tetrachloro-2,4-cyclohexadieno)-pentacene ( | 2008-10-09 |
20080246025 | Semiconductor device and method for manufacturing the same - It is an object to provide an element structure in which defects are not easily generated and a semiconductor device that has the element. An element has a structure in which a layer containing an organic compound is interposed between a pair of electrode layers of a first electrode layer and a second electrode layer. At least one of the pair of the electrode layers has a Young's modulus of 7.5×10 | 2008-10-09 |
20080246026 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes a substrate on which a transistor area and a capacitor area are defined, a semiconductor layer formed at the transistor area, and a capacitor having a plurality of electrodes. The plurality of electrodes include a first electrode, a second electrode that is disposed on the first electrode with an insulation layer formed between the first and second electrodes, and a third electrode that is disposed on the second electrode with an insulation layer formed between the second and third electrodes and connected to the first electrode through at least two contact holes. | 2008-10-09 |
20080246027 | Organic light emitting display and manufacturing method thereof - An organic light emitting display and a fabricating method thereof, where the display has sub-pixels of various types, which have distinctive shapes formed therein according to type is disclosed. Pixels of a particular type e.g., red, green, or blue, can be identified through visual recognition of the distinctive pattern. | 2008-10-09 |
20080246028 | MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING MEMORY DEVICE - Objects are to solve inhibition of miniaturization of a memory element and complexity of a manufacturing process thereof and to provide a nonvolatile memory device and a semiconductor device each having the memory device, in which data can be additionally written except at the time of manufacture and in which forgery or the like caused by rewriting of data can be prevented, and a memory device and a semiconductor device that are inexpensive and nonvolatile. The present invention provides a semiconductor device that includes a plurality of memory elements, in each of which a first conductive layer, a second conductive layer disposed beside the first conductive layer, and a mixed film that are disposed over the same insulating film. The mixed film contains an inorganic compound, an organic compound, and a halogen atom and is disposed between the first conductive layer and the second conductive layer. | 2008-10-09 |
20080246029 | Thin film transistor, organic light emitting display device including the same, and method of manufacturing the organic light emitting display device - A thin film transistor, e.g., for use in an organic light emitting display, may include: a gate insulating layer disposed on a gate electrode located on a substrate; a semiconductor layer, disposed on the gate insulating layer; and a planarization layer disposed on the gate insulating layer, the source and drain electrodes, and the channel area, and having openings exposing parts of the first source and drain areas and the source and drain electrodes, respectively. The semiconductor layer may include: a channel area corresponding to the gate electrode; first source and drain areas doped with an impurity outside the channel area; second source and drain areas, including a metal, outside the first source and drain areas; and source and drain electrodes disposed on the second source and drain areas and exposing the first source and drain areas. A pixel electrode may be disposed in one of the openings. | 2008-10-09 |
20080246030 | TEST STRUCTURES AND METHODS FOR INSPECTION OF SEMICONDUCTOR INTEGRATED CIRCUITS - Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area. | 2008-10-09 |
20080246031 | PCM pad design for peeling prevention - A semiconductor structure is provided. The semiconductor structure includes a semiconductor chip and a scribe line adjoining the semiconductor chip. A conductive feature is formed in the scribe line and exposed on the surface of the scribe lines, wherein the conductive feature has an edge facing the semiconductor chip. A kerf path is in the scribe line. A first cut is formed in the conductive feature, wherein the first cut extends from the first edge to the kerf path. | 2008-10-09 |
20080246032 | TEST STRUCTURE FOR DETECTING VIA CONTACT SHORTING IN SHALLOW TRENCH ISOLATION REGIONS - A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area. | 2008-10-09 |
20080246033 | THIN FILM TRANSISTOR, ORGANIC LIGHT EMITTING DEVICE INCLUDING THIN FILM TRANSISTOR, AND MANUFACTURING METHOD THEREOF - The present invention relates to a thin film transistor, a method thereof and an organic light emitting device including the thin film transistor. According to an embodiment of the present invention, the thin film transistor includes a substrate, a control electrode, an insulating layer, a first electrode and a second electrode, a first ohmic contact layer and a second ohmic contact layer, and a semiconductor layer. The control electrode is formed on the substrate, and the insulating layer is formed on the control electrode. The first and the second electrodes are formed on the insulating layer. The first ohmic contact layer and the second ohmic contact layer are formed on the first electrode and the second electrode. The semiconductor layer is formed on the first ohmic contact layer and the second ohmic contact layer to fill between the first and the second electrodes. | 2008-10-09 |
20080246034 | THIN FILM TRANSISTOR FOR FLAT PANEL DISPLAY AND METHOD OF FABRICATING THE SAME - A thin film transistor for a flat panel display, and more particularly to a thin film transistor for a flat panel display having a protrusion in a part of a gate electrode includes a substrate on which an insulating layer is deposited, a semiconductor layer, which is a layer having predetermined width and length on the insulating layer, provided with doping regions in a letter U shape and a channel region between the doping regions; a gate insulating layer formed on the semiconductor layer; a gate electrode formed on the gate insulating layer to traverse the doping region; and a protrusion, which is a part of the gate electrode, formed on the gate insulating layer to be opposed to the channel region. | 2008-10-09 |
20080246035 | Semiconductor device and display appliance using the semiconductor device - In order to provide a semiconductor device having a circuit for operating normally even when the amplitude of a signal voltage is smaller than the amplitude of a power source voltage, a correcting circuit is provided before a digital circuit to be operated normally. As for a signal outputted from the correcting circuit, when a transistor in the objective digital circuit is required to be turned OFF, the correcting circuit outputs a corresponding signal, namely a first power source potential. At this time, the transistor is turned OFF. On the other hand, when the transistor is required to be turned ON, the correcting circuit outputs a first input potential. Consequently, the objective digital circuit is turned OFF when it is required to be in an OFF state while turned ON when it is required to be in an ON state. Thereby, the objective digital circuit can be normally operated. | 2008-10-09 |
20080246036 | Semiconductor Device, Television Set, and Method for Manufacturing The Same - An object of the invention is to provide a method for manufacturing a substrate having a film pattern such as an insulating film, a semiconductor film, or a conductive film with an easy process, and further, a semiconductor device and a television set having a high throughput or a high yield at low cost and a manufacturing method thereof. One feature of the invention is that a first film pattern is formed by a droplet discharge method, a photosensitive material is discharged or applied to the first film pattern, a mask pattern is formed by irradiating a region where the first film pattern and the photosensitive material are overlapped with a laser beam and by developing, and a second film pattern having a desired shape is formed by etching the first film pattern using the mask pattern as a mask. | 2008-10-09 |
20080246037 | Flat display device and method of manufacturing the same - Provided is a flat display device, and more particularly, an active matrix (AM) flat display device having a thin film transistor (TFT). The flat display device includes a substrate, a plurality of TFTs (thin film transistors) provided on the substrate, each TFT comprising an active layer, a source electrode and a drain electrode that contact the active layer, and an ohmic contact layer interposed between the active layer and the source and drain electrodes, and a light emitting device electrically connected to the TFT, wherein the ohmic contact layer and a layer including the source and drain electrodes are formed to have the same pattern. | 2008-10-09 |
20080246038 | DISPLAY DEVICE AND CONTROL METHOD OF THE SAME - A display device including a first gate line and a second gate line that extend in parallel with each other, a data line crossing the first and second gate lines to form a pixel region, a pixel electrode in the pixel region and including a main pixel electrode and a sub pixel electrode, which are connected to the first gate line and the data line, a control thin film transistor connected to the second gate line and the sub pixel electrode, and a gate driver. The gate driver outputs a first gate signal to the first gate line and a second gate signal to the second gate line. The first gate signal activates the first gate line during a first time and a second time following the first time, and the second gate signal activates the second gate line during the first time but not the second time. | 2008-10-09 |
20080246039 | Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor - The formation of contact holes and a capacitor is performed in a semiconductor integrated circuit such as an active matrix circuit. An interlayer insulator having a multilayer (a lower layer is silicon oxide; an upper layer is silicon nitride) each having different dry etching characteristic is formed. Using a first mask, the silicon nitride corresponding to the upper layer in the interlayer insulator is etched by dry etching. This etching is completed by using the silicon oxide corresponding to the lower layer as an etching stopper. A pattern is formed using a second mask to form selectively the silicon oxide corresponding to the lower layer. Thus a first portion that the silicon oxide and the silicon nitride are etched and a second portion that only silicon nitride is etched are obtained. The first portion is used as a contact hole. A capacitor is formed in the second portion. | 2008-10-09 |
20080246040 | LIGHT EMITTING DEVICE HAVING LIGHT EMITTING ELEMENTS - A light-emitting device operating on a high drive voltage and a small drive current. LEDs ( | 2008-10-09 |
20080246041 | METHOD OF FABRICATING SOI nMOSFET AND THE STRUCTURE THEREOF - A method of fabricating a silicon-on-insulator (SOI) N-channel metal oxide semiconductor field effect transistor (nMOSFET), where the transistor has a structure incorporating a gate disposed above a body of the SOI substrate. The body comprises of a first surface and a second surface. The second surface interfaces between the body and the insulator of the SOI. Between the first surface and second surface is defined a channel region separating a source region and a drain region. Each of the source region and drain region includes a third surface under which is embedded crystalline silicon-carbon (Si:C), which extends from the second surface to the third surface. | 2008-10-09 |
20080246042 | Pixel structure and method for forming the same - A pixel structure comprising at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer, and a third conductive layer is provided. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at least one first opening covers the first conductive layer. The second conductive layer is formed on a part of the interlayer dielectric layer and is electrically connected to the first conductive layer through the first opening. The passivation layer having at least one second opening covers the transistor and the second conductive layer. The third conductive layer is formed on a part of the passivation layer and is electrically connected to the transistor through the second opening. The first storage capacitor is formed by the third conductive layer, the passivation layer, and the second conductive layer. | 2008-10-09 |
20080246043 | Light-emitting device - A pair of bonding electrodes of each of light-emitting semiconductor devices of RGB is disposed in a point symmetrical relationship, the devices are mounted on a common electrode of a package, and a bonding wire is suspended from a commonized bonding electrode of the respective devices to the common electrode. Bonding wires are suspended from the other bonding electrodes of the respective devices to first to third electrodes on the package which are independent from one another. | 2008-10-09 |
20080246044 | LED device with combined Reflector and Spherical Lens - A light source and method for making the same are disclosed. The light source includes a substrate having a top surface, a die, and a first encapsulating layer. The die includes an LED attached to the top surface and electrically connected to traces in the substrate that power the LED. The first dome covers the die and is in contact with the top surface, the dome having an angle of contact greater than 90° with respect to the top surface. The first dome has an outer surface that includes a truncated sphere characterized by a center for the spherical portion of the surface, and the die is situated at a position below the center. A second dome can be provided around the outside of the first dome. In addition, the first dome may include light converting and/or scattering materials. | 2008-10-09 |
20080246045 | Light-emitting diode packaging structure - A light-emitting diode packaging structure includes a thermally conductive substrate; a circuit layer provided on one surface of the substrate and having an electric connection element; at least one chip mounted on the circuit layer to electrically connect to the electric connection element; alight-reflective case enclosing at least part of the substrate and being formed of a window, via which light emitted by the chip is projected outward; and a light-pervious colloidal seal fitted in the window of the case to form a protection around the chip. With the above structure, heat produced by the chip during operation thereof may be effectively radiated and dissipated via the thermally conductive substrate. | 2008-10-09 |
20080246046 | Pixel Structure For A Solid State Light Emitting Device - A light emitting device includes an active layer structure, which has one or more active layers with luminescent centers, e.g. a wide bandgap material with semiconductor nano-particles, deposited on a substrate. For the practical extraction of light from the active layer structure, a transparent electrode is disposed over the active layer structure and a base electrode is placed under the substrate. Transition layers, having a higher conductivity than a top layer of the active layer structure, are formed at contact regions between the upper transparent electrode and the active layer structure, and between the active layer structure and the substrate. Accordingly the high field regions associated with the active layer structure are moved back and away from contact regions, thereby reducing the electric field necessary to generate a desired current to flow between the transparent electrode, the active layer structure and the substrate, and reducing associated deleterious effects of larger electric fields. | 2008-10-09 |
20080246047 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device comprises an N-type semiconductor layer, an active layer formed on the surface of the N-type semiconductor layer, a P-type semiconductor layer formed on the surface of the active layer, and a reflective layer formed on the surface of the P-type semiconductor layer. A plurality of ohmic contact blocks with electrical properties of ohmic contact are on the surface of the reflective layer adjacent to the P-type semiconductor layer, and the remaining part of the surface acts as the reflective regions with higher reflectivity, and the reflective regions can effectively reflect the light generated from the active layer. | 2008-10-09 |
20080246048 | Semiconductor Light-Emitting Device - A semiconductor light-emitting device, the device includes a substrate, a semiconductor stacked layer, a lead electrode and a lead, wherein the semiconductor stacked layer at least includes a N-type layer and a P-type layer, at least one of the N-type layer and the P-type layer has an opening, the opening is just beneath the lead; or includes a conductive substrate having a main surface and a back surface, an adhesive metal layer, a reflective/ohmic metal layer, a semiconductor stacked layer, a lead electrode and a lead sequentially deposited on the main surface of the substrate, the reflective/ohmic metal layer has an opening, the opening is just beneath the lead. | 2008-10-09 |
20080246049 | Semiconductor Device, Method for Fabricating an Electrode, and Method for Manufacturing a Semiconductor Device - A semiconductor device includes a p-type nitride semiconductor layer ( | 2008-10-09 |
20080246050 | ORGANIC LIGHT-EMITTING DEVICE INCLUDING TRANSPARENT CONDUCTING OXIDE LAYER AS CATHODE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting device including a transparent conducting oxide layer as a cathode and a method of manufacturing the organic light-emitting device. The organic light-emitting device includes an anode disposed on a substrate. An organic functional layer including at least an organic light-emitting layer is disposed on the anode. The transparent conducting oxide layer used as the cathode is disposed on the organic functional layer. The transparent conducting oxide layer cathode is formed by plasma-assisted thermal evaporation. A microcavity structure is not formed in the organic light-emitting device, thereby avoiding a luminance change and a color shift as a function of viewing angle. | 2008-10-09 |
20080246051 | LIGHT EMITTING APPARATUS AND METHOD FOR MANUFACTURING SAME - A light emitting apparatus includes: a light emitting element including a laminated body, an electrode provided on the laminated body, and a pad electrode provided on the electrode, the laminated body including a semiconductor light emitting layer; a mounting member having a metal bonding layer; and an alloy solder containing gold for bonding the pad electrode to the metal bonding layer. The pad electrode has at least a first gold layer provided on the electrode and being thicker than the electrode and a first metal barrier layer provided on the first gold layer, and the melting point of the alloy solder is lower than the melting point of alloys with elements constituting the first metal barrier layer and the alloy solder. | 2008-10-09 |
20080246052 | Electronic component assembly with composite material carrier - The present invention relates to an electronic component assembly including a composite material carrier, a circuit carrier made of a dielectric material, a circuit with a conductive material formed on the circuit carrier, an intermediate layer between the circuit carrier and the composite material carrier, and an electronic component arranged on the composite material carrier and electrically connecting to the circuit. | 2008-10-09 |
20080246053 | P-Type Group III Nitride Semiconductor and Production Method Thereof - An object of the present invention is to provide a method for producing a p-type Group III nitride semiconductor which can be used to produce a light-emitting device exhibiting a low operation voltage and a sufficiently high reverse voltage. | 2008-10-09 |
20080246054 | SELF-SUPPORTED NITRIDE SEMICONDUCTOR SUBSTRATE AND ITS PRODUCTION METHOD, AND LIGHT-EMITTING NITRIDE SEMICONDUCTOR DEVICE USING IT - A self-supported nitride semiconductor substrate of 10 mm or more in diameter having an X-ray diffraction half width of 500 seconds or less in at least one of a {20-24} diffraction plane and a {11-24} diffraction plane. | 2008-10-09 |
20080246055 | SEMICONDUCTOR COMPONENT INCLUDING A MONOCRYSTALLINE SEMICONDUCTOR BODY AND METHOD - A semiconductor component comprising a monocrystalline semiconductor body, and to a method for producing the same is disclosed. In one embodiment, the semiconductor body has a semiconductor component structure with regions of a porous-mono crystalline semiconductor. | 2008-10-09 |
20080246056 | SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET - Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen-containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel. | 2008-10-09 |
20080246057 | Silicon layer for stopping dislocation propagation - A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices. | 2008-10-09 |
20080246058 | GALLIUM NITRIDE MATERIAL TRANSISTORS AND METHODS ASSOCIATED WITH THE SAME - Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation. | 2008-10-09 |
20080246059 | Device Fabrication by Anisotropic Wet Etch - A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal. | 2008-10-09 |
20080246060 | TRANSISTOR - A transistor includes a nitride semiconductor layer and a gate electrode layer. The gate electrode layer includes a tantalum nitride layer being formed on the nitride semiconductor layer. The tantalum nitride layer forms a Schottky junction with the nitride semiconductor layer. The transistor also includes an insulating film formed on the nitride semiconductor layer. The insulating film surrounds the gate electrode layer. The portion of the gate electrode layer in contact with the nitride semiconductor layer has a higher nitrogen mole fraction than the other portion of the gate electrode layer. | 2008-10-09 |
20080246061 | STRESS LAYER STRUCTURE - A stress layer structure disposed on a substrate including a device region and a non-device region is provided. The device region includes active regions and a non-active region. The stress layer structure has stress patterns, at least one partition line, and at least one dummy stress pattern. Each of the stress patterns is disposed on the substrate of each of the active regions, respectively. The partition line exposes a portion of the substrate and divides the two adjacent stress patterns. The dummy stress pattern is disposed on the substrate in the partition line. | 2008-10-09 |
20080246062 | Semiconductor based controllable high resistance device - The field of invention is in the area of MOS integrated circuits operating with very low currents in the weak inversion region or sub threshold. The method aims at providing linear resistor with a value in the multi-mega ohm range. | 2008-10-09 |
20080246063 | PHOTODIODE WITH MULTI-EPI FILMS FOR IMAGE SENSOR - The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate; a first epitaxy semiconductor layer disposed on the semiconductor substrate and having a first type of dopant and a first doping concentration; a second epitaxy semiconductor layer disposed over the first epitaxy semiconductor layer and having the first type of dopant and a second doping concentration less than the first doping concentration; and an image sensor on the second epitaxy semiconductor layer. | 2008-10-09 |
20080246064 | Semiconductor device and electronic device using the same - To provide a semiconductor device which can detect low illuminance. A photoelectric conversion element, a diode-connected first transistor, and a second transistor are included. A gate of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor through the photoelectric conversion element. The other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor. By using transistors which have different threshold voltages for the first transistor and the second transistor, a semiconductor device which can perform detecting of low illuminance can be obtained. | 2008-10-09 |
20080246065 | IMAGING APPARATUS, IMAGING SYSTEM, ITS CONTROLLING METHOD, AND STORAGE MEDIUM STORING ITS PROGRAM - An idling time period after applying a bias to a conversion element until a start of an accumulation of the conversion element for deriving an image and an accumulation period from the start of the accumulation to a termination of the accumulation are measured. An offset correction of the image is conducted by using a dark current accumulation charge quantity in the accumulation calculated based on the measured idling time period and accumulation period and stored dark current response characteristics. Thus, even just after applying the bias to the conversion element, the offset correction can be properly conducted. An imaging apparatus which can execute a good radiographing without increasing costs and a size even just after applying the bias to the conversion element is provided. | 2008-10-09 |
20080246066 | Optic wafer with reliefs, wafer assembly including same and methods of dicing wafer assembly - An optic wafer for assembly with an imager wafer, the optic wafer comprising a plurality of reliefs in a surface thereof coincident with street locations separating mutually adjacent optic element locations. A wafer assembly that includes the optic wafer and an imager wafer and methods of dicing a wafer assembly are also disclosed. | 2008-10-09 |
20080246067 | Dram device and method of manufacturing the same - In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device. | 2008-10-09 |
20080246068 | TRENCH CAPACITORS AND MEMORY CELLS USING TRENCH CAPACITORS - A trench structure, a method of forming the trench structure, a memory cell using the trench structure and a method of forming a memory cell using the trench structure. The trench structure includes: a substrate; a trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into said substrate; the upper region of the trench having a vertical sidewall profile; and the middle region of the trench having a tapered sidewall profile. | 2008-10-09 |
20080246069 | Folded Node Trench Capacitor - A trench capacitor is filled with a set of two or more storage plates by consecutively depositing layers of dielectric and conductor and making contact to the ground plates by etching an aperture through the plates to the buried plate in the substrate and connecting the one or more ground plate to the substrate; the charge storage plates are connected at the top of the capacitor by blocking the end of the first plate during the formation of the second ground plate and exposing the material of the first storage plate during deposition of the second storage plate. | 2008-10-09 |
20080246070 | METHODS AND APPARATUS FOR FORMING A POLYSILICON CAPACITOR - An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a high dose of implant into the first layer of polysilicon. The method also includes depositing a layer of dielectric over the first layer of polysilicon and depositing a second layer of polysilicon over the layer of dielectric. The method further includes implanting an equivalent concentration of implant in both the first layer of polysilicon into the second layer of polysilicon. | 2008-10-09 |
20080246071 | MOS VARACTORS WITH LARGE TUNING RANGE - A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the MOS varactor to reduce C | 2008-10-09 |
20080246072 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - In a nonvolatile semiconductor memory device including a memory cell column formed by connecting in series a plurality of memory cells each having a structure in which a charge-storage layer and a control gate are stacked via an insulating layer on a semiconductor substrate, a first selection transistor formed on the semiconductor substrate and connected between one end of the memory cell column and a common source line, and a second selection transistor formed on the semiconductor substrate and connected between the other end of the memory cell column and a bit line, a recessed portion is formed on a surface of the semiconductor substrate between the first selection transistor and a memory cell adjacent to the first selection transistor, and an edge at a side of the first selection transistor in the recessed portion reaches an end portion at a side of the memory cell in a gate of the first selection transistor. | 2008-10-09 |
20080246073 | Nonvolatile Memory Devices Including a Resistor Region - Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor. | 2008-10-09 |
20080246074 | Two-Bits Per Cell Not-And-Gate (NAND) Nitride Trap Memory - A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semiconductor substrate between the first source/drain region and the second source/drain region. A plurality of memory cells are disposed on the main surface above the well region. Each memory cell includes a first oxide layer formed on the main surface of the substrate, a charge storage layer disposed above the blocking oxide layer relative to the main surface of the semiconductor substrate and second oxide layer disposed above the charge storage layer relative to the main surface of the semiconductor substrate. A plurality of wordlines are disposed above the second oxide layer relative to the main surface of the semiconductor substrate. | 2008-10-09 |
20080246075 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a plurality of gate electrodes for a plurality of memory cell transistors on a surface of a semiconductor substrate, each gate electrode including a polycrystalline layer on an upper portion thereof; filling a first silicon oxide film between the plurality of gate electrodes; exposing the polycrystalline layers; depositing a metal layer on the polycrystalline layers; alloying the metal layer with the polycrystalline layers to form silicide layers and removing a remainder metal layer unused as the silicide layer; forming a second silicon oxide film on and between the gate electrodes, an upper surface of the second silicon oxide film being higher than an upper surface of the gate electrode in regions over the gate electrodes and regions between the gate electrodes; and forming a silicon nitride film on the second silicon oxide film. | 2008-10-09 |
20080246076 | Methods for nanopatterning and production of nanostructures - Methods for nanopatterning and methods for production of nanoparticles utilizing such nanopatterning are described herein. In exemplary embodiments, masking nanoparticles are disposed on various substrates and to form a nanopatterned mask. Using various etching and filling techniques, nanoparticles and nanocavities can be formed using the masking nanoparticles and methods described throughout. | 2008-10-09 |
20080246077 | Method of fabricating semiconductor memory device and semiconductor memory device fabricated by the method - In a method for fabricating a semiconductor memory device and a semiconductor memory device fabricated by the method, the method includes forming a multi-layered dielectric structure including a first dielectric layer with an ion implantation layer and a second dielectric layer without an ion implantation layer, over a semiconductor substrate; forming nanocrystals in the first and second dielectric layers by diffusing ions of the ion implantation layer by thermally treating the multi-layered dielectric structure; and forming a gate electrode on the multi-layered dielectric structure. | 2008-10-09 |
20080246078 | Charge trap flash memory device and memory card and system including the same - A charge trap flash memory device and method of making same are provided. The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity. | 2008-10-09 |
20080246079 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode. | 2008-10-09 |
20080246080 | Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS) - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device further includes a shallow trench isolation (STI) region to increase the resistance from the drain region to the source region. The STI region includes a first side vertically aligned with a second side of the gate region. The STI region extends from the first side to a second side in contact with a second side of the drain region. The breakdown voltage of the n-type semiconductor device is directly proportional to a vertical length, or a depth, of the first side and/or the second side of the STI region. The horizontal length, or distance from the first side to the second side, of the STI region does not substantially contribute to the breakdown voltage of the semiconductor device. As a result, a conventional CMOS logic foundry technology may fabricate the STI region of the semiconductor device using a low operating voltage process minimum design rule. | 2008-10-09 |
20080246081 | Self-Aligned Trench MOSFET and Method of Manufacture - A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions. | 2008-10-09 |
20080246082 | Trenched mosfets with embedded schottky in the same cell - A semiconductor power device includes trenched semiconductor power device comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an insulation layer covering the trenched semiconductor power device with a source-body contact trench opened therethrough the source and body regions and extending into an epitaxial layer below the body regions and filled with contact metal plug therein. The semiconductor power device further includes an embedded Schottky diode disposed near a bottom of the source-body contact trench below the contact metal plug wherein the Schottky diode further includes a Schottky barrier layer having a barrier height for reducing a leakage current through the embedded Schottky diode during a reverse bias between the drain and the source. | 2008-10-09 |
20080246083 | Recessed drift region for HVMOS breakdown improvement - A high-voltage metal-oxide-semiconductor (HVMOS) device having increased breakdown voltage and methods for forming the same are provided. The HVMOS device includes a semiconductor substrate; a gate dielectric on a surface of the semiconductor substrate; a gate electrode on the gate dielectric; a source/drain region adjacent and horizontally spaced apart from the gate electrode; and a recess in the semiconductor substrate and filled with a dielectric material. The recess is between the gate electrode and the source/drain region, and is horizontally spaced apart from the gate electrode. | 2008-10-09 |
20080246084 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A power semiconductor device includes: a first semiconductor substrate; a second semiconductor layer; a plurality of third semiconductor pillar regions and a plurality of fourth semiconductor pillar regions that are provided in an upper layer of the second semiconductor layer and alternatively arranged along a direction parallel to an upper surface of the first semiconductor substrate; a first main electrode; and a second main electrode. A concentration of first-conductivity-type impurity in a connective portion between the second semiconductor layer and the third semiconductor pillar regions is lower than concentrations of first-conductivity-type impurity in portions of both sides of the connective portion in a direction from the second semiconductor layer to the third semiconductor pillar regions. | 2008-10-09 |
20080246085 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer that are provided above the first semiconductor layer and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layers and connected to the third semiconductor layer; a fifth semiconductor layer; a control electrode; a gate insulating film; a first main electrode; and a second main electrode. An array period of the fourth semiconductor layers is larger than an array period of the second semiconductor layers. A thickness of a part of the gate insulating film disposed in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of a part of the gate insulating film disposed in the immediate upper region of the fourth semiconductor layer. Sheet impurity concentrations of the second semiconductor layer and the third semiconductor layer that are located in the central portion are higher than a sheet impurity concentration of the third semiconductor layer disposed in an immediately lower region of the fourth semiconductor layer. | 2008-10-09 |
20080246086 | SEMICONDUCTOR DEVICES HAVING CHARGE BALANCED STRUCTURE - A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region. | 2008-10-09 |
20080246087 | MOS TRANSISTOR FOR REDUCING SHORT-CHANNEL EFFECTS AND ITS PRODUCTION - The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove. And the process for the MOS transistor includes the following steps: forming the groove; carrying out well implantation, anti-punchthrough implantation and threshold-voltage adjustment implantation; forming the gate stack in the groove which comprising patterning the gate electrode; carrying lightly doped drain implantation and halo implantation; forming the gate sidewall spacer; carrying source and drain implantation to get the source and drain areas; forming a metal silicide layer on the source and drain areas. | 2008-10-09 |
20080246088 | Self-Aligned Lightly Doped Drain Recessed-Gate Thin-Film Transistor - A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench. | 2008-10-09 |
20080246089 | Method of manufacturing thin film transistor - Disclosed is a method of manufacturing a thin film transistor, in which a semiconductor layer and a gate insulating film may be formed through ink jet printing using a single bank, thereby simplifying the manufacturing process and decreasing the manufacturing cost, leading to more economical thin film transistors. The thin film transistor manufactured using the method of example embodiments may be used as a switching element for sensors, memory devices, optical devices, and active matrix flat panel displays. | 2008-10-09 |
20080246090 | SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE - A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body. | 2008-10-09 |
20080246091 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows. | 2008-10-09 |
20080246092 | Semiconductor device structure with strain layer and method of fabricating the semiconductor device structure - A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect. | 2008-10-09 |
20080246093 | STRUCTURE AND METHOD OF MAKING A SEMICONDUCTOR INTEGRATED CIRCUIT TOLERANT OF MIS-ALIGNMENT OF A METAL CONTACT PATTERN - Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer is deposited in/or on the semiconductor substrate. Subsequently a second spacer covering the surface of the first spacer, and a contact liner over at least the gate stack, the second spacer and the silicide, are formed. Then an interlayer dielectric over the contact liner is deposited. Next, a metal contact opening is formed to expose the contact liner over the silicide. Finally, the opening is extended through the contact liner to expose the silicide without exposing the substrate. | 2008-10-09 |
20080246094 | Method for Manufacturing SRAM Devices with Reduced Threshold Voltage Deviation - A semiconductor device includes a semiconductor substrate; a gate dielectric layer disposed on the semiconductor substrate; a gate conductive layer doped with impurities selected from nitrogen, carbon, silicon, germanium, fluorine, oxygen, helium, neon, xenon or a combination thereof on the gate dielectric layer; and source/drain doped regions formed adjacent to the gate conductive layer in the semiconductor substrate, wherein the source and drain doped regions are substantially free of the impurities doped into the gate conductive layer. These impurities reduce the diffusion rates of the N-type of P-type dopants in the gate conductive layer, thereby improving the device performance. | 2008-10-09 |
20080246095 | AMBIPOLAR TRANSISTOR DESIGN - An ambipolar transistor, including a p-type semiconductor region and an n-type semiconductor region near the p-type semiconductor region. Also a first terminal and second terminal contact both the p-type semiconductor region and the n-type semiconductor region. Furthermore, the p-type semiconductor region and the n-type semiconductor region substantially do not overlap each other. A method of manufacturing an ambipolar transistor is also disclosed, including forming a p-type semiconductor region, forming an n-type semiconductor region near the p-type semiconductor region, forming a first terminal contacting both the p-type semiconductor region and n-type semiconductor region, forming a second terminal contacting both the p-type semiconductor region and n-type semiconductor region; and wherein the p-type semiconductor region and the n-type semiconductor region substantially do not overlap, and have substantially no interfacial area. | 2008-10-09 |
20080246096 | Semiconductor device including schottky barrier diode and method of manufacturing the same - A semiconductor device includes a substrate, a plurality of first columns having a first conductivity type, a plurality of second columns having a second conductivity type, a first electrode, and a second electrode. The first columns and the second columns are alternately arranged on the substrate to provide a super junction structure. The first electrode is disposed on the super junction structure, forms schottky junctions with the first columns, and forms ohmic junctions with the second columns. The second electrode is disposed on the substrate on an opposite side of the super junction structure. At least a part of the substrate and the super junction structure has lattice defects to provide a lifetime control region at which a lifetime of a minority carrier is controlled to be short. | 2008-10-09 |
20080246097 | METHODS FOR REDUCING WITHIN CHIP DEVICE PARAMETER VARIATIONS - A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip. | 2008-10-09 |
20080246098 | SPLIT-CHANNEL ANTIFUSE ARRAY ARCHITECTURE - Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor. More specifically, the present invention provides an effective method for utilizing split channel MOS structures as an anti-fuse cell suitable for OTP memories. | 2008-10-09 |