41st week of 2020 patent applcation highlights part 69 |
Patent application number | Title | Published |
20200321903 | CONTROL DEVICE FOR AN AC ROTATING ELECTRIC MACHINE - Provided is a control device for an AC rotating electric machine, which includes: a temperature detection unit configured to detect a temperature of a protection unit provided in an object to be protected when a current is supplied from a power conversion circuit including a switching element to the AC rotating electric machine and output, as a detected temperature, one of the temperature and a temperature of the object to be protected that is estimated from the temperature; a temperature compensation unit configured to calculate, through use of the detected temperature output from the temperature detection unit, a compensated temperature equal to or higher than the detected temperature; and a torque limiting unit configured to limit, through use of the compensated temperature calculated by the temperature compensation unit, a torque command value input thereto. | 2020-10-08 |
20200321904 | MOUNTING SYSTEM FOR ROOF MOUNTED SOLAR PANELS - A method and apparatus for efficiently securing flexible solar panels on a roof surface that does not require penetration of the roof membrane. The apparatus is composed of extruded aluminum bars with two grooves. The apparatus has a low profile relative to the surface of the roof. The aluminum bars' streamlined design allows free drainage between and over the aluminum structure, as well as an aerodynamic profile to counteract air flow resistance in a high wind environment. | 2020-10-08 |
20200321905 | SOLAR PANEL RACKING SYSTEM - A one-piece elongated roll-formed sheet metal rack channel made to order on-site, for supporting solar panels, in rows of an array, at a desired inclination relative to a generally flat horizontal surface, the channel being formed of a strip of sheet metal with a horizontal base and spaced upstanding legs, the legs being of unequal height and each with lower portions integral with a respective longitudinal margin of the base, each leg having an inturned panel supporting flange at an upper longitudinal edge, the flanges having inclined panel supporting surfaces that lie in planes generally parallel to a plane of the desired inclination, with an air gap between the upper flange and the supported solar panel, the panels along a row being electrically grounded to rack channels at the row. | 2020-10-08 |
20200321906 | METHOD OF ROUTING AND SECURING ELECTRICAL POWER CABLES FOR A SOLAR ROOF INSTALLATION - A solar roof tile with an integrated cable management system includes a roof tile weighing less than 400 lbs per 100 square feet of installed roof area and a photovoltaic solar panel attached to a front side of the roof tile. A rear side of the roof tile includes one or more channels configured to accommodate one or more electrical power cables. A method of routing and securing electrical power cables for a solar roof installation using the solar roof tiles is also disclosed. | 2020-10-08 |
20200321907 | ROOF INTEGRATED PHOTOVOLTAIC SYSTEM - A roof integrated photovoltaic (RIPV) system has a plurality of solar tiles that are mounted to a roof. The tiles may be mounted using a metal batten and hanger system or some other attachment system. Each tile has an electrical edge junction extending rearwardly from its top edge. The edge junction is coextensive with or contains the plane of the solar tile and may be slightly thicker than the solar tile. Sockets on opposed ends of the edge junction receive plugs of electrical cables for interconnecting the array of solar tiles together electrically. The edge junctions provide for a low profile installation that mimics the appearance of a traditional roofing tile such as a slate tile. The slightly thicker edge junctions may raise solar tiles of one course above the surfaces of solar tiles of a next lower course to provide ventilation for the RIPV array and to provide accommodating space for system wiring. | 2020-10-08 |
20200321908 | GLAZING ASSEMBLIES WITH INTEGRATED PHOTOVOLTAIC STRUCTURE AND SPACER STRUCTURES FOR SUCH GLAZING ASSEMBLIES - Glazing assembly are described comprising at least a first (inner) glass pane, a second (outer) glass pane and at least one peripheral spacer structure for providing a predetermined separation between the first and second glass pane, the peripheral spacer structure being positioned at the peripheral area of the first and second glass pane; one or more photovoltaic (PV) cell modules mounted on at least part of the peripheral spacer structure, the one or more PV cell modules being positioned in the space defined by the first and second glass panes and the peripheral spacer structure (inter-pane space); wherein at least part of the peripheral spacer structure comprises one or more mounting members adapted to orient a light receiving surface of PV cells of the PV cell modules in a tilted position with respect to the plane of the second (outer) glass pane. | 2020-10-08 |
20200321909 | Solar Tracking System for a Recreational Vehicle - The present disclosure is a lightweight, portable solar tracker assembly that has a bottom frame coupled to a rotation drive disc coupled to a rotational linear actuator and a middle frame rotatably coupled to the bottom frame via the rotation drive disc such that when activated, the middle frame rotates. The assembly further has a solar array mounting frame coupled to the middle frame and comprising a vertical linear actuator coupled to the middle frame such than when activated, the solar array mounting frame moves vertically, and when the middle frame rotates, the solar array mounting frame rotates and at least one solar cell fixedly coupled to the solar array mounting frame. In addition, the assembly has a processor configured to determine a position in a sky of a sun, actuate the vertical linear actuator and the rotational linear actuator so that the at least one solar cell is aligned with the sun. | 2020-10-08 |
20200321910 | INTEGRATED CIRCUIT FOR ENERGY HARVESTING WITH SYNCHRONIZATION MEANS - An integrated circuit (IC) for energy harvesting is provided. The IC includes a voltage converter for converting an input power into an output power and a power point tracker for determining a target voltage for regulating the input voltage of the voltage converter. The IC includes an interface circuit to exchange information between the controller of the IC and one or more additional IC's for energy harvesting. The controller of the IC is configured to enable switching to a normal operating state on condition that a trigger signal from the interface circuit changes from a first reference value to a second reference value. The controller is further configured for outputting a status signal to the interface circuit wherein the status signal indicates if the power point tracker is enabled or disabled. | 2020-10-08 |
20200321911 | METHOD AND APPARATUS FOR RECTIFYING DEGRADATION OF PHOTOVOLTAIC MODULE IN PHOTOVOLTAIC POWER STATION - A method for rectifying degradation of a photovoltaic module in a photovoltaic power station, includes: controlling a to-be-rectified photovoltaic module in a photovoltaic power station to stop outputting; and then injecting a rectification current into a positive or negative electrode of the to-be-rectified photovoltaic module. | 2020-10-08 |
20200321912 | ENERGY HARVESTING APPARATUS - Disclosed is an energy harvesting apparatus which comprises: a flexible energy harvesting module having a flat plate shape; a connector which is mechanically and electrically connectable to an external connector; a rigid member having a flat plate shape; and an electric wiring constituting a part of a front surface of the rigid member, wherein an edge of a back surface of the energy harvesting module is disposed on the front surface of the rigid member, and the connector is disposed on the front surface of the rigid member at a position spaced apart from the energy harvesting module and is electrically connected to the energy harvesting module via the electric wiring. | 2020-10-08 |
20200321913 | SWING TRACKING AND CONTROL - In certain aspects, an apparatus includes a transformer including an input inductor and an output inductor, wherein the input inductor is magnetically coupled to the output inductor. The apparatus also includes a transconductance driver configured to drive the input inductor based on an input signal. The apparatus further includes a feedback circuit configured to detect an output voltage swing at the output inductor, generate a regulated voltage at the input inductor, and control the regulated voltage based on the detected output voltage swing. | 2020-10-08 |
20200321914 | SEMICONDUCTOR DEVICE AND WIRELESS COMMUNICATION APPARATUS - [Overview] [Problem to be Solved] To provide a semiconductor device and a wireless communication apparatus each of which makes it possible to suppress the manufacturing cost and the power consumption while maintaining the manual operability. [Solution] There is provided a semiconductor device including: an oscillation circuit including a plurality of capacitors provided on a semiconductor substrate; a conversion circuit that converts an analog signal into a digital signal; and a switch circuit that switches the capacitors on the basis of the digital signal. An oscillation frequency linearly varies with respect to a variation in the analog signal. | 2020-10-08 |
20200321915 | MULTIPLE ADJACENT SLICEWISE LAYOUT OF VOLTAGE-CONTROLLED OSCILLATOR - Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances. | 2020-10-08 |
20200321916 | Radio Frequency Power Amplifier With Adjustable Power Supply - A semiconductor device includes at least one RF power amplifier (RFPA) and a voltage supply adjustment network coupled with the RFPA for providing an internal supply voltage to the RFPA based on an applied input voltage. The voltage supply adjustment network includes multiple resistors, multiple Zener diodes, a voltage return connection, an internal supply voltage connection coupled with the RFPA for conveying the supply voltage to the RFPA, an input voltage connection adapted to receive the input voltage, and a configurable connection network coupled with the resistors and Zener diodes. A subset of the resistors and Zener diodes are selectively connected together between the input voltage and the voltage return connections via corresponding conductive links to provide a prescribed output voltage to the internal supply voltage connection as a function of the applied input voltage. The connection network is configured by applying an energy source to a selected conductive link(s) in the connection network. | 2020-10-08 |
20200321917 | SYMBOL POWER TRACKING AMPLIFICATION SYSTEM AND A WIRELESS COMMUNICATION DEVICE INCLUDING THE SAME - A symbol power tracking amplification system including: a modem to generate data and symbol tracking signals; a symbol tracking modulator including a control circuit, first and second voltage supply circuits and a switch circuit, the control circuit generates first and second voltage level control signals in response to the symbol tracking signal, the first voltage supply circuit generates a first output voltage in response to the first voltage level control signal, the second voltage supply circuit generates a second output voltage in response to the second voltage level control signal and the switch circuit outputs the first or second output voltages as a supply voltage in response to a switch control signal; an RF block to generate an RF signal based on the data signal from the modem; and a power amplifier to adjust a power level of the RF signal based on the supply voltage. | 2020-10-08 |
20200321918 | INTEGRATED DOHERTY AMPLIFIER - An integrated Doherty amplifier based on a multichip module structure is disclosed. The amplifier comprises an input integrated passive die including a Wilkinson power divider, a phase compensation circuit and input matching circuits for the main and peaking amplifiers based on lumped components, the active GaN HEMT die including the main device, a peaking device and a bondwire inductor connected between the drain terminals of the main and peaking devices, and an output matching network including a two-section matching circuit with low-pass and high-pass matching section operating as an impedance-transforming bandpass filter and a dc-feed power supply circuit based on lumped components and microstrip lines. | 2020-10-08 |
20200321919 | NEGATIVE IMPEDANCE CIRCUIT FOR REDUCING AMPLIFIER NOISE - A circuit includes a first operational amplifier having an inverting input and a non-inverting input, and a negative resistance circuit connected to the inverting input of the operational amplifier. The negative resistance circuit includes a second operational amplifier, a current source controlled by the second operational amplifier, and a cross-coupled transistor circuit having at least one transistor biased by a current produced by the current source. | 2020-10-08 |
20200321920 | DUAL-INPUT VOLTAGE MEMORY DIGITAL PRE-DISTORTION CIRCUIT AND RELATED ENVELOPE TRACKING APPARATUS - A dual-input voltage memory digital pre-distortion (mDPD) circuit and related ET apparatus are provided. In examples discussed herein, an ET apparatus includes an amplifier circuit(s) configured to amplify a radio frequency (RF) signal based on an ET voltage. A tracker circuit is configured to generate the ET voltage based on a number of target voltage amplitudes derived from a number of signal amplitudes of the RF signal. However, the tracker circuit can cause the ET voltage to deviate from the target voltage amplitudes due to various inherent impedance variations, particularly at a higher modulation bandwidth. In this regard, a dual-input voltage mDPD circuit is configured to digitally pre-distort the target voltage amplitudes based on the signal amplitudes such that the ET voltage can closely track the target voltage amplitudes. As such, it is possible to mitigate ET voltage deviation, thus helping to improve overall linearity performance of the ET apparatus. | 2020-10-08 |
20200321921 | COMMON SOURCE PREAMPLIFIER FOR A MEMS CAPACITIVE SENSOR - A common source preamplifier for a MEMS capacitive sensor is disclosed. The preamplifier is a single-stage amplifier employing negative feedback. The preamplifier provides stable gain independent of temperature and at the same time provides effective buffering for a subsequent stage. Further, the preamplifier may be configured to provide different values of gain. Furthermore, the preamplifier has lower noise and consumes lesser area and lesser power than prior art. | 2020-10-08 |
20200321922 | POWER AMPLIFIER FAULT DETECTOR - Herein disclosed in some embodiments is a fault detector for power amplifiers of a communication system. The fault detector can detect a portion of the power amplifiers that are in fault condition and can prevent or limit current flow to the power amplifiers in fault condition while allowing the rest of the power amplifiers to operate normally. The fault detector can further indicate which power amplifiers are in fault condition and/or the cause for the power amplifiers to be in fault condition. Based on the indication, a controller can direct communications away from the power amplifiers in fault condition and/or perform operations to correct the fault condition. | 2020-10-08 |
20200321923 | CONCURRENT ELECTROSTATIC DISCHARGE AND SURGE PROTECTION CLAMPS IN POWER AMPLIFIERS - Concurrent electrostatic discharge and surge protection clamps in power amplifiers. In some embodiments, a semiconductor die can include a semiconductor substrate and an integrated circuit implemented on the semiconductor substrate. The integrated circuit can include a power amplifier and a controller. The semiconductor die can further include a clamp circuit implemented on the semiconductor substrate and configured to provide electrostatic discharge protection and surge protection for at least some of the integrated circuit. | 2020-10-08 |
20200321924 | Switched capacitor radio frequency digital power amplifier and radio frequency digital-to-analog converter - A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells. | 2020-10-08 |
20200321925 | MATCHING CIRCUIT STRUCTURE FOR EFFECTIVELY SUPPRESSING LOW-FREQUENCY CLUTTER OF POWER AMPLIFIER OF MOBILE PHONE, AND METHOD USING SAME - A matching circuit structure for effectively suppressing the low-frequency clutter of a power amplifier of a mobile phone, falling within the technical field of radio frequency Pas is provided. The circuit structure includes an input end, a blocking capacitor, a power amplifier (PA), an output matching network and an output end connected in series; and the matching circuit structure further includes a negative feedback network connected in parallel to a transmission end of the PA; the negative feedback network includes a resonant capacitor, a resonant inductor and a matching inductor; the resonant capacitor and the resonant inductor are connected in parallel to form a frequency selecting network, and the frequency selecting network is connected in series with the matching inductor and to the ground. The matching circuit structure above can be used to effectively suppress the low-frequency clutter of a power amplifier. | 2020-10-08 |
20200321926 | ADAPTABLE RECEIVER AMPLIFIER - Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node. | 2020-10-08 |
20200321927 | POWER AMPLIFIER APPARATUS - A power amplifier apparatus includes a semiconductor substrate, a plurality of first transistors on the semiconductor substrate, a plurality of second transistors, at least one collector terminal electrically connected to collectors of the plurality of first transistors, a first inductor having a first end electrically connected to the collector terminal and a second end electrically connected to a power supply potential, at least one emitter terminal electrically connected to emitters of the plurality of second transistors and adjacent to the collector terminal in a second direction, a second inductor having a first end electrically connected to the emitter terminal and a second end electrically connected to a reference potential, and at least one capacitor having a first end electrically connected to the collectors of the plurality of first transistors and a second end electrically connected to the emitters of the plurality of second transistors. | 2020-10-08 |
20200321928 | LOW POWER MODE OF OPERATION FOR MM-WAVE RADAR - Disclosed examples include a radar system that operates in a first mode and a second mode. In the first mode, the system detects the presence of an object within a threshold range. In response to detection of the presence of the object, the system transitions to the second mode, and the system generates range data, velocity data, and angle data of the object in the second mode. When the object is no longer detected within the threshold range, the system transitions back to the first mode. | 2020-10-08 |
20200321929 | RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE - A first power amplifier amplifies first transmission signals in a first frequency band and outputs the resultant signals. A first matching circuit includes a plurality of first inductor portions and is connected to an output pad electrode of the first power amplifier. A second power amplifier amplifies second transmission signals in a second frequency band higher than the first frequency band and outputs the resultant signals. A second matching circuit includes at least one second inductor portion and is connected to an output side of the second power amplifier. A multilayer substrate has a first main surface and a second main surface located opposite to each other and is provided with the first and second power amplifiers and the first and second matching circuits. The first inductor portion closer than the other first inductor portions to the output pad electrode includes an inner-layer inductor portion located in the multilayer substrate. | 2020-10-08 |
20200321930 | DIFFERENTIAL NOISE CANCELLATION - In one implementation, a circuit can include a reference pin and an operational amplifier that can include an output pin, an inverting input pin and a non-inverting input pin. The inverting input pin can be electrically coupled to the output pin via a first impedance and to the reference pin via a second impedance. The non-inverting input pin can be electrically coupled to the reference pin via a third impedance and can be configured to receive a detection signal. The reference pin can be configured to receive a detection reference signal associated with the detection signal. | 2020-10-08 |
20200321931 | AMPLIFIERS SUITABLE FOR MM-WAVE SIGNAL SPLITTING AND COMBINING - A MIMO amplifier circuit operable to couple one or more selectable input ports to one or more selectable output ports. The circuit includes N input transistors and M output transistors. Each input transistor has its base coupled to a respective input port node, its emitter coupled to ground, and its collector connected to an intermediate node. Each output transistor has its base coupled to a bias node, its emitter connected to the intermediate node, and its collector coupled to a respective output port nodes. Each input transistor enables the respective input port node when its base is biased. Each output transistor enables the respective output port node when its bias node is asserted. The base of the input transistor for each enabled port is biased to provide a quiescent current I | 2020-10-08 |
20200321932 | SLEW BOOST CIRCUIT FOR AN OPERATIONAL AMPLIFIER - A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node. | 2020-10-08 |
20200321933 | ACOUSTIC WAVE DEVICE, HIGH-FREQUENCY FRONT END CIRCUIT, COMMUNICATION DEVICE, AND METHOD FOR MANUFACTURING ACOUSTIC WAVE DEVICE - An acoustic wave device includes a piezoelectric substrate including a support substrate and a piezoelectric layer on the support substrate, the piezoelectric substrate including a first principal surface on the piezoelectric layer side, and a second principal surface on the support substrate side, an IDT electrode on the first principal surface, a support layer on the support substrate, a cover on the support layer, a through-via electrode provided through the support substrate and electrically connected to the IDT electrode, a first wiring electrode on the second principal surface of the piezoelectric substrate and electrically connected to the through-via electrode, and a protective film on the second principal surface to cover at least a portion of the first wiring electrode. The protective film is provided on an inner side of the support layer when viewed in a direction normal or substantially normal to the second principal surface. | 2020-10-08 |
20200321934 | ELECTROSTATIC CHUCK FILTER BOX AND MOUNTING BRACKET - An apparatus and method electrically coupling an electrostatic chuck RF filter box with a pedestal lift. The RF filter box has a contact block and at least one alignment feature on an outer mating surface of the RF filter block. The contact block includes self-aligning electrical connectors and the alignment feature is configured for aligning self-aligning electrical connectors with corresponding electrical connectors on the bracket of the pedestal lift such that the self-aligning electrical connectors and the corresponding electrical connectors on the bracket of the pedestal lift automatically mate when the contact block is mounted to the bracket of the pedestal lift. | 2020-10-08 |
20200321935 | Adaptive Tuning Networks with Direct Mapped Multiple Channel Filter Tuning - A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability. In a third version, CA direct mapped adaptive tuning networks include filter tuning blocks for selected lower frequency bands. | 2020-10-08 |
20200321936 | DIPLEXER HAVING LOW BAND FILTER AND HIGH BAND FILTER - A diplexer having a low band filter and a high band filter is disclosed. The disclosure provides a diplexer having a low band filter and a high band filter for preventing the circuit damage due to an electrostatic discharge in the diplexer itself, and minimizing the signal loss according to addition of an electrostatic discharge prevention circuit. | 2020-10-08 |
20200321937 | ACOUSTIC WAVE DEVICE, HIGH-FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION DEVICE - An acoustic wave device includes a silicon support substrate that includes first and second main surfaces opposing each other, a piezoelectric structure provided on the first main surface and including the piezoelectric layer, an IDT electrode provided on the piezoelectric layer, a support layer provided on the first main surface of the silicon support substrate and surrounding the piezoelectric layer, a cover layer provided on the support layer, a through-via electrode that extending through the silicon support substrate and the piezoelectric structure, and a first wiring electrode connected to the through-via electrode and electrically connected to the IDT electrode. The piezoelectric structure includes at least one layer having an insulating property, the at least one layer including the piezoelectric layer. The first wiring electrode is provided on the layer having an insulating property in the piezoelectric structure. | 2020-10-08 |
20200321938 | ACOUSTIC WAVE DEVICE, HIGH-FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION DEVICE - In an acoustic wave device, a piezoelectric body is directly or indirectly laminated on a silicon support substrate, and a functional electrode is provided on the piezoelectric body. A support layer is directly or indirectly laminated on the silicon support substrate, and the support layer is located outside the functional electrode when viewed in plan view. A silicon cover layer is provided on the support layer that includes an insulating material, and a space A is defined by the silicon support substrate, the support layer, and the silicon cover layer. The electric resistance of the silicon support substrate is higher than the electric resistance of the silicon cover layer. | 2020-10-08 |
20200321939 | TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATOR PACKAGE AND METHOD - Acoustic resonator devices and filters are disclosed. A piezoelectric plate is attached to a substrate, a portion of the piezoelectric plate forming a diaphragm spanning a cavity in the substrate. A first conductor pattern is formed on a surface of the piezoelectric plate. The first conductor pattern includes interleaved fingers of an interdigital transducer disposed on the diaphragm, and a first plurality of contact pads. A second conductor pattern is formed on a surface of a base, the second conductor pattern including a second plurality of contact pads. Each pad of the first plurality of contact pads is directly bonded to a respective pad of the second plurality of contact pads. A ring-shaped seal is form between a perimeter of the piezoelectric plate and a perimeter of the base. | 2020-10-08 |
20200321940 | ACOUSTIC RESONATOR FILTER PACKAGE - An acoustic resonator filter package includes an acoustic resonator including a piezoelectric layer, a first electrode disposed on a first surface of the piezoelectric layer, and a second electrode disposed on a second surface of the piezoelectric layer; a first substrate having an upper surface on which the acoustic resonator is disposed, the first substrate comprising a first coupling member surrounding the acoustic resonator; a filter spaced apart from the acoustic resonator in an upward direction; a second substrate having a lower surface on which the filter is disposed, the second substrate including a second coupling member disposed above the first coupling member; and a connection member connecting the first coupling member and the second coupling member to each other, the connection member being made of a material different from a material of which the first coupling member and the second coupling member are made. | 2020-10-08 |
20200321941 | ACOUSTIC WAVE FILTER, MULTIPLEXER, RADIO FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION DEVICE - An acoustic wave filter includes a substrate having piezoelectricity, input/output terminals on the substrate, ground terminals on the substrate and separated from each other, and a longitudinally coupled resonator on the substrate and arranged on a path connecting the input/output terminals, in which each of IDT electrodes included in the longitudinally coupled resonator includes a pair of comb-shaped electrodes each of which is provided with a plurality of electrode fingers and a busbar electrode, the other of the pair of the comb-shaped electrodes included in the IDT electrode arranged at a position closest to the input/output terminal is connected to the ground terminal on the substrate, and the other of the pair of comb-shaped electrodes included in each of all the IDT electrodes other than the IDT electrode is connected to the ground terminal on the substrate. | 2020-10-08 |
20200321942 | Tunable Filter for RF Circuits - A tunable filter is described where the frequency response as well as bandwidth and transmission loss characteristics can be dynamically altered, providing improved performance for transceiver front-end tuning applications. The rate of roll-off of the frequency response can be adjusted to improve performance when used in duplexer applications. The tunable filter topology is applicable for both transmit and receive circuits. A method is described where the filter characteristics are adjusted to account for and compensate for the frequency response of the antenna used in a communication system. | 2020-10-08 |
20200321943 | SYSTEMS AND METHODS FOR ANALOG FINITE IMPULSE RESPONSE FILTERS - Systems and methods for analog finite impulse response (FIR) filters are provided. In certain embodiments, a receiver includes a cascade of a mixer, an analog FIR filter, and an analog-to-digital converter (ADC). By including the analog FIR filter along the signal path between the mixer and the ADC, design constraints of the ADC are relaxed. For example, the ADC can operate with relaxed specifications with respect to resolution and/or dynamic range when the analog FIR filter is included. The analog FIR filter can include a controllable transconductance circuit that delivers an integration current to a capacitor over an integration period, with the analog FIR filter's coefficients used to change the transconductance setting of the controllable transconductance circuit to different values over the integration period. | 2020-10-08 |
20200321944 | LVDS Driver Circuit, Integrated Circuit Device, Oscillator, Electronic Apparatus, And Vehicle - An LVDS driver circuit includes: a current source; a differential unit configured to receive a first input signal and a second input signal and output a first output signal and a second output signal; and a feedback control circuit configured to be coupled to a first output node and a second output node and to perform, by outputting a control voltage to a gate of a transistor, feedback control that sets a common voltage of a differential output signal. In the differential unit, the first output node and the second output node are in a high impedance state in the high impedance mode, the differential unit is configured to output the first output signal and the second output signal in the signal output mode, and the control voltage in the high impedance mode is larger than the control voltage in the signal output mode. | 2020-10-08 |
20200321945 | DEVICE FOR MAINTAINING OPERATION STATE OF RELAY - A device for maintaining an operation state of a relay with a second voltage value that is less than a first voltage value, the first voltage value being an initial driving voltage for the relay, includes: a main switch to output an output voltage to the relay by switching an input voltage according to a main operating voltage that varies according to an ON-OFF state of a first switch; the first switch to adjust the main operating voltage according to a first operating voltage that varies according to an ON-OFF state of a second switch; the second switch to control the first operating voltage according to an output voltage of a comparator; the comparator to output the output voltage by comparing a reference voltage value with a voltage of a reference node; and a third switch to control the voltage of the reference node according to an input signal. | 2020-10-08 |
20200321946 | Generating Voltage Pulse with Controllable Width - A width of a voltage pulse signal is directly proportional to a difference between first and second resistances in a pulse generator. The voltage pulse signal is generated with a ramp signal, two reference voltages, and two comparators. The first reference voltage is generated with the first resistance and a first current, and the second reference voltage is generated with the second resistance and a second current. The first comparator produces a first comparator output in response to the first reference voltage and the ramp signal, and the second comparator produces a second comparator output in response to the second reference voltage and the ramp signal. A logic circuitry generates the voltage pulse signal in response to the two comparator outputs. | 2020-10-08 |
20200321947 | LOGIC CIRCUIT, SEQUENCE CIRCUIT, POWER SUPPLY CONTROL CIRCUIT, SWITCHING POWER SUPPLY DEVICE - A sequence circuit ( | 2020-10-08 |
20200321948 | ULTRA LOW-VOLTAGE CIRCUITS - An ultra-low voltage inverter includes a first inverter, a second inverter, and third inverter. The first inverter receives an input from a delay cell and generates an output for a subsequent delay cell. The second inverter is coupled to the first inverter. The third inverter is coupled to the first inverter, wherein outputs of the second and third inverters are coupled to source terminals of a p-type transistor and an n-type transistor of the first inverter, respectively. The ultra-low voltage inverter forms a delay cell, which is a building block of an ultra-low voltage ring-oscillator. A NAND gate is formed using three inverters such that outputs of two inverters are coupled to the p-type transistors of the NAND gate, while an output of the third inverter of the three inverters is coupled to an n-type transistor of the NAND gate. | 2020-10-08 |
20200321949 | QUANTUM LOGIC GATE DESIGN AND OPTIMIZATION - A method of performing a computational process using a quantum computer includes generating a laser pulse sequence comprising a plurality of laser pulse segments used to perform an entangling gate operation on a first trapped ion and a second trapped ion of a plurality of trapped ions that are aligned in a first direction, each of the trapped ions having two frequency-separated states defining a qubit, and applying the generated laser pulse sequence to the first and second trapped ions. Each of the plurality of laser pulse segments has a pulse shape with ramps formed using a spline at a start and an end of each of the plurality of laser pulse segments. | 2020-10-08 |
20200321950 | MEASUREMENT AND CORRECTION OF MULTIPHASE CLOCK DUTY CYCLE AND SKEW - Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal. | 2020-10-08 |
20200321951 | Signal Detector for GPON Optical Line Terminal - A circuit detects a digital pattern with a first counter having an input receiving a digital pattern, and an output providing an output signal after detecting a first number of pulses during a first time period. A latch has an input coupled to the output of the first counter for latching the output signal of the first counter. A second counter has an input receiving the digital pattern, and an output providing an output signal after detecting a second number of pulses during a second time period. A logic gate has a first input coupled the output of the first counter, and a second input coupled to the output of the second counter, and an output coupled to the input of the latch. An amplitude detection circuit has an input coupled for receiving the digital pattern and an output coupled to the input of the first counter. | 2020-10-08 |
20200321952 | COMPARATOR LOW POWER RESPONSE - In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal. | 2020-10-08 |
20200321953 | INTEGRATED CIRCUIT AND METHOD OF TESTING - An integrated circuit includes a first circuit having a loopback path electrically coupled to an inverter and a test circuit having a controller and a counter. The test circuit is electrically coupled to the first circuit, and the controller is configured to select the loopback path. The first circuit is configured to receive a first voltage signal and to generate an oscillating signal from the received first voltage signal. The first voltage signal is either a substantially low logic level signal or a substantially high logic level signal. The counter is configured to count oscillations of the oscillating signal. | 2020-10-08 |
20200321954 | TRANSISTOR CONTROL CIRCUIT - A transistor control circuit is disclosed. In an embodiment a method includes simultaneously controlling several transistors by a first signal and separately controlling the transistors by distinct second pulsed signals. | 2020-10-08 |
20200321955 | AC Coupling Modules for Bias Ladders - A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGs is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGs type, or a mix of positive-logic and zero VGs type FETs with end-cap FETs of the zero VGs type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules. | 2020-10-08 |
20200321956 | TECHNIQUES FOR MULTIPLE SIGNAL FAN-OUT - Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state. | 2020-10-08 |
20200321957 | RF Switch with Compensation - A radio frequency switch includes a first transistor and a second transistor coupled together to establish a switchable RF path, and a first compensation network coupled between the body terminal of the first transistor and the drain terminal of the second transistor, wherein the first compensation network establishes a path for current flowing between the body terminal of the first transistor and the drain terminal of the second transistor in a first direction and blocks current flowing in a second direction opposite to the first direction. | 2020-10-08 |
20200321958 | WAVEFORM CONVERSION CIRCUIT FOR GATE DRIVER - A waveform conversion circuit for converting a control signal of a control node ranging from a high voltage level to a low voltage level of a reference node into a driving signal of a first node is provided. The waveform conversion circuit includes a first resistor, a unidirectional conducting device, and a voltage clamp unit. The first resistor is coupled between the control node and the first node. The unidirectional conducting device unidirectionally discharges the first node to the control node. The voltage clamp unit is coupled between the first node and the reference node and is configured to clamp a driving signal. | 2020-10-08 |
20200321959 | MINIMIZING RINGING IN WIDE BAND GAP SEMICONDUCTOR DEVICES - Embodiments include a power conversion circuit comprising first and second semiconductor switches, and a drive circuit configured to create a period of operational overlap for the first and second switches by setting a gate voltage of the first switch to an intermediate value above a threshold voltage of the first switch, during turn-on and turn-off operations of the second switch. Embodiments also include a method of operating first and second semiconductor devices, comprising: reducing a gate voltage of the first device to an intermediate value above a threshold voltage while the second device is off; turning off the first device after the second device is on; increasing the gate voltage of the first device to the intermediate value while the second device is on; and fully turning on the first device after the second device is off. | 2020-10-08 |
20200321960 | CONVERSION CIRCUIT - A conversion circuit includes a main device and a voltage control switching circuit. The voltage control switching circuit includes a first terminal configured to receive an original signal, a second terminal coupled to the control terminal of the main device and configured to transmit a driving signal to drive the main device, and a reference terminal coupled to the second terminal of the main device. A voltage level of the driving signal is generated by the voltage control switching circuit. The voltage control switching circuit further includes a first voltage-control switch. The first drain terminal of the voltage-control switch is coupled to the first terminal. The first source terminal of the voltage-control switch is coupled to the second terminal. The first gate terminal of the voltage-control switch is coupled to the reference terminal. | 2020-10-08 |
20200321961 | MATERIAL-DISCERNMENT PROXIMITY SENSOR - A material-discerning sensing device includes an antenna, a capacitive proximity sensor, and a control circuit. The antenna includes multiple conductive loops and is configured to radiate a wireless signal. The antenna defines an interior region devoid of the conductive loops and an exterior region outside the conductive loops. The capacitive proximity sensor includes a conductive pattern provided within the interior region or within a projection of the interior region, as well as a conductive bar. The control circuit is configured to detect a change in a characteristic of an electrical signal from the capacitive sensor. The conductive pattern includes a longitudinal portion, a first plurality of parallel conductors extending away from the longitudinal portion in a first direction and orthogonal to the longitudinal portion, and a second plurality of parallel conductors extending away from the longitudinal portion in a second direction opposite the first direction. | 2020-10-08 |
20200321962 | CAPACITIVE TOUCH PANEL UNIT WITH AN INTERNAL CARRIER SHEET - A capacitive touch panel unit ( | 2020-10-08 |
20200321963 | PROGRAMMABLE INPUT/OUTPUT CIRCUIT - A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time. | 2020-10-08 |
20200321964 | HIGH-SPEED CORE INTERCONNECT FOR MULTI-DIE PROGRAMMABLE LOGIC DEVICES - Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies. | 2020-10-08 |
20200321965 | METHOD FOR PROGRAMMING A FIELD PROGRAMMABLE GATE ARRAY AND NETWORK CONFIGURATION - A method for programming a Field Programmable Gate Array (FPGA) via a network, the network being operated according to a predetermined communications protocol, can include: establishing a communication connection between the FPGA and an external master, setting the FPGA into a programming mode, the master providing an FPGA programming image to the FPGA in a sequence of frames so that the frames can be parsed and enabling the FPGA to write only during receiving the payload section of the frames. The FPGA programming image and parsing the sequence of frames can be performed by a permanently programmed or hardwired logic component. A network, FPGA, and a communication system can be configured to utilize embodiments of the method. | 2020-10-08 |
20200321966 | DETECTION DEVICE AND DETECTION METHOD - The present technology relates to a detection device and a detection method that are designed to be capable of detecting a locked state with a higher degree of accuracy. | 2020-10-08 |
20200321967 | MULTI-MODAL DATA-DRIVEN CLOCK RECOVERY CIRCUIT - Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode. | 2020-10-08 |
20200321968 | DIGITAL-TO-TIME CONVERTER (DTC) ASSISTED ALL DIGITAL PHASE LOCKED LOOP (ADPLL) CIRCUIT - A digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit is disclosed, which comprises: a DTC error compensator arranged to receive a phase offset signal being a processed output from a time-to-digital converter (TDC) circuit, the phase offset signal includes a DTC error corresponding to a phase difference between a reference clock signal processed by a DTC circuit and a feedback clock signal derived from an output signal of the ADPLL circuit. The compensator is arranged to process the phase offset signal for generating a digital signal representative of the DTC error, which is provided as an output signal. Also, the output signal is arranged to be subtracted from the phase offset signal to obtain a phase rectified signal of the phase offset signal. | 2020-10-08 |
20200321969 | PHASE CANCELLATION IN A PHASE-LOCKED LOOP - A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit. | 2020-10-08 |
20200321970 | REDUCED NOISE DYNAMIC COMPARATOR FOR A SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER - A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level. | 2020-10-08 |
20200321971 | METHODS AND APPARATUS FOR A SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER - Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output. | 2020-10-08 |
20200321972 | DYNAMIC INTEGRATION TIME ADJUSTMENT OF A CLOCKED DATA SAMPLER USING A STATIC ANALOG CALIBRATION CIRCUIT - Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler. | 2020-10-08 |
20200321973 | ANALOG TO DIGITAL CONVERTER, ANALOG TO DIGITAL CONVERSION METHOD, AND DISPLACEMENT DETECTION APPARATUS - Errors in a cyclic analog to digital converter are reduced. An analog to digital converter is a cyclic analog to digital converter for converting an analog input signal into a digital output signal by performing a plurality of times of cycle processing on the analog input signal. A cycle processing unit performs the cycle processing and outputs a digital signal indicating a value of each bit of the digital output signal. An output circuit receives the digital signal output from the cycle processing unit and outputs, as an output signal, a signal obtained by inverting the digital signal every other cycle. A signal input to the cycle processing unit in second and subsequent cycles is generated in the cycle processing in a previous cycle. In the cycle processing, processing for inverting the signal input to the cycle processing is performed. | 2020-10-08 |
20200321974 | RECEIVER FOR A TELECOMMUNICATION SYSTEM - A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal. | 2020-10-08 |
20200321975 | IMPROVED CONVOLUTIONS OF DIGITAL SIGNALS USING A BIT REQUIREMENT OPTIMIZATION OF A TARGET DIGITAL SIGNAL - The invention relates to improved convolutions of digital signals. When a first digital signal is convoluted with a second digital signal to obtain an output digital signal, to be converted afterwards using a limited number of bits. In order to prevent a loss of information, and therefore a degradation of the output digital signal upon the future conversion, at least one of the first and the second digital signal is formed of suitable values that store the information from the first digital signal within the most significant bits of the output digital signal. | 2020-10-08 |
20200321976 | AUTOMATIC HASH FUNCTION SELECTION - Compressing data includes hashing a first token length of an incoming data steam into a hash table, where the first token length includes a plurality of bytes. A second token length of the incoming data stream may be hashed into the hash table. The second token may be larger than the first token length and includes the plurality of bytes. The method may further include automatically comparing which token length enabled more efficient data compression, and automatically adjusting at least one of the first and second token lengths based on the comparison. | 2020-10-08 |
20200321977 | DATA SERIALIZATION CIRCUIT - A data serialization circuit includes a clock data operation circuit configured to generate a plurality of delay clock signals and a plurality of synchronous data signals in response to a plurality of parallel data signals and a plurality of multi-phase clock signals and a multiplexer configured to output a serial data signal in response to the plurality of delay clock signals and the plurality of synchronous data signals. A first one of the plurality of delay clock signals substantially aligns with a first one of the plurality of synchronous data signals. | 2020-10-08 |
20200321978 | Techniques For Link Partner Error Reporting - Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed. | 2020-10-08 |
20200321979 | ECC MEMORY CHIP ENCODER AND DECODER - An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit. | 2020-10-08 |
20200321980 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code. | 2020-10-08 |
20200321981 | TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF - A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. | 2020-10-08 |
20200321982 | ERROR-CORRECTION ENCODING METHOD AND DEVICE, AND DECODING METHOD AND DEVICE USING CHANNEL POLARIZATION - [Problem] Encoding and decoding techniques capable of speeding up an error-correction decoding process utilizing channel polarization are provided. | 2020-10-08 |
20200321983 | ENCODING AND DECODING OF HAMMING DISTANCE-BASED BINARY REPRESENTATIONS OF NUMBERS - Systems and methods for dynamically encoding and decoding binary numbers using linear-time algorithms that encode and decode Hamming Distance-Based representations for the binary numbers are described. The binary numbers may correspond with integer values, such as 64-bit, 128-bit, or 256-bit integer values. In some cases, in response to detecting that a binary number is to be stored using a particular type of memory (e.g., a phase change memory), the binary number may first be encoded using a Hamming Distance-Based representation and then the encoded data may be written to the particular type of memory. The binary number may be encoded by generating a binary string or a binary array representing the binary number such that if one bit flips within the binary string or the binary array, the maximum distortion in the number is less than a threshold amount (e.g., less than 256). | 2020-10-08 |
20200321984 | POLAR ENCODING AND DECODING METHOD, SENDING DEVICE, AND RECEIVING DEVICE - This application provides a polar encoding and decoding method, a sending device, and a receiving device, to help overcome disadvantages in transmission of medium and small packets, a code rate, reliability, and complexity in the prior art. The method includes: pre-storing, by a computing device, at least one mother code sequence, wherein each mother code sequence comprises at least one subsequence and at least one subset, the at least one subsequence and the at least one subset each comprises one or more sequence numbers corresponding to one or more polarized channels, and wherein the one or more sequence numbers in each subsequence are arranged in an ascending order according to reliability of the corresponding one or more polarized channels; determining, by the computing device, a set of information bit sequence numbers from the at least one mother code sequence based on a code length of a target polar code; and performing, by the computing device, polar encoding on information bits based on the set of information bit sequence numbers. | 2020-10-08 |
20200321985 | NON-CONCATENATED FEC CODES FOR ULTRA-HIGH SPEED OPTICAL TRANSPORT NETWORKS - A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture. | 2020-10-08 |
20200321986 | Methods and Devices for Puncturing a Polar Code - Methods and devices for puncturing of a polar code in a wireless network, wherein nested puncturing sets are determined based on a puncturing order which is determined based on a reliability order of information bit channels, so that only one index sequence needs to be stored for both the determination of the information set and the determination of the punctured set and so that puncturing does not require to adjust the information set at error prone indexes corresponding to puncturing indexes. The puncturing order might start with indexes corresponding to high reliability bit channels or to low reliability bit channels. | 2020-10-08 |
20200321987 | MULTI-CHANNEL, MULTI-BAND LINEARIZED DIGITAL TRANSCEIVERS - A multi-channel, multi-band system for wireless communication includes a radio frequency (RF) front end, a mixed-signal front end for converting an incoming analog RF signal into an incoming digital RF signal and converting a composite outgoing digital RF signal into an outgoing analog RF signal, a summation circuit for combining multiple outgoing digital RF signals to the composite outgoing digital RF signal, and multi-band transceivers. Each of the multi-band transceivers may process the incoming digital RF signal to provide an incoming baseband signal and process an outgoing baseband signal to provide an outgoing digital RF signal. The mixed-signal front end may apply a loading control to each transceiver for adjusting an amount of loading on the transmit path from the transceiver to the mixed-signal front-end. The transceivers may individually conduct a feedback calibration on the receive path to optimize the incoming baseband signal for each band. | 2020-10-08 |
20200321988 | ELECTRONIC DEVICE COMPRISING ANTENNA AND METHOD FOR TRANSMITTING OR RECEIVING SIGNAL - Disclosed is an electronic device which includes a housing that includes a first plate, a second plate facing away from the first plate, and a side member surrounding a space between the first plate and the second plate, wherein the side member includes a first conductive portion including a first end and being elongated, a second conductive portion including a second end and a third end and being elongated, the second end being adjacent to the first end, a third conductive portion including a fourth end adjacent to the third end and being elongated, a first insulating portion disposed between the first end and the second end to contact the first end and the second end, and a second insulating portion disposed between the third end and the fourth end to contact the third end and the fourth end, a display that is exposed through the first plate, at least one wireless communication circuit that is electrically connected with a first point placed at the first conductive portion and adjacent to the first end, a first switching element electrically connected with a second point, which is placed at the second conductive portion and is adjacent to the third end, through a capacitive element and electrically connected with a third point placed at the second conductive portion and adjacent to the third end, and a fourth point placed at the third conductive portion and adjacent to the fourth end, at least one ground member that is electrically connected with a fifth point placed at the first conductive portion and more distant from the first end than the first point, a second switching element electrically connected with a sixth point placed at the second conductive portion and adjacent to the second end, a seventh point placed at the second conductive portion and adjacent to the third point, and an eighth point placed at the third conductive portion and more distant from the fourth end than the fourth point, and a control circuit that is configured to control the first switching element and the second switching element. Moreover, various embodiment found through the present disclosure are possible. | 2020-10-08 |
20200321989 | DEVICES AND METHODS FOR RADIO FREQUENCY FRONT END SYSTEMS - A wireless device comprising a first antenna and second antenna, a transceiver and a radio frequency front end system electrically coupled between the transceiver and the antennas. The RF front end system includes a first module operable to provide a high band transmit signal to the first antenna, receive a first high band receive signal and a first mid band receive signal from the first antenna. The first high band receive signal has a frequency range greater than that of the first mid band receive signal. The RF front end system further includes a second module operable to provide a mid band transmit signal to the second antenna, receive a second mid band receive signal and a second high band receive signal from the second antenna. The second high band receive signal has a frequency range greater than that of the second mid band receive signal. | 2020-10-08 |
20200321990 | Antenna Switching Circuit, Antenna Switching Method and Electronic Device - An antenna switching circuit comprises a detection device, a controller, a first antenna, a second antenna, a first switch and a radio frequency transceiver. The detection device is used to detect a change in an input impedance of the first antenna and a change in an input impedance of the second antenna; the controller is used to compare the change in the input impedance of the first antenna with the change in the input impedance of the second antenna; the first switch is used to turn on a first radio frequency circuit and turn off a second radio frequency circuit when the change in the input impedance of the first antenna is less than the change in the input impedance of the second antenna. | 2020-10-08 |
20200321991 | ITEM STATUS TRACKING SYSTEM AND METHOD - A tracking device includes an antenna, a printed energy storage device, a transmitter powered by the printed energy storage device, and control circuitry configured to control the transmitter to transmit, using the antenna, information indicating a status detected by a sensor. | 2020-10-08 |
20200321992 | SYSTEM AND METHOD FOR NONLINEARITY ESTIMATION WITH REFERENCE SIGNALS - A transmitter may be configured to generate a reference signal having a non-constant envelope for nonlinearity estimation by a receiver. The transmitter may transmit the reference signal. A receiver may be configured to receive, from the transmitter, the reference signal having the non-constant envelope. The receiver may estimate at least one nonlinearity characteristic based on the reference signal having the non-constant envelope. The receiver may transmit feedback based on the at least one nonlinearity characteristic and/or perform at least one digital post distortion (DPoD) operation based on the at least one nonlinearity characteristic. | 2020-10-08 |
20200321993 | RECEPTION CIRCUIT, SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE RECEPTION CIRCUIT - A reception circuit includes a receiver, a noise boosting circuit and a buffer. The receiver generates a positive amplification signal and a negative amplification signal by amplifying a first input signal and a second input signal. The noise boosting circuit adjusts voltage levels of the positive amplification signal and the negative amplification signal based on the first input signal and the second input signal. The buffer generates an output signal by amplifying the positive amplification signal and the negative amplification signal. | 2020-10-08 |
20200321994 | HIGH-PERFORMANCE RECEIVER ARCHITECTURE - A wireless communication device can include an antenna array configured to receive a plurality of radio frequency (RF) signals, RF circuitry, and digital baseband receive circuitry. The RF circuitry is configured to process the plurality of RF signals received via the antenna array to generate a single RF signal. The digital baseband receive circuitry is coupled to the RF circuitry and is configured to generate a downconverted signal based on the single RF signal, amplify the downconverted signal to generate an amplified downconverted signal, and convert the amplified downconverted signal to generate a digital output signal for processing by a wireless modem. The digital baseband receive circuitry further includes at least a first filtering system configured to filter the downconverted signal prior to amplification. | 2020-10-08 |
20200321995 | FINGERPRINT SENSOR COMPATIBLE SCREEN PROTECTOR - Systems, devices, and methods that ensures that an ultrasonic fingerprint detection process is not interfered with by using a screen protector. An example screen protector for a mobile device is disclosed that is capable of an in-screen fingerprint detection. The screen protector includes a first layer made of a clear rigid material and configured to be touched by a user. The screen protector also includes a second layer beneath the first layer and made of a film. Additionally, the screen protector includes a third layer beneath the second layer and configured to contact the mobile device. The third layer includes a fingerprint conduit configured to facilitate the in-screen fingerprint detection. | 2020-10-08 |
20200321996 | DEVICES AND METHODS RELATED TO RADIO-FREQUENCY FILTERS ON SILICON-ON-INSULATOR SUBSTRATE - Devices and methods related to radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate. In some embodiments, an RF device can include a silicon die such as an SOI die including a first side and a second side. The silicon die can further include a plurality of vias, with each via configured to provide an electrical connection between the first side and the second side of the silicon die. The RF device can further include at least one RF flip chip mounted on the first side of the silicon die. The silicon die can include, for example, an RF circuit such as a switch circuit, and the RF flip chip can include, for example, a filter such as a surface acoustic wave (SAW) filter. | 2020-10-08 |
20200321997 | HIGH-FREQUENCY SIGNAL TRANSMISSION-RECEPTION CIRCUIT - A high-frequency signal transmission-reception circuit includes a plurality of band pass filter groups each including a plurality of band pass filter pairs; a first switch including a plurality of band pass filter-side terminal groups each including a plurality of band pass filter-side terminals, and an antenna-side terminal group; a plurality of couplers configured to output respective signal strengths of high-frequency signals transmitted on a plurality of transmission paths; and a second switch including an input terminal group electrically connected to the plurality of couplers, and an output terminal configured to output a detection signal output from one of the plurality of couplers. The first switch electrically connects one band pass filter-side terminal in one band pass filter-side terminal group and one antenna-side terminal, and also electrically connects one band pass filter-side terminal in another band pass filter-side terminal group and another antenna-side terminal. | 2020-10-08 |
20200321998 | RADIO FREQUENCY SWITCHES WITH CONTROLLABLE RESONANT FREQUENCY - Radio frequency (RF) switches with controllable resonant frequency are provided herein. In certain embodiments, an RF switch includes a stack of two or more field-effect transistors (FETs) electrically connected between a first terminal and a second terminal. Additionally, the RF switch further includes an inductor connected between the first terminal and the second terminal and in parallel with the stack of FETs. A first portion of the FETs are controlled to turn on or off the RF switch. Additionally, a second portion of the FETs are controlled to provide tuning to a resonant frequency of the RF switch when the RF switch is turned off. | 2020-10-08 |
20200321999 | Non-Orthogonal Multiple Access Wireless Communications Methods And Apparatus Thereof - Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance. | 2020-10-08 |
20200322000 | ADVANCED BACKHAUL SERVICES - “Tiered” groups of devices (tiered service radios) and/or licenses associated with the devices or users so as to provide a hieratical set of interference protection mechanisms for members of each tier of service are disclosed. Point-to-point and point-to-multipoint data links for any communication application, including wireless backhaul applications, are also disclosed. Exemplary systems, devices, and methods disclosed herein allow for the efficient operation of such a tiered service. Interference protection among tiered service devices belonging to one or more tiers of the service, from other devices within the same tier of service, or devices of other tiers of service, is disclosed. Identification of other devices of the same or differing tiers of service, and interference mitigation between other tiered service devices based upon intercommunication between the devices, and/or via a central registry database, are also disclosed. | 2020-10-08 |
20200322001 | Pseudo Channel Hopping using Scan Dwell Times in Mesh Networks without Time Synchronization - A method for pseudo channel hopping in a node of a wireless mesh network is provided that includes scanning each channel of a plurality of channels used for packet transmission by the node, wherein each channel is scanned for a scan dwell time associated with the channel, updating statistics for each channel based on packets received by the node during the scanning of the channel, and changing scan dwell times of the plurality of channels periodically based on the statistics. | 2020-10-08 |
20200322002 | COEXISTENCE PRIMITIVES IN POWER LINE COMMUNICATION NETWORKS - Systems and methods for setting a carrier-sensing mechanism in a PLC node are disclosed. In a PLC standard, coexistence is achieved by having the nodes detect a common preamble and backing off by a Coexistence InterFrame Space (cEIFS) time period to help the node to avoid interfering with the other technologies. In one embodiment, a PHY primitive is sent from the PHY to the MAC know that there has been a preamble detection. A two-level indication may be used—one indication after receiving the preamble and other indication after decoding the entire frame. The MAC sets the carrier-sensing mechanism based on the preamble detection. | 2020-10-08 |