41st week of 2009 patent applcation highlights part 13 |
Patent application number | Title | Published |
20090250728 | SOLID STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME - A solid state imaging device has a plurality of photodetector parts | 2009-10-08 |
20090250729 | CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCER AND MANUFACTURING METHOD - The integrated circuit/transducer device of the preferred embodiment includes a substrate, a complementary-metal-oxide-semiconductor (CMOS) circuit that is fabricated on the substrate, and a capacitive micromachined ultrasonic transducer (cMUT) element that is also fabricated on the substrate. The CMOS circuit and cMUT element are fabricated during the same foundry process and are connected. The cMUT includes a lower electrode, an upper electrode, a membrane structure that support the upper electrode, and a cavity between the upper electrode and lower electrode. | 2009-10-08 |
20090250730 | MICROWAVE SEMICONDUCTOR DEVICE USING COMPOUND SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME - An undoped AlGaN layer | 2009-10-08 |
20090250731 | Field-effect transistor structure and fabrication method thereof - A field-effect transistor (FET) structure is provided. The FET structure includes a gate substrate, a dielectric layer, conductive electrodes, and a carbon nanotube (CNT). The gate substrate is made of a conductive material. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer, and contain nickel and chromium. The CNT is disposed on the dielectric layer and electrically connects two conductive electrodes | 2009-10-08 |
20090250732 | Semiconductor device and method of fabricating the same - In a method of fabricating a semiconductor device on a substrate having thereon a conductive layer, the conductive layer is patterned to form a plurality of opened regions. A gate insulation layer is formed on a sidewall of each of the opened regions. A pillar pattern is formed in each opened region. On each pillar pattern, a gate electrode, which encloses the pillar pattern, is formed by removing the conductive layer between the pillar patterns. | 2009-10-08 |
20090250733 | PIXEL SENSOR WITH REDUCED IMAGE LAG - A tensile-stress-generating structure is formed above a gate electrode in a CMOS image sensor to apply a normal tensile stress between a charge collection well of a photodiode, which is also a source region of a transfer transistor, and a floating drain in the direction connecting the source region and the floating drain. The tensile stress lowers the potential barrier between the source region and the body of the transfer transistor to effect a faster and more through transfer of the electrical charges in the source region to the floating drain. Image lag is thus reduced in the CMOS image sensor. Further, charge capacity of the source region is also enhanced due to the normal tensile stress applied to the source region. | 2009-10-08 |
20090250734 | PIXEL WITH ASYMMETRIC TRANSFER GATE CHANNEL DOPING - A pixel including a substrate of a first conductivity type and having a surface, a photodetector of a second conductivity type that is opposite the first conductivity type, a floating diffusion region of the second conductivity type, a transfer region between the photodetector and the floating diffusion, a gate positioned above the transfer region and partially overlapping the photodetector, and a pinning layer of the first conductivity type extending at least across the photodetector from the gate. A channel implant of the first conductivity type extending from between a midpoint of the transfer gate and the floating diffusion to at least across the photodiode and having a dopant concentration such that a dopant concentration of the transfer region is greater proximate to the photodetector than the floating diffusion, and wherein a peak dopant concentration of the channel implant is at a level and at a depth below the surface such that a partially-buried channel is formed in the transfer region between the photodiode and floating diffusion when the transfer gate is energized. | 2009-10-08 |
20090250735 | SEMICONDUCTOR MEMORY - A semiconductor memory according to an embodiment of the present invention including first and second adjacent bit lines extending in a first direction and provided in the same interconnect layer, an active provided in a memory cell array, a first and second adjacent word lines extending in a second direction intersecting the first direction, a cell group having two transistor provided in the active region and two resistive storage element, wherein the active region has a striped structure, and extends from one end of the memory cell array to the other. | 2009-10-08 |
20090250736 | Semiconductor device - In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern. | 2009-10-08 |
20090250737 | SECURE MEMORY DEVICE OF THE ONE-TIME PROGRAMMABLE TYPE - The integrated circuit includes a memory device of the irreversibly electrically programmable type. This device includes several memory cells, each memory cell having a dielectric zone positioned between a first electrode and a second electrode. Each memory cell is further associated with an access transistor. At least one first electrically conductive link electrically couples to the first electrodes of at least two memory cells, these first two electrodes being coupled to one and the same bias voltage. The first electrically conductive link is positioned in substantially a same plane as the first electrodes of the two memory cells. | 2009-10-08 |
20090250738 | SIMULTANEOUS BURIED STRAP AND BURIED CONTACT VIA FORMATION FOR SOI DEEP TRENCH CAPACITOR - A node dielectric, an inner electrode, and a buried strap cavity are formed in the deep trench in an SOI substrate. A buried layer contact cavity is formed by lithographic methods. The buried strap cavity and the buried layer contact cavity are filled simultaneously by deposition of a conductive material, which is subsequently planarized to form a buried strap in the deep trench and a buried contact via outside the deep trench. The simultaneous formation of the buried strap and the buried contact via enables formation of a deep trench capacitor in the SOI substrate in an economic and efficient manner. | 2009-10-08 |
20090250739 | Device Structures with a Hyper-Abrupt P-N Junction, Methods of Forming a Hyper-Abrupt P-N Junction, and Design Structures for an Integrated Circuit - Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction. | 2009-10-08 |
20090250740 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a semiconductor substrate in which a plurality of device regions and a plurality of device isolation regions are alternately formed to extend in a first direction; and a plurality of contact plugs formed on the semiconductor substrate, connected to the device regions and arranged on the semiconductor substrate in a zigzag pattern in a second direction perpendicular to the first direction, wherein the contact plugs have a rectangular cross section. | 2009-10-08 |
20090250741 | Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same - A semiconductor device and/or gate structure having a composite dielectric layer and methods of manufacturing the same is provided. In the semiconductor device, gate structure, and methods provided, a first conductive layer may be formed on a substrate. A native oxide layer formed on the first conductive layer may be removed. A surface of the first conductive layer may be nitrided so that the surface may be altered into a nitride layer. A composite dielectric layer including the first and/or second dielectric layers may be formed on the nitride layer. A second conductive layer may be formed on the composite dielectric layer. The first dielectric layer may include a material having a higher dielectric constant. The second dielectric layer may be capable of suppressing crystallization of the first dielectric layer. | 2009-10-08 |
20090250742 | NEURON DEVICE - A neuron device includes: a semiconductor layer; source and drain regions formed in the semiconductor layer at a distance from each other; a protection film formed on an upper face of the semiconductor layer; a channel region formed in the semiconductor layer between the source region and the drain region; a pair of gate insulating films formed on two side faces of the channel region; a floating gate electrode including: a first portion covered on the gate insulating films and the protection film; a second portion connected to the first portion; and a third portion provided on the substrate so as to connect to the end portion of the second portion on the opposite side from the first portion; an interelectrode insulating film provided on the first to third portions; and a plurality of control gate electrodes provided on the third portion. | 2009-10-08 |
20090250743 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device has side surfaces of neighboring bit lines that do not face each other to reduce a capacitance of a parasitic capacitor formed between adjacent bit lines. The semiconductor memory device includes contact plugs formed on a semiconductor substrate. Each contact plug is disposed between gate patterns. First and second conductive pads extend in different directions and are connected to the contact plugs. First and second pad contact plugs are formed on extended peripheries of the first and second conductive pads, respectively. Each of the first pad contact plugs has a height which differs from a height of each of the second pad contact plugs. First bit lines are connected to the first pad contact plugs, and second bit lines are connected to the second pad contact plugs. | 2009-10-08 |
20090250744 | Semiconductor memory device and manufacturing method therefor - A semiconductor memory device has a cover film ( | 2009-10-08 |
20090250745 | Memory devices and methods of forming and operating the same - A memory device, including a first ground selection transistor, a first string selection transistor, and first memory cell transistors disposed in series between the first ground selection transistor and the first string selection transistor, wherein the first ground selection transistor and the first memory cell transistors have a same structure. A method of programming the memory device may include programming the ground selection transistor before programming the memory cell. | 2009-10-08 |
20090250746 | NOR-Type Flash Memory Cell Array and Method for Manufacturing the Same - Disclosed is a non-volatile (e.g., NOR type flash) memory cell array and a method for manufacturing the same. The memory cell array includes a plurality of isolation layers on a semiconductor substrate, parallel to a bit line and defining an active device area, a plurality of common source areas in the semiconductor substrate, separated from each other by the isolation layers such that the common source areas connect memory cells adjacent to each other in a bit line direction, a common source line on the semiconductor substrate, connected to each source area and extending in a word-line direction, an insulating spacer along a first sidewall of the common source line, a gate at a second sidewall of the insulating spacer including a tunnel oxide layer, a first electrode, an inter-electrode dielectric layer, and a second electrode, and a drain area in the semiconductor substrate on an opposite side of the gate from the common source area. | 2009-10-08 |
20090250747 | NON-VOLATILE MEMORY DEVICES HAVING A MULTI-LAYERED CHARGE STORAGE LAYER - A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material. | 2009-10-08 |
20090250748 | Semiconductor device and method of fabricating the same - A semiconductor device and method of fabricating the same includes preparing a substrate, forming a plurality of conductive layer patterns on the substrate, forming a gate insulation layer on sidewalls of the conductive layer patterns, forming a pillar neck pattern between the conductive layer patterns, forming a pillar head over the pillar neck pattern and the conductive layer patterns, and forming a gate electrode surrounding the pillar neck pattern and forming a pillar head pattern by selectively etching the conductive layer patterns and the pillar head formed over the pillar neck pattern. | 2009-10-08 |
20090250749 | Methods of Forming Asymmetric Recesses and Gate Structures that Fill such Recesses and Related Methods of Forming Semiconductor Devices that Include such Recesses and Gate Structures - In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufacturing the semiconductor device, a semiconductor substrate is etched to form a first sub-recess having a first central axis. A second sub-recess is formed under the first sub-recess. The second sub-recess is in communication with the first sub-recess. The second sub-recess has a second central axis substantially parallel with the first central axis. The second central axis is spaced apart from the first central axis. | 2009-10-08 |
20090250750 | TRENCH GATE POWER MOSFET - A trench gate power MOSFET ( | 2009-10-08 |
20090250751 | MOS DEVICE WITH LOW ON-RESISTANCE - Some of the embodiments of the present disclosure provide a metal oxide semiconductor (MOS) device comprising a drain region, a gate region surrounding the drain region and formed in a loop around the drain region, a plurality of source regions arranged around the gate region, wherein each source region is situated across from a corresponding side of the drain region, and a plurality of bulk regions arranged around the gate region, wherein one or more of the plurality of source regions separate one or more of the plurality of bulk regions from the gate region. Other embodiments are also described and claimed. | 2009-10-08 |
20090250752 | Methods of fabricating semiconductor device having a metal gate pattern - A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H | 2009-10-08 |
20090250753 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode. | 2009-10-08 |
20090250754 | PARTIALLY DEPLETED SILICON-ON-INSULATOR METAL OXIDE SEMICONDUCTOR DEVICE - A partially depleted silicon-on-insulator metal oxide semiconductor (PD-SOI MOS) device is provided. The PD-SOI MOS device includes a gate structure on a silicon-on-insulator substrate, source and drain regions in the silicon-on-insulator substrate beside the gate structure and a silicon dislocation leakage path in an interface of the source region and the silicon-on-insulator substrate. | 2009-10-08 |
20090250755 | Semiconductor Device - A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer. | 2009-10-08 |
20090250756 | N-TYPE SCHOTTKY BARRIER TUNNEL TRANSISTOR AND MANUFACTURING METHOD THEREOF - An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer. | 2009-10-08 |
20090250757 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There is provided a semiconductor device having excellent device characteristics and reliability in which V | 2009-10-08 |
20090250758 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, EVALUATION METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A semiconductor element formed over the same substrate as a TFT, includes a semiconductor film having an impurity region; an insulating film formed over the semiconductor film; an electrode divided into a plurality of parts over the insulating film by spacing a distance a in a first direction (channel width direction); an insulator with a width b formed to be in contact with a side wall of the electrodes and an insulator formed in a region between the electrodes divided into a plurality of parts; a silicide layer formed over part of the surface of the impurity region; and characteristics of the TFT are evaluated by measuring resistance of the semiconductor film of the semiconductor element. | 2009-10-08 |
20090250759 | SEMICONDUCTOR DEVICE - A breakdown voltage of a clamp diode can be reduced while a leakage current is suppressed. A P | 2009-10-08 |
20090250760 | METHODS OF FORMING HIGH-K/METAL GATES FOR NFETS AND PFETS - Methods of forming high-k/metal gates for an NFET and PFET and a related structure are disclosed. One method includes recessing a PFET region; forming a first high-k dielectric layer and a first metal layer over the substrate; removing the first high-k dielectric layer and the first metal over the NFET region using a mask; forming a forming a second high-k dielectric layer and a second metal layer over the substrate, the first high-k dielectric layer being different then the second high-k dielectric layer and the first metal being different than the second metal; removing the second high-k dielectric layer and the second metal over the PFET region using a mask; depositing a polysilicon over the substrate; and forming a gate over the NFET region and the PFET region by simultaneously etching the polysilicon, the first high-k dielectric layer, the first metal, the second high-k dielectric layer and the second metal. | 2009-10-08 |
20090250761 | Semiconductor device with transistors and its manufacturing method - A semiconductor device includes a semiconductor substrate, a first transistor including a first gate electrode, a first diffusion region, and a second diffusion region respectively formed above the semiconductor substrate, second transistor including a second gate electrode, the first diffusion region, and a third diffusion region respectively formed above the semiconductor substrate, and a node electrode formed above the first diffusion layer, and coupled thereto. The first gate electrode and the second gate electrode are formed separately at respective side walls of the node electrode. | 2009-10-08 |
20090250762 | INTEGRATED CIRCUIT SYSTEM EMPLOYING SACRIFICIAL SPACERS - An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof. | 2009-10-08 |
20090250763 | INTEGRATED CIRCUIT INCLUDING A FIRST CHANNEL AND A SECOND CHANNEL - An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a second channel that has a second width. The first channel and the second channel provide a combined current that is greater than a single current provided via a single channel having a single width that is substantially equal to the sum of the first width and the second width. | 2009-10-08 |
20090250764 | STRESSED DIELECTRIC LAYER WITH STABLE STRESS - An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O | 2009-10-08 |
20090250765 | LOW ON RESISTANCE CMOS "WAVE" TRANSISTOR FOR INTEGRATED CIRCUIT APPLICATIONS - In one embodiment of the present invention an array of power transistors on a semiconductor chip has repeating patterns of two “wave” gates which have alternating longer and shorter horizontal sections which are offset mirror images of each other together with a third straight horizontal section. Alternating source and drain regions lie between adjacent gates. Contacts are located adjacent each side of sections of the “wave” gates which connect the ends of the horizontal sections of the “wave” gates. | 2009-10-08 |
20090250766 | Work Function Based Voltage Reference - A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference. | 2009-10-08 |
20090250767 | ED INVERTER CIRCUIT AND INTEGRATE CIRCUIT ELEMENT INCLUDING THE SAME - A second semiconductor layer of a second nitride-based compound semiconductor with a wider bandgap formed on a first semiconductor layer of a first nitride-based compound semiconductor with a smaller bandgap includes an opening, on which a gate insulating layer is formed at a portion exposed through the opening. A first source electrode and a first drain electrode formed across a first gate electrode make an ohmic contact to the second semiconductor layer. A second source electrode and a second drain electrode formed across a second gate electrode that makes a Schottky contact to the second semiconductor layer make an ohmic contact to the second semiconductor layer. | 2009-10-08 |
20090250768 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate | 2009-10-08 |
20090250769 | Semiconductor Device Having Multiple Fin Heights - A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal. | 2009-10-08 |
20090250770 | INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET - A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices. | 2009-10-08 |
20090250771 | Mosfet and production method of semiconductor device - To provide a MOSFET which is increased in substrate bias effect γ without increasing parasitic capacitance and junction leak current, the MOSFET includes: a gate electrode ( | 2009-10-08 |
20090250772 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE - A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device. | 2009-10-08 |
20090250773 | Semiconductor device - A semiconductor device includes a first metal region, a plurality of vias, a plurality of second metal regions, a plurality of openings and a third metal region. The first metal region conducts source/drain current. The second metal regions are electrically connected to the first metal region through the vias for conducting the source/drain current, in which each of the second metal regions is disposed in a distance from the adjacent second metal regions. The third metal region is electrically connected to the second metal regions through the openings, in which the resistance of the third metal region is smaller than the resistances of the first metal region and the second metal regions. | 2009-10-08 |
20090250774 | Gate Structure - A gate structure includes a gate insulation layer pattern, a gate electrode, a first spacer and a protecting layer pattern. The gate insulation layer pattern is on a substrate. The gate electrode is on the gate insulation layer pattern, the gate electrode including a lower portion having a first width, a central portion having a second width smaller than the first width and an upper portion having a third width. The first spacer is on a lower sidewall of the gate electrode. The protecting layer pattern is on a central sidewall of the gate electrode. | 2009-10-08 |
20090250775 | MAGNETIC DEVICE WITH INTEGRATED MAGNETO-RESISTIVE STACK - This magnetic device integrates a magneto-resistive stack, the stack comprising at least two layers made out of a ferromagnetic material, separated from each other by a layer of non-magnetic material; and means for causing an electron current to flow perpendicular to the plane of the layers, with at least one integrated nano-contact intended to inject the current into the magneto-resistive stack. The nano-contact is made in a bilayer composed of a solid electrolyte on which has been deposited a soluble electrode composed of a metal, and at least partially dissolved in the electrolyte. | 2009-10-08 |
20090250776 | MAGNETIC MEMORY DEVICE - There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length smaller than the half of the maximum length in the direction perpendicular to the easy-axis, and on the one side and on the other side of the primary straight line respectively, the planar shape has a first part situated over a length in the direction perpendicular to the easy-axis, and a second part situated over a length smaller than the length in the direction perpendicular to the easy-axis. The outer edge of the first part includes only a smooth curve convex outwardly of the outer edge. | 2009-10-08 |
20090250777 | IMAGE SENSOR AND IMAGE SENSOR MANUFACTURING METHOD - In an upper waveguide structure ( | 2009-10-08 |
20090250778 | PHOTOELECTRIC CONVERSION DEVICE, IMAGING SYSTEM, PHOTOELECTRIC CONVERSION DEVICE DESIGNING METHOD, AND PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING METHOD - A photoelectric conversion device comprises a plurality of photoelectric conversion units, a first antireflection portion including a first insulation film which has a first refractive index and a second insulation film which has a second refractive index, and a second antireflection portion including an element isolation portion which includes an insulator having a third refractive index and a third insulation film which has the second refractive index, wherein the first antireflection portion reduces reflection of light entering the photoelectric conversion unit in the photoelectric conversion unit, and the second antireflection portion reduces reflection of light entering the element isolation portion in the element isolation portion. | 2009-10-08 |
20090250779 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF - A solid-state imaging device in the present invention includes plural photoelectric conversion elements, plural wiring layers, and plural optical waveguide regions each corresponding to and arranged over one of the plural photoelectric conversion elements. A top end of each of the plural optical waveguide regions is higher than a top end of at least one of the plural wiring layers. A bottom end of each of the plural optical waveguide regions is lower than a bottom end of at least one of the plural wiring layers. The plural optical waveguide regions include plural types of optical waveguide regions each having different light absorbing characteristics. | 2009-10-08 |
20090250780 | HIGH FILL-FACTOR LASER-TREATED SEMICONDUCTOR DEVICE ON BULK MATERIAL WITH SINGLE SIDE CONTACT SCHEME - The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side and an architecture that enables the laser step to be the final step or a late step in the fabrication process. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor. | 2009-10-08 |
20090250781 | POWER SEMICONDUCTOR DEVICE - The present invention relates to a power semiconductor device comprising a switching power semiconductor element, and a free wheeling diode in anti-parallel connection to the switching power semiconductor element. The power semiconductor is characterized in that a reverse electrode of the switching power semiconductor element and a reverse electrode of the free wheeling diode are bonded and mounted on a circuit pattern formed on the main surface of the first substrate, and that a circuit pattern, which is so formed on the main surface of the second substrate as to oppose a surface electrode of the switching power semiconductor element and a surface electrode of the free wheeling diode, is connected to the surface electrodes of the switching power semiconductor element and the free wheeling diode through connective conductors to be soldered, respectively. | 2009-10-08 |
20090250782 | SUBGROUNDRULE SPACE FOR IMPROVED METAL HIGH-K DEVICE - The present invention provides a semiconducting device including a substrate including at least one semiconducting region and isolation regions; a gate structure atop the substrate having a gate dielectric layer positioned on the semiconducting region and a metal layer atop the gate dielectric layer, the gate structure having a width equal to or greater than the width of the at least one semiconducting region; and a contact structure including a base having a first width equal to the width of the gate structure and an upper surface having a second width, wherein the first width is greater than the second width. In one embodiment, the contact structure includes a polysilicon conductor and dielectric spacers, wherein each spacer of the dielectric spacer abuts a sidewall of the polysilicon conductor. In another embodiment, the contact structure includes a polysilicon conductor having a tapered sidewall. | 2009-10-08 |
20090250783 | SEMICONDUCTOR DEVICE HAVING AN ANNULAR GUARD RING - A semiconductor chip | 2009-10-08 |
20090250784 | Structure and method for elimination of process-related defects in poly/metal plate capacitors - An integrated circuit includes silicon layer ( | 2009-10-08 |
20090250785 | METHODS OF FORMING A SHALLOW BASE REGION OF A BIPOLAR TRANSISTOR - The disclosed subject matter provides a method of forming a bipolar transistor. The method includes depositing a first insulating layer over a first layer of material that is doped with a dopant of a first type. The first layer is formed over a substrate. The method also includes modifying a thickness of the first oxide layer based on a target dopant profile and implanting a dopant of the first type in the first layer. The dopant is implanted at an energy selected based on the modified thickness of the first insulating layer and the target dopant profile. | 2009-10-08 |
20090250786 | FUSE PART OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A fuse part of a semiconductor device includes an insulation layer over a substrate, and a fuse over the insulation layer, wherein the fuse includes a plurality of blowing pads for irradiating a laser beam and the plurality of blowing pads have laser coordinates different from one another. | 2009-10-08 |
20090250787 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor storage device includes: a first conductive adhesive layer selectively formed over a semiconductor substrate; an insulating film formed on the semiconductor substrate to cover the first conductive adhesive layer and having an opening exposing a central part of the first conductive adhesive layer; and a capacitive element including a bottom electrode formed along a bottom surface and a wall surface of the opening, a capacitive insulating film formed on the bottom electrode, and a top electrode formed on the capacitive insulating film. The first conductive adhesive layer is in contact with the bottom electrode only at a bottom surface part of the opening which includes a corner where the bottom surface of the opening meets the wall surface thereof. | 2009-10-08 |
20090250788 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction, a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction. | 2009-10-08 |
20090250789 | METHODS OF COUNTER-DOPING COLLECTOR REGIONS IN BIPOLAR TRANSISTORS - The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. The implanted dopant has a first dopant profile in the silicon layer. The method also includes performing a second implant process to implant additional dopant of the second type in the silicon layer. The additional implanted dopant has a second dopant profile in the silicon layer different than the first dopant profile. The method further includes growing an insulating layer formed over the silicon layer by consuming a portion of the silicon layer and the first type of dopant. | 2009-10-08 |
20090250790 | NITRIDE SEMICONDUCTOR WAFER AND METHOD OF PROCESSING NITRIDE SEMICONDUCTOR WAFER - Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs. Ordinary one-surface polishing having the steps of gluing a wafer with a surface on a flat disc, bringing another surface in contact with a lower turntable, pressing the disc, rotating the disc, revolving the turntable and whetting the lower surface, cannot remedy the inherent distortion. The Distortion worsens morphology of epitaxial wafers, lowers yield of via-mask exposure and invites cracks on surfaces. Nitride crystals are rigid but fragile. Chemical/mechanical polishing has been requested in vain. Current GaN wafers have roughened bottom surfaces, which induce contamination of particles and fluctuation of thickness. | 2009-10-08 |
20090250791 | Crystalline Semiconductor Stripes - Crystalline semiconductor stripes and an associated fabrication process are provided. The method provides an insulator substrate, and deposits a semiconductor layer overlying the insulator substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor material, oriented crystalline semiconductor stripes are formed on the insulator substrate. The crystalline semiconductor stripes are aligned approximately with a straight line stripe axis overlying a top surface of the insulating substrate. Each crystalline semiconductor stripe includes a plurality of consecutive ring segments aligned with the stripe axis. The rings segments have a width about equal to the laser annealing process step distance. The crystalline semiconductor stripes typically have a top surface shape of a truncated cylinder or a parabolic cross section. | 2009-10-08 |
20090250792 | Curing Low-k Dielectrics for Improving Mechanical Strength - An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer. | 2009-10-08 |
20090250793 | BPSG FILM DEPOSITION WITH UNDOPED CAPPING - Semiconductor devices containing a CVD BPSG layer and an undoped CVD oxide cap layer are described. The cap layer can be any silicon oxide material with a thickness between about 50 Å and about 350 Å. The cap layer may be formed using a low temperature CVD process that is controlled for density by adjusting the amount of silicon precursor in the gas-phase. In some embodiments, the cap layer is deposited on the BPSG layer followed immediately by the BPSG film deposition prior to any annealing of the BPSG layer. The cap layer may prevent dopant out-diffusion and/or out-gassing during storage and high-temperature annealing, and moisture penetration into the BPSG layer, as well as suppress defect nucleation on the as-deposited BPSG surface and defect formation during high temperature annealing, while still allowing flow ability of the BPSG layer. Other embodiments are also described. | 2009-10-08 |
20090250794 | METHOD OF FORMING A SEMICONDUCTOR PACKAGE AND STRUCTURE THEREFOR - In one embodiment, a semiconductor package is formed to include a leadframe that includes a plurality of die attach areas for attaching a semiconductor die to the leadframe. The leadframe is positioned to overlie another leadframe that forms some of the external terminals or leads of the package. | 2009-10-08 |
20090250795 | LEADFRAME FOR PACKAGED ELECTRONIC DEVICE WITH ENHANCED MOLD LOCKING CAPABILITY - A packaged electronic device ( | 2009-10-08 |
20090250796 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 2009-10-08 |
20090250797 | Multi-Chip Package - A lead frame assembly includes at least one die paddle. The die paddle includes a first landing area for receiving a first semiconductor chip and a second landing area for receiving a second semiconductor chip. One or more steps are provided between the first landing area and the second landing area. | 2009-10-08 |
20090250798 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECT SUPPORT - An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the chip support. | 2009-10-08 |
20090250799 | Power Semiconductor Module Comprising an Explosion Protection System - A power semiconductor module for energy distribution, includes at least one power semiconductor, connection terminals for connecting the power semiconductor module, and a housing, in which protection from explosion is ensured in the module even in the event of electric arcs. Therefore, each power semiconductor and each connection terminal is disposed in the housing, and the housing includes an exhaust gas channel for the controlled withdrawal of hot gases and/or plasma in the event of an explosion. | 2009-10-08 |
20090250800 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device is provided that includes a semiconductor chip and a resin section that molds the semiconductor chip and has a first through-hole. A through electrode that is electrically coupled to the semiconductor chip, extends through the resin section, and extends between a top edge and a bottom edge of an inner surface of the first through-hole. A cavity which extends between planes corresponding to an upper surface and a lower surface of the resin section is formed inside the first through-hole. | 2009-10-08 |
20090250801 | Semiconductor device - A semiconductor device in which a plurality of semiconductor elements are stacked, yet realizing high speed operation of the semiconductor elements. The semiconductor device is provided with semiconductor packages, and a spacer. The semiconductor packages are stacked, with the spacer interposed therebetween. The semiconductor packages have, respectively, package boards, and semiconductor elements mounted on the package boards. The spacer has a plurality of conductive vias and a capacitor element. The semiconductor packages are electrically connected through the conductive vias. The capacitor element is electrically connected, among the conductive vias, to a conductive via that electrically connects the semiconductor element and power supply, and a conductive via that electrically connects the semiconductor element and ground. | 2009-10-08 |
20090250802 | Multilayer wiring substrate, semiconductor package, and methods of manufacturing semiconductor package - A multilayer wiring substrate included in the semiconductor package includes: a first insulating layer and a second insulating layer, in which wiring layers are respectively provided on the upper and the lower surfaces; and; a core layer provided between the first insulating layer and the second insulating layer. The first insulating layer and the second insulating layer are constituted by different materials from each other. | 2009-10-08 |
20090250803 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a chip, a laminated wiring structure formed integrally with the chip, a frame disposed to surround the chip and made of a material having stiffness, and a sealing resin formed to bury therein the frame and at least the periphery of the side surface of the chip. The laminated wiring structure includes a required number of wiring layers, which are formed by patterning in such a manner that a wiring pattern directly routed from an electrode terminal of the chip is electrically connected to pad portions for bonding external connection terminals, the pad portions being provided, at a position directly below a mounting area of the chip and at a position directly below an area outside the mounting area, on a surface to which the external connection terminals are bonded. | 2009-10-08 |
20090250804 | LEADFRAME-BASED IC-PACKAGE WITH SUPPLY-REFERENCE COMB - An IC package includes a leadframe-diepad ( | 2009-10-08 |
20090250805 | Heat Dissipation For Integrated Circuit - A packaged integrated circuit having a thermal pathway to exhaust heat from the integrated circuit. The integrated circuit is disposed on a package substrate, with an encapsulant disposed around the integrated circuit. A heat sink is disposed at least partially within the encapsulant, with at least a portion of one surface of the heat sink exposed outside of the encapsulant. The integrated circuit has an uppermost passivation layer, where the passivation layer is not electrically conductive, with a port disposed in the passivation layer. The port extends completely through the passivation layer to expose an underlying layer. A thermal pathway is disposed at least partially within the port, and makes thermal contact to both the underlying layer and the heat sink. The thermal transfer rate of the thermal pathway is greater than the thermal transfer rate either the passivation layer or the encapsulant. | 2009-10-08 |
20090250806 | SEMICONDUCTOR PACKAGE USING AN ACTIVE TYPE HEAT-SPREADING ELEMENT - A semiconductor package includes a carrier, a chip, a stiffener, a heat spreader and an active type heat-spreading element. The chip and the stiffener are disposed on the carrier. The heat spreader is disposed on the stiffener and includes a through opening. The active type heat-spreading element is disposed on the chip and located in the through opening. | 2009-10-08 |
20090250807 | Electronic Component and Method for its Production - An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s). | 2009-10-08 |
20090250808 | RELIABILITY IMPROVEMENT IN A COMPOUND SEMICONDUCTOR MMIC - A semiconductor package (M) includes a semiconductor substrate layer ( | 2009-10-08 |
20090250809 | Semiconductor package having thermal stress canceller member - A semiconductor package includes a package-substrate, a first cavity formed on a first main surface of the package substrate, a first semiconductor chip mounted on the bottom surface of the first cavity, a first resin layer filled into the first cavity, and a thermal stress canceller member mounted on the package substrate for cancelling the thermal stress caused by the difference in the thermal expansion rates between the package substrate and mounting section including a first semiconductor chip and a first resin layer. The thermal stress canceller member may include a second cavity, a second resin layer filled into the second cavity, and a semiconductor chip. | 2009-10-08 |
20090250810 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system is provided including: providing a substrate; and placing a patterned layer over the substrate for substantially removing crying warpage from the substrate. | 2009-10-08 |
20090250811 | Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask - A semiconductor device has a semiconductor die with an die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow. | 2009-10-08 |
20090250812 | FLIP-CHIP MOUNTING SUBSTRATE AND FLIP-CHIP MOUNTING METHOD - A solder resist and a central pad to which a central Au bump provided on a semiconductor chip is flip-chip bonded are formed on a substrate main body. In a flip-chip mounting substrate where an underfill resin is provided after the semiconductor chip is mounted, a central opening portion for exposing the central pad is formed in the solder resist, and also, an edge portion forming the central opening portion of the solder resist is partially overlapped with the outer peripheral portion of the central pad. | 2009-10-08 |
20090250813 | INTEGRATED CIRCUIT SOLDER BUMPING SYSTEM - An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the openings therethrough. A second UBM layer of chromium/copper alloy is deposited on the first UBM layer. A third UBM layer of copper is deposited on the second UBM layer. UBM pads of at least two different sizes are formed from the UBM layers. Solder paste is printed over at least some of the UBM pads. The solder paste is reflowed to form at least smaller solder bumps on at least some of the UBM pads. Bigger solder bumps are formed on at least some of the UBM pads. | 2009-10-08 |
20090250814 | Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof - A semiconductor device is made by providing a semiconductor die having a contact pad, forming a circular solder bump on the contact pad, providing a substrate having a trace line, disposing a non-circular solder resist opening over the trace line, placing the solder bump in proximity to the trace line, and reflowing the circular solder bump to metallurgically connect the circular solder bump to the trace line. The circular solder bump contacts less than an entire perimeter of the non-circular solder resist opening which creates one or more vents in areas where the circular solder bump is discontinuous with the non-circular solder resist opening. The non-circular solder resist opening can be a rectangle, triangle, ellipse, oval, star, and tear-drop. An underfill material is deposited under the first substrate. The underfill material penetrates through the vents to fill an area under the solder bump. | 2009-10-08 |
20090250815 | SURFACE TREATMENT FOR SELECTIVE METAL CAP APPLICATIONS - Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal cap formation provides a means for controlling the selective formation of the metal cap directly on the non-recessed surface of a conductive material. That is, the selective formation of the metal cap directly on the non-recessed surface of a conductive material is enhanced since the formation rate of the metal cap on the non-recessed surface of a conductive material is greater than on the hydrophobic surface of the low k dielectric material. It is observed that the hydrophobic surface may be a result of treating a damaged surface of the dielectric material with a silylating agent prior to the selective formation of the noble metal cap or, as a result of forming a hydrophobic polymeric layer on the surface of the dielectric material prior to the selective deposition of the noble metal cap. The hydrophobic polymeric layer typically includes atoms of Si, C and O. | 2009-10-08 |
20090250816 | ULTRA-THIN DIFFUSION-BARRIER LAYER FOR CU METALLIZATION - Diffusion barrier layer is required during copper metallization in IC processing to prevent Cu from diffusion into the contacting silicon material and reacting to form copper silicide, which consumes Cu and deteriorates electrical conduction. With decreasing feature sizes of IC devices, such as those smaller than 90 nano-meter (nm), the thickness of diffusion barrier layer must be thinner than 10 nm. For example, a thickness of 2 nm will be called for at the feature size 27 nm. Disclosed in the present invention is ultra-thin barrier materials and structures based on tantalum silicon carbide, and its composite with another metallic layer Ru film. The retarding temperature, by which no evidence of copper diffusion can be identified, is 600˜850° C. depending on thickness, composition and film structure, at a thickness 1.6˜5 nm. | 2009-10-08 |
20090250817 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to embodiments includes forming a resist film above an object to be etched, the resist film having a pattern with notches provided in the vicinity of corners having an angle of less than 180 degrees on an opening side, and dry etching the object to be etched using the resist film as a mask, thereby transferring the pattern of the resist film. | 2009-10-08 |
20090250818 | VIA ELECTROMIGRATION IMPROVEMENT BY CHANGING THE VIA BOTTOM GEOMETRIC PROFILE - An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer. | 2009-10-08 |
20090250819 | METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - The invention relates to a metal line of a semiconductor device and a method of forming the same. According to a method of forming a metal line of a semiconductor device in accordance with an aspect of the invention, a semiconductor substrate in which contact plugs are formed within contact holes of a first dielectric layer is first provided. An etch-stop layer and a hard mask pattern are formed over the first dielectric layer and the contact plugs. The etch-stop layer is patterned along the hard mask pattern. The exposed first dielectric layer and the contact plugs are etched to thereby form trenches in the first dielectric layer over the contact plugs. A metal layer is formed to gap-fill the trenches. A polishing process is performed to expose the etch-stop layer. | 2009-10-08 |
20090250820 | CONFIGURABLE NON-VOLATILE LOGIC STRUCTURE FOR CHARACTERIZING AN INTEGRATED CIRCUIT DEVICE - An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure. | 2009-10-08 |
20090250821 | CORROSION RESISTANT VIA CONNECTIONS IN SEMICONDUCTOR SUBSTRATES AND METHODS OF MAKING SAME - Devices and methods for protecting the metal within a via in a semiconductor substrate from corrosion are provided. Specifically, embodiments of the present invention relate to disposing a corrosion resistant metal layer within a recess formed in a semiconductor substrate such that the metal subsequently deposited within the via will adhere to the corrosion resistant metal layer, then backgrinding the bottom surface of the semiconductor substrate to expose the corrosion resistant metal. For example, the metal deposited within the recess may be copper, while the corrosion resistant metal may be a noble metal such as palladium. | 2009-10-08 |
20090250822 | MULTI-CHIP STACK PACKAGE - A multi-chip stack package comprising a first wiring substrate, a first chip, a second wiring substrate, and a second chip is provided. The first wiring substrate is with a front side and a rear side. The first chip is disposed on the front side of the first wiring substrate and electrically connected to the first wiring substrate and the first chip has a first active surface. The second wiring substrate is disposed on the first active surface of the first chip and electrically connected to the first wiring substrate. The second chip is disposed on the second wiring substrate and electrically connected to the second wiring layer. The second active surface of the second chip faces the first active surface of the first chip. | 2009-10-08 |
20090250823 | Electronic Modules and Methods for Forming the Same - Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate. | 2009-10-08 |
20090250824 | METHOD AND APPARATUS TO REDUCE PIN VOIDS - A semiconductor package comprises a substrate that utilizes one or more pins to form external interconnects. The pins are bonded to bonding pads on the substrate by solder. The pins may each has a pin head that may have a bonding surface, wherein the bonding surface may comprises a center portion and a side portion that is tapered away relative to the center portion. In some embodiments, the bonding surface may comprise a round shape. In some embodiments, a gas escape path may be provided by the shape of the bonding surface to increase pin pull strength and/or solder strength. The package may further comprise a surface finish that may comprise a palladium layer with a reduced thickness to reduce the amount of palladium based IMC precipitation into the solder. | 2009-10-08 |
20090250825 | PROCESS FOR PRODUCING ACID ANHYDRIDE-BASED EPOXY RESIN CURING AGENT, ACID ANHYDRIDE-BASED EPOXY RESIN COMPOSITION, AND CURED PRODUCT AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAME - The present invention relates to a process for producing an acid anhydride-based epoxy resin curing agent, an acid anhydride-based epoxy resin curing agent, an epoxy resin composition, and a cured product and optical semiconductor device using the same. The process for producing an acid anhydride-based epoxy resin curing agent according to the present invention comprises heating a mixture containing a polyvalent carboxylic acid anhydride and a polyester resin in the presence of hydrogen gas and a hydrogenation catalyst. | 2009-10-08 |
20090250826 | Process for manufacturing semiconductor device and semiconductor device manufactured by such process - A process for manufacturing a semiconductor device that inhibits deterioration in the quality of the semiconductor device and a semiconductor device manufactured on such manufacturing process are presented. An operation of determining time-variation of water content in the resin substrate | 2009-10-08 |
20090250827 | SYSTEM FOR MANUFACTURING MICRO-RETARDER AND METHOD FOR MANUFACTURING THE SAME - A system for manufacturing a micro-retarder and a method for manufacturing the same are provided. The system for manufacturing a micro-retarder includes a carrying device, a heating device and a movement control device. The carrying device is used for carrying a polymolecule film. The polymolecule film is selected from a polymolecule film having an arrangement direction. The heating device is used for providing a heating source. The energy formed in the central area of the heating source is smaller than that in the peripheral area of the heating source. The movement control device is used for controlling the heating source and the polymolecule film to relatively move along a first direction, so that the adjusted heating source heats at least one partial area of the polymolecule film along the first direction and resumes the partial area of the polymolecule film to be non-directional. | 2009-10-08 |