40th week of 2016 patent applcation highlights part 68 |
Patent application number | Title | Published |
20160293427 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, a first insulation film, a conductive film, a silicon-containing second insulation film, and a third film formed of silicon are sequentially formed at the surface of a control gate electrode. Then, the third film is etched back to leave the third film at the side surface of the control gate electrode via the first insulation film, the conductive film, and the second insulation film, thereby to form a spacer. Then, the conductive film is etched back to form a memory gate electrode formed of the conductive film between the spacer and the control gate electrode, and between the spacer and the semiconductor substrate. | 2016-10-06 |
20160293428 | FINFET DEVICE WITH VERTICAL SILICIDE ON RECESSED SOURCE/DRAIN EPITAXY REGIONS - A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed. | 2016-10-06 |
20160293429 | Free-Edge Semiconductor Chip Bending - Techniques for fabricating a semiconductor chip having a curved surface may include placing a substantially flat semiconductor chip in a recess surface of a concave mold such that corners or edges of the semiconductor chip are unconstrained or are the only portions of the semiconductor chip in physical contact with the concave mold; and bending the substantially flat semiconductor chip to form a concave shaped semiconductor chip by applying a force on the semiconductor chip toward the bottom of the recessed surface. The corners or edges of the semiconductor chip move or slide relative to the recess surface during the bending. | 2016-10-06 |
20160293430 | SULFUR AND FLUORINE CONTAINING ETCH CHEMISTRY FOR IMPROVEMENT OF DISTORTION AND BOW CONTROL FOR HAR ETCH - In accordance with this disclosure, there is provided several inventions, including a method for etching a plurality of features in a stack comprising alternating layers above a substrate, comprising: providing a steady state flow of an etching gas, wherein the etching gas comprises: a molecule A comprising sulfur and fluorine; a molecule B comprising carbon, fluorine, and hydrogen; and a molecule C comprising carbon and fluorine and not hydrogen; forming the etching gas into a plasma; and etching the features into the stack through the plurality of alternating layers. | 2016-10-06 |
20160293431 | GAS REACTION TRAJECTORY CONTROL THROUGH TUNABLE PLASMA DISSOCIATION FOR WAFER BY-PRODUCT DISTRIBUTION AND ETCH FEATURE PROFILE UNIFORMITY - Methods, systems, and computer programs are presented for controlling gas flow in a semiconductor manufacturing chamber. The method includes flowing a reactant gas thorough an inner feed and a tuning gas through an outer feed surrounding the inner feed, such that the gases do not mix until both are introduced in the chamber. Further, the flow of the reactant gas is convective, and the flow of the tuning gas is directed at an angle from the direction of the reactant gas, providing a delivery of the tuning gas in closer proximity to the RF power before further mixing with the reactant gas. Radio frequency power is provided to the electrode to ignite a plasma using the reactant and tuning gases. | 2016-10-06 |
20160293432 | METHOD FOR ATOMIC LAYER ETCHING - A method of etching a layer on a substrate includes disposing a substrate in a plasma processing system configured to facilitate an etching process, performing an atomic layer etching process cycle to etch a monolayer of an exposed surface of the substrate, and repeating the atomic layer etching process cycle until a target depth is reached. Each process cycle etches the monolayer from the exposed surface. The atomic layer etching process cycle sequentially includes forming an adsorption monolayer comprising an etchant on an exposed surface of the substrate by introducing the etchant while concurrently coupling electromagnetic power to the plasma processing system at a power level targeted to achieve an etchant radical flux at the substrate greater than a total ion flux at the substrate, which power level is less than or equal to 50 W, purging the plasma processing system to remove any excess etchant, desorbing the adsorption monolayer by exposing the adsorption monolayer to gas ions to activate a reaction of the etchant, and purging the plasma processing system again. | 2016-10-06 |
20160293433 | Methods of Fabricating Features Associated With Semiconductor Substrates - Some embodiments include a method of fabricating features associated with a semiconductor substrate. A first region of the semiconductor substrate is altered relative to a second region. The altered first region has different physisorption characteristics for polynucleotide relative to the second region. The altered first region and the second region are exposed to polynucleotide. The polynucleotide selectively adheres to either the altered first region or the second region to form a polynucleotide mask. The polynucleotide mask is used during fabrication of features associated with the semiconductor substrate. | 2016-10-06 |
20160293434 | Polishing of Small Composite Semiconductor Materials - A device includes a crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by using a planarization process configured with a selectivity of the crystalline material to the insulator greater than one. In a preferred embodiment, the planarization process uses a composition including abrasive spherical silica, H | 2016-10-06 |
20160293435 | PARTIAL ETCH MEMORIZATION VIA FLASH ADDITION - Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives. | 2016-10-06 |
20160293436 | POLISHING COMPOSITION - Provided is a polishing composition which exhibits favorable storage stability and polishes a polishing object poor in chemical reactivity at a high speed. | 2016-10-06 |
20160293437 | CYCLIC SPACER ETCHING PROCESS WITH IMPROVED PROFILE CONTROL - Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile. | 2016-10-06 |
20160293438 | CYCLIC SPACER ETCHING PROCESS WITH IMPROVED PROFILE CONTROL - Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile. | 2016-10-06 |
20160293439 | ETCHING METHOD - A method of concurrently etching a first region in which silicon oxide films and silicon nitride films are alternately stacked and a second region including the silicon oxide film having a thickness larger than a thickness of the silicon oxide film of the first region is provided. The method includes generating plasma of a first processing gas containing a fluorocarbon gas and a hydrofluorocarbon gas within a processing vessel of a plasma processing apparatus into which a processing target object is carried; and generating plasma of a second processing gas containing a hydrogen gas, a hydrofluorocarbon gas and a nitrogen gas within the processing vessel of the plasma processing apparatus. Further, the generating of the plasma of the first processing gas and the generating of the plasma of the second processing gas are repeated alternately. | 2016-10-06 |
20160293440 | ETCHING METHOD - Provided is an etching method for simultaneously etching first and second regions of a workpiece. The first region has a multilayered film configured by alternately laminating a silicon oxide film and a silicon nitride film and a second region has a silicon oxide film having a film thickness that is larger than that of the silicon oxide film in the first region. A mask is provided on the workpiece to at least partially expose each of the first and second regions. In the etching method, plasma of a first processing gas containing fluorocarbon gas, hydrofluorocarbon gas, and oxygen gas is generated within a processing container of a plasma processing apparatus. Subsequently, plasma of a second processing gas containing fluorocarbon gas, hydrofluorocarbon gas, oxygen gas, and a halogen-containing gas is generated within the processing container. Subsequently, plasma of a third processing gas containing oxygen gas is generated within the processing container. | 2016-10-06 |
20160293441 | MASK ETCH FOR PATTERNING - A hard mask layer is deposited on a feature layer over a substrate. The hard mask layer comprises an organic mask layer. An opening in the organic mask layer is formed using a first gas comprising a halogen element at a first temperature greater than a room temperature to expose a portion of the feature layer. In one embodiment, a gas comprising a halogen element is supplied to a chamber. An organic mask layer on an insulating layer over a substrate is etched using the halogen element at a first temperature to form an opening to expose a portion of the insulating layer. | 2016-10-06 |
20160293442 | METHODS OF FORMING PATTERNS - A method of forming patterns includes forming an array of pillars on an underlying layer stacked on an etch target layer, forming a separation wall layer on the pillars to provide separation walls covering sidewalls of the pillars, forming a block copolymer layer on the separation wall layer, annealing the block copolymer layer to form first domains located between the pillars, and a second domain surrounding and isolating the first domains, selectively removing the first domains to form second openings, selectively removing the pillars to form fourth openings, forming fifth openings that extend from the second and fourth openings to penetrate the underlying layer, forming a sealing pattern that covers and seals dummy openings among the fifth openings, and forming seventh openings that extend from the fifth openings exposed by the sealing pattern to penetrate the etch target layer. | 2016-10-06 |
20160293443 | METHODS OF FORMING DIFFERENT SIZED PATTERNS - A method includes forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including first separation wall portions surrounding sidewalls of the pillars, and forming second separation wall portions covering sidewalls of the first opening trench portion; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, and forming second domains surrounding and separating the first domains by annealing the block copolymer layer; forming second openings by selectively removing the first domains; forming third openings between the second openings, and forming a fourth opening adjacent to the first isolated pattern by selectively removing the pillars and the template portion; and forming fifth openings, which extend from the second and third openings and penetrate the underlying layer, and forming a sixth opening, which extends from the fourth opening and penetrates the underlying layer. | 2016-10-06 |
20160293444 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, the method including forming an insulating layer on a substrate; forming a metallic hardmask pattern on the insulating layer; forming a recess by partially etching the insulating layer; forming a metallic protection layer on an inner side wall of the recess; etching the insulating layer to form a hole that penetrates the insulating layer by using the metallic hardmask pattern and the metallic protection layer as etching masks; and removing the metallic hardmask pattern and the metallic protection layer. | 2016-10-06 |
20160293445 | METHOD OF FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is disclosed. The method may include forming an target layer on a substrate, forming a mask pattern on a target layer, performing a first process to etch the target layer and form a first sub-trench, and performing a second process to further etch the target layer and form a second sub-trench. First and second sidewall patterns may be formed on a sidewall of the mask pattern to be used as an etch mask in the first and second processes, respectively. Outer sidewalls of the first and second sidewall patterns may be formed to have different angles with respect to a top surface of the substrate. | 2016-10-06 |
20160293446 | METHOD FOR MANUFACTURING A SILICON WAFER - Provided is a method for manufacturing a silicon wafer including a first step of heat-treating a raw silicon wafer sliced from a silicon single crystal ingot grown by the Czochralski method in an oxidizing gas atmosphere at a maximum target temperature of 1300 to 1380° C., a second step of removing an oxide film on a surface of the heated-treated silicon wafer obtained in the first step, and a third step of heat-treating the stripped silicon wafer obtained in the second step in a non-oxidizing gas atmosphere at a maximum target temperature of 1200 to 1380° C. and at a heating rate of 1° C./sec to 150° C./sec in order that the silicon wafer may have a maximum oxygen concentration of 1.3×10 | 2016-10-06 |
20160293447 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus ( | 2016-10-06 |
20160293448 | ETCHING PROCESS IN CAPACITOR PROCESS OF DRAM USING A LIQUID ETCHANT COMPOSITION - An etching process in a capacitor process for DRAM is described. A substrate is provided, which has thereon a silicon layer and metal electrodes in the silicon layer. The silicon layer is removed using a liquid etchant composition. The liquid etchant composition contains tetramethylammonium hydroxide (TMAH), an additive including hydroxylamine or a metal corrosion inhibitor, and water as a solvent. | 2016-10-06 |
20160293449 | Methods Of Etching Films Comprising Transition Metals - Provided are methods for etching films comprising transition metals. Certain methods involve activating a substrate surface comprising at least one transition metal, wherein activation of the substrate surface comprises exposing the substrate surface to heat, a plasma, an oxidizing environment, or a halide transfer agent to provide an activated substrate surface; and exposing the activated substrate surface to a reagent comprising a Lewis base or pi acid to provide a vapor phase coordination complex comprising one or more atoms of the transition metal coordinated to one or more ligands from the reagent. Certain other methods provide selective etching from a multi-layer substrate comprising two or more of a layer of Co, a layer of Cu and a layer of Ni. | 2016-10-06 |
20160293450 | SEMICONDUCTOR DEVICE WITH SLOPED SIDEWALL AND RELATED METHODS - A semiconductor device may include a multi-layer interconnect board having in stacked relation a lower conductive layer, a dielectric layer, and an upper conductive layer. The dielectric layer may have a recess formed with a bottom and sloping sidewall extending upwardly from the bottom. The upper conductive layer may include upper conductive traces extending across the sloping sidewall, and the lower conductive layer may include lower conductive traces. The semiconductor device may include vias extending between the lower and upper conductive layers, an IC carried by the multi-layer interconnect board in the recess, bond wires coupling upper conductive traces to the IC, and encapsulation material adjacent the IC and adjacent portions of the multi-layer interconnect board. | 2016-10-06 |
20160293451 | METHOD FOR CREATING THROUGH-CONNECTED VIAS AND CONDUCTORS ON A SUBSTRATE - A method for creating electrically or thermally conductive vias in both vertical and horizontal orientations in a dielectric material has the steps of: (a) depositing a powder comprising metallic particles on a planar surface of a dielectric material having through or blind vias; (b) drying the deposited powder of metallic particles; (c) polishing the powder of metallic powders into the through or blind vias; (d) repeating steps (a)-(c) on a reverse side of the dielectric material; and (e) repeating steps (a)-(d) until no unfilled vias are detected. | 2016-10-06 |
20160293452 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The manufacturing efficiency of a semiconductor device is improved. A method for manufacturing a semiconductor device includes a step of sealing a semiconductor chip using a mold die having a cavity, a gate part communicating with the cavity, and a vent part provided opposite to the gate part via the cavity, and extending in a first direction in a sealing step. Further, a lead frame has a first through hole provided at a position overlapping the cavity in the sealing step, and a second through hole provided outside the first through hole, and provided at a position overlapping the vent part in the sealing step. Whereas, in a second direction crossing with the first direction, the length of the second through hole is larger than the length (groove width) of the vent part. | 2016-10-06 |
20160293453 | INTEGRATED CIRCUIT PACKAGE CONFIGURATIONS TO REDUCE STIFFNESS - Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed. | 2016-10-06 |
20160293454 | SUBSTRATE PROCESSING DEVICE - A substrate processing device capable of quickly increasing oxygen concentration in an area outside a substrate transfer part up to the oxygen concentration in the air while maintaining the interior of the substrate transfer part in nitrogen atmosphere is provided. In the substrate processing device, an interior of a loader module is maintained in a nitrogen atmosphere at a pressure slightly higher than the atmospheric pressure outside the substrate processing device. A blower part is disposed along a side surface of an outer upper portion of the loader module to generate an air flow along the side surface of the loader module, so that the nitrogen gas leaking from the loader module is diffused and circulated due to convection and thus, the oxygen concentration in an area outside the loader module is quickly increased up to the oxygen concentration in the air. | 2016-10-06 |
20160293455 | PLASMA PROCESSING APPARATUS, PLASMA PROCESSING METHOD, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - Linear coils, a first ceramic block, and a second ceramic block are arranged in an inductively-coupled plasma torch. A chamber has an annular shape. Plasma generated inside the chamber is ejected to a substrate through an opening portion in the chamber. The substrate is processed by relatively moving the chamber and the substrate in a direction perpendicular to a longitudinal direction of the opening portion. The coil is arranged inside a rotating cylindrical ceramic pipe. Accordingly, the plasma can be generated with excellent power efficiency, and fast plasma processing can be performed. | 2016-10-06 |
20160293456 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck mechanism including an electrode portion inside the stage; a heater inside the stage; a support portion which supports a conveyance carrier between a stage-mounted position on the stage and a transfer position distant from the stage upward; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage by lowering the support portion, application of voltage to the electrode portion is started in a state that the stage is being heated, and the plasma generation unit generates plasma after at least a part of an outer circumferential portion of a holding sheet holding the conveyance carrier contacts the stage and also after the heating of the stage is stopped. | 2016-10-06 |
20160293457 | HEAT TREATMENT APPARATUS, HEAT TREATMENT METHOD, AND PROGRAM - Disclosed is a heat treatment apparatus including: a heating unit that heats an inside of a processing chamber that accommodates a plurality of workpieces; a temperature drop rate model storing unit that stores a temperature drop rate model; and a heat treatment performing unit that sets the temperature drop rate model stored in the temperature drop model storing unit and sets the inside of the processing chamber to the temperature and the time represented in the temperature drop rate model. The temperature drop rate model storing unit stores a plurality of temperature drop rate models, each of which has a different temperature drop rate. The processing chamber is divided into a plurality of zones, and the temperature drop rate mode is set for each of the zones. The heat treatment performing unit sets different temperature drop rate models in a plurality of zones to heat the plurality of workpieces. | 2016-10-06 |
20160293458 | Device And Method For Substrate Heating During Transport - A system for heating substrates while being transported between processing chambers is disclosed. The system comprises an array of light emitting diodes (LEDs) disposed in the transfer chamber. The LEDs may be GaN LEDs, which emit light at a wavelength which is readily absorbed by silicon, thus efficiently and quickly heating the substrate. A controller is in communication with the LEDs. The LEDs may be independently controllable, so that the LEDs that are disposed above the substrate as it is moved from one processing chamber to another are illuminated. In other words, the illumination of the LEDs and the movements of the substrate handling robot may be synchronized by the controller. | 2016-10-06 |
20160293459 | APPARATUS FOR PROCESSING SUSTRATE AND SEMICONDUCTOR FABRICATION LINE INCLUDING THE SAME - In a substrate processing apparatus and a fabrication line including the same, the substrate processing apparatus includes a first unit apparatus performing a first unit process of a substrate, a second unit apparatus facing the first unit apparatus and performing a second unit process, and a load port providing a carrier receiving the substrate to the first unit apparatus and the second unit apparatus. The load port connects between the first unit apparatus and the second unit apparatus. | 2016-10-06 |
20160293460 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING SYSTEM - A substrate processing apparatus includes a reception part configured to receive film thickness distribution data of a substrate on which a channel region, an insulating film on the channel region, and a first silicon-containing layer as a portion of a silicon-containing film on the insulating film are formed; a substrate mounting part configured to mount the substrate; and a gas supply part configured to supply a gas to form a second silicon-containing layer as a portion of the silicon-containing film on the first silicon-containing layer to have a film thickness distribution different from a film thickness distribution of the film thickness distribution data, thereby correcting a film thickness of the silicon-containing film. | 2016-10-06 |
20160293461 | SEMICONDUCTOR DEVICE HANDLER THROUGHPUT OPTIMIZATION - A method and system are provided for optimizing operational throughput for a semiconductor device handler having multiple stages. The method includes receiving semiconductor devices for testing at an input carrier buffer, and operating the handler in the testing of semiconductor devices. The method also includes recording operational throughput characteristics for each operational stage of the handler, and analyzing recorded operational throughput characteristics for each operational stage of the handler. Additionally, the method includes determining which operational stage of the handler has the most limiting constraint causing a lowest operational drumbeat, and adjusting operational parameters of the operational stage of the handler that has the lowest operational drumbeat to increase the operational drumbeat. The method further includes repeating the method until an operational state is achieved such that further adjustments to operational parameters result in a decrease in the operational throughput for the semiconductor device handler. | 2016-10-06 |
20160293462 | ABNORMALITY PORTENT DETECTION SYSTEM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, in an abnormality portent detection system, a collection unit is configured to time-sequentially collect plural kinds of parameters related to a state of an apparatus. A calculation unit is configured, while temporally changing a boundary between a first period and a second period in a time-sequential variation characteristic of each of plural kinds of parameters, to calculate a contribution rate of each of the plural kinds of parameters with respect to a transition from a first state of the apparatus before the boundary to a second state of the apparatus after the boundary. An extraction unit is configured to extract, among the plural kinds of parameters, a parameter showing a change in which the contribution rate has a maximum value at a timing before an abnormality occurrence timing of the apparatus with respect to a time of the boundary, based on a result of the calculation. | 2016-10-06 |
20160293463 | SEMICONDUCTOR MANUFACTURING DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR CHIP - Provided is a semiconductor manufacturing device including an expanding unit that expands a holding member having an adhesive layer on which a substrate in a state of being diced into plural semiconductor chips is held, a detection unit that detects an adhesive state between one of the semiconductor chips and the holding member, in a state in which the holding member is expanded, and a pickup unit that picks up the semiconductor chip by changing an operation relevant to pickup of the semiconductor chip based on the detected adhesive state. | 2016-10-06 |
20160293464 | Linearly Moving and Rotating Device - The linearly moving and rotating device includes a support portion that supports an operated member integrally provided with the article support portion, for rotation about the movable axis and for movement along the first direction, and a linearly movable member which is moved along the first direction by the actuator. The operated member is connected to the linearly movable member in a portion spaced apart from the movable axis as seen along a direction along the movable axis. The linearly moving and rotating device includes an operating state switching portion which can be switched to a linearly moving state for restricting rotation of the operated member about the movable axis and for allowing movement of the operated member along the first direction, and to a rotating state for allowing rotation of the operated member about the movable axis and for restricting movement of the operated member along the first direction. | 2016-10-06 |
20160293465 | SUBSTRATE TRANSPORTING DEVICE, SUBSTRATE TREATING APPARATUS, AND SUBSTRATE TRANSPORTING METHOD - Disclosed is a substrate transporting device including a transport mechanism, a transport chamber, a first exhaust fan, and a controller. The transport mechanism is movable in parallel in a given direction. The transport chamber includes a first wall disposed on a first side of the given direction of the transport mechanism, and a plurality of transportation ports each used for moving the substrate between an exterior and an interior of the transport chamber. The first exhaust fan is disposed closer to the first wall than any of the transportation ports, and exhausts gas in the transport chamber outside the transport chamber. The controller performs control such that, when the transport mechanism moves toward the first wall in a first proximal area whose distance from the first wall is of a given value or less, an exhaust amount of the first exhaust fan is larger than that when the transport mechanism moves toward the first wall out of the first proximal area. | 2016-10-06 |
20160293466 | SUBSTRATE TRANSFERRING APPARATUS - Substrate transferring apparatus includes a first-hand mechanism and second hand mechanism. The first-hand mechanism includes a first lower arm, first upper arm, first-hand having a tip end portion as a first substrate holding portion, and first driven mechanism to rotate the first-hand with rotation of the first upper arm. The first-hand mechanism so the first substrate holding portion movable by rotations of the first lower arm, first upper arm, and first-hand between a contracted and extended positions. The second-hand mechanism includes a second lower arm, second upper arm, second-hand having a tip end portion as a second substrate holding portion, and second driven mechanism to rotate the second-hand with rotation of the second upper arm. The second-hand mechanism so the second substrate holding portion movable by rotations of the second lower arm, second upper arm, and second-hand in sync with the first substrate holding portion between a contracted and extended positions. | 2016-10-06 |
20160293467 | PROCESSING APPARATUS - In accordance with one or more aspects of the disclosed embodiment a semiconductor processing apparatus is provided. The semiconductor processing apparatus includes a frame forming a sealable chamber having a longitudinal axis and lateral sides astride the longitudinal axis, the sealable chamber being configured to hold a sealed environment therein, at least one transport module mounted to the sealable chamber and having a telescoping carriage being configured so that the telescoping carriage is linearly movable relative to another portion of the transport module where the telescoping carriage and the other portion define a telescoping motion along the longitudinal axis, and at least one transfer robot mounted to the carriage, each of the at least one transfer robot having at least one transfer arm configured for holding a substrate thereon. | 2016-10-06 |
20160293468 | Article Transport Facility - When a transport start condition, which includes at least a condition that the controller is receiving a closed state signal, is satisfied, a controller allows a transport operation by an article transport device, and suspends the transport operation by the article transport device when the controller stops continually receiving the closed state signal after the transport operation by the article transport device is started, and further, allows the transport operation by the article transport device to continue while the controller is receiving the closed state signal after the transport operation by the article transport device is started, even if an object to be detected is detected by a monitoring detector. | 2016-10-06 |
20160293469 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck mechanism including an electrode portion disposed inside the stage; a support portion which supports the conveyance carrier; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage, the electrostatic chuck mechanism performs an operation of applying a voltage to the electrode portion after contact of an outer circumferential portion of a holding sheet of the conveyance carrier to the stage, the operation including a voltage varying operation of increasing and decreasing an absolute value of the voltage, and the plasma generation unit generates plasma after completion of the voltage varying operation. | 2016-10-06 |
20160293470 | DEVICE FOR AT LEAST EMPTYING A TRANSPORT CONTAINER - A device for at least emptying a transport container having a stack of plate-shaped items, including semiconductor wafers and/or packaging material, includes at least one measuring device and a holder at least part of which can travel into the transport container, the holder having: a holding surface; a number of holding nozzles for at least holding an item in the stack; and, in the region of the holding surface, at least one recess for the measuring device for acquiring measurement data from the item in the stack. In order to permit the transport container to be emptied in a stable manner, the holder includes at least one separating nozzle arranged outside the holding surface and arranged on the holder such that the nozzle(s) can move between a rest position and a separating position, in such a way that when the separating nozzle is in the separating position, a gas stream directed towards the end face of the stack is formed, in order to release at least one item in the stack that is adhered to the item held by the holder. | 2016-10-06 |
20160293471 | METHOD AND SYSTEM FOR POSITIONING WAFER IN SEMICONDUCTOR MANUFACTURING FABRICATION - A method for positioning a wafer in semiconductor fabrication is provided. The method includes sending a wafer into a processing chamber by a transferring module. The method further includes producing a video image in relation to an edge of the wafer by a monitoring module. The method also includes performing an image analysis on the video image to determine if the edge of the wafer is in a correct position. If the edge of the wafer is not in a correct position a shifting value is calculated and the wafer is moved according to the shifting value. | 2016-10-06 |
20160293472 | ORGANIC LAYER DEPOSITION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY DEVICE BY USING THE SAME - An organic layer deposition apparatus, and a method of manufacturing an organic light-emitting display device using the organic layer deposition apparatus. The organic layer deposition apparatus includes: an electrostatic chuck that fixedly supports a substrate that is a deposition target; a deposition unit including a chamber maintained at a vacuum and an organic layer deposition assembly for depositing an organic layer on the substrate fixedly supported by the electrostatic chuck; and a first conveyor unit for moving the electrostatic chuck fixedly supporting the substrate into the deposition unit, wherein the first conveyor unit passes through inside the chamber, and the first conveyor unit includes a guide unit having a receiving member for supporting the electrostatic chuck to be movable in a direction. | 2016-10-06 |
20160293473 | Method For Manufacturing Semiconductor Device - Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape. | 2016-10-06 |
20160293474 | SEMICONDUCTOR PROCESSING SYSTEM - The semiconductor processing system includes a reactor chamber that has an upper wall and a lower wall. A hold member is disposed in the reactor chamber to hold a semiconductor substrate in such a way that it faces the lower wall of the reactor chamber. | 2016-10-06 |
20160293475 | SYSTEMS AND METHODS TO REDUCE PARASITIC CAPACITANCE - Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps. | 2016-10-06 |
20160293476 | PROCESS FOR FABRICATING A STRUCTURE HAVING A BURIED DIELECTRIC LAYER OF UNIFORM THICKNESS - A process is used for fabricating a final structure comprising in succession a useful semiconductor layer, a dielectric layer and a carrier substrate. The process comprises providing an intermediate structure including an upper layer, the dielectric layer and the carrier substrate, and finishing the intermediate structure to form the final structure by performing a treatment nonuniformly modifying the thickness of the dielectric layer following a predetermined dissolution profile. The dielectric layer of the intermediate structure has a thickness profile complementary to the predetermined dissolution profile. | 2016-10-06 |
20160293477 | SILICON-ON-INSULATOR (SOI) WAFERS EMPLOYING MOLDED SUBSTRATES TO IMPROVE INSULATION AND REDUCE CURRENT LEAKAGE - Silicon-on-insulator (SOI) wafers employing molded substrates to improve insulation and reduce current leakage are provided. In one aspect, a SOI wafer comprises a substrate. An insulating layer (e.g., a buried oxide (BOX) layer) is disposed above the substrate to insulate an active semiconductor layer disposed above the insulating layer, from the substrate. Transistors are formed in the active semiconductor layer. To provide for improved insulation between the active semiconductor layer and the substrate to reduce leakage and improve performance of the active semiconductor layer, the substrate is provided in the form of a molded substrate. A coating layer is also disposed between the molded substrate and the insulating layer of the SOI wafer, in case, for example, the melting temperature of a molding compound used to form the molded substrate is not low enough to prevent contamination of the active semiconductor layer into the insulating layer. | 2016-10-06 |
20160293478 | SELF-ALIGNED DOUBLE PATTERNING PROCESS FOR METAL ROUTING - Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask over a dielectric layer; forming a patterning template including plural parallel linear elements on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces therebetween; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material. | 2016-10-06 |
20160293479 | Selectively Removing Titanium Nitride Hard Mask and Etch Residue Removal - Formulations for stripping titanium nitride hard mask and removing titanium nitride etch residue comprise an amine salt buffer, a non-ambient oxidizer, and the remaining being liquid carrier includes water and non-water liquid carrier selected from the group consisting of dimethyl sulfone, lactic acid, glycol, and a polar aprotic solvent including but not limited to sulfolanes, sulfoxides, nitriles, formamides and pyrrolidones. The formulations have a pH <4, preferably <3, more preferably <2.5. The aqueous formulations having water as liquid carrier and semi-aqueous formulation having water and non-polar aprotic solvent(s) further contain acidic fluoride. The formulations offer high titanium nitride etch rates while provide excellent compatibility towards W, AlN, AlO, and low k dielectric materials. The formulations may comprise weakly coordinating anions, corrosion inhibitors, and surfactants. Systems and processes use the formulations for stripping titanium nitride hard mask and removing titanium nitride etch residue. | 2016-10-06 |
20160293480 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first insulating film as a portion of a laminated insulating film on a substrate in which a plurality of circuit configurations is formed; polishing the first insulating film; measuring a film thickness distribution of the first insulating film; and forming a second insulating film as a portion of the laminated insulating film on the polished first insulating film at a film thickness distribution differing from the film thickness distribution of the first insulating film to correct a film thickness of the laminated insulating film. | 2016-10-06 |
20160293481 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer. | 2016-10-06 |
20160293482 | Semiconductor Constructions and Methods of Forming Intersecting Lines of Material - Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches. | 2016-10-06 |
20160293483 | PROCESS OF FILLING THE HIGH ASPECT RATIO TRENCHES BY CO-FLOWING LIGANDS DURING THERMAL CVD - Implementations of the present disclosure generally relate to methods for forming thin films in high aspect ratio feature definitions. In one implementation, a method of processing a substrate in a process chamber is provided. The method comprises flowing a boron-containing precursor comprising a ligand into an interior processing volume of a process chamber, flowing a nitrogen-containing precursor comprising the ligand into the interior processing volume and thermally decomposing the boron-containing precursor and the nitrogen-containing precursor in the interior processing volume to deposit a boron nitride layer over at least one or more sidewalls and a bottom surface of a high aspect ratio feature definition formed in and below a surface of a dielectric layer on the substrate. | 2016-10-06 |
20160293484 | METHODS OF FORMING WIRING STRUCTURES - In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer. | 2016-10-06 |
20160293485 | SELF-ALIGNED STRUCTURE - A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material. | 2016-10-06 |
20160293486 | METHOD FOR FABRICATING ELECTRONIC DEVICES HAVING SEMICONDUCTOR MEMORY UNIT - Devices and methods based on disclosed technology include, among others, an electronic device including silicide layers capable of effectively reducing contact resistance in the electronic device including buried gates and a method for fabricating the electronic device. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate and silicide layers formed over the substrate between the buried gates and protruding upwardly from the buried gates. | 2016-10-06 |
20160293487 | PROTECTED THROUGH SEMICONDUCTOR VIA (TSV) - Method for forming a through semiconductor via (TSV) in a semiconductor wafer comprising: etching an annular recess into a front side of the semiconductor wafer, the annular recess surrounding a pillar of the semiconductor material; filling the annular recess with an insulative material to form an insulative annulus; etching a recess into the front side in the pillar of the semiconductor material; filling the recess in the portion of the semiconductor material with a metal to form a through semiconductor via (TSV); thinning the semiconductor wafer from a backside of the semiconductor wafer and stopping on the insulative annulus to expose the pillar of the semiconductor material; recessing the pillar of the semiconductor material from the back side to form a recess that exposes an end of the TSV; and filling the recess with a metal to a level at least even with a level of the insulative annulus. | 2016-10-06 |
20160293488 | ELECTRONIC DIE SINGULATION METHOD - In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and applying a pressure substantially uniformly along the second major surface to batch separate the layer of material in the singulation lines. In one embodiment, a fluid filled vessel can be used to apply the pressure. | 2016-10-06 |
20160293489 | Laser liftoff of epitaxial thin film structures - This work provides a new approach for epitaxial liftoff. Instead of using a sacrificial layer that is selectively etched chemically, the sacrificial layer selectively absorbs light that is not absorbed by other parts of the structure. Under sufficiently intense illumination with such light, the sacrificial layer is mechanically weakened, melted and/or destroyed, thereby enabling epitaxial liftoff. The perimeter of the semiconductor region to be released is defined (partially or completely) by lateral patterning, and the part to be released is also adhered to a support member prior to laser irradiation. The end result is a semiconductor region removed from its substrate and adhered to the support member. | 2016-10-06 |
20160293490 | Integrated High-K/Metal Gate in CMOS Process Flow - A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function. | 2016-10-06 |
20160293491 | FIN STRUCTURE AND FIN STRUCTURE CUTTING PROCESS - A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process. | 2016-10-06 |
20160293492 | STABLE MULTIPLE THRESHOLD VOLTAGE DEVICES ON REPLACEMENT METAL GATE CMOS DEVICES - A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure. | 2016-10-06 |
20160293493 | STABLE MULTIPLE THRESHOLD VOLTAGE DEVICES ON REPLACEMENT METAL GATE CMOS DEVICES - A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure. | 2016-10-06 |
20160293494 | METHOD FOR MAKING STRAINED SEMICONDUCTOR DEVICE AND RELATED METHODS - A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states. | 2016-10-06 |
20160293495 | METHOD OF UTILIZING TRENCH SILICIDE IN A GATE CROSS-COUPLE CONSTRUCT - A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures. | 2016-10-06 |
20160293496 | METHOD OF UTILIZING TRENCH SILICIDE IN A GATE CROSS-COUPLE CONSTRUCT - A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures. | 2016-10-06 |
20160293497 | SOLDERING THREE DIMENSIONAL INTEGRATED CIRCUITS - A method for soldering three-dimensional integrated circuits is provided. A three-dimensional integrated circuit is heated to a base temperature, wherein the base temperature is lower than the melting point of a solder, and wherein the three-dimensional integrated circuit includes a plurality of solder bumps. A first on-chip heat source reflows a first portion of the plurality of solder bumps that is within a first local-hot-zone. A second on-chip heat source reflows a second portion of the plurality of solder bumps that is within a second local-hot-zone. | 2016-10-06 |
20160293498 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present disclosure provides a technique capable of suppressing a deviation in a characteristic of a semiconductor device. There is provided a technique includes: (a) receiving data representing a thickness distribution of a polished silicon-containing layer on a substrate comprising a convex structure whereon the polished silicon-containing layer is formed; (b) calculating, based on the data, a process data for reducing a difference between a thickness of a portion of the polished silicon-containing layer formed at a center portion of the substrate and that of the polished silicon-containing layer formed at a peripheral portion of the substrate; (c) loading the substrate into a process chamber; (d) supplying a process gas to the substrate; and (e) compensating for the difference based on the process data by activating the process gas with a magnetic field having a predetermined strength on the substrate. | 2016-10-06 |
20160293499 | SEMICONDUCTOR ASSEMBLY AND METHOD TO FORM THE SAME - A semiconductor device having a composite pad including a primary portion and a subsidiary portion is disclosed. The primary portion is provided for the electrical connection to the internal circuit of the semiconductor device. While, the subsidiary portion is provided for the probing, in particular, for testing high frequency performance of the semiconductor device by probing the RF-probe. Because the subsidiary portion is independent from the primary portion, the subsidiary portion causes no effect in the electrical performance of the semiconductor device. Also, the subsidiary portion with a narrowed contact area with respect to the RF-probe leaves lesser flakes of the pad onto the probe. | 2016-10-06 |
20160293500 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes receiving film thickness distribution data of a polished first insulating film of a substrate; calculating processing data for reducing a difference between a film thickness at a center side of the substrate and a film thickness at a periphery side of the substrate, based on the film thickness distribution data; loading the substrate into a process chamber; supplying a process gas to the substrate; and correcting a film thickness of the first insulating film based on the processing data by activating the process gas so that a concentration of active species of the process gas generated at the center side of the substrate differs from a concentration of active species of the process gas generated at the periphery side of the substrate. | 2016-10-06 |
20160293501 | METHOD OF DIVIDING WAFER - Disclosed herein is a method of dividing a wafer including an exposed area incising step of lowering a cutting blade to a preset lowered position for fully severing the wafer to cause the cutting blade to incise an exposed area of a wafer unit, an image capturing step of capturing an image of the exposed area which the cutting blade has incised in the exposed area incising step, with image capturing means, a determining step of determining whether or not it is possible to fully sever the wafer on the basis of the captured image in the image capturing step, and an adjusting step of increasing a distance by which to lower the cutting blade if it is determined that it is impossible to fully sever the wafer in the determining step. | 2016-10-06 |
20160293502 | METHOD AND APPARATUS FOR DETECTING DEFECTS ON WAFERS - Methods and apparatuses for detecting particle defects on partially fabricated semiconductor wafers using chemical markers capable of binding to defects that are not detectable by laser diffractometry are provided herein. | 2016-10-06 |
20160293503 | APPARATUS AND METHOD FOR ENDPOINT DETECTION - An apparatus to control processing conditions for a substrate. The apparatus may include a current measurement component to perform a plurality of extraction current measurements for extraction current in a processing apparatus housing the substrate, the extraction current comprising ions extracted from a plasma and directed to the substrate; and an endpoint detection component comprising logic to generate an endpoint detection signal based upon a change in extraction current during the plurality of extraction current measurements. | 2016-10-06 |
20160293504 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY PANEL HAVING THE SAME - A thin film transistor (TFT) substrate includes a base substrate, a TFT disposed on the base substrate. The TFT includes a gate electrode, a semiconductor layer comprising a channel region, and a source electrode and a drain electrode spaced apart from one another by a length of the channel region. The TFT substrate further includes a gate insulating layer disposed between the gate electrode and the semiconductor layer and a measuring pattern configured to measure a length of the channel region. | 2016-10-06 |
20160293505 | Accelerated Failure Test of Coupled Device Structures Under Direct Current Bias - A method of conducting an in situ reliability test on a cross-section of a device with layered structure at micron-scale and at least two electrodes. The method includes steps of locating an electron transparent cross-sectional portion of the device in a holder and transmitting a direct current bias voltage to the cross-sectional portion of the device through at least two electrodes of the device, and observing and quantifying the microstructural changes of the device cross-section on the holder. A system for conducting an in situ reliability test on a device with a layered structure at a micron-scale and at least two electrodes is also provided. | 2016-10-06 |
20160293506 | SCAN TESTABLE THROUGH SILICON VIAs - The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs. | 2016-10-06 |
20160293507 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MEASURING METHOD - A semiconductor device reduces measurement time. The semiconductor device according to an embodiment of the invention includes: plural series-coupled resistance elements for testing; plural switches coupled to a coupling path coupling the resistance elements; and plural selection circuits to select, by turning on or off the switches, a number of the series-coupled resistance elements to be measured as a group. In the semiconductor device: the switches include plural first switches coupled to plural groups of the resistance elements, each of the groups including N (N=2 or a larger integer) of the resistance elements; and the selection circuits turn the first switches on or off and thereby select a number of the series-coupled resistance elements to be measured as a group, the number equaling the N. | 2016-10-06 |
20160293508 | SEMICONDUCTOR DEVICE PACKAGES - A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver. | 2016-10-06 |
20160293509 | Metal Top Stacking Package Structure and Method for Manufacturing the same - The present invention relates to a meal top stacking package structure and a method for manufacturing the same, wherein the metal top stacking package structure comprises a metal base including an upper surface and a lower surface, and a die receiver cavity formed in the upper surface; a first chip fixed on the die receiver cavity by a first adhesion layer; a substrate with an upper surface; a second chip fixed on the upper surface of the substrate by a second adhesion layer; and a plurality of connecting components formed on the upper surface of the substrate; wherein the upper surface of the metal base is connected with the substrate by the connecting components. Thereby, the structure and method can enhance heat dissipation and electromagnetic shield of the stacking package structure. | 2016-10-06 |
20160293510 | SEMICONDUCTOR DEVICE HAVING ELECTRODE PADS ARRANGED BETWEEN GROUPS OF EXTERNAL ELECTRODES - The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps. | 2016-10-06 |
20160293511 | Conductive Line System and Process - A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers. | 2016-10-06 |
20160293512 | ELECTRONIC DEVICE WITH DUMMY IC DIE AND RELATED METHODS - An electronic device may include a substrate, an active IC die above the substrate, and a dummy IC die above the active IC die. The electronic device may include a first adhesive layer between the active IC die and the dummy IC die, and a heat sink layer above the dummy IC die and extending laterally outwardly to define a gap between the substrate and opposing portions of the heat sink layer. | 2016-10-06 |
20160293513 | SEMICONDUCTOR DEVICE HAVING A HEAT TRANSFER PATH THROUGH A GROUND LAYER - A semiconductor device includes a first substrate including a surface layer and a ground layer, the surface layer including a plurality of first vias that is exposed on a surface of the first substrate and electrically connected to the ground layer, a second substrate disposed on the first substrate and including a plurality of second vias penetrating through the second substrate, a plurality of conduction elements, each disposed between one of the first vias and one of the second vias, a semiconductor device unit disposed on the second substrate, and a heat transfer layer covering the semiconductor device unit and in contact with the second vias at a periphery of the semiconductor device unit, such that heat generated by the semiconductor device unit is transferred to the ground layer, through the heat transfer layer, the second vias, the conduction elements, and the first vias. | 2016-10-06 |
20160293514 | SEMICONDUCTOR ASSEMBLY WITH BUILT-IN STIFFENER AND INTEGRATED DUAL ROUTING CIRCUITRIES AND METHOD OF MAKING THE SAME - A semiconductor assembly with built-in stiffener and integrated dual routing circuitries is characterized in that a semiconductor device and a first routing circuitry are positioned within a through opening of a stiffener whereas a second routing circuitry extends to an area outside of the through opening of the stiffener. The mechanical robustness of the stiffener can prevent the assembly from warping. The first routing circuitry can enlarge the pad size and pitch of the semiconductor device, whereas the second routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the first routing circuitry with the stiffener. | 2016-10-06 |
20160293515 | PROGRAMMABLE ACTIVE COOLING DEVICE - Cooling devices for SOI wafers and methods for forming the devices are presented. A substrate having a top surface layer, a support substrate and an insulator layer isolating the top surface layer from the support substrate is provided. At least one device is disposed in the top surface layer of the substrate. The IC includes a cooling device. The cooling device includes a doped layer which is disposed in a top surface of the support substrate, and a RDL layer disposed within the support substrate below the doped layer for providing connections to hotspots in the doped layer to facilitate thermoelectric conduction of heat in the hotspots away from the hotspots. | 2016-10-06 |
20160293516 | HEAT EXCHANGER - A thermal exchange device with reduced sizes and suitable to cool down electronic components in data center is disclosed. The device includes:
| 2016-10-06 |
20160293517 | SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE - A semiconductor module includes a semiconductor element having a gate electrode and source electrode on the front surface, and a drain electrode on the rear surface, the drain electrode being electrically connected to the front surface of a drain plate; a laminated substrate having, on the front surface of an insulating plate, a first circuit plate to which the gate electrode is electrically connected, and a second circuit plate to which the source electrode is electrically connected, and which is disposed on the front surface of the drain plate; a gate terminal disposed on the first circuit plate; a source terminal disposed on the second circuit plate; and a cover disposed opposite to the front surface of the drain plate, and having an opening in which the gate terminal and the source terminal are positioned and a guide groove contacting the opening and extending to the outer peripheral portion. | 2016-10-06 |
20160293518 | SEMICONDUCTOR MODULE COOLER AND METHOD FOR MANUFACTURING SAME - A semiconductor module cooler for reducing a pressure loss of a coolant includes a first plate mounted with a first semiconductor module; a jacket disposed under the first plate and having a distribution portion, and first and second through-holes separated from each other to be disposed at end portions of the depression respectively; an inlet-side header disposed to cover the first through-hole from under the jacket; an outlet-side header disposed to cover the second through-hole from under the jacket and extending in parallel to the inlet-side header; and a plurality of cooling fins disposed in the depression and extending from above a distribution portion of the inlet-side header to above a water collection portion of the outlet-side header. | 2016-10-06 |
20160293519 | SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON-VIA AND METHODS OF FORMING THE SAME - Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material. | 2016-10-06 |
20160293520 | STACKED INTERCONNECT STRUCTURE AND METHOD OF MAKING THE SAME - A method is provided of forming an interconnect structure. The method comprises forming a first dielectric layer overlying a first conductive layer, etching a trench opening in the first dielectric layer, depositing a sacrificial material layer in the trench opening, and forming a second conductive layer overlying the sacrificial layer. The method also comprises forming a via to the sacrificial layer, and performing an etch to remove the sacrificial material layer through the via and leave a resultant air gap between the first conductive layer and the second conductive layer increasing the effective dielectric constant between the first and second conductive layers. | 2016-10-06 |
20160293521 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire. | 2016-10-06 |
20160293522 | AU-BASED SOLDER DIE ATTACHMENT SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention, having an Au-based solder layer ( | 2016-10-06 |
20160293523 | SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE CLIP WITH FLEXIBLE LEADS AND RELATED METHODS - An integrated circuit (IC) device may include a leadframe and an IC die having a first surface coupled to the lead frame and a second surface opposite the first surface. The IC device may further include a conductive clip including a first portion coupled to the second surface of the IC die, a second portion coupled to the first portion and extending laterally away from the IC die, and at least one flexible lead coupled to the second portion and looping back under the second portion toward the leadframe. Furthermore, a package may be over the leadframe, IC die, and conductive clip and have an opening therein exposing the at least one flexible lead. | 2016-10-06 |
20160293524 | Printed Circuit Board Including a Leadframe with Inserted Packaged Semiconductor Chips - An electronic module includes a circuit board, having a carrier layer, the carrier layer having a plurality of recess areas in a main surface thereof, and a plurality of electronic sub-modules, each one of the sub-modules being disposed in one of the recess areas and each one of the sub-modules having a carrier, a semiconductor chip disposed on the carrier, and an encapsulation material disposed on the carrier and on the semiconductor chip. | 2016-10-06 |
20160293525 | LEAD FRAME, MOLD AND METHOD OF MANUFACTURING LEAD FRAME WITH MOUNTED COMPONENT - A lead frame includes one metal plate | 2016-10-06 |
20160293526 | LEAD FRAME WITH DEFLECTING TIE BAR FOR IC PACKAGE - A packaged integrated circuit (IC) device having a heatsink mounted onto an IC die, itself mounted onto a die pad, is assembled using a lead frame having tie bars that deflect during an encapsulation phase of the device assembly, which enables the die pad, the die, and the heatsink to move relative to the lead frame support structure when compressive force is applied by the molding tool. This movement results in negligible relative displacement between the heatsink and the die during encapsulation, which reduces the probability of physical damage to the die. Each tie bar has a number of differently angled sections that enable it to deflect when compressive force is applied to it. | 2016-10-06 |