40th week of 2011 patent applcation highlights part 36 |
Patent application number | Title | Published |
20110242847 | LAMINATED DOUBLE-SIDED LIGHT GUIDE PLATE - The present invention provides a light guide plate having an input surface for receiving light from a light source, a micro-patterned output surface for emitting light, and a micro-patterned bottom surface opposing to the output surface, made in steps comprising: extruding a first resin into the nip between a first pressure roller and a first patterned roller to form a first layer. Extruding a second resin into the nip between a second pressure roller and a second patterned roller to form a second layer. Laminating the first layer and the second layer at their unpatterned surfaces to form an optical sheet comprising a plurality of light guide plate patterns, and cutting and finishing the optical sheet into a plurality of double-sided light guide plates having the specified length and width dimensions. | 2011-10-06 |
20110242848 | PRINTED DOUBLE-SIDED LIGHT GUIDE PLATE - The present invention provides a light guide plate having an input surface for receiving light from a light source, a micro-patterned output surface for emitting light, and a micro-patterned bottom surface opposing to the output surface, made in steps comprising: extruding a resin into the nip between a pressure roller and a patterned roller to form a layer at a patterned roller surface temperature T1 and a nip pressure P1, the layer having an un-patterned surface and a patterned surface, the patterned surface having a pattern transferred from the patterned roller. Printing a discrete pattern on the un-patterned surface of the layer to form an optical sheet comprising a plurality of light guide plate patterns, and cutting and finishing the said optical sheet into a plurality of double-sided light guide plates having the specified length and width dimensions. | 2011-10-06 |
20110242849 | THIN DOUBLE-SIDED LIGHT GUIDE PLATE - The present invention provides a light guide plate having an input surface for receiving light from a light source, a micro-patterned output surface for emitting light, and a micro-patterned bottom surface opposing to the output surface, made in steps comprising: extruding a first resin into the nip between a first pressure roller and a first patterned roller to form a first layer. Extruding a second resin into the nip between a second pressure roller and a second patterned roller and onto the unpatterned surface of the first layer to form a second layer. The second layer having a pattern transferred from the second patterned roller; the combined first and second layers form an optical sheet comprising a plurality of light guide plate patterns and cutting and finishing the optical sheet into a plurality of double-sided light guide plates having the specified length and width dimensions. | 2011-10-06 |
20110242850 | DOUBLE-SIDED LIGHT GUIDE PLATE MANUFACTURED WITH MICRO-PATTERNED CARRIER - The present invention provides a light guide plate having an input surface for receiving light from a light source, a micro-patterned output surface for emitting light, and a micro-patterned bottom surface opposing to the output surface, made in steps comprising: extruding a resin into the nip between a patterned roller and a patterned carrier film at a nip pressure P | 2011-10-06 |
20110242851 | DOUBLE-SIDED LIGHT GUIDE PLATE MANUFACTURED WITH PATTERNED ROLLERS - The present invention provides a light guide plate having an input surface for receiving light from a light source, a micro-patterned output surface for emitting light, and a micro-patterned bottom surface opposing to the output surface. The invention provides extruding a resin into the nip between a first patterned roller and a second patterned roller at a first patterned roller surface temperature T | 2011-10-06 |
20110242852 | BACKLIGHT UNIT AND DISPLAY APPARATUS - Provided is a backlight unit, which includes at least one supporter, at least one light guide panel, and at least one light emitting module. The supporter includes a recess stepped at a lower height than that of a first region of an upper surface. The light guide panel is disposed on the supporter and is coupled to the supporter. The light emitting module is disposed in the recess of the supporter and provides light through a side surface of the light guide panel. | 2011-10-06 |
20110242853 | HIGH VOLTAGE POWER SUPPLY - A high voltage power supply is provided. The high voltage power supply includes an inverter which converts a DC voltage input to the high voltage power supply into a first AC voltage, a transformer including an input winding unit and a plurality of output winding units, wherein the input winding unit receives the first AC voltage from the inverter and the plurality of output winding units generates and outputs a second AC voltage, and a voltage multiplier unit which boosts the second AC voltage output by the transformer and outputs a boosted voltage, and the voltage multiplier unit includes a plurality of voltage multipliers which are connected to each other in series and the plurality of voltage multipliers may be connected to the plurality of output winding units respectively. | 2011-10-06 |
20110242854 | SWITCHING POWER UNIT - There is provided switching power unit comprising: a PFC voltage detector that detects PFC voltages of the power-factor improvement unit; an output voltage detector that is provided in a current resonance converter unit; a switching controller into which output signals from the PFC voltage detector and output signals from the output voltage detector are input, wherein the switching controller in a full-bridge circuit of first to fourth switching elements, based on output signals from the PFC voltage detector and the output voltage detector, controls the PFC voltages by changing on-duty of the first and second switching elements, and also controls the output voltages by changing switching frequencies of the full-bridge circuit. | 2011-10-06 |
20110242855 | Power Converter - A DC-DC power converter ( | 2011-10-06 |
20110242856 | RESONANT CONVERTER - A resonant converter ( | 2011-10-06 |
20110242857 | MAXIMUM POWER POINT TRACKER, POWER CONVERSION CONTROLLER, POWER CONVERSION DEVICE HAVING INSULATING STRUCTURE, AND METHOD FOR TRACKING MAXIMUM POWER POINT THEREOF - Disclosed are a maximum power point tracker, a power conversion controller, a power conversion device having an insulating structure, and a method for tracking maximum power point. The power conversion device includes: a DC/AC converter including a primary DC chopper unit having a primary switch, a transformer, and an AC/AC conversion unit including a secondary switch; a current detector detecting current from an input stage of the DC/AC converter and providing a detected current value; a voltage detector detecting a system voltage from an output stage of the DC/AC converter; and a power conversion controller generating a primary PWM signal to be provided to the primary DC chopper unit and secondary first and second PWM signals, having the mutually opposing phases, to be provided to the AC/AC conversion unit by using the detected current value and the system voltage. | 2011-10-06 |
20110242858 | SWITCHING CONVERTER SYSTEMS WITH ISOLATING DIGITAL FEEDBACK LOOPS - Switching converter systems are provided to control output voltage across a load by means of a converter forward path and a converter feedback path. The forward path preferably includes a transistor, an inductive element, a diode and a capacitor arranged to switchably exchange energy with the capacitor to thereby generate the output voltage. The feedback path preferably extends from the capacitor and is configured to digitally control a duty cycle of the transistor in response to the output voltage. In a system embodiment, the feedback path includes at least one comparator arranged to provide a digital error signal in response to a comparison of the output voltage to a reference voltage; a first isolation channel configured to isolatably transport a clock signal to digitally gate the error signal; a second isolation channel configured to isolatably transport the error signal; and a controller coupled to the first and second isolation channels and configured to control the duty cycle in response to the error signal. A transformer is preferably inserted into the first and second isolation channels to enhance isolation and, preferably, the first and second isolation channels respectively include first and second digital gates that each have an output port coupled to an input port of the other. | 2011-10-06 |
20110242859 | ISOLATED PRIMARY CIRCUIT REGULATOR - An isolated primary circuit regulator is applied to a primary side of a transformer of a power supply. The isolated primary circuit regulator outputs a switching signal, and switches the transformer by using the switching signal, thereby stabilizing an output current. The isolated primary circuit regulator includes a discharge time detector, an oscillator, a pulse width modulator and a control circuit. The discharge time detector is used for detecting a discharge time of a switching current generated at a secondary side of the transformer. The oscillator is used for generating an oscillation signal. The control circuit is used for outputting an adjustment signal. The pulse width modulator outputs a switching signal according to the oscillation signal output by the oscillator and the adjustment signal output by the control circuit. The switching signal has a duty cycle and a frequency corresponding to the oscillation signal and the adjustment signal. | 2011-10-06 |
20110242860 | POWER SEMICONDUCTOR DEVICE AND POWER CONVERSION SYSTEM USING THE DEVICE - In some aspects of the invention, a power semiconductor module is applied to a multi-level converter circuit with three or more levels of voltage waveform. A first IGBT, a diode whose cathode is connected to the emitter of the first IGBT, and a second IGBT having reverse blocking voltage whose emitter is connected to the emitter of the first IGBT, are housed in one package, and each of the collector of the first IGBT, the collector of the second IGBT, the connection point of the emitter of the first IGBT and the emitter of the second IGBT, and the anode of the diode, is an external terminal. | 2011-10-06 |
20110242861 | ELECTRONIC DEVICE AND SEMICONDUCTOR DEVICE - The present invention provides a method of improving efficiency in a full load region in a PFC power source of an active filter method by controlling a switch circuit of the PFC power source in association with an output power of the PFC power source. A pair of two switches controlling charging/discharging an inductor is provided. A MOSFET switch having a small current capacity is used as one of the switches, and an IGBT switch of a large current capacity is used as the other switch. When an output of a voltage dividing circuit for dividing voltage of an output terminal of the PFC power source is smaller than a threshold voltage, only the MOSFET switch is operated. When the output exceeds a threshold voltage, the IGBT switch is also operated. | 2011-10-06 |
20110242862 | SOFT START CIRCUIT FOR POWER FACTOR CORRECTION NETWORK - A soft start circuit for a power factor correction circuit. In one embodiment, the soft start circuit controls an input to a power factor correction pre-regulator chip to allow the output voltage to be set initially to a value lower than the desired nominal output voltage of the power factor correction circuit. Once stabilized, the input to the power factor correction pre-regulator chip is changed to increase the output voltage to the desired nominal output voltage of the power factor correction, thereby avoiding any significant overshoot of the desired nominal output. | 2011-10-06 |
20110242863 | PATCH ANTENNA AND RECTENNA USING THE SAME - A patch antenna for receiving high frequency wireless signal and a rectenna using the same, more particularly, an impedance-matched patch antenna adopting a slot capacitive coupling structure and a rectenna capable of generating electrical energy from the wireless signals having different frequency band. A rectenna for receiving an A.C. wireless signal carrying electrical energy and converting the wireless signal into a D.C. electrical energy, is comprised of: a patch antenna for receiving the wireless signal comprising an dielectric substrate, a patch that is formed at the upper area of the surface of the dielectric substrate and providing the first frequency response characteristics, a ground plane formed on the other surface of the dielectric substrate, and an impedance matching means providing the second frequency response characteristics; and a rectifying unit that converts the wireless signal, received via the patch antenna, into a D.C. electrical energy by rectifying the wireless signal. | 2011-10-06 |
20110242864 | CURRENT SOURCE POWER CONVERSION CIRCUIT - An example of the current source power conversion circuit is provided with a plurality of half-bridge rectifier circuits which are connected in parallel, each including a serial connection of a first switch circuit having a first self-turn-off element and a first diode which are connected in series to each other, and a second switch circuit having a second self-turn-off element and a second diode which are connected in series to each other. A first current electrode of said first self-turn-off element in one of said half-bridge rectifier circuits and a first current electrode of said first self-turn-off element in other one of said half-bridge rectifier circuits are short-circuited and connected. | 2011-10-06 |
20110242865 | Self-powered Active Rectifier Circuit and Related Method of Operation for Photovoltaic Solar Power Arrays - The active rectifier circuit and related method of operation disclosed herein is self-powered and improves the efficiency and reliability of photovoltaic solar power systems by replacing the conventional bypass and blocking rectifiers used in such systems. The circuit includes a power MOSFET used as a switch between the anode and cathode terminals, and control circuitry that turns on the MOSFET when the anode voltage is greater than the cathode voltage. The method of operation utilizes resonance to produce a large periodic voltage waveform from the small anode-to-cathode dc voltage drop, and then converts the period voltage waveform to a dc voltage to drive the gate of the power MOSFET. | 2011-10-06 |
20110242866 | POWER SEMICONDUCTOR DEVICE AND POWER CONVERSION SYSTEM USING THE DEVICE - Aspects of the invention are related to a power semiconductor module applied to a multi-level converter circuit with three or more levels of voltage waveform. Aspects of the invention can include a first IGBT to which a diode is reverse parallel connected and a second IGBT having reverse blocking voltage whose emitter is connected to the emitter of the first IGBT are housed in one package, and each of the collector of the first IGBT, the collector of the second IGBT, and the connection points of the emitter of the first IGBT and the emitter of the second IGBT, is an external terminal. | 2011-10-06 |
20110242867 | Power Inverters and Related Methods - Some embodiments include power inverters and related methods. Other embodiments of related systems and methods are also disclosed. | 2011-10-06 |
20110242868 | CIRCUIT AND METHOD FOR COUPLING ELECTRICAL ENERGY TO A RESONATED INDUCTIVE LOAD - A switching circuit (Q | 2011-10-06 |
20110242869 | THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREOF - A three-dimensional stacked semiconductor integrated circuit including a plurality of stacked chips. The semiconductor integrated circuit is configured to simultaneously select the plurality of chips in response to an external command and an address, and to activate one of memory banks which are aligned on the same line in a vertical direction, among a plurality of memory banks included in the plurality of chips. | 2011-10-06 |
20110242870 | STACKED MEMORY AND DEVICES INCLUDING THE SAME - In one embodiment, the stacked memory includes a first group of stacked memory chips, a second group of stacked memory chips, and connection terminals configured to electrically connect a first memory chip among the stacked memory chips in the first group to a second memory chip among the stacked memory chips in the second group. | 2011-10-06 |
20110242871 | Vertically stacked third-dimensional embedded re-writeable non-volatile memory and registers - A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations. | 2011-10-06 |
20110242872 | SEMICONDUCTOR DEVICE - A highly-reliable, highly-integrated large-capacity phase-change memory is achieved. For this purpose, for example, memory tiles MT | 2011-10-06 |
20110242873 | Photo-Responsive Memory Resistor and Method of Operation - An optically-controlled memory resistor, comprising (1) a memory resistor comprising a first electrode, a second electrode, and a photo-responsive active layer disposed between the first and second electrodes, and (2) a light source in cooperation with the memory resistor, the light source configured to controllably illuminate the memory resistor for affecting a resistance state exhibited by the memory resistor. Also disclosed is a method for operating a memory resistor, the method comprising changing a resistance state of the memory resistor in response to an application of a plurality of photons to the memory resistor. | 2011-10-06 |
20110242874 | RESISTIVE MEMORY AND METHOD FOR CONTROLLING OPERATIONS OF THE SAME - A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance. | 2011-10-06 |
20110242875 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array. | 2011-10-06 |
20110242876 | Buffering systems for accessing multiple layers of memory in integrated circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 2011-10-06 |
20110242877 | METHOD AND APPARATUS PROVIDING A CROSS-POINT MEMORY ARRAY USING A VARIABLE RESISTANCE MEMORY CELL AND CAPACITANCE - The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is a capacitor. | 2011-10-06 |
20110242878 | METHODS FOR OPERATING MEMORY ELEMENTS - Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays. | 2011-10-06 |
20110242879 | TWO WORD LINE SRAM CELL WITH STRONG-SIDE WORD LINE BOOST FOR WRITE PROVIDED BY WEAK-SIDE WORD LINE - An integrated circuit having a static random access memory (SRAM) includes an array of SRAM cells arranged in rows and columns having a write word line and a read/write word line connected to provide row access to the array of SRAM cells. The SRAM also includes a coupling capacitance connected between the write word line and a detachable allocation of the read/write word line as well as an overdrive module connected to charge the coupling capacitance and provide an overdrive voltage on the detachable allocation of the read/write word line during activation of the write word line. A method of operating an integrated circuit having an SRAM includes providing an overdrive voltage on the detachable allocation of the read/write word line corresponding to a charge redistribution across the coupling capacitance during part of a write cycle. | 2011-10-06 |
20110242880 | MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY - Integrated circuits with memory cells are provided. A memory cell may have four inverter-like circuits connected in a ring configuration and four corresponding storage nodes. The four inverter-like circuits may form a storage portion of the memory cell. Some of the inverter-like circuits may have tri-state transistors in pull-up and pull-down paths. The tri-state transistors may be controlled by address signals. Address and access transistors may be coupled between some of the storages nodes and a data line. The address and access transistors may be used to read and write into the memory cell. During write operations, the address signals may be asserted to turn off the tri-state transistors and eliminate contention current from the cell. During read and normal operations, the address signals may be deasserted to allow the inverter-like circuits to hold the current state of the cell while providing soft error upset immunity. | 2011-10-06 |
20110242881 | SRAM DEVICE - An object of the present invention is to provide an SRAM device which can set a threshold voltage of a selection transistor appropriate for all the cells on an SRAM array. The SRAM device uses a field effect transistor as the selection transistor, the field effect transistor comprising a gate to drive the transistor and a terminal to control a threshold voltage, which are electrically separated from each other, wherein the SRAM device comprises a circuit which gradually increases, on a reading operation, a voltage supplied to the terminal to control the threshold of the selection transistor from a voltage at the start of the reading. | 2011-10-06 |
20110242882 | Semiconductor memory device including SRAM cell - A semiconductor memory device includes: a first word line and a second word line; a plurality of first SRAM cells; a plurality of second SRAM cells; and a mediating cell. Each first SRAM cell includes the first word line and the second word line and is connected to the first word line. Each second SRAM cell includes the first word line and the second word line and is connected to the second word line. The mediating cell is arranged between and adjacent to one first SRAM cell and one second SRAM cell and is connected to the first word line and the second word line. In the mediating cell and the plurality of first SRAM cells, cells adjacent to each other share a contact for the first word line. In the mediating cell and the plurality of second SRAM cells, cells adjacent to each other share a contact for the second word line. | 2011-10-06 |
20110242883 | THERMALLY ASSISTED MULTI-BIT MRAM - Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation. | 2011-10-06 |
20110242884 | Programming at Least One Multi-Level Phase Change Memory Cell - A method of applying at least one programming pulse to the a PCM cell for programming the PCM cell to have a respective definite cell state, the definite cell state being defined by a definite resistance level using an annealing pulse or a melting pulse. The respective definite cell state represents two information entities, a step of applying a first reading pulse to the respective programmed PCM cell to provide a first resistance value, a step of applying at least a second reading pulse to the respective programmed PCM cell to provide a second resistance value, the first reading pulse and the second reading pulse being different pulses; and a step of determining the respective definite cell state of the respective programmed PCM cell dependent on the respective provided first resistance value and the respective provided second resistance value. | 2011-10-06 |
20110242885 | THREE-DIMENSIONAL PHASE CHANGE MEMORY - A memory device includes a stack of semiconductor layers. A circuit is on a layer of the stack of semiconductor layers. A primary memory array is on another layer of the stack of semiconductor layers different from the layer comprising the circuit. A plurality of electrical communication paths are between the circuit and the primary memory array. The circuit controls the operation of the primary memory array over the electrical communication paths. | 2011-10-06 |
20110242886 | Apparatus and Systems Using Phase Change Memories - Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit. | 2011-10-06 |
20110242887 | Programmable Resistance Memory with Feedback Control - A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory cell. | 2011-10-06 |
20110242888 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap. | 2011-10-06 |
20110242889 | PROGRAMMING NON-VOLATILE MEMORY WITH HIGH RESOLUTION VARIABLE INITIAL PROGRAMMING PULSE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a program pulse associated with achieving a particular result for a respective programming process and performing one or more sensing operations at one or more alternative results for the non-volatile storage elements. Subsequent programming process are adjusted based on a first alternative result and the identification of the program pulse if the one or more sensing operations determined that greater than a predetermined number of non-volatile storage elements achieved the first alternative result. Subsequent programming process are adjusted based on the identification of the program pulse if the one or more sensing operations determined that less than a required number of non-volatile storage elements achieved any of the alternative results. | 2011-10-06 |
20110242890 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining | 2011-10-06 |
20110242891 | OPERATION METHODS FOR MEMORY CELL AND ARRAY FOR REDUCING PUNCH THROUGH LEAKAGE - A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells. | 2011-10-06 |
20110242892 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage. | 2011-10-06 |
20110242893 | NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction. | 2011-10-06 |
20110242894 | METHOD AND SYSTEM TO ISOLATE MEMORY MODULES IN A SOLID STATE DRIVE - A method and system to facilitate the usage of memory modules that have one or more defective memory dies. In one embodiment of the invention, a memory module is packaged with a number of dies and the memory module is tested and sorted according to the number of dies that pass testing. Each signal of each die in the memory module has an unique bond-out or connection point in the package of the memory module. By separating the signals of each die in the memory module, any defective die can be easily isolated and this allows a significant cost reduction in products that use a large number of dies. | 2011-10-06 |
20110242895 | MEMORY DEVICE, MANUFACTURING METHOD FOR MEMORY DEVICE AND METHOD FOR DATA WRITING - A memory device to which an electron beam is irradiated to store data therein is provided. The memory device includes a plurality of floating electrodes that store data through irradiation of the electron beam thereto, a charge amount detecting section that detects data stored in each of the floating electrodes based on a charge amount accumulated in each of the floating electrode. | 2011-10-06 |
20110242896 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor device includes a booster circuit and a detector. The booster circuit is configured to boost an input voltage and output an output voltage, and the detector is configured to output the output voltage, which is output from the booster circuit, and control the booster circuit to generate a plurality of different voltages in accordance with an operating mode. | 2011-10-06 |
20110242897 | PROGRAM AND READ TRIM SETTING - A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability. | 2011-10-06 |
20110242898 | 4-TRANSISTOR NON-VOLATILE MEMORY CELL WITH PMOS-NMOS-PMOS-NMOS STRUCTURE - A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node. | 2011-10-06 |
20110242899 | EXTRA DUMMY ERASE PULSES AFTER SHALLOW ERASE-VERIFY TO AVOID SENSING DEEP ERASED THRESHOLD VOLTAGE - An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify operation. The verify operation uses a verify level which is offset higher from a final desired threshold voltage level. The erase pulses step up in amplitude until a maximum level is reached, at which point additional erase pulses at the maximum level are applied. The first phase ends when the verify operation passes. The second phase applies one or more extra erase pulses which are higher in amplitude than the last erase pulse in the first phase and which are not followed by a verify operation. This avoids the need to perform a verify operation at deep, negative threshold voltages levels, which can cause charge trapping which reduces write-erase endurance, while still achieving the desired deep erase. | 2011-10-06 |
20110242900 | MEMORY CELL SENSING DEVICES AND METHODS - The present disclosure includes methods, devices, and systems for sensing memory cells. One or more embodiments include providing an output of a first counter to a digital-to-analog converter (DAC). An output of the DAC can correspond to a ramping voltage provided to a control gate of the memory cell. An output of a second counter can be provided to sensing circuitry coupled to a sense line of the memory cell. Conduction of the sense line in response to the ramping voltage can be sensed, and an output value of the second counter can be determined in response to the sensed conduction of the sense line. | 2011-10-06 |
20110242901 | LIFETIME MARKERS FOR MEMORY DEVICES - The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells. | 2011-10-06 |
20110242902 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a memory cell array including a plurality of memory cells; a plurality of word lines each connected in common to memory cells arranged in a corresponding one of rows among the plurality of memory cells; a voltage generator including a clock signal cycle controller configured to lengthen a cycle of a clock signal every time writing is performed at a stepped-up program voltage to the memory cells connected to a word line selected from the word lines, the voltage generator being configured to generate a desired output voltage by using the clock signal, wherein the clock signal cycle controller performs control in such a way that a ramp up rate for writing at the stepped-up program voltage is kept substantially equal to a ramp up rate for writing at an initial program voltage. | 2011-10-06 |
20110242903 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENIN ERASE TIME - In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage. | 2011-10-06 |
20110242904 | Read Only Memory and Operating Method Thereof - A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second voltage range; a word line driver, powered by a second power source with a voltage which is higher than that of the first power source, for driving one of a plurality of word lines of a read only memory cell array according to the control signal which is expanded to be within the second voltage range; and an input/output circuit, for connecting the plurality of bit lines to read out messages. | 2011-10-06 |
20110242905 | SEMICONDUCTOR MODULE INCLUDING MODULE CONTROL CIRCUIT AND METHOD FOR CONTROLLING THE SAME - A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal to output a first group identification signal, latch the identification signal in accordance with a second enable signal to output a second group identification signal, and latch the internal command signal in accordance with the second enable signal to output a group command signal. A comparator is configured to compare the first group identification signal with the second group identification signal, and generate a selection signal. A multiplexer is configured to select one of the group command signal and a module command signal as an input command in response to the selection signal. | 2011-10-06 |
20110242906 | DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE - A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation. | 2011-10-06 |
20110242907 | SEMICONDUCTOR MEMORY APPARATUS AND READ/WRITE CONTROL METHOD THEREOF - A semiconductor memory apparatus includes: a read/write control unit configured to generate a write control signal and a read control signal using internal signals generated through separate signal paths in response to a write command and a read command respectively; and a plurality of ranks configured to perform a write operation or read operation according to the write control signal or the read control signal. | 2011-10-06 |
20110242908 | COMMAND DECODER AND A SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A command decoder includes a snoop read control signal generation unit that generates a snoop read control signal from a internal chip select signal according to a level of a transmission mode control signal, and an internal snoop read command generation unit that generates an internal snoop read command by driving a first node in response to an internal command and the snoop read control signal. | 2011-10-06 |
20110242909 | SEMICONDUCTOR DEVICE AND SYSTEM - A system includes a data transmitting device and a data receiving device. The data transmitting device includes a data strobe signal generation unit configured to generate first and second data strobe signals in response to an output enable signal, and a data output unit configured to transmit data in synchronization with the first data strobe signal. The data receiving device is configured to receive the data in synchronization with the second data strobe signal. | 2011-10-06 |
20110242910 | DATA STROBE CLOCK BUFFER IN SEMICONDUCTOR MEMORY APPARATUS, METHOD OF CONTROLLING THE SAME, AND SEMICONDUCTOR APPARATUS HAVING THE SAME - A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal. | 2011-10-06 |
20110242911 | COLUMN COMMAND BUFFER AND LATENCY CIRCUIT INCLUDING THE SAME - A column command buffer includes a variable delay section configured to determine a delay time based on a frequency of a clock, and output a column command after delaying it by the delay time; and a buffering section configured to receive an output of the variable delay section and generate internal column commands. | 2011-10-06 |
20110242912 | Random Access Memory Devices Having Word Line Drivers Therein That Support Variable-Frequency Clock Signals - Integrated circuit memory devices include an array of memory cells electrically coupled to a plurality of word lines and a word line driver circuit. The word line driver circuit includes a variable-width pulse generator having a first delay unit therein. The word line driver circuit is configured to drive a selected one of the plurality of word lines with a first word line signal having a leading edge synchronized with a leading edge of a clock signal and a trailing edge synchronized with a trailing edge of the clock signal when a one-half period of the clock signal is greater than a length of delay provided by the first delay unit. The word line driver circuit is further configured to drive the selected one of the plurality of word lines with a second word line signal having a leading edge synchronized with the leading edge of a clock signal and a trailing edge synchronized with an edge of a signal generated by the first delay unit when the one-half period of the clock signal is less than the length of the delay provided by the first delay unit. | 2011-10-06 |
20110242913 | SELF REFRESH CIRCUIT - A self refresh circuit includes a continuous output interrupting unit and a glitch removing unit. The continuous output interrupting unit is configured to receive a delay self refresh signal, transmit a pulse of an internal active signal as a first output active signal and interrupt the transmission of the pulse of the internal active signal during a first time period. The glitch removing unit is configured to generate and output a second output active signal when the first output active signal has a predetermined pulse width. | 2011-10-06 |
20110242914 | CLOCK DELAY ADJUSTMENT CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD OF THE SAME - A clock signal adjustment circuit in a semiconductor integrated circuit includes: multiple circuit blocks; multiple clock delay circuits supplying delayed clock signals of the input clock signals under the control of the delay control signals to the corresponding circuit blocks; a control circuit conducting a delay test of the circuit blocks; a recovery group memory circuit storing information in the circuit blocks requiring the delay process among the circuit blocks, responsive to the result of the delay test; delay setting circuits storing information about the delay value for circuit blocks requiring the delay process among the circuit blocks, responsive to the result of the delay test; and a delay setting dispatch control circuit dispatching the delay control signal corresponding to the delay value information stored in the delay setting circuit to the clock delay circuits corresponding to the information about the circuit blocks stored in the recovery group memory circuit. | 2011-10-06 |
20110242915 | METHOD AND APPARATUS FOR REDUCING OSCILLATION IN SYNCHRONOUS CIRCUITS - Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line. | 2011-10-06 |
20110242916 | ON-DIE TERMINATION CIRCUIT, DATA OUTPUT BUFFER AND SEMICONDUCTOR MEMORY DEVICE - An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate. | 2011-10-06 |
20110242917 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes: a repair address generation unit configured to generate a repair address signal in response to a first address signal; a line choice address generation unit configured to generate a line choice address signal by combining the first address signal and the repair address signal according to a determination as to whether the repair address signal is to be used; and a cell line decoding unit configured to select one of a normal cell region and a redundancy cell region according to the determination, and select one of a plurality of local cell lines provided in the selected cell region in response to the line choice address signal. | 2011-10-06 |
20110242918 | GLOBAL LINE SHARING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - A global line sharing circuit of a semiconductor memory device includes: a ZQ calibration unit configured to adjust an impedance of a DQ output driver; a test unit configured to control a test operation; and a shared global line coupled to and used in common by the ZQ calibration unit and the test unit. | 2011-10-06 |
20110242919 | Precharge Voltage Supplying Circuit - A precharge voltage supplying circuit comprises a transistor operating in response to a control signal, wherein the transistor is connected between a first node to which an internal voltage is supplied and a second node to which a precharge voltage is supplied, and a resistance element connected in parallel to the transistor between the first node and the second node. | 2011-10-06 |
20110242920 | VOLTAGE SENSING CIRCUIT CAPABLE OF CONTROLLING A PUMP VOLTAGE STABLY GENERATED IN A LOW VOLTAGE ENVIRONMENT - Herein, a voltage sensing circuit, which is capable of controlling a pumping voltage to be stably generated in a low voltage environment, is provided. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by a reference voltage, a second switching element configured to control current from the second terminal of the current mirror in response to a pumping voltage, and a third switching element configured to control current sources of the first and second switching elements to receive a negative voltage. | 2011-10-06 |
20110242921 | Systems And Methods Of Non-Volatile Memory Sensing Including Selective/Differential Threshold Voltage Features - Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them. | 2011-10-06 |
20110242922 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first data selection section inputted with the first data and second data and output one of the first data and the second data as first selection data in response to an address signal, a second data selection section inputted with the second data and the first selection data and output one of the second data and the first selection data as second selection data depending upon an input and output mode, and a data output section configured to be inputted with the first and second selection data and output first and second output data. | 2011-10-06 |
20110242923 | SEMICONDUCTOR MEMORY DEVICE INCLUDING CLOCK CONTROL CIRCUIT AND METHOD FOR OPERATING THE SAME - A clock control circuit includes a first clock buffer configured to toggle a first clock signal when a self-refresh exit command signal is inputted during a self-refresh operation; and a second clock buffer configured to toggle a second clock signal when the self-refresh operation is finished, the second clock being provided to internal circuits. | 2011-10-06 |
20110242924 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic circuit controls the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually operate in a second operation mode. | 2011-10-06 |
20110242925 | REDUCTION OF FUSIBLE LINKS AND ASSOCIATED CIRCUITRY ON MEMORY DIES - The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy. | 2011-10-06 |
20110242926 | PSEUDO-INVERTER CIRCUIT ON SeO1 - A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage. | 2011-10-06 |
20110242927 | Encoded Read-Only Memory (ROM) Decoder - Decoder circuits capable of decoding encoded ROM memory are provided. Embodiments provide several improvements over prior solutions which rely primarily on CMOS logic (e.g., inverters). For example, embodiments provide faster decoding by limiting the number of decoding stages to a single stage. Further, embodiments allow the use of partial swing (as opposed to full swing) on the bit lines, which results in significant power reduction. This, in turn, results in reduced amounts of capacitor discharges when reading the data. | 2011-10-06 |
20110242928 | ADDRESS DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses. | 2011-10-06 |
20110242929 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a counting control circuit and an address counting circuit. The counting control circuit is configured to generate a first counting start signal, a second counting start signal and a counting count signal in response to an auto-refresh signal, a voltage stabilization signal and a fuse control signal. The address counting circuit is configured to count a plurality of count addresses in response to the first counting start signal, and to count one or more specified count addresses from among the plurality of count addresses in response to the second counting start signal and the counting control signal. | 2011-10-06 |
20110242930 | REACTIVE STATIC MIXER - This disclosure relates to a static phosgene mixer, and more generally, to an apparatus for mixing of fluid components such as phosgene and amine during an highly reactive, chemical reaction that is vulnerable to the creation of undesired by-products, and equipment fouling. A guide element is disposed in the static mixer to divert the incoming flow of phosgene around the guide element and create an annular mixing passage in the static mixer. This allows for the use of an increased external radius of the effective phosgene flow while maintaining phosgene velocity by creating a blockage of the flow. The same flow, when transformed from a circular configuration to an annular configuration has an increased external radius, and a greater quantity of MDA jets can be placed along the increased radius, thus increasing the overall homogeneity of the mixture. Further, the cross-sectional area of the annular passage section of phosgene defined around the guide element controls the velocity of phosgene which facilitates the mixing of MDA injected through the jets into the phosgene. | 2011-10-06 |
20110242931 | ROTATIONAL RESTRAINT METHODOLOGY IN A FROZEN MIXING SYSTEM AND CONTAINER - A container for containing food and/or beverage ingredients is described. The container is of a type which may be supported in a support while the ingredients inside the container are processed, such as by a rotating blade or other mechanism. The container includes anti-rotation elements positionable in anti-rotational contact with a corresponding protruding portion in a container support in a manner which restricts rotational movement of the vessel relative to the container support. | 2011-10-06 |
20110242932 | CMUT CELL FORMED FROM A MEMBRANE OF NANOTUBES OR NANOWIRES OR NANORODS AND DEVICE FOR ULTRA HIGH FREQUENCY ACOUSTIC IMAGING INCLUDING MULTIPLE CELLS OF THIS KIND - A cMUT-type capacitive electroacoustic transducer including: at least one membrane configured to oscillate under effect of an electric field and/or an acoustic wave, wherein the membrane is formed from one or more layers of juxtaposed nanotubes or nanowires or nanorods, and an acoustic imaging device or UHF sonar including such transducers. | 2011-10-06 |
20110242933 | DETERMINING A CHARACTERISTIC OF A SEISMIC SENSING MODULE USING A PROCESSOR IN THE SEISMIC SENSING MODULE - A seismic sensing module comprises a seismic sensing element and a processor configured to generate a test signal applied to the seismic sensing element, receive a response from the seismic sensing element, and determine a characteristic of the seismic sensing module according to the response. | 2011-10-06 |
20110242934 | PASSIVE SEISMIC DATA ACQUISITION AND PROCESSING USING MULTI-LEVEL SENSOR ARRAYS - A method for passive seismic surveying includes deploying seismic sensors in a plurality of spatially distributed wellbores disposed above a volume of subsurface formations to be evaluated. The sensors in each wellbore form a line of sensors. Each sensor generate optical or electrical signals in response to seismic amplitude. The seismic signals from each sensor are recorded for a selected period of time. The response of the seismic sensor recordings is beam steered to at least one of a selected point and a selected volume in the subsurface. At least one microseismic event is identified in the beam steered response. | 2011-10-06 |
20110242935 | METHOD OF PROVIDING SEISMIC DATA - A method of providing seismic data (such as marine seismic data). A seismic source is actuated at a plurality of source locations (S | 2011-10-06 |
20110242936 | METHODS AND APPARATUS TO IDENTIFY LAYER BOUNDARIES IN SUBTERRANEAN FORMATIONS - Methods and apparatus to identify layer boundaries in subterranean formations are described. An example method of identifying a layer boundary of a subterranean formation includes transmitting an acoustic signal from a transmitter into a borehole of the subterranean formation and receiving the acoustic signal at a receiver coupled to the downhole tool and spaced from the transmitter. Additionally, the example method includes logging an energy value associated with the acoustic signal received by the receiver as the downhole tool is moved in the borehole and identifying a change in the logged energy value associated with an impedance change in the subterranean formation to identify the layer boundary. | 2011-10-06 |
20110242937 | Method for separating up and down propagating pressure and vertical velocity fields from pressure and three-axial motion sensors in towed streamers - A measured pressure field, a measured vertical velocity field, and two measured orthogonal horizontal velocity fields are obtained. A programmable computer is used to perform the following. A scaling factor is determined from water acoustic impedance, the measured pressure field, and the horizontal velocity fields. One of the measured pressure field and measured vertical velocity field is combined with one of the measured vertical velocity field scaled by the scaling factor and the measured pressure field scaled by the scaling factor, generating one of up-going and down-going pressure and velocity wavefields. | 2011-10-06 |
20110242938 | ULTRASONIC MEASUREMENTS PERFORMED ON ROCK CORES - One or more embodiments and methods of analyzing a formation sample with in a coring tool are disclosed herein. The methods and embodiments may include extracting a first core from a sidewall of a wellbore with a coring tool at a first depth, ultrasonically measuring a sound speed of the first core, transmitting the ultrasonically measured sound speed of the first core to a surface display unit, analyzing the ultrasonically measured sound speed in real time, determining the quality of the first core, extracting a second core at the first depth if the first core is determined to be low quality, and extracting the second core at a second depth if the core first is determined to be high quality. | 2011-10-06 |
20110242939 | ACTIVE SONAR SYSTEM AND ACTIVE SONAR METHOD USING A PULSE SORTING TRANSFORM - An active sonar system, a method associated therewith, and a computer-readable medium associate therewith, each provide a method of sonar signal processing. The method includes receiving a plurality of initial detections of a target and associated initial detection times, associated with sound transmitted at a pulse rate interval (PRI), and associated with received sound including echoes from a target. The echoes result from the transmitted sound. The method also includes analyzing the plurality of initial detection times with a pulse sorting transform configured to identify periodic PST detection times within the plurality of initial detection times that are equally spaced in time and that are representative of the echoes from the target. | 2011-10-06 |
20110242940 | Noise suppression by adaptive speed regulation of towed marine geophysical streamer - A method for towing marine geophysical sensor streamers in a body of water includes moving a towing vessel at a selected speed along the surface of the body of water. At least one geophysical sensor streamer is towed by the vessel at a selected depth in the water. A velocity of the streamer in the water is measured at at least one position along the streamer. The selected speed of the towing vessel is adjusted if the measured velocity exceeds a selected threshold. | 2011-10-06 |
20110242941 | DISTANCE SENSOR FOR VEHICLE WITH ELECTRICAL CONNECTOR - A distance sensor equipped with a mount for mounting the sensor in a mount hole of a bumper of a vehicle. The mount includes a casing with a sensor holder, a bezel, and a resin-made retainer. The bezel is made up of a cylindrical member joined to the sensor holder and a flange having an outer diameter greater than an inner diameter of the mount hole. The retainer includes an annular base joined to the bezel, a plurality of arms, and a plurality of protrusions. The protrusions extend from ends of the arms radially outward of the base and serve to establish a snap-fit on a peripheral edge of the mount hole, thereby nipping a wall of the bumper between the protrusions and the flange tightly to secure the distance sensor to the bumper. | 2011-10-06 |
20110242942 | DISTANCE SENSOR FOR VEHICLE WITH ELECTRICAL CONNECTOR - A distance sensor for vehicles is provided which includes a sensor device and an electric connector for an electrical connection between the sensor device and a mating connector. The connector includes at least one first terminal pin and at least one second terminal pin. The first terminal pin has a first section leading to the sensor device and a second section extending toward an inlet opening of the connector. The second terminal pin has a first section leading to the sensor device and at least two branched second sections extending toward the inlet opening of the connector. Specifically, the second terminal pin is shaped to provide two-pin plugs, thereby permitting the size of the connector to be reduced, which facilitates ease of installation of the distance sensor to, for example, a bumper of the automotive vehicle. | 2011-10-06 |
20110242943 | Hydrophone and Hydrophone Assembly for Performing Stereophonic Underwater Sound Recordings - A hydrophone for recording underwater sound includes a housing having an outer surface designed to serve as a boundary surface for an incident sound wave and at least one vibration sensor having a sensor surface for recording sound waves and for preparing a sensor signal. The sensor surface of the vibration sensor is in an opening of the housing. A hydrophone assembly includes a plurality of the hydrophones. | 2011-10-06 |
20110242944 | Unrestricted Mounting of Ultrasonic Transducers - An ultrasonic processing apparatus is disclosed that supports an ultrasonic rod transducer without restricting the transmission of ultrasonic vibrations from the rod transducer to liquid in a processing tank. A support structure supports one or both converter heads of the rod transducer without restricting its vibration. | 2011-10-06 |
20110242945 | Device for Combining an Alarm Clock with a Light Source - A device for integrating an alarm clock with an independent light source is provided, including a light fixture for giving off light and alarm for emitting sound. The light fixture and alarm are in communication with an alarm clock having programmable light and alarm controls. The alarm clock is either hard-wired into existing room circuitry, thereby combining and replacing conventional alarm clocks and light switches, or in other embodiments, the alarm clock is installed on a mobile device and is in wireless communication with the light fixture. Several example embodiments are provided, including a specialized light bulb that is in wireless communication with an alarm clock application on a cellular telephone and a coupling device designed to open and close the electrical circuit providing power to a conventional light bulb when activated by a cell phone alarm clock. | 2011-10-06 |
20110242946 | Stepping motor control circuit and analog electronic timepiece - It is configured to include: a secondary battery as a power supply that supplies power at least to a stepping motor; a rotation detection portion that detects a rotation state of the stepping motor; a control portion that drives the stepping motor by selecting a drive pulse having energy corresponding to the rotation state of the stepping motor from a plurality of drive pulses; and a solar battery that charges the secondary battery. Upon determination that it is possible to rotate the stepping motor by an overcharge indicating drive pulse having predetermined energy, the control portion drives the stepping motor by changing a current drive pulse to an overconsuming drive pulse having larger energy than the overcharge indicating drive pulse. It thus becomes possible to suppress deterioration of a secondary battery caused by overcharge without having to provide a dedicated voltage detection circuit, such as a comparator circuit. | 2011-10-06 |