40th week of 2017 patent applcation highlights part 73 |
Patent application number | Title | Published |
20170287831 | LOCALIZED HIGH DENSITY SUBSTRATE ROUTING - Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough. | 2017-10-05 |
20170287832 | SEMICONDUCTOR PACKAGE DEVICES INTEGRATED WITH INDUCTOR - The present disclosure provides an inductor structure. The inductor structure, comprising a first surface, a second surface intersecting with the first surface, a first conductive pattern and a second conductive pattern. The first conductive pattern is formed on the first surface. The second conductive pattern is formed on the second surface. The first conductive pattern is connected with the second conductive pattern. | 2017-10-05 |
20170287833 | THREE DIMENSIONAL STORAGE CELL ARRAY WITH HIGHLY DENSE AND SCALABLE WORD LINE DESIGN APPROACH - An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure. | 2017-10-05 |
20170287834 | Contact Expose Etch Stop - The present disclosure relates to semiconductor devices and the teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET). Some embodiments may include a power MOSFET with transistor cells, each cell comprising a source and a drain region; a first dielectric layer disposed atop the transistor cells; a silicon rich oxide layer on the first dielectric layer; grooves through the multi-layered dielectric, each groove above a respective source or drain region and filled with a conductive material; a second dielectric layer atop the multi-layered dielectric; openings in the second dielectric layer, each opening exposing a contact area of one of the plurality of grooves; and a metal layer disposed atop the second dielectric layer and filling the openings. The metal layer may form at least one drain metal wire and at least one source metal wire. The at least one drain metal wire may connect two drain regions through respective grooves. The at least one source metal wire may connect two source regions through respective grooves. Each groove has a length extending from the at least one drain metal wire to the at least one source metal wire in an adjacent pair. | 2017-10-05 |
20170287835 | Combined Source And Base Contact For A Field Effect Transistor - The present disclosure relates to semiconductor devices. The teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET) and methods for their manufacture. Some embodiments may include: depositing a base within an epitaxial layer; implanting a source implant extending into the base, wherein the epitaxial layer, the base, and the source implant form a continuous plane surface; depositing an insulating layer on the continuous plane surface forming a gate in contact with both the epitaxial layer and the base; opening a contact groove through the insulating layer to expose a central portion of the source implant; depositing a layer of photoresist on top of the insulating layer above exposed portions of the source implant; patterning a set of stripes in the photoresist, each stripe perpendicular to the contact groove; etching the set of stripes with an etch chemistry selective to the insulating layer; and filling the contact groove with a conductive material creating a base-source contact groove reaching through the insulating layer to the surface of the source implant and comprising a plurality of sections spaced apart from each other reaching through the source implant into the base. | 2017-10-05 |
20170287836 | NON-SYMMETRIC BODY CONTACTS FOR FIELD-EFFECT TRANSISTORS - Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. For example, body contacts can be implemented between S/G/D assemblies rather than on the ends of such assemblies. This can advantageously improve body contact influence on the S/G/D assemblies while maintaining a targeted size for the FET device. | 2017-10-05 |
20170287837 | DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD - A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer. | 2017-10-05 |
20170287838 | ELECTRICAL INTERCONNECT BRIDGE - Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers. | 2017-10-05 |
20170287839 | FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME - A fan-out semiconductor package includes a redistribution layer, the redistribution layer including a first insulating layer, a first wiring disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first wiring, a line via passing through the second insulating layer continuously and connected to the first wiring, and a second wiring disposed on the second insulating layer and connected to the line via; a semiconductor chip disposed on one side of the redistribution layer, and having an electrode pad electrically connected to the first wiring, the second wiring, and the line via; and an encapsulant disposed on the one side of the redistribution layer, and encapsulating the semiconductor chip. | 2017-10-05 |
20170287840 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced. | 2017-10-05 |
20170287841 | THROUGH VIA STRUCTURE FOR STEP COVERAGE IMPROVEMENT - A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole. | 2017-10-05 |
20170287842 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer. | 2017-10-05 |
20170287843 | SEMICONDUCTOR DEVICE HAVING CONTACT PLUGS WITH DIFFERENT INTERFACIAL LAYERS - According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a first region and a second region; a first contact plug on the first region, and a second contact plug on the second region. Preferably, the first contact plug includes a first interfacial layer having a first conductive type and a first work function metal layer having the first conductive type on the first interfacial layer, and the second contact plug includes a second interfacial layer having a second conductive type and a second work function metal layer having the second conductive type on the second interfacial layer. | 2017-10-05 |
20170287844 | 3D INTEGRATED CIRCUIT DEVICE - A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the second transistor is overlaying the first transistor, where the first transistor controls the supply of a ground or a power signal to the third transistor, and where the first transistor, the second transistor and the third transistor are aligned to each other with less than 100 nm misalignment. | 2017-10-05 |
20170287845 | Alignment Mark Design for Packages - A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. | 2017-10-05 |
20170287846 | SYSTEMS AND METHODS FOR ELECTROMAGNETIC INTERFERENCE SHIELDING - Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material. | 2017-10-05 |
20170287847 | INTEGRATED CIRCUIT PACKAGE HAVING INTEGRATED EMI SHIELD - Apparatus and methods are provided for an integrated circuit package that includes an integrated EMI shield. In an example, an integrated circuit package can include an integrated circuit mounted to a substrate via connections on the bottom surface of the integrated circuit, a conductive fence surrounding side surfaces of the integrated circuit, a conductive film coupled to the conductive fence, the film located above a top surface of the integrated circuit and coextensive with a footprint defined by the conductive fence. | 2017-10-05 |
20170287848 | ELECTRONIC CIRCUIT PACKAGE USING COMPOSITE MAGNETIC SEALING MATERIAL - Disclosed herein is an electronic circuit package includes a substrate, an electronic component mounted on a surface of the substrate, and a magnetic mold resin covering the surface of the substrate so as to embed therein the electronic component. The magnetic mold resin includes a resin material and a filler blended in the resin material in a blended ratio of 30 vol. % or more to 85 vol. % or less. The filler includes a magnetic filler containing Fe and 32 wt. % or more and 39 wt. % or less of a metal material contained mainly of Ni, thereby a thermal expansion coefficient of the magnetic mold resin is 15 ppm/° C. or less. | 2017-10-05 |
20170287849 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes: providing, on a substrate, a first magnetic substrate including a base, a first side wall portion and a second side wall portion at opposed ends of the base, the sidewall portions extending from the base, providing a semiconductor chip over the base at a location between the first side wall portion and the second side wall portion, providing a plate-like magnetic substrate having a second surface, the second surface provided with a resin thereon, and positioning the plate-like magnetic substrate having a second surface with the resin thereon such that the second surface faces the base of the first magnetic substrate. Then the plate like magnetic substrate is moved in the direction of the first magnetic substrate to contact the second surface of the plate like magnetic substrate with the first side wall portion and the second side wall portion. | 2017-10-05 |
20170287850 | Stacked Die Ground Shield - The present disclosure relates to semiconductor devices. Embodiments of the teachings thereof may include processes for manufacturing of semiconductor devices and the devices themselves. For example, some embodiments may include an integrated circuit package comprising: a lead frame; a first die mounted on the lead frame in flip-chip fashion, with a frontside of the first die connected to the lead frame; wherein the first die comprises an oxide layer deposited on a backside of the first die and a back metal layer deposited on the oxide layer; and a second die mounted on the back metal layer of the first die. | 2017-10-05 |
20170287851 | SEMICONDUCTOR PACKAGE HAVING AN EMI SHIELDING LAYER - Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation. | 2017-10-05 |
20170287852 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a first substrate including a first ground conductor disposed on at least a second surface of a first surface and the second surface; a plurality of electronic elements mounted on the first surface and the second surface of the first substrate; a second substrate adhered to the second surface of the first substrate and including a penetration part formed to accommodate the plurality of electronic elements mounted on the second surface of the first substrate and a second ground conductor connected to the first ground conductor; a molded portion encapsulating the plurality of electronic elements mounted on the first surface of the first substrate; and a shielding layer formed on outer surfaces of the molded portion and the first substrate and at least a portion of a side surface of the second substrate to shield electromagnetic waves. | 2017-10-05 |
20170287853 | FAN-OUT SEMICONDUCTOR PACKAGE - The fan-out semiconductor package includes: a semiconductor chip having an active surface having a connection pad disposed thereon and an inactive surface disposed to oppose the active surface; a first capacitor disposed adjacently to the semiconductor chip; an encapsulant at least partially encapsulating the first connection member and the semiconductor chip; a first connection member disposed on the encapsulant, the first capacitor, and the semiconductor chip, and a second capacitor disposed on the other surface of the first connection member opposing one surface of the first connection member on which the semiconductor chip is disposed, wherein the first connection member includes a redistribution layer electrically connected to the connection pad of the semiconductor chip, the first capacitor, and the second capacitor, and the first capacitor and the second capacitor are electrically connected to the connection pad through a common power wiring of the redistribution layer. | 2017-10-05 |
20170287854 | TUNABLE ACTIVE SILICON FOR COUPLER LINEARITY IMPROVEMENT AND RECONFIGURATION - An electromagnetic coupler assembly includes a handle wafer having an oxide layer disposed on a first surface thereof. A layer of active semiconductor is disposed on the oxide layer and includes a voltage terminal to receive a supply voltage. A layer of dielectric material is disposed on the layer of active semiconductor. A main transmission line is disposed on the layer of dielectric material. A coupled transmission line is disposed on the layer of active semiconductor and is one of inductively coupled to the main transmission line and capacitively coupled to the main transmission line. At least a portion of one of the main transmission line and the coupled transmission line is disposed directly above at least a portion of the layer of active semiconductor. | 2017-10-05 |
20170287855 | VARIABLE HANDLE WAFER RESISTIVITY FOR SILICON-ON-INSULATOR DEVICES - Variable handle wafer resistivity for silicon-on-insulator devices. In some embodiments, a radio-frequency device can include a silicon-on-insulator substrate having an insulator layer and a handle wafer. The radio-frequency device can further include a plurality of field-effect transistors implemented over the insulator layer to cover a corresponding portion of the handle wafer having a non-uniform distribution of resistivity values. | 2017-10-05 |
20170287856 | ELECTRONIC COMPONENT PACKAGE - An electronic component package includes: a frame, including a through-hole and a through-wiring; an electronic component disposed in the through-hole of the frame; a metal plate disposed on a first side of the electronic component and the frame; and a redistribution layer disposed on a second side of the electronic component opposing the first side and electrically connected to the electronic component. | 2017-10-05 |
20170287857 | UNDER-BUMP METAL STRUCTURES FOR INTERCONNECTING SEMICONDUCTOR DIES OR PACKAGES AND ASSOCIATED SYSTEMS AND METHODS - The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die. | 2017-10-05 |
20170287858 | SEMICONDUCTOR DEVICE WITH MODIFIED PAD SPACING STRUCTURE - A semiconductor device is provided, including a substrate, an interconnection structure formed on the substrate, a first top conductive layer formed on the interconnection structure, bars formed on the interconnection structure, and a second top conductive layer formed above the first top conductive layer. The first top conductive layer includes several first conducting portions spaced apart from each other, and at least one of the bars is positioned between adjacent two of the first conducting portions. | 2017-10-05 |
20170287859 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a semiconductor substrate having an insulating film in which an opening that exposes each of a plurality of electrode pads is formed is provided, and a flux member including conductive particles is arranged over each of the electrode pads. Thereafter, a solder ball is arranged over each of the electrode pads via the flux member, and is then heated via the flux member so that the solder ball is bonded to each of the electrode pads. The width of the opening of the insulating film is smaller than the width (diameter) of the solder ball. | 2017-10-05 |
20170287860 | SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES - An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process. | 2017-10-05 |
20170287861 | Cu PILLAR CYLINDRICAL PREFORM FOR SEMICONDUCTOR CONNECTION - A material for Cu pillars is formed as cylindrical preforms in advance and connecting these cylindrical preforms to electrodes on a semiconductor chip to form Cu pillars. Due to this, it becomes possible to make the height/diameter ratio of the Cu pillars 2.0 or more. Since electroplating is not used, the time required for production of the Cu pillars is short and the productivity can be improved. Further, the height of the Cu pillars can be raised to 200 μm or more, so these are also preferable for moldunderfill. The components can be freely adjusted, so it is possible to easily design the alloy components to obtain highly reliable Cu pillars. | 2017-10-05 |
20170287862 | Cu Column, Cu Core Column, Solder Joint, and Through-Silicon Via - Provided are a Cu column, a Cu core column, a solder joint, and a through-silicon via, which have the low Vickers hardness and the small arithmetic mean roughness. For the Cu column 1 according to the present invention, its purity is equal to or higher than 99.9% and equal to or lower than 99.995%, its arithmetic mean roughness is equal to or less than 0.3 μm, and its Vickers hardness is equal to or higher than 20 HV and equal to or less than 60 HV. Since the Cu column 1 is not melted at a melting temperature in the soldering and a definite stand-off height (a space between the substrates) can be maintained, it is preferably applied to the three dimensional mounting or the pitch narrowing mounting. | 2017-10-05 |
20170287863 | SEMICONDUCTOR DIE, SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THE SAME - A semiconductor die includes a semiconductor body, an insulating layer, a conductive circuit layer and at least one conductive bump. The semiconductor body has a first surface, a second surface and a side surface extending between the first surface and the second surface. The insulating layer is disposed on the first surface and the side surface of the semiconductor body. The insulating layer includes a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later. The insulating layer includes a step structure. The conductive circuit layer is electrically connected to the first surface of the semiconductor body, the conductive circuit layer includes at least one pad, and the conductive bump is electrically connected to the pad. | 2017-10-05 |
20170287864 | BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING - A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads. | 2017-10-05 |
20170287865 | PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME - Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface. | 2017-10-05 |
20170287866 | INTERLAYER FILLER COMPOSITION FOR SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - To provide an interlayer filler composition capable of forming a cured adhesive layer sufficiently cured and excellent in adhesion without letting voids be formed in the cured adhesive layer while minimizing leak out of a filler. An interlayer filler composition for a semiconductor device, comprises an epoxy resin (A), a curing agent (B), a filler (C) and a flux (D), has a minimum value of its viscosity at from 100 to 150° C. and satisfies the following formulae (1) and (2) simultaneously: | 2017-10-05 |
20170287867 | ANISOTROPIC CONDUCTIVE FILM INCLUDING A REFLECTIVE LAYER - An anisotropic conductive film (ACF) is disclosed. In one approach, the ACF includes a non-reflective adhesive layer including a top surface, a plurality of conductive particles included with the non-reflective adhesive layer, and a reflective adhesive layer disposed along the top surface of the non-reflective adhesive layer. | 2017-10-05 |
20170287868 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring. | 2017-10-05 |
20170287869 | WIRE CONNECTING METHOD AND TERMINAL - A method of connecting a wire with a terminal including a plurality of conductors is provided. The method includes: positioning the terminal by holding a part of the terminal between an upper side jig and a lower side jig; and connecting the wire and one of a plurality of conductors, which is exposed on a surface of the positioned terminal. The terminal includes a laminate structure that includes an insulator interposed between a first conductor and a second conductor. The part of the terminal held in the positioning of the terminal includes a pressure receiving area, where a contact area between the upper side jig and an upper surface of the terminal and a contact area between the lower side jig and a lower surface of the terminal overlap. The laminate structure exists outside of the pressure receiving area, and does not exist in the pressure receiving area. | 2017-10-05 |
20170287870 | STACKED CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A stacked chip package structure includes a first chip, stud bumps, a second chip, pillar bumps, an encapsulant and conductive vias. The first stud bumps are respectively disposed on a plurality of first pads of the first chip, wherein each first stud bump includes a rough surface, and the rough surface of each first stud bump is rougher than a top surface of each first pad. The second chip is disposed on the first chip and exposes the first pads. The pillar bumps are respectively disposed on a plurality of second pads of the second chips. The encapsulant encapsulates the first chip and the second chip and exposes a top surface of each second stud bump. The first conductive vias penetrate the encapsulant and connect the first stud bumps. Each first conductive via covers the rough surface of each first stud bump. | 2017-10-05 |
20170287871 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package structure includes a conductive structure, a semiconductor element disposed on and electrically connected to the conductive structure, a supporting structure, an encapsulant, and a metal layer. The supporting structure is disposed on the conductive structure and surrounds the semiconductor element. The encapsulant covers the semiconductor element. The metal layer is disposed on or embedded in the encapsulant. | 2017-10-05 |
20170287872 | BUMPLESS WAFER LEVEL FAN-OUT PACKAGE - An integrated circuit package may include a first conductive pad on an interposer substrate, and a second conductive pad formed on a front surface of an integrated circuit die. The second conductive pad may directly contact the first conductive pad on the interposer substrate. The integrated circuit package may further include a package substrate having a cavity, in which the interposer substrate and the integrated circuit are disposed in the cavity. The interposer substrate may include interconnect pathways that are electrically coupled to the first and second conductive pads. A heat spreader may subsequently form over the integrated circuit die and the package substrate. | 2017-10-05 |
20170287873 | ELECTRONIC ASSEMBLY COMPONENTS WITH CORNER ADHESIVE FOR WARPAGE REDUCTION DURING THERMAL PROCESSING - An IC package, an electronic assembly, and methods of preventing warpage of components of an electronic assembly during fabrication of the electronic assembly are shown. An IC package including an adhesive disposed at or near at least one of four corners of a die of the IC package is shown. An electronic assembly including an IC package that includes an adhesive disposed at or near at least one of four corners of a second surface of a first substrate is shown. Methods of preventing warpage of components of an electronic assembly during fabrication of the electronic assembly that include applying an adhesive to at least one of four corners of a first surface of a first component are shown. | 2017-10-05 |
20170287874 | STACKED CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer. | 2017-10-05 |
20170287875 | THREE DIMENSIONAL FULLY MOLDED POWER ELECTRONICS MODULE HAVING A PLURALITY OF SPACERS FOR HIGH POWER APPLICATIONS - A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the substrates, and at least three spacers. The spacers control a height variation of the power electronic package and protect the chips and other electronics from experiencing excessive stress. The height of the spacers is determined based on a height of the chips, on a height of solder blocks that connect the chips to the top substrate, and on a height of solder blocks that connect the chips to the bottom substrate. | 2017-10-05 |
20170287876 | METHOD AND DEVICE FOR CONTROLLING OPERATION USING TEMPERATURE DEVIATION IN MULTI-CHIP PACKAGE - A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m2017-10-05 | |
20170287877 | SEMICONDUCTOR PACKAGE ASSEMBLY - In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die, a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure, and a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die. | 2017-10-05 |
20170287878 | HYBRID BOND PAD STRUCTURE - In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between integrated chip die at a location laterally offset from a bond pad. The integrated chip structure has a first die and a second die. The first die has a first plurality of interconnect layers arranged within a first dielectric structure disposed on a first substrate. The second die has a second plurality of interconnect layers arranged within a second dielectric structure disposed between the first dielectric structure and a second substrate. A bond pad is disposed within a recess extending through the second substrate. A redistribution structure electrically couples the first die to the second die at a position that is laterally offset from the bond pad. | 2017-10-05 |
20170287879 | THIN STACK PACKAGES - The stack package includes a substrate body layer having a top surface and a bottom surface, first circuit patterns disposed on the bottom surface of the substrate body layer, second circuit patterns disposed on the top surface of the substrate body layer, a first semiconductor chip including first bumps, and a second semiconductor chip including second bumps. The first bumps extend through the substrate body layer to be electrically coupled to the first circuit patterns, and the second bumps extend past sidewalls of the first semiconductor chip to be electrically coupled to the second circuit patterns. The second semiconductor chip is stacked on the first semiconductor chip. | 2017-10-05 |
20170287880 | Electronic Device Package Having a Dielectric Layer and an Encapsulant - A method for fabricating an electronic device package includes providing a carrier, disposing a semiconductor chip onto the carrier, the semiconductor chip having a contact pad on a main face thereof remote from the carrier, applying a contact element onto the contact pad, applying a dielectric layer on the carrier, the semiconductor chip, and the contact element, and applying an encapsulant onto the dielectric layer. | 2017-10-05 |
20170287881 | SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF - A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a substrate and multiple semiconductor chips disposed thereon. The semiconductor chips are arranged to form multiple sequentially nested circle(s), and a circumference of each of which is arranged with multiple the semiconductor chips. The numbers of the semiconductor chips arranged on the respective circumferences of the sequentially nested circle(s) from inside to outside are gradually increased, and distances among the circumferences are gradually decreased from inside to outside. The disclosure optimizes the arrangement of the semiconductor chips to make the arrangement of the semiconductor chips be loose in the central region while more dense towards outside, which is in favor of uniform heat distribution and therefore can slow down aging and failure of the semiconductor chips and improve heat dissipation performance and light emitting effect of product. | 2017-10-05 |
20170287882 | Micro-Transfer Printed LED and Color Filter Structure - A micro-transfer printed intermediate structure comprises an intermediate substrate and one or more pixel structures disposed on the intermediate substrate. Each pixel structure includes an LED, a color filter, and a fractured pixel tether physically attached to the pixel structure. A fractured intermediate tether is physically attached to the intermediate substrate. A method of making an intermediate structure source wafer comprises providing a source wafer having a patterned sacrificial layer including sacrificial portions separated by anchors, disposing an intermediate substrate over the patterned sacrificial layer, and disposing one or more pixel structures on the intermediate substrate entirely on or over each sacrificial portion. Each pixel structure includes an LED, a color filter, and a fractured pixel tether physically attached to the pixel structure to form an intermediate structure. | 2017-10-05 |
20170287883 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a light-emitting device includes steps of: preparing at least one substrate having a plurality of through holes; providing an electric wire on a rear surface side of the substrate so that a plurality of portions of the electric wire communicates with a front surface side of the substrate at the plurality of through holes of the substrate; and respectively mounting a plurality of light-emitting diodes to the respective portions of the electric wire that communicate with the front surface side of the substrate. | 2017-10-05 |
20170287884 | LED LIGHTING APPARATUS - An LED lighting apparatus includes an LED substrate, a LED chip, a sealing resin member, and a reflecting face. The LED substrate has a main surface. The LED chip is mounted on the main surface of the LED substrate. The sealing resin member is made of a material that transmits light from the LED chip. The sealing resin member covers the LED chip. The sealing resin member has a shape bulging in the direction in which the main surface faces. The reflecting face surrounds the sealing resin member. | 2017-10-05 |
20170287885 | IMPROVED SUBSTRATE FOR SYSTEM IN PACKAGE (SIP) DEVICES - Methods, systems, and devices for enabling the use of a special, generic, or standard substrate for similar system SIP assemblies are disclosed. The required customization, which is defined by a system's interconnecting scheme, is done during package assembly by creating appropriate connections using wire bonds on pads that are placed on the substrate and intentionally left open for purpose of customization. The wire bond links can be changed as required for a given system design. | 2017-10-05 |
20170287886 | WAFER LEVEL PROXIMITY SENSOR - Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor and can be manufactured using a shorter fabrication process at a lower cost. The proximity sensors are coupled to external components by a signal path that includes the through-silicon vias and a ball grid array formed on a lower surface of the silicon substrate. The design of the wafer level proximity sensor passes more light from the light emitter and more light to the light sensor. | 2017-10-05 |
20170287887 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display apparatus including a first substrate including a plurality of light emitting diodes regularly disposed thereon, a second substrate including a thin-film transistor (TFT) panel part including a plurality of TFTs configured to drive the light emitting diodes, and a third substrate including a light converter configured to convert light emitted from the first substrate, in which the first substrate and the second substrate are coupled to face each other, the light emitting diodes are electrically connected to the TFTs, respectively, the first substrate and the third substrate are coupled to face each other, and light emitted from the light emitting diodes is converted into at least one of blue light, green light, and red light through the light converter. | 2017-10-05 |
20170287888 | LIGHTING APPARATUSES AND LED MODULES FOR BOTH ILLUMINATION AND OPTICAL COMMUNICATION - An LED module has a controller with a modulator and illumination driver, and first and second LED chains. The first LED chain is connected to the modulator, has a first group of LED cells, and emits a first light under a pulse mode current input from the modulator. The first light has a digital data over a signal carrier. The second LED chain is connected to the illumination driver, has a second group of LED cells, and emits a second light under a constant current input from the illumination driver. There are fewer LED cells in the first group than the second group. The illumination driver is independent from the modulator in controlling emission of the first light. Alternatively, the LED module has a controller, an LED chain connected to the modulator, a first group of LED cells, and a second group of LED cells directly connected to the first group of LED cells. The first group of LED cells operates under a pulse mode current input from the modulator and emits a first light having a digital data over a signal carrier. The second group of LED cells emits a second light under a constant current input from the illumination driver. | 2017-10-05 |
20170287889 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps. | 2017-10-05 |
20170287890 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor device package is provided. The semiconductor device package includes a first substrate and a conductive element fared on the first substrate. The conductive element has a recess away from the first substrate, and the recess has a first depth greater than a second depth from a top surface of the conductive element to a center of the conductive element semiconductor device package includes a conductive connector bonded to the conductive element, and a melting point of the conductive element is higher than a melting point of the conductive connector, and the conductive connector is filled into the recess of the conductive element. | 2017-10-05 |
20170287891 | Schottky-CMOS Asynchronous Logic Cells - Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors. | 2017-10-05 |
20170287892 | POWER COMPONENT PROTECTED AGAINST OVERHEATING - A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization. | 2017-10-05 |
20170287893 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE HAVING AN ADJUSTABLE TRIGGERING THRESHOLD - An electrostatic discharge protection device includes first and second diodes series-connected between first and second connection terminals. A third connection terminal is coupled to a junction of the first and second diodes. A capacitor is connected in parallel with the first and second diodes between the first and second terminals. | 2017-10-05 |
20170287894 | DEVICES WITH AN EMBEDDED ZENER DIODE - In one aspect, a silicon-controlled rectifier (SCR) includes a Zener diode embedded in the SCR. In another aspect, a laterally diffused metal oxide semiconductor (LDMOS) includes a Zener diode embedded in the LDMOS. In a further aspect, a lateral insulated-gate bipolar transistor (IGBT) includes a Zener diode embedded in the IGBT. | 2017-10-05 |
20170287895 | ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND APPLICATIONS THEREOF - An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region and a fourth doping region. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in the semiconductor substrate. The first doping region having the second conductivity is disposed in the first well. The second doping region having the first conductivity is at least partially disposed in the first well and surrounds the first doping region. The third doping region and the fourth doping region respectively having the first conductivity and the second conductivity are disposed in the second well. The first doping region, the third doping region, the first well and the second well are integrated to form a first parasitic BJT and a second parasitic BJT that have different majority carriers. | 2017-10-05 |
20170287896 | BIPOLAR SCR - A high-voltage bipolar semiconductor controlled rectifier (SCR) includes an emitter region having a first polarity and overlying a base region having a second polarity different from the first polarity; a collector region having the first polarity and lying under the base region; an anode region having the second polarity; a first sinker region having the first polarity and contacting the collector region, wherein the anode region is between the first sinker region and the base region; and a second sinker region having the first polarity and contacting the collector region, the second sinker region lying between the anode region and the base region, wherein an extension of the anode region extends under a portion of the second sinker region. | 2017-10-05 |
20170287897 | HIGH VOLTAGE ESD DEVICE FOR FINFET TECHNOLOGY - An ESD protection device includes a semiconductor substrate, first and second fins, first and second doped regions adjacent to each other and having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin. The second doped region includes a second portion of the substrate and a second region of the first fin. The device also includes a first gate structure on a portion of first and second regions of the first fin, a first highly doped region in the first region of the first fin and having a same conductivity type as the first doped region, and a dopant concentration higher than the first doped region, and a second highly doped region in the second fin and having a same conductivity type as the second doped region, and a dopant concentration higher than the second doped region. | 2017-10-05 |
20170287898 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration. | 2017-10-05 |
20170287899 | ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND APPLICATIONS THEREOF - An ESD protection apparatus includes a semiconductor substrate, a first gate structure, a first doping region, a second doping region and a third doping region. The semiconductor substrate has a doping well with a first conductivity one end of which is grounded. The first gate structure is disposed on the doping well. The first doping region having a second conductivity, is disposed in the doping well and adjacent to the first gate structure, and is electrically connected to a pad. The second doping region having the second conductivity is disposed in the doping well and adjacent to the first gate structure. The third doping region having the first conductivity is disposed in the doping well and forms a P/N junction interface with the second doping region, wherein the second doping region and the third doping region respectively have a doping concentration substantially greater than that of the doping well. | 2017-10-05 |
20170287900 | CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE - A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming fin trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the fin trenches to form a dummy layer liner; forming a vertical fin in the fin trenches with the dummy layer liner; forming diode trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the diode trenches to form a dummy layer liner; forming a first semiconductor segment in a lower portion of the diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction. | 2017-10-05 |
20170287901 | SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR INCLUDING A GATE ELECTRODE REGION PROVIDED IN A SUBSTRATE AND METHOD FOR THE FORMATION THEREOF - A semiconductor structure includes a bulk semiconductor substrate, an electrically insulating layer over the substrate, an active layer of semiconductor material over the electrically insulating layer and a transistor. The transistor includes an active region, a gate electrode region and an isolation junction region. The active region is provided in the active layer of semiconductor material and includes a source region, a channel region and a drain region. The gate electrode region is provided in the bulk semiconductor substrate and has a first type of doping. The isolation junction region is formed in the bulk semiconductor substrate and has a second type of doping opposite the first type of doping. The isolation junction region separates the gate electrode region from a portion of the bulk semiconductor substrate other than the gate electrode region that has the first type of doping. | 2017-10-05 |
20170287902 | CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE - A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming fin trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the fin trenches to form a dummy layer liner; forming a vertical fin in the fin trenches with the dummy layer liner; forming diode trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the diode trenches to form a dummy layer liner; forming a first semiconductor segment in a lower portion of the diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction. | 2017-10-05 |
20170287903 | VARIABLE SNUBBER FOR MOSFET APPLICATION - Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events. | 2017-10-05 |
20170287904 | CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE - A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming fin trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the fin trenches to form a dummy layer liner; forming a vertical fin in the fin trenches with the dummy layer liner; forming diode trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the diode trenches to form a dummy layer liner; forming a first semiconductor segment in a lower portion of the diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction. | 2017-10-05 |
20170287905 | MONOLITHIC THREE-DIMENSIONAL (3D) ICs WITH LOCAL INTER-LEVEL INTERCONNECTS - Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected. | 2017-10-05 |
20170287906 | 3D CROSS-POINT MEMORY MANUFACTURING PROCESS HAVING LIMITED LITHOGRAPHY STEPS - The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers. | 2017-10-05 |
20170287907 | 3D CROSS-POINT MEMORY MANUFACTURING PROCESS HAVING LIMITED LITHOGRAPHY STEPS - The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers. | 2017-10-05 |
20170287908 | METHOD FOR FORMING DEEP TRENCH ISOLATION FOR RF DEVICES ON SOI - A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors. | 2017-10-05 |
20170287909 | LAYOUT METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines. | 2017-10-05 |
20170287910 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an isolation layer, first and second fin structures, a gate structure and a source/drain structure. The isolation layer is disposed over a substrate. The first and second fin structures are disposed over the substrate, and extend in a first direction in plan view. Upper portions of the first and second fin structures are exposed from the isolation layer. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The source/drain structure is formed on the upper portions of the first and second fin structures, which are not covered by the first gate structure and exposed from the isolation layer, and wraps side surfaces and a top surface of each of the exposed first and second fin structures. A void is formed between the source/drain structure and the isolation layer. | 2017-10-05 |
20170287911 | MULTI-FINGER DEVICES IN MUTLIPLE-GATE-CONTACTED-PITCH, INTEGRATED STRUCTURES - The present disclosure generally relates to semiconductor structures and, more particularly, to multi-finger devices in multiple-gate-contacted-pitch, integrated structures and methods of manufacture. The structure includes: a first plurality of fin structures formed on a substrate having a channel surface in a {110} plane; and a second plurality of fin structures formed on the substrate with a channel surface in a {100} plane, positioned in relation to the first plurality of fin structures. | 2017-10-05 |
20170287912 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation region defined by an element isolation insulating film, and a substrate contact portion. The substrate contact portion is formed in a region of a semiconductor substrate that is positioned between the high voltage NMOS transistor formation region and the element isolation insulating film so as to reach from the main surface side to a position deeper than the bottom of the element isolation insulating film. The substrate contact portion is in contact with the semiconductor substrate from a depth over a depth. | 2017-10-05 |
20170287913 | SEMICONDUCTOR DEVICE WITH METAL GATE - A semiconductor device including a first gate structure is disposed on the semiconductor substrate. The first gate structure includes a gate dielectric layer, a layer, a first work function metal, a second work function metal, and a fill metal. A second gate structure is also disposed on the semiconductor substrate. The second gate structure includes the gate dielectric layer, a second work function metal, and the fill metal. In an embodiment, the second gate structure also includes an etch stop layer. | 2017-10-05 |
20170287914 | Method and Apparatus for Forming Boron-Doped Silicon Germanium Film, and Storage Medium - A method for forming a boron-doped silicon germanium film on a base film in a surface of an object to be processed includes: forming a seed layer by adsorbing a chlorine-free boron-containing gas to a surface of the base film; and forming a boron-doped silicon germanium film on the surface of the base film to which the seed layer is adsorbed by using a silicon raw material gas, a germanium raw material gas, and a boron doping gas through a chemical vapor deposition method. | 2017-10-05 |
20170287915 | METHOD OF MANUFACTURING CAPACITOR STRUCTURE - A method of manufacturing a semiconductor device includes forming a source/drain region in a substrate. An interlevel dielectric layer is formed on the substrate. A conducting plug is formed in the interlevel dielectric layer. The conducting plug is electrically coupled to the source/drain region. A crown oxide is formed on the interlevel dielectric layer. A deep trench is formed in the crown oxide to expose a top wall and a sidewall of the conducting plug. A spacer is formed on the sidewall of the conducting plug. A metal-insulator-metal film is formed in the deep trench. | 2017-10-05 |
20170287916 | SEMICONDUCTOR DEVICE - To effectively prevent short circuit between capacitors adjacent to each other. A semiconductor device has a substrate, an interlayer insulating film, a plurality of capacitors, and an isolation insulating film. The interlayer insulating film is located over the substrate. The capacitors are located in a plurality of recesses, respectively. The recesses each have an opening in the surface of the interlayer insulating film. The isolation insulating film lies in the interlayer insulating film. The isolation insulating films are located between recesses adjacent to each other in plan view. Further, the isolation insulating film is made of a material different from that of the interlayer insulating film. | 2017-10-05 |
20170287917 | EMBEDDED MEMORY WITH ENHANCED CHANNEL STOP IMPLANTS - An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants are blocked from the logic MOS transistors. | 2017-10-05 |
20170287918 | STATIC RANDOM ACCESS MEMORY (SRAM) DEVICE - To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed. | 2017-10-05 |
20170287919 | SINGLE EVENT UPSET (SEU) MITIGATION FOR FINFET TECHNOLOGY USING FIN TOPOLOGY - Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (H | 2017-10-05 |
20170287920 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME - A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of a capacitor are prevented from being abnormally oxidized. A capacitor is formed by layering a lower electrode, a dielectric film including a ferroelectric substance or a high dielectric substance, and an upper electrode in this order on top of an interlayer insulation film with at least a conductive oxygen barrier film in between, and at least a portion of a side of the conductive oxygen barrier film is covered with an oxygen entering portion or an insulating oxygen barrier film. | 2017-10-05 |
20170287921 | METHOD OF IMPROVING LOCALIZED WAFER SHAPE CHANGES - A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a <100> lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved. | 2017-10-05 |
20170287922 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor memory device. The method includes providing a substrate and forming a stacked layer on the substrate, where the stacked layer includes a tunneling dielectric layer and a floating gate layer sequentially formed on the substrate. The method also includes forming a plurality of stacked structures by etching the stacked layer and the substrate, where the spacing between the adjacent stacked structures forms a plurality of parallel first trenches. In addition, the method includes forming a plurality of second trenches and forming a plurality of third trenches. Moreover, the method includes forming a second dielectric layer on the floating gate layer and the side wall and bottom of the third trenches and forming a control gate layer on the second dielectric layer. Further, the method includes forming a plurality of fourth trenches and removing the sacrificial layer along the fourth trenches. | 2017-10-05 |
20170287923 | Method and system for object reconstruction - pattern. A processor reconstructs a three-dimensional (3D) map of the object responsively to a shift of the pattern in the image data relative to a reference image of the pattern. | 2017-10-05 |
20170287924 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A fin includes a first region and a second region arranged on a positive side in an X-axis direction with respect to the first region. A control gate electrode covers an upper surface of the first region, and a side surface of the first region on the positive side in a Y-axis direction. A memory gate electrode covers an upper surface of the second region, and a side surface of the second region on the positive side in the Y-axis direction. The upper surface of the second region is lower than the upper surface of the first region. The side surface of the second region is arranged on the negative side in the Y-axis direction with respect to the side surface of the first region in the Y-axis direction. | 2017-10-05 |
20170287925 | COBALT-CONTAINING CONDUCTIVE LAYERS FOR CONTROL GATE ELECTRODES IN A MEMORY STRUCTURE - A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt. | 2017-10-05 |
20170287926 | MULTILEVEL MEMORY STACK STRUCTURE EMPLOYING STACKS OF A SUPPORT PEDESTAL STRUCTURE AND A SUPPORT PILLAR STRUCTURE - Memory-opening semiconductor material portions and support opening fill structures can be simultaneously formed through a first alternating stack of first insulating layers and first sacrificial material layers. Dopant species that retard or prevent etching of the material of the support opening fill structures can be implanted into an upper portion of each support opening fill structure, while memory-opening semiconductor material portions are masked from implantation. After formation of a second alternating stack and second openings therethrough, the sacrificial material of the memory-opening semiconductor material portions is removed while the support opening fill structures is not removed. Damage to the first sacrificial material layers during formation of the staircase contact region and resulting leakage paths from word lines to the substrate through support pillar structures can be avoided or reduced by not removing the support opening fill structures. | 2017-10-05 |
20170287927 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE INCLUDING BARRIER PATTERN - The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns. | 2017-10-05 |
20170287928 | SEMICONDUCTOR MEMORY DEVICES - Semiconductor devices are provided. Semiconductor devices may include a stack structure including word lines stacked on a substrate, first vertical pillars and second vertical pillars that extend through the stack structure, a first string select line overlapping the first vertical pillars in a plan view, and a second string select line overlapping the second vertical pillars in the plan view and being spaced apart from the first string select line in a first direction. In a plan view, a shortest distance between a side of one of the first vertical pillars and a side of one of the second vertical pillars is less than a shortest distance between a side of the first string select line and a side of the second string select line. | 2017-10-05 |
20170287929 | SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness. | 2017-10-05 |
20170287930 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels. | 2017-10-05 |